JP6713167B2 - Triple gate H-diamond MISFET and manufacturing method thereof - Google Patents

Description

The present invention relates to a triple gate H-diamond MISFET and a method for manufacturing the same.

Semiconductor diamond has a wide band gap energy (5.45 eV), a low relative dielectric constant (5.7), a high dielectric breakdown electric field strength (10 MV cm ⁻¹ ), and a high carrier saturation rate (1.5 to 5 for electrons and holes, respectively). 2.7×10 ⁷ cm s ⁻¹ and 0.85 to 1.2×10 ⁷ cm s ⁻¹ (Non-Patent Documents 1 and 2), high thermal conductivity (22 W cm ⁻¹ K ⁻¹ ) and high. carrier mobility such (respectively for electrons and holes 4500cm ² V ^-1 s ^-1 and 3800cm ² V ^-1 s ^-1) (non-Patent Document 3), has some time standing physical properties. From the figure of merit of diamonds and other semiconductors [4], diamond-based electronic devices show the highest power-frequency product, the highest thermal limit, and the lowest power loss at high frequencies. Therefore, diamond is considered to be an optimal material for producing next-generation electronic devices with high power, high frequency, high temperature and low power loss, and energy saving (Non-Patent Document 5).

Many diamond electronic devices have been fabricated on hydrogenated diamond (H-diamond) channel layers because the activation energy of diamond dopants is significantly higher than room temperature thermal energy (Non-Patent Documents 6-11). H-diamond can accumulate holes on its surface with a sheet hole density (p _sheet ) of 10 ¹² to 10 ¹³ cm ^-2 . Notably, by exposing the H-diamond to a NO ₂ atmosphere (Non-Patent Document 12) or annealing the oxygen-terminated diamond in a mixed atmosphere of NH ₃ and H ₂ (Non-Patent Document 13), The p- _sheet of H-diamond can reach up to 10 ¹⁴ cm ^-2 .

Recently, a metal-insulator-semiconductor field effect transistor (MISFET) using H-diamond has been greatly developed. The maximum drain-source current (I _DS,max ) of the MISFET (Non-Patent Document 14) produced on the NO ₂ treated H-diamond was as large as −1.35 A mm ⁻¹ . Its cut-off frequency was above 10 GHz over a wide gate-source voltage ( _VGS ) range of approximately 10.0V. In addition, the operation of MISFETs based on H-diamond was comparable to that of MISFETs based on SiC or GaN at high temperatures (400°C) and high voltage (500V) (Non-Patent Document 15). ..

Although H-diamond based MISFETs have excellent electrical properties, their high cost and lack of large area single crystal diamond wafers have hampered their widespread practical application. Diamond substrates grown by microwave plasma-enhanced chemical vapor deposition (MPCVD) technology have become commercially available at a higher growth rate and lower cost than diamond substrates grown by high pressure high temperature (HPHT) technology (Non-patent Reference). References 16-18). Thus, using MPCVD substrates would probably allow diamond electronic devices to be made at relatively low cost.

On the other hand, the absence of a large-area single crystal diamond wafer promotes miniaturization of the diamond electronic device. In the present inventor's previous studies (Non-patent Document 19 and 20), making the H- diamond MISFET miniaturized by eliminating the gap between the source / drain and gate contacts _{(I S / D-G)} did. No I _{S / D-G} H- ON resistance of the diamond MISFET _{(R ON)} was very low than MISFET with _{I S / D-G.} Its current output and extrinsic transconductance (g _m ) were also greatly improved. In addition, a study focusing on miniaturization of the gate length (L _G ) of H-diamond MISFET (hereinafter, may be simply referred to as “MISFET” unless otherwise confused) is also reported. Ever, H- _{L G} diamond MISFET is miniaturized to almost 100 nm (Non-Patent Document 21). H- diamond metal - shortest _{L G} of the semiconductor FET was only 50 nm (Non-Patent Document 22).

With the progress of miniaturization of H-diamond MISFET, suppressing the short channel effect (SCE) in such MISFET becomes one of the main problems. In order to suppress SCE for planar type MISFETs based on Si, InGaAs, and GaN, a triple-gate MISFET architecture has been developed (Non-Patent Documents 23 to 31). Here, the “triple gate FET” is an FET having a structure in which a semiconductor in which a channel is formed has a three-dimensional structure and channels are formed on two sidewalls and an upper surface thereof. Compared with the same area (the area occupied by the substrate), the size of the contact surface between the insulator and the semiconductor is larger in the triple gate MISFET than in the planar type, so the current output of the triple gate MISFET is larger. It is expected to be much larger. Therefore, if a triple-gate MISFET can be formed on H-diamond, it will be an important step to eliminate SCE and give a larger current output in the miniaturization of H-diamond device.

However, in the prior art, a triple gate MISFET on Si, GaAs and GaN could be produced, but this structure could not be realized on diamond. This is because the process used to form triple gates on Si, GaAs, GaN could not be used to form triple gates on diamond. In other words, the manufacturing process of the diamond fin pattern is special, and therefore, the key gate structure for realizing the triple gate MISFET on the diamond could not be manufactured. In fact, although planar type and T-type H-diamond MISFETs have been produced so far, no report has been made so far regarding the successful production of a triple gate MISFET made of diamond.

An object of the present invention is to solve the above-mentioned problems of the prior art and provide an operable triple gate H-diamond MISFET.

According to one aspect of the present invention, there is provided a method for manufacturing a triple-gate H-diamond MISFET, which includes the following steps (A) to (E).
(A) A tungsten metal layer is formed on a diamond substrate, and the tungsten metal layer is etched through a photoresist mask to form a tungsten metal mask on the diamond substrate.
(B) A fin pattern is formed on the diamond substrate by selectively etching the diamond substrate through the tungsten metal mask and then removing the tungsten metal mask.
(C) An H-diamond layer is epitaxially grown on the fin pattern.
(D) The H-diamond layer is selectively etched to form a mesa structure in which at least a part of the fin pattern having the H-diamond layer on the surface remains on the diamond substrate.
(E) A gate insulator layer and a gate electrode conductor layer are deposited on the surface of the diamond substrate on which the mesa structure is formed.
(F) The deposited gate insulator layer and gate electrode conductor layer are selectively etched to form a gate in the middle of a fin pattern having the H-diamond layer on the surface, and the gate is formed. One side of the fin pattern is a source and the other side is a drain as viewed from the position.
Here, before the step (E), conductors for a source electrode and a drain electrode are electrically connected to the one side and the other side of the fin pattern having the H-diamond layer on the surface thereof, respectively. May be provided.
Also, the fin pattern may include a plurality of fins that are parallel to each other.
According to another aspect of the present invention, a fin at least the surface is H- diamond is provided on the diamond substrate, the full fin side and a triple gate H- diamond MISFET the channel is formed on the upper surface Given.
According to still another aspect of the present invention, a fin pattern having a diamond substrate, a gate electrode, a source electrode and a drain electrode, and having one or more fins is formed on the diamond substrate. Of at least the surface is made of H-diamond, and the gate electrode is formed on the upper surface and the side surface of the fin pattern with an insulator layer interposed therebetween. The gate electrode is sandwiched between the first side and the first side. On the side of 2, there is provided a triple gate H-diamond MISFET in which the source electrode and the drain electrode are provided separately from the gate electrode, respectively .
Here, the H- diamond layer may be an epitaxial layer formed on the integral structure surface is an integral part of the diamond substrate.
In addition, the sidewall of the fin may have an inclined angle with respect to the surface of the diamond substrate.
Further, a plurality of the fins may be provided, and the opposing side walls of the adjacent fins may form a V-shaped groove.
Alternatively, the sidewalls of the fins may be perpendicular to the diamond substrate surface.
Further, the gate and at least one of the drain and the source may be adjacent to each other on the fin without any space.

According to the present invention, it is possible to provide a triple gate H-diamond MISFET that operates well. This triple gate H-diamond MISFET has higher performance than a planar type MISFET formed on H-diamond in the same size, and can suppress the short channel effect.

The figure which shows notionally the manufacturing process of the fin pattern of H- diamond. FIG. 3 is a diagram conceptually showing a manufacturing process of a triple gate H-diamond MISFET on an H-diamond fin pattern. The conceptual diagram of the triple gate H-diamond MISFET completed by the manufacturing process shown in FIG. 1B. The top surface photograph of the whole sample produced in Example 1 of this invention and two triple gate H-diamond MISFETs in it. 5 is an SEM image of a diamond substrate on which a fin pattern is formed in the manufacturing process of Example 1 of the present invention. 5 is an SEM image of a diamond substrate on which a fin pattern is formed in the manufacturing process of Example 1 of the present invention. 3 is a TEM image of the triple gate H-diamond MISFET of Example 1 of the present invention. 3 is a TEM image of the triple gate H-diamond MISFET of Example 1 of the present invention. 3 is a TEM image of the triple gate H-diamond MISFET of Example 1 of the present invention. 3 is a TEM image of the triple gate H-diamond MISFET of Example 1 of the present invention. The inset is the SAD pattern of the H-diamond epitaxial layer grown on the etched area of the diamond substrate. 3 is a TEM image of the triple gate H-diamond MISFET of Example 1 of the present invention. 1 is a conceptual diagram showing the structure of a triple gate MISFET according to a first embodiment of the present invention. The conceptual diagram which shows the structure of the planar type MISFET of a comparative example. 5 is a graph of a leak current I _leak of the MISFET according to the first embodiment of the present invention. Here, a circle (◯) indicates I _{leak of the} triple gate MISFET, and a square (□) indicates I _{leak of the} planar type MISFET. 3 is a graph of I _DS -V _DS characteristics of the triple-gate MISFET of Example 1 of the present invention. Here, V _GS was changed from -10.0 V to 20.0 V in +1.0 V steps. 6 is a graph of I _DS -V _DS characteristics of a planar type MISFET of a comparative example. Here, V _GS was changed from -10.0 V to 20.0 V in +1.0 V steps. 6 is a graph showing log| _IDS |-V _GS characteristics of the triple-gate MISFET (top) of Example 1 of the present invention and the planar type MISFET of the comparative example (bottom). 6 is a graph showing −√(|I _DS |)-V _GS characteristics of the triple-gate MISFET (top) of Example 1 of the present invention and the planar MISFET (bottom) of Comparative Example. 3 is a graph showing g _m -V _GS characteristics of the triple-gate MISFET (top) of Example 1 of the present invention and the planar MISFET (bottom) of Comparative Example. FIG. 6 is a conceptual diagram showing a cross-sectional structure of a triple-gate MISFET having a source/drain/gate spacing ( _IS/ DG) of 2.0 μm, which is Embodiment 2 of the present invention. Here, the gate length (L _G ) is 500 nm. The top surface photograph of the triple gate MISFET of Example 2 of this invention. 6 is a graph showing I _DS -V _DS characteristics of the triple gate MISFET of Example 2 of the present invention. Here, V _GS was changed from -10.0 V to 20.0 V in +1.0 V steps. 5 is an SEM image of a diamond substrate on which a second fin pattern is formed in order to manufacture the triple gate MISFET of Example 3 of the present invention. The length of the fin is 7 μm, and the width of each fin and the space between the fins are both 500 nm. 7 is a TEM image of the triple-gate MISFET of Example 3 of the present invention formed on the diamond substrate on which the second fin pattern is formed. L _G and _{I S / D-G} are each a 500 nm. 7 is a graph showing I _DS -V _DS characteristics of the triple gate MISFET of Example 3 of the present invention. V _GS was changed from -10.0 V to 20.0 V in +1.0 V steps. FIG. 9 is a conceptual diagram showing a cross-sectional structure of an IS _/DG- less triple gate MISFET of Example 4 of the present invention. This MISFET has T-shaped gates having a top length and a bottom length of 2.5 μm and 500 nm, respectively. The top surface photograph of two IS _/DG- less triple gate MISFETs of Example 4 of this invention. 16 is a graph showing I _DS -V _DS characteristics of the triple gate MISFET without IS _/ DG of Example 4 of the present invention. V _GS was changed from -10.0 V to 20.0 V in +1.0 V steps.

Here, the inventor of the present application found a novel method for producing a triple gate MISFET using a fin pattern on a diamond substrate, and based on this, produced an H-diamond triple gate MISFET on an MPCVD single crystal diamond substrate. The electrical characteristics of this MISFET were compared with those of a planar type MISFET. The triple gate MISFET had an I _DS,max of −242.0 mA mm ⁻¹ , which was much higher than the planar type −45.2 mA mm ⁻¹ . In addition to this, the on/off ratio and the subthreshold swing of this triple gate MISFET were values higher than 10 ^{8 and} 110 mV dec ^-1 respectively.

Hereinafter, the present invention will be described in detail based on examples.

<Example 1: Triple pattern H-diamond MISFET manufactured on fin pattern H-diamond>
FIG. 1A is a diagram conceptually showing a manufacturing process of H-diamond having a fin pattern formed, FIG. 1B is a diagram conceptually showing a manufacturing process of triple gate H-diamond MISFET, and FIG. 1C is a completed triple gate H-diamond. A conceptual view of the MISFET, and FIG. 1D is a top view photograph of the entire fabricated sample and two triple-gate H-diamond MISFETs therein. To form a fin pattern on a diamond (001) substrate, tungsten (W) metal is first sputtered using an atomic sputtering system (step 1 of FIG. 1A). Photoresist (using positive photoresist FEP-171 in the example) is coated on the substrate and an electron beam (EB) lithography system is used to create the fin mold (step 2 in FIG. 1A). An inductively coupled plasma reactive ion etching (ICP-RIE) system is used to dry etch the W metal and diamond substrate, respectively, in areas where photoresist is not present (step 3 of FIG. 1A). 4; Examples use SF ₆ and O ₂ atmospheres, respectively). The remaining W metal is removed again in the SF ₆ atmosphere to form a fin pattern on the diamond substrate (step 5 in FIG. 1A). Next, an H-diamond epitaxial layer is grown on the substrate using the MPCVD technique to form a fin pattern H-diamond (step 6 of FIG. 1A).

After forming the fin pattern H-diamond, a triple gate MISFET is formed. This process is shown in FIG. 1B. First, the fin pattern H-diamond is etched in an O ₂ atmosphere using a capacitively coupled plasma RIE (CCP-RIE) system to form a mesa structure (step 1 in FIG. 1B). Palladium/titanium/gold (Pd/Ti/Au) ohmic contacts are deposited on the fin pattern H-diamond using an electron gun (E gun) deposition system to form the source/drain electrodes (step of FIG. 1B). 2). Although a layered structure of Pd/Ti/Au is used here to form an ohmic contact with H-diamond, it is of course possible to use another layered structure that is normally used (for example, Au). Atomic oxide deposition (ALD) and ultra high vacuum (UHV) sputtering techniques are used to deposit aluminum oxide (Al ₂ O ₃ ) gate insulator and aluminum (Al) gate electrode, respectively (step 3 in FIG. 1B). Next, this is covered with a photoresist such as PMGI-SF6S/FEP-171 bilayer photoresist and exposed by an EB lithography system to form a gate mold. Al and Al ₂ O ₃ in regions where the photoresist is not present are wet-etched with mixed acid and tetramethylammonium hydroxide (TMAH) solution, respectively. Lifting off the photoresist in N-methylpyrrolidone (NMP) solution yields a triple-gate H-diamond MISFET (step 4 in FIG. 1B).

A planar type MISFET and a triple gate MISFET were simultaneously formed on the same diamond substrate. The upper photograph in FIG. 1D is a top photograph of the entire sample thus produced. The total number of MISFETs in the design was 128. However, as shown in the figure, three ohmic contacts dropped during the fabrication process. The lower photograph in FIG. 1D is an enlarged photograph of two triple-gate H-diamond MISFETs out of the entire sample. These MISFET _{L G} (see Figure _1C), (see Figure 1C) _{I S / D-G} and the gate width _(W G) are each 500nm, it was 500nm and 100.5Myuemu. The lower photo of FIG. 1D shows the pair of two triple-gate H-diamond MISFETs in which the drain electrodes are commonly connected to each other, but to simplify the expression, the connection is as follows. It should be noted that the paired MISFETs referred to herein are simply two MISFETs.

<Morphology of surface and interface>
2A and 2B show scanning electron microscope (SEM) images of a diamond substrate having a fin pattern, and FIG. 2B has a higher magnification. 2C to 2G are transmission electron microscope (TEM) images of the triple gate H-diamond MISFET. The inset of FIG. 2F is the selected area description (SAD) pattern of the H-diamond epitaxial layer grown in the etched region of the diamond substrate. The SEM images shown in FIGS. 2A and 2B, the entire width of the diamond fin pattern is 100.5Myuemu, which is the same as _{W G} of MISFET. The fin length is 7 μm. The width of each fin and the distance between the two fins are both 500 nm. The height of the fin was confirmed to be 500 nm by a 3D measuring laser microscope. It should be noted that the entire fin pattern shown in FIG. 2A is covered by the single mesa structure conceptually shown in step 1 of FIG. 1B, and finally the entire fin pattern is a triple gate. It is housed in an H-diamond MISFET and used to realize its gate structure.

The gate, source and drain contacts of the H-diamond triple gate MISFET are clearly shown in FIG. 2C. After growing the H-diamond epitaxial layer using the MPCVD technique, the fin length and width increased to 7.8 μm and 600 nm, respectively. Also, from FIG. 2D, it can be seen that the spacing between the two fins and the height of the fins were reduced to 400 nm and 340 nm, respectively. It can be seen from FIG. 2E that the thickness of the H-diamond epitaxial layer is about 50 nm, and from FIG. 2F that the angle between the two fins is 60°. The two tilted active surfaces of each fin of this triple-gate MISFET (H-diamond surface functioning as a channel; in addition to the top surface of the fin, both side surfaces also function as channels)

On the side. Equivalent _{W G} of the triple gate MISFET can be calculated and 139.6μm. The thickness of ALD-Al ₂ O ₃ is approximately 27.9 nm, which is in good agreement with the result of measurement using an ellipsometer system. The inset SAD pattern in FIG. 2F shows that the H-diamond grown on the etched region also maintains single crystallinity in the (001) direction. As can be seen in FIG. 2G, an interface layer of approximately 0.6 nm thickness exists between H-diamond and Al ₂ O ₃ , but this layer is also observed at the AlN/H-diamond interface (non- Patent document 32). It is unknown at this time what this layer is responsible for. However, this is probably due to the reaction of the oxide or nitride with the adsorbate on the H-diamond epitaxial layer.

<Electrical Characteristics of Triple Gate MISFET and Planar MISFET>
3A and 3B are conceptual diagrams showing the structures of a triple gate H-diamond MISFET and a planar type H-diamond MISFET, respectively. FIG. 3C shows the gate leakage current (I _leak ) of the triple gate H-diamond MISFET and the planar type H-diamond MISFET. FIGS. 3D and 3E is a drain of each triple gate H- diamond MISFET and a planar type H- diamond MISFET - represents the source current versus voltage relationship _{(V DS -V} DS). The triple gate H- diamond MISFET and a planar-type H- diamond MISFET, have the same _L G, _{W G} and _{I S / D-G.} The difference between the two MISFETs is that the fin pattern is present on the diamond substrate in the triple gate MISFET. The I _leak curves for these MISFETs were obtained by measuring the current-voltage relationship between the gate and source contacts while varying V _GS from 30.0V to -10V. When V _GS is −10 V, holes are accumulated at the Al ₂ O ₃ /diamond interface and the MISFET is turned on. I _{leak of the} triple gate MISFET was 1.4×10 ⁻¹⁰ A, which is larger than 2.3×10 ⁻¹² A of the planar type MISFET. This perhaps is equivalent W _G and etching the surface of the triple gate MISFET, is believed to be due to compared to their planar respective longer also rough large. The I _leak density of the planar type MISFET can be calculated as 4.6×10 ⁻⁶ A cm ⁻² by using I _leak divided by the area of the gate electrode (5.025×10 ⁻⁷ cm ² ). This value is an order of magnitude larger than 1.1×10 ⁻⁷ A cm ^{−2 for} Al ₂ O ₃ /H-diamond MIS capacitors. Since the manufacturing process of a MISFET is more complicated than that of a MIScapacitor, the damage or defects in the gate or source/drain regions of the MISFET are more severe than those of a MIScapacitor, and it is presumed that this makes the I _leak of the MISFET larger. .. When V _GS is 30.0 V, it is difficult for holes to accumulate at the Al ₂ O ₃ /H-diamond interface and the MISFET is turned off. I _{leak of the} triple gate MISFET is 1.8×10 ⁻¹² A, but this value is smaller than 1.2×10 ⁻¹⁰ A in the planar type. Therefore, in the off state, the gate power loss is smaller in the triple gate MISFET.

In measuring the I _DS -V _DS characteristics of the triple gate MISFET and the planar type MISFET of FIGS. 3D and 3E, V _GS was changed from -10.0 V to 20.0 V in +1.0 V steps. To compare their electrical characteristics in the same area for both types of MISFET, _{I DS} for triple gate MISFET also normalized by _{W G} (Not equal to _{W G).} Both types of MISFETs clearly show p-type channel characteristics and pinch-off characteristics. Both types of MISFETs have a good linear relationship between the low voltage region of I _DS and V _DS . This indicates that good ohmic contact was established between Pd/Ti/Au and the H-diamond channel layer. The triple gate MISFET had an I _DS,max of −242.0 mA mm ⁻¹ , which is much larger than −45.2 mA mm ^{−1 in the} planar type.

Normalized _{R ON} in W _G can be extracted from the linear region of the _I DS _{-V DS} characteristics. _{W G} normalized _{R ON} determined in this way are respectively 23.0Omu mm and 98.0Omu mm for triple gate MISFET and a planar type MISFET. R _ON of the triple gate H-diamond MISFET is a fin pattern channel resistance (R _CH ) under an Al ₂ O ₃ insulator, fin pattern H-diamond surface resistance (2R _SD ) when IS _/ DG is 500 nm, And Pd/Ti/Au ohmic connection resistance (2R _C ). Since 2R _C is much smaller than _{R CH} and _{2R SD,} 2R _C is negligible. By I _{S / D-G} is combined with _{R ON} value of triple-gate MISFET of Example 2 (described later) of 2.0 _.mu.m, presumed _{R CH} and _{2R SD} are respectively 16.6Omu mm and 6.4Omu mm it can.

A transfer characteristic corresponding to the I _DS -V _DS curve shown in FIG 4A~ Figure 4C. As shown in the upper graph of FIG. 4A, the on/off ratio of the triple gate MISFET is larger than 10 ⁸ , but this value is the same as the on/off ratio of the planar MISFET shown in the lower graph of FIG. 4A. It is a level. This is large enough for practical applications.

Subthreshold swing (SS) is an important parameter for evaluating the power consumption of MISFET. SS is log _| is defined as the inverse slope of the pair _{V DS} (the reciprocal of the gradient) | _{I DS.} The value of SS was 110 mV dec ⁻¹ at V _DS −10.0 V as shown in the upper part of FIG. 4A for the triple gate MISFET. This value is much smaller than 460 mV dec ^{-1 in} the case of the planar type MISFET shown in the lower part of FIG. 4A. The following relationship is established between the SS and the _Al 2 _O 3 / H- trapped charge capacitance at the diamond surface _{(C it).}

Where k, T, q, C _H-diamond and

Are Boltzmann constant (8.62×10 ⁻⁵ eV K ⁻¹ ), room temperature (298.15 K), charge of one electron (1.6×10 ⁻¹⁹ C), capacitance of H-diamond, and Al _{2 respectively.} It is the capacitance of the O ₃ layer.

Is the formula

From this, it is calculated to be 0.171 μF cm ⁻² . Where ε ₀ ,

,as well as

Are vacuum permittivity (8.85×10 ⁻¹² F m ⁻¹ ), Al ₂ O ₃ relative permittivity (5.4) (Non-patent document 34), and Al ₂ O ₃ thickness (27). 1.9 nm). If C _H-diamond can be ignored in the deep subthreshold region, the C _it values of the triple gate MISFET and the planar MISFET are calculated to be 0.143 μF cm ⁻² and 1.143 μF cm ⁻² , respectively. Therefore, the interface trap charge densities of these two MISFETs are estimated to be 8.95×10 ¹¹ eV ⁻¹ cm ⁻² and 7.14×10 ¹² eV ⁻¹ cm ⁻² , respectively. The threshold voltage (V _TH ) of both MISFETs can be determined by −√(I _DS ) as a function of V _GS . As shown in FIGS. 4B and 4C, these values are 10.2±0.1 eV and 7.6±0.1 eV for triple-gate MIS and planar MISFET, respectively. Therefore, both MISFETs operate in the depletion mode.

There is the following relationship between R _ON , V _TH, and effective mobility (μ _eff ).

R _ON , L _G , W _G for the triple gate MISFET,

, V _GS , V _TH, and R _SD were 23.0 Ω mm, 500 nm, 100.5 μm, 0.171 μF cm ⁻² , −10.0 V, 10.2±0.1 V, and 6.4 Ω mm, respectively. .. The μ _eff of the fin pattern H-diamond channel layer can be calculated as 8.7±0.5 cm ² V ⁻¹ s ⁻¹ . This value is lower than the previously reported 38.7±0.5 cm ² V ⁻¹ s ^{−1 of} the planar type MISFET (Non-Patent Document 35). This is probably due to the increased surface roughness in the etched area for fin patterned H-diamonds. Extrinsic transconductance _{(g m)} is determined by the gradient of _I DS _{-V GS} curve. As shown in FIG. 4C, the maximum values of gm (g _m,max ) of the triple gate MISFET and the planar type MISFET were 21.3±0.1 mS mm ⁻¹ and 3.8±0.1 mS mm ⁻¹ . ..

<Example 2: Triple gate MISFET having a source/drain/gate spacing ( _IS/ DG) of 2.0 μm>
A triple gate MISFET of Example 2 was produced in the same manner as in Example 1 except that it had a cross-sectional structure shown in FIG. 05A and that IS _/ DG was 2.0 μm.

The maximum value of the _{I DS} of triple-gate MISFET of _{I S / D-G} is 2.0μm Example 2 _{(I DS, max)} was -207.9mA mm ^-1. This value _{I S / D-G} is a triple-gate MISFET of Example 1 is 500 nm _{I DS,} slightly smaller than -242.0mA mm ^-1 is the value of _max. In Example 2, the ON resistance (R _ON ) normalized by W _G was 42.2 Ω mm. If the surface resistance of the fin pattern H-diamond channel layer of the triple gate MISFET of Example 1 in which IS _/ DG is 500 nm is 2R _SD , in Example 2 in which IS _/ DG is 2 μm. Is considered to have a surface resistance of 8R _SD . The R _ON (23.0 Ω mm) of the triple-gate MISFET of the first embodiment is the sum of fin-type channel resistance (R _CH ) under the Al ₂ O ₃ insulator and 2R _SD . _R ON of triple-gate MISFET is Embodiment 2 _{I S / D-G} is 2μm (42.2Ω mm) is the sum of the _{R CH} and _{8R SD.} Therefore, R _CH and 2R _SD can be estimated to be 16.6 Ω mm and 6.4 Ω mm, respectively.

<Example 3: Triple gate MISFET manufactured on a diamond substrate using another fin pattern>
A triple gate MISFET of Example 3 was manufactured in the same manner as in Example 1 except that the fin pattern of the SEM image shown in FIG. 6A was provided, which was different from the SEM images shown in FIGS. 2A and 2B.

In Example 1 and Example 3, two types of fin patterns were produced by changing the etching process. The fin pattern of Example 1 shown in FIG. 2B etched the edges of the diamond substrate, whereas the fin pattern of Example 3 shown in FIG. 6A did not etch the edges of the diamond substrate. The triple gate MISFET of Example 3 having the fin pattern shown in FIG. 6A had an I _DS,max of −202.3 mA mm ⁻¹ as shown in FIG. 6C. This value is slightly smaller than the value in Example 1 of -242.0 mA mm ^-1 . However, each value is considerably larger than I _DS,max (−45.2 mA mm ⁻¹ ) of the planar type MISFET of the comparative example.

<Example 4: Triple gate MISFET without IS _/ DG>
A triple-gate MISFET of Example 4 was manufactured in the same manner as in Example 1 except that it had the cross-sectional structure shown in FIG. 7A and that there was no _IS/ DG. I _{S / D-G} of the triple gate MISFET without _{I DS, max} is a was the -349.2mA mm ^-1, the value _{I S / D-G} of Example 1 is 500 nm _{I DS, max} It is larger than (-242.0 mA mm ^-1 ). The R _ON of this triple gate MISFET was only 9.8 Ω mm, but this value is lower than the R _ON (23.0 Ω mm) of the triple gate MISFET of the first embodiment. However, the triple gate MISFET without IS _/ DG of this example could not sufficiently control the current output when V _GS was changed.

<Common items of Examples>
-Fin pattern H-Creation of diamond-
A single crystal diamond (001) substrate with dimensions of 5.0 mm×5.0 mm×0.3 mm was purchased from EDP Corp. This substrate was purified in a mixed acid solution (H ₂ SO ₄ and HNO ₃ , volume ratio 1:1) at 300° C. for 30 minutes. On this diamond substrate, W metal was sputtered at 300 W in an Ar gas atmosphere using an automatic sputtering system (ULVAC, JSP-8000). The thickness of the sputtered W metal and the sputter time were 200 nm and 30 minutes, respectively. The W/diamond sample was coated with the positive photoresist FEP-171 at rotation speed and rotation time of 5000 rpm and 1 second, respectively. The baking temperature and time of FEP-171 photoresist were 120° C. and 2 minutes, respectively. This photoresist was exposed with an EB lithography system (Elionix ELS-7000), and then the sample was developed in a TMAH solution for 1.5 minutes. The W metal was etched by SF ₆ and C ₄ F ₈ gas in the Bosch process using an ICP-RIE dry etching system (MUC-21 manufactured by Sumitomo Precision Industries, Ltd.). The flow rates of SF ₆ and C ₄ F ₈ were 75 sccm and 60 sccm, respectively. These plasma powers were 175 W and 150 W, respectively. Diamond in areas without photoresist was etched under an O ₂ gas atmosphere using the same equipment. The etching output, flow rate, chamber pressure and etching time were 400 W, 10 sccm, 0.5 Pa and 25 minutes, respectively. The remaining W was removed to form a fin-patterned diamond substrate. An H-diamond epitaxial layer was then grown using the MPCVD system (AX 5200S from Seki Technotron). Prior to growth, the fin patterned diamond substrate was cleaned in an MPCVD chamber at 1000° C. for 20 minutes. The growth temperature, time and chamber internal pressure of the H-diamond epitaxial layer were 900 to 940° C., 20 minutes and 80 Torr, respectively. Here, the flow rates of H ₂ and CH ₄ were 500 sccm and 0.5 sccm, respectively.

-Fabrication of Triple Gate MISFET-
The production of the triple gate Al ₂ O ₃ /H-diamond MISFET was basically carried out based on a combination of EB lithography, CCP-RIE dry etching, E-gun evaporation, ALD, UHV sputtering, wet etching and lift-off technology. PMGI-SF6S and FEP-171 bilayer photoresist were sequentially coated on a fin-patterned diamond substrate. The baking conditions for FEP-171 have been described above. The baking temperature and time for PMGI-SF6S were 180°C and 5 minutes, respectively. The H-diamond epitaxial channel layer was etched at a pressure of 10 Pa in an O ₂ atmosphere using a CCP-RIE system (Samco Corporation, RIE-200NL) to form a mesa structure. Plasma power and etching time were 50 W and 1.5 minutes, respectively. Pd/Ti/Au ohmic contacts were formed using an E gun deposition system (R-DEC Co. Ltd., RDEB-1206K). Here, the fin pattern H-diamond surface was first contacted with Pd metal. The thicknesses of Pd, Ti and Au were 10 nm, 20 nm and 100 nm, respectively. The vapor deposition rates of these metals were 0.05 nm s ^-1 , 0.05 nm s ^-1, and 0.2 nm s ^-1 , respectively. The pressure in the chamber was in the range of 1.0 to 2.5×10 ⁻⁵ Pa. Al ₂ O ₃ gate insulator and Al gate electrode were sequentially deposited on the fin-patterned H-diamond channel layer by ALD system (Picosun, Sunale R-100B) and UHV sputtering system (Biemtron, LS-420R). .. Precursors of _ALD-Al 2 _{O 3} was Al _{(CH 3) 4} and water vapor. The pulse time and purge time in both cases were 0.1 seconds and 4.0 seconds, respectively. The deposition temperature was 120°C. The plasma output, chamber pressure, Ar gas flow rate and deposition time for Al metal were 50 W, 0.3 Pa, 10 sccm and 7 minutes, respectively. The Al metal was wet-etched for 1 minute using a mixed acid solution (volume ratio of H ₃ PO ₄ :HNO ₃ :CH ₃ COOH:H ₂ O 16:2:2:1). The Al ₂ O ₃ insulator was wet etched for 10 minutes using TMAH solution. The photoresist was removed by treating with NMP solution at room temperature for 3 hours.

-Measurement system-
The surface morphology of the fin-patterned diamond substrate was examined using the SEM system (Hitachi High-Technologies Corporation, S-4800). A sample for TEM measurement was prepared using a focused ion beam SEM system (Seiko Instruments Inc., Xvision-200DB). The observation by TEM was performed using a JEM-2100F system at an acceleration voltage of 200 kV. The height of the fin pattern was measured by a 3D measuring laser microscope system (OLS-4000, Olympus Corporation). The thickness of the Al ₂ O ₃ film was measured by an ellipsometer system (Five Lab, MARY-102FM). The electrical characteristics of the MISFET were examined using an MX-200/B prober (Vector Semiconductor Corp.) and a B1500A parameter analyzer (Agilent Technologies Inc.).

<Discussion>
In reducing the size of the H-diamond MISFET, an H-diamond triple gate MISFET was manufactured in order to suppress the SCE problem and obtain a larger I _DS,max . Table 1 shows a summary of the electrical characteristics of the triple-gate MISFET and the planar type MISFET of Example 1.

In Table 1, I _leak (I _leak,off ) in the off state of the triple gate MISFET is almost two orders of magnitude lower than that in the planar type. Equivalent _{W G} of the triple gate MISFET despite not long only 1.4 times compared to the _{W G} of the planar type MISFET, _{I DS} of a triple-gate _{MISFET, max} is _{I DS} of the planar type _MISFET, even five times the _max large. This was also confirmed in the other triple gate MISFET shown in Example 3. In explaining that I _DS,max of the triple-gate MISFET becomes larger than the theoretical value, there are two possible reasons. It is reported that the inclined H-diamond (111) plane has a higher p _sheet than the flat H-diamond (001) plane (Non-Patent Document 36). In the triple-gate MISFET of Example 1, each fin has two slopes.

It is reasoned that the fin pattern H-diamond channel layer has a higher p _sheet than the flat H-diamond (001) channel layer because it has a face. On the other hand, the increase of surface roughness where caused by the etching process of the fin pattern H- diamond channel layer, the equivalent W _G is probably longer than the theoretical value.

As shown in Example 4, a triple gate MISFET without IS _/ DG was also manufactured and its electrical characteristics were measured. In the fourth example, I _DS,max was as large as −349.2 mA mm ⁻¹ , but its current output could not be sufficiently controlled by the change in V _GS . I _{S / D-G} without triple gate _Al 2 _O 3 / Al gate layer in MISFET also covered with the source / drain ohmic contacts. During the Al ₂ O ₃ /Al etching process (step 4 in FIG. 1B), some damage may occur in the edge area. Since the subthreshold current of the triple gate MISFET is considered to flow in the middle of the fin (Non-Patent Documents 31 and 37s), the trap charge density at the Al ₂ O ₃ /fin pattern H-diamond interface is Al ₂ O ₃ /planar. It becomes smaller than the trap charge density at the H-diamond interface. Perhaps this is the reason why the SS of the triple gate MISFET is significantly lower than that of the planar type. The value of V _TH is greater than zero for both types of MISFETs. This indicates that these MISFETs operate with normally-on characteristics. Since the normally-off H-diamond MISFET can be manufactured by depositing a double-layer gate and annealing at 180° C. to 300° C., it is expected that a normally-off triple-gate MISFET can be manufactured in the future.

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Claims (10)

A method of manufacturing a triple-gate H-diamond MISFET, comprising the following steps (A) to (E).
(A) A tungsten metal layer is formed on a diamond substrate, and the tungsten metal layer is etched through a photoresist mask to form a tungsten metal mask on the diamond substrate.
(B) A fin pattern is formed on the diamond substrate by selectively etching the diamond substrate through the tungsten metal mask and then removing the tungsten metal mask.
(C) An H-diamond layer is epitaxially grown on the fin pattern.
(D) In order to form a mesa structure in which at least a part of the fin pattern having the H-diamond layer on the surface remains on the diamond substrate, the H-diamond layer is selectively etched.
(E) A gate insulator layer and a gate electrode conductor layer are deposited on the surface of the diamond substrate on which the mesa structure is formed.
(F) The deposited gate insulator layer and gate electrode conductor layer are selectively etched to form a gate in the middle of a fin pattern having the H-diamond layer on the surface, and the gate is formed. One side of the fin pattern is a source and the other side is a drain as viewed from the position. Before the step (E), a conductor for a source electrode and a drain electrode is formed so as to be electrically connected to the one side and the other side of the fin pattern having the H-diamond layer on the surface. The method for manufacturing a triple-gate H-diamond MISFET according to claim 1, further comprising steps. The method for manufacturing a triple-gate MISFET according to claim 1, wherein the fin pattern has a plurality of fins that are parallel to each other. A fin having at least a surface of H-diamond is provided on a diamond substrate,
Triple gate H- diamond MISFET the channel is formed on the side surfaces and upper surface of the full fin. It has a diamond substrate, a gate electrode, a source electrode and a drain electrode,
A fin pattern having a single fin or a plurality of fins is formed on the diamond substrate,
At least the surface of the fin pattern is made of H-diamond,
The gate electrode is formed on an upper surface and a side surface of the fin pattern via an insulating layer,
The source electrode and the drain electrode are respectively provided on the first side and the second side facing each other with the gate electrode interposed therebetween, apart from the gate electrode.
Triple Gate H-Diamond MISFET. Wherein H- diamond layer is an epitaxial layer formed on the integral structure surface is an integral part of the diamond substrate, a triple gate H- diamond MISFET of claim 5. 7. The triple-gate H-diamond MISFET according to claim 5 or 6, wherein sidewalls of the fin have an inclined angle with respect to the diamond substrate surface. A plurality of the fins are provided,
Opposing sidewalls of adjacent fins form a V-shaped groove,
The triple gate H-diamond MISFET according to claim 7. 7. The triple-gate H-diamond MISFET according to claim 5 or 6, wherein the fin sidewall is perpendicular to the diamond substrate surface. 10. The triple-gate H-diamond MISFET according to claim 4, wherein the gate and at least one of the drain and the source are adjacent to each other on the fin without any space.