JP6705219B2 - Semiconductor device - Google Patents

Description

The present invention relates to the structure of a semiconductor device in which a large current flows in the in-plane direction of a semiconductor layer.

As a semiconductor device that performs a high-current switching operation, for example, a HEMT (High Electron Mobility Transistor) using a group III nitride semiconductor (GaN or the like) is known. Since a high breakdown voltage is required in the HEMT when it is turned off, a structure that does not form a portion where the electric field strength locally increases in the semiconductor layer when it is turned off is adopted.

As an example of such a structure, Patent Document 1 describes a structure provided with a field plate. FIG. 6 is a cross-sectional view of the semiconductor device 200, in which a source electrode (first main electrode) 21 and a drain electrode (second main electrode) 22 formed on one main surface of the semiconductor layer 11 are shown. A cross section along the side-by-side direction (direction in which current flows) and perpendicular to the surface of the semiconductor layer 11 is shown. Here, the semiconductor layer 11 in which the substrate 10, the non-doped GaN layer (channel layer) 11A, and the AlGaN layer (barrier layer) 11B are sequentially formed is used, and is formed at the heterojunction interface between the non-doped GaN layer 11A and the AlGaN layer 11B. ON/OFF of the current flowing between the source electrode 21 and the drain electrode 22 by the two-dimensional electron gas layer is controlled by the potential of the gate electrode (control electrode) 123. At this time, the source electrode 21 is normally set to the ground potential, and a high voltage is applied to the drain electrode 22. The potential of the gate electrode 123 changes according to control, but its absolute value is smaller than the potential of the drain electrode 22 and is within a range that can be regarded as approximately the ground potential. These configurations are the same as those of the generally known HEMT. The source electrode 21 and the drain electrode 22 are both made of a material that makes ohmic contact with the AlGaN layer 11B, and the gate electrode 123 is a material that can control the on/off of the two-dimensional electron gas layer at the heterojunction interface immediately thereunder. Composed.

An interlayer insulating layer 112 made of SiO ₂ or the like is formed so as to cover the surface of the semiconductor layer 11, the source electrode 21, the drain electrode 22, and the gate electrode 123, and the source electrode 21 has a source wiring 31 and a drain. A drain wiring 32 is connected to the electrode 22, and the source wiring 31 and the drain wiring 32 are taken out on the interlayer insulating layer 112. The source wiring 31 and the drain wiring 32 are both low resistance materials (such as Al) that are preferably used as wiring materials, and are configured separately from the source electrode 21 and the drain electrode 22. On the other hand, the gate electrode 123 has a T-shaped cross section as shown in the figure, and has a narrower width on the lower side and is in direct contact with the AlGaN layer 11B (gate electrode lower portion 123A), and on the upper side, the source electrode 21, A portion (gate electrode upper portion 123B) that protrudes toward the drain electrode 22 and faces the surface of the semiconductor layer 11 with the interlayer insulating layer 11 in between is provided. Here, it is the lower gate electrode lower portion 123A that is directly involved in turning the current on and off.

On the other hand, since the upper part 123B of the gate electrode faces the AlGaN layer 11B via the interlayer insulating layer 112, it functions as a field plate for controlling the surface potential of the semiconductor layer 11. As described above, since the potential of the gate electrode 123 is substantially equal to the potential of the source electrode 21 (ground potential), this part of the semiconductor layer 11 functions as a field plate substantially at ground potential. Due to the MOS effect using such a field plate structure, the potential distribution of the semiconductor layer 11 is controlled, and a portion where the electric field strength locally increases (a portion where the potential sharply changes) is formed in the semiconductor layer 11 when the semiconductor layer 11 is off. Is suppressed.

Although it is possible to form such a field plate structure separately from the gate electrode 123 and the source electrode 21 with the same wiring material as the source wiring 31 and the drain wiring 32, in the structure of FIG. It can be formed at the same time when the gate electrode 123 is formed. At this time, since the gate electrode upper portion 123B to be the field plate can be formed close to the semiconductor layer 11 (AlGaN layer 11B), the effect as the field plate becomes particularly large.

JP, 2013-98222, A

When the HEMT is actually used, it is in a form of being sealed with a resin material and mounted in the package. Since various heating steps are required for mounting in this way, a thermal cycle was applied to the above structure. In such a case, it spreads in the horizontal direction between the material forming the interlayer insulating layer 112 and the material forming the gate electrode 123, or due to the difference in the coefficient of thermal expansion between these materials and the resin material used for sealing. Peeling between the upper part of the gate electrode 123A and the interlayer insulating layer 112, cracks in the interlayer insulating layer 112, and the like were likely to occur. Therefore, the reliability of the semiconductor device using the field plate structure is lowered.

That is, it is difficult to obtain a highly reliable semiconductor device using the field plate structure.

The present invention has been made in view of the above problems, and an object thereof is to provide an invention that solves the above problems.

The present invention has the following configurations in order to solve the above problems.
The semiconductor device of the present invention includes a first main electrode serving as a source electrode, a second main electrode serving as a drain electrode, and a control serving as a gate electrode for controlling on/off of a current flowing between the source electrode and the drain electrode. a field effect transistor having an electrode, an interlayer insulating layer in said upper surface between the both provided with the first main electrode and the second main electrode on the side of the surface to be one main surface of the semiconductor layer A semiconductor device comprising a field plate, which is an electrode provided so as to face the surface through the field plate, the field plate being provided integrally with the control electrode and facing the surface of the field plate. in part, the protrusion coated on the interlayer insulating layer is formed to project to the side of the locally said surface, said surface facing the portion of the field plate, the control electrode is close to the most said surface portion The protrusions are provided on the first main electrode side and the second main electrode side, respectively, and the protrusions are portions facing the surface of the field plate on the first main electrode side and the second main electrode side. In a cross-sectional view perpendicular to the surface along the direction in which the current flows, a plurality of portions are provided in a portion of the field plate on the side of the first main electrode or the side of the second main electrode that faces the surface. It is characterized in that a protrusion is provided.
The semiconductor device of the present invention is provided in a portion facing the surface of the field plate on the side of the first main electrode and the side of the second main electrode in a sectional view perpendicular to the surface along the direction in which the current flows. The number of the protrusions is different.
In the semiconductor device of the present invention, in a cross-sectional view perpendicular to the surface along the direction of the current flow, the number of the protrusions provided on a portion of the field plate facing the surface on the second main electrode side is It is characterized in that the number of projections provided on a portion of the field plate facing the surface on the side of the first main electrode is larger than that of the projections.
The semiconductor device of the present invention includes a first main electrode serving as a source electrode, a second main electrode serving as a drain electrode, and a control serving as a gate electrode for controlling on/off of a current flowing between the source electrode and the drain electrode. a field effect transistor having an electrode, an interlayer insulating layer in said upper surface between the both provided with the first main electrode and the second main electrode on the side of the surface to be one main surface of the semiconductor layer A semiconductor device comprising a field plate, which is an electrode provided so as to face the surface through the field plate, the field plate being provided integrally with the control electrode and facing the surface of the field plate. in part, the protrusion coated on the interlayer insulating layer is formed to project to the side of the locally said surface, said surface facing the portion of the field plate, the control electrode is close to the most said surface portion The protrusions are provided on the first main electrode side and the second main electrode side, respectively, and the protrusions are portions facing the surface of the field plate on the first main electrode side and the second main electrode side. Are provided on the first main electrode side and the second main electrode side, respectively, in a portion facing the surface in a cross-sectional view perpendicular to the surface along the current flow direction. wherein the width of the protrusion is different.
In the semiconductor device of the present invention, the width of the protrusion is thicker on the second main electrode side.
The semiconductor device of the present invention includes a first main electrode serving as a source electrode, a second main electrode serving as a drain electrode, and a control serving as a gate electrode for controlling on/off of a current flowing between the source electrode and the drain electrode. a field effect transistor having an electrode, an interlayer insulating layer in said upper surface between the both provided with the first main electrode and the second main electrode on the side of the surface to be one main surface of the semiconductor layer A semiconductor device comprising a field plate, which is an electrode provided so as to face the surface through the field plate, the field plate being provided integrally with the control electrode and facing the surface of the field plate. in part, the protrusion coated on the interlayer insulating layer is formed to project to the side of the locally said surface, said surface facing the portion of the field plate, the control electrode is close to the most said surface portion The protrusions are provided on the first main electrode side and the second main electrode side, respectively, and the protrusions are portions facing the surface of the field plate on the first main electrode side and the second main electrode side. Are provided on the first main electrode side and the second main electrode side, respectively, in a portion facing the surface in a sectional view perpendicular to the surface along the current flowing direction. wherein the height of the protrusions is different.
In the semiconductor device of the present invention, the height of the protrusion is increased on the second main electrode side.
In the semiconductor device of the present invention, the semiconductor layer includes a group III nitride semiconductor heterojunction, and the current flows through the heterojunction interface.

Since the present invention is configured as described above, it is possible to obtain a highly reliable semiconductor device using the field plate structure.

It is a sectional view of a semiconductor device concerning an embodiment of the invention. FIG. 6 is a process cross-sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 6 is a cross-sectional view showing a specific configuration of a gate electrode in the semiconductor device according to the embodiment of the present invention. FIG. 3 is a plan view showing a configuration of each electrode in the semiconductor device according to the exemplary embodiment of the present invention. FIG. 11 is a cross-sectional view showing a specific configuration of a gate electrode in a modification of the semiconductor device according to the embodiment of the present invention. It is sectional drawing of an example of the conventional semiconductor device.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. FIG. 1 is a partial cross-sectional view of the peripheral structure including the semiconductor device 1 gate electrode 23, which corresponds to the cross section near the gate electrode 123 in FIG. The semiconductor layer 11, the source electrode 21, the drain electrode 22, the source wiring 31, and the drain wiring 32 in this semiconductor device 1 have the same shapes as those of the semiconductor device 200 shown in FIG. The material forming the gate electrode 23 is also the same as that of the gate electrode 123.

In this semiconductor device 1 as well, the gate electrode 23 has a substantially T-shaped cross section, and has a narrow width (the lower portion of the gate electrode 23A) that is in direct contact with the AlGaN layer 11B, and the source electrode 21 and the drain electrode 22 above it. Each side (left and right sides in the drawing) is provided with a portion (gate electrode upper portion 23B) that protrudes and faces the surface of the semiconductor layer 11 via the interlayer insulating layer 12. As described above, the lower gate electrode 23A functions to control the on/off of the current, and the upper gate electrode 23B functions as a field plate. The lower part 23A of the gate electrode does not have to be in direct contact with the semiconductor layer 11 (AlGaN layer 11B), and it is possible to control the two-dimensional electron gas layer formed at the heterojunction interface between the non-doped GaN layer 11A and the AlGaN layer 11B. Other layers may be interposed between them as long as However, in any case, the lower gate electrode 23A is closest to the surface of the AlGaN layer 11B (semiconductor layer 11) in the gate electrode 23.

The left and right gate electrode upper portions 23B are provided with protrusions 100 that protrude downward. The protrusion 100 is covered with the interlayer insulating layer 12 around it. The height of the protrusion 100 (the height from the gate electrode upper portion 23B of the protrusion 100 toward the lower side (surface side of the semiconductor layer 11)) is set smaller than the thickness of the interlayer insulating layer 12. At a place where the protrusion 100 is present, the space between the gate electrode upper portion 23B, which serves as a field plate, and the semiconductor layer 11 is locally narrowed.

Peeling occurs between the gate electrode 23 and the interlayer insulating layer 12 due to the difference in thermal expansion between the metal material forming the gate electrode 23 and the insulator (SiO ₂ or the like) forming the interlayer insulating layer 12. This peeling is likely to occur particularly in the case of a structure in which the gate electrode upper portion 23B is provided so as to spread in the left-right direction so that the gate electrode 23 also functions as a field plate. On the other hand, in the configuration of FIG. 1, since the protrusion 100 functions as a wedge, this peeling can be suppressed. In particular, since the projection 100 can be embedded in the interlayer insulating layer 12 and the entire periphery of the projection 100 can be covered with the interlayer insulating layer 12 by the manufacturing method described later, this effect is enhanced.

2A to 2H are process cross-sectional views showing a method for manufacturing the structure of FIG. Here, only the peripheral structure including the gate electrode 23 is described as in FIG. 1, and the steps of forming the semiconductor layer 11, the source electrode 21, the drain electrode 22 and the like are the same as those well known.

First, as shown in FIG. 2A, a first interlayer insulating layer 12A forming a lower portion of the interlayer insulating layer 12 is formed on the semiconductor layer 11 (AlGaN layer 11B). The thickness of the first interlayer insulating layer 12A corresponds to the distance between the field plate (gate electrode upper portion 23B) and the semiconductor layer 11, and is set according to the characteristics of the MIS structure formed by the field plate. ..

Next, as shown in FIG. 2B, an opening (gate opening 12AA) corresponding to the gate electrode lower portion 23A is formed in the first interlayer insulating layer 12A. A gate electrode lower portion 23A is formed in the gate opening 12AA, and the gate electrode 23 controls ON/OFF of the two-dimensional electron gas layer at the heterojunction interface immediately below. The gate opening 12AA is formed by forming a mask (for example, a photoresist) on a portion other than the place to be the gate opening 12AA and dry etching the first interlayer insulating layer 12A (SiO ₂ ).

Next, as shown in FIG. 2C, a photoresist layer 300 having an opening only at a portion corresponding to the protrusion 100 is formed on the entire surface. Then, for example, the interlayer insulating layer 12A (SiO ₂ ) is slightly etched for a short time to form a recess 12AB on the surface of the first interlayer insulating layer 12A as shown in FIG. 2D. .. Unlike the gate opening 12AA in FIG. 2B, the recess 12AB may be formed by slightly digging the surface of the first interlayer insulating layer 12A (for example, about 100 nm). Therefore, this etching is performed by wet etching or dry etching. Either of them can be used, and the recess 12AB can be formed by determining the etching time.

Then, after removing the photoresist layer 300 as shown in FIG. 2E, the metal layer 400 forming the gate electrode 23 is filled in the gate opening 12AA and the recess 12AB as shown in FIG. 2F. Can be formed over the entire surface. After that, a mask is formed on a portion other than the portion to be the gate electrode 23, and the metal layer 400 is dry-etched, so that the protrusion 100 is provided on the gate electrode upper portion 23B as shown in FIG. 23 is formed.

Then, as shown in FIG. 2H, if the second interlayer insulating layer 12B, which is the upper portion of the interlayer insulating layer 12, is formed so as to cover the whole, the structure of FIG. 1 is obtained.

In this manufacturing method, since the protrusion 100 is formed corresponding to the recess 12AB formed in the first interlayer insulating layer 12A, the protrusion 100 is formed such that the periphery thereof is covered with the first interlayer insulating layer 12A. To be done. Therefore, the fixing strength between the gate electrode 23 and the first interlayer insulating layer 12A (interlayer insulating layer 12) by the protrusion 100 can be increased. Further, as described above, the depth of the recess 12AB (height of the protrusion 100) is set to be smaller than the thickness of the interlayer insulating layer 12, and the accuracy required for this depth is low, so the step of forming the recess 12AB. (FIG. 2d) can be easily performed.

The conventional semiconductor device 200 shown in FIG. 6 is manufactured in a process in which the processes of FIGS. 2C to 2E in FIG. 2 are omitted. On the other hand, since the step of forming the recess 12AB provided for manufacturing the semiconductor device 1 can be easily performed, the semiconductor device 1 can be easily manufactured after all. ..

A specific configuration of the gate electrode 23 in FIG. 1 is shown in FIG. Here, the description of the interlayer insulating layer 12 is omitted. The distance between the protrusion 100 on the left side (source electrode 21 side) and the lower gate electrode 23 in the horizontal plane is C1, and the distance between the protrusion 100 on the right side (drain electrode 22 side) and the lower gate electrode 23 is in the horizontal plane. C2, and C1=C2. The distance between the protrusion 100 and the semiconductor layer 11 (the thickness of the first interlayer insulating layer 12A in FIG. 2) is A, and the heights of the protrusions 100 are equal on the left and right sides. Therefore, this structure is bilaterally symmetrical (symmetrical on the source electrode 21 side and the drain electrode 22 side) when viewed from the center of the gate electrode 23. Here, the range of 2≦A/B≦30 is preferable. If A/B is less than 2, the effect of potential control by the field plate is too strong, and conversely the breakdown voltage decreases. When A/B exceeds 30, the wedge effect by the protrusion 100 becomes small.

FIG. 4 is a plan view showing the arrangement of the source electrode 21, the drain electrode 22, and the gate electrode 23 in this semiconductor device 100. In order to pass a large current between the source electrode 21 and the drain electrode 22, it is necessary to make the length of the source electrode 21 and the drain electrode 22 facing each other large within a limited area. Therefore, as described in Patent Document 1, the source electrode 21 and the drain electrode 22 which are both comb-shaped are interdigitated, and the gate electrode 23 is provided in a meandering shape between them.

In the configuration of FIG. 1, the gate electrode 23 has a symmetrical (horizontal symmetry) shape on the source electrode 21 side and the drain electrode 22 side. Such a configuration is particularly useful on either the source electrode 21 side or the drain electrode 22 side. It is preferable when stress is less likely to be generated unevenly (peeling occurs). The place where such a situation occurs is a place where the symmetry of the structure from the source electrode 21 side to the drain electrode 22 side is high, for example, the place of cross section AA in FIG.

On the other hand, in the locations of the cross section BB and the cross section C-C in FIG. 4, the degree of stress generation is asymmetric between the source electrode 21 and the drain electrode 22 side, and peeling is likely to occur in the source electrode. 21 or the drain electrode 22 on either side. The side on which peeling is likely to occur depends on the resin material used in the package and the conditions of its mounting process, but the top of the gate electrode on the side where peeling is likely to occur It is preferable that

FIG. 5 shows four examples showing the structure of the gate electrode having the asymmetric structure on the source electrode 21 side and the drain electrode 22 side as described above. In the gate electrode 43 of FIG. 5A, a gate electrode lower portion 43A and a left gate electrode upper portion 43B1 and a right gate electrode upper portion 43B2 are provided. Here, the protrusion 100 is provided only on the gate electrode upper portion 43B2, and the protrusion 100 is not provided on the electrode upper portion 43B1. As a result, peeling on the gate electrode upper portion 43B2 side can be suppressed. Similarly, in the gate electrode 53 of FIG. 5B, the left side gate electrode upper portion 53B1 side protrusion 100 is one and the right side gate electrode upper portion 53B2 side protrusion 100 is 3 The peeling on the upper portion 53B2 side is particularly suppressed. Alternatively, the right gate electrode upper portion 53B2 is made longer than the left gate electrode upper portion 52B1 to have an asymmetrical structure, so that the effect as a field plate on the right side is made larger than that on the left side. Since the drain electrode 22 side has a higher potential than the source electrode 21 side and the electric field strength increases in the semiconductor layer 11, it is preferable to set the right side to the drain electrode 22 side in FIG. 5B.

Further, in FIG. 5B, in the cross-sectional view along the current flow direction, the number of the protrusions 100 is different between the left and right (source electrode 21 side and drain electrode 22 side), and the cross-sectional view along the current flow direction is shown. In, the three protruding portions 100 are provided at intervals on the gate electrode upper portion 53B2 side. However, since the upper part 53B2 of the gate electrode actually extends in the direction perpendicular to the paper surface of FIG. 5B, a plurality of protrusions 100 are arranged at intervals along the direction perpendicular to the paper surface (direction perpendicular to the current flow). It may be provided.

FIG. 5C shows a configuration in which the width of the protrusion 101 on the left side gate electrode upper portion 63B1 side and the width of the protrusion portion 102 on the right side gate electrode upper portion 63B2 side are changed in the horizontal direction. In this case, not only the resistance to peeling, but also the effect of the field plate on the right side gate electrode upper portion 63B2 side becomes particularly high. Further, the structure of FIGS. 5A to 5C can be manufactured in the same manner as the structure of FIG. 1 by the manufacturing method of FIG. 2 only by changing the pattern of the photoresist layer 200 in FIG. 2C. ..

On the other hand, in FIG. 5D, the depth B1 of the protrusion 103 on the left side gate electrode upper portion 73B1 side and the depth B2 of the protrusion 104 on the right side gate electrode upper portion 73B2 side are set so that B1<B2. The changed configuration is shown. Also in this case, not only the resistance to peeling, but also the effect of the field plate on the right side gate electrode upper portion 73B2 side becomes particularly high. In this case, in the manufacturing method of FIG. 2, although it is necessary to manufacture the concave portion corresponding to the protruding portion 103 and the concave portion corresponding to the protruding portion 104 in separate steps, it is possible to suppress peeling at the electrode upper portion 73B2 on the right side. It is possible to particularly enhance the effect.

In addition, the number, size, and shape of the protrusions can be appropriately set as long as the protrusions can be embedded in the interlayer insulating layer. At this time, the number, size, and shape of the protrusions can be set in consideration of the resistance to peeling and the effect as a field plate (the degree of control of the surface potential with respect to the semiconductor layer).

Further, in the above-mentioned structure, the upper part of the gate electrode is used as the field plate, but the field electrode structure having the above-mentioned protrusion may be provided in the source electrode. Further, the same structure as the above can be provided also in the field plate which is formed separately from the gate electrode and the source electrode and is electrically connected to these materials.

Further, the semiconductor device described above is a HEMT using GaN or the like (group III nitride semiconductor), but a current flows between the first main electrode and the second main electrode provided on one surface of the semiconductor layer. The field plate as described above is effective as long as it is an element to be swept. At this time, since the field plate has a configuration that spreads in a plane and peeling easily occurs, the above structure is effective. That is, the above structure is also effective in semiconductor devices other than HEMTs.

1,200 Semiconductor device (HEMT)
10 substrate 11 semiconductor layer 11A non-doped GaN layer 11B AlGaN layers 12 and 112 interlayer insulating layer 12A first interlayer insulating layer 12AA gate opening 12AB recess 12B second interlayer insulating layer 21 source electrode (first main electrode)
22 Drain electrode (second main electrode)
23, 43, 53, 63, 73, 123 Gate electrode (control electrode)
23A, 43A, 53A, 63A, 73A, 123A Lower gate electrode 23B, 43B1, 43B2, 53B1, 53B2, 63B1, 63B2, 73B1, 73B2, 123B Upper gate electrode (field plate)
31 Source Wiring 32 Drain Wirings 100 to 104 Protrusions 300 Photoresist Layer 400 Metal Layer

Claims (8)

A field-effect transistor including a first main electrode to be a source electrode, a second main electrode to be a drain electrode, and a control electrode to be a gate electrode for controlling on/off of a current flowing between the source electrode and the drain electrode. , and the opposite to the surface via the interlayer insulating layer at said upper surface between the both provided with the first main electrode and the second main electrode on the side of the surface as the one main surface of the semiconductor layer A semiconductor device comprising a field plate which is an electrode provided as
The field plate is provided integrally with the control electrode,
In a portion of the field plate that faces the surface, a protrusion that locally protrudes toward the surface and is covered with the interlayer insulating layer is formed,
The portion of the field plate facing the surface is provided on each of the first main electrode side and the second main electrode side as viewed from the portion where the control electrode is closest to the surface,
The protrusions are provided on portions of the field plate on the first main electrode side and the second main electrode side that face the surface, respectively.
In a sectional view perpendicular to the surface along the direction in which the current flows,
Wherein a plurality of the projections on the surface facing the portion of the field plate of the first main electrode side or the second main electrode side is provided. In a sectional view perpendicular to the surface along the direction in which the current flows,
2. The semiconductor device according to claim 1, wherein the number of the protrusions provided on the first main electrode side and the second main electrode side of the field plate facing the surface is different. In a sectional view perpendicular to the surface along the direction in which the current flows,
The number of the protrusions provided on a portion of the field plate facing the surface on the second main electrode side is the same as the number of protrusions provided on a portion of the field plate facing the surface on the first main electrode side. The semiconductor device according to claim 1, wherein the number of protrusions is greater than the number of protrusions. A field-effect transistor including a first main electrode to be a source electrode, a second main electrode to be a drain electrode, and a control electrode to be a gate electrode for controlling on/off of a current flowing between the source electrode and the drain electrode. , and the opposite to the surface via the interlayer insulating layer at said upper surface between the both provided with the first main electrode and the second main electrode on the side of the surface as the one main surface of the semiconductor layer A semiconductor device comprising a field plate which is an electrode provided as
The field plate is provided integrally with the control electrode,
In a portion of the field plate that faces the surface, a protrusion that locally protrudes toward the surface and is covered with the interlayer insulating layer is formed,
The portion of the field plate facing the surface is provided on each of the first main electrode side and the second main electrode side as viewed from the portion where the control electrode is closest to the surface,
The protrusions are provided on portions of the field plate on the first main electrode side and the second main electrode side that face the surface, respectively.
In a sectional view perpendicular to the surface along the direction in which the current flows,
Wherein a said first main electrode side, the width of said protrusion provided on the portion facing the surface of the second main electrode side said field plate is different. The semiconductor device according to claim 4, wherein the width of the protrusion is increased on the second main electrode side. A field-effect transistor including a first main electrode to be a source electrode, a second main electrode to be a drain electrode, and a control electrode to be a gate electrode for controlling on/off of a current flowing between the source electrode and the drain electrode. , and the opposite to the surface via the interlayer insulating layer at said upper surface between the both provided with the first main electrode and the second main electrode on the side of the surface as the one main surface of the semiconductor layer A semiconductor device comprising a field plate which is an electrode provided as
The field plate is provided integrally with the control electrode,
In a portion of the field plate that faces the surface, a protrusion that locally protrudes toward the surface and is covered with the interlayer insulating layer is formed,
The portion of the field plate facing the surface is provided on each of the first main electrode side and the second main electrode side as viewed from the portion where the control electrode is closest to the surface,
The protrusions are provided on portions of the field plate on the first main electrode side and the second main electrode side that face the surface, respectively.
In a sectional view perpendicular to the surface along the direction in which the current flows,
Wherein a said first main electrode side, the height of said projections provided on the surface facing the portion of the second main electrode side said field plate is different. 7. The semiconductor device according to claim 6, wherein the height of the protrusion is increased on the second main electrode side. 8. The semiconductor device according to claim 1, wherein the semiconductor layer includes a group III nitride semiconductor heterojunction, and the current flows through the heterojunction interface.

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