JP6699598B2 - Vehicle control device - Google Patents

Description

  The present invention relates to a vehicle control device.

  Some vehicle control devices manage data in a non-volatile memory typified by a flash memory, and separately manage a data area in the non-volatile memory into a data management unit and a data storage unit. This is for performing data management by writing actual data in the data storage unit and writing a value indicating whether or not the data is written in the data management unit.

  In this case, for example, in the process of writing the program data to the flash memory by reprogramming or the like, first, an unused area of the data storage unit is searched from the data stored in the data management unit, and the found data storage unit is not used. Data is written to the area. Then, after the data writing is completed, a value indicating that the data has been written is written in the data management unit.

  In such a technique, when the power is cut off during data writing, the data storage unit has written the data up to the time before the power cut, but the data management unit is in a state indicating an unused area. Therefore, when data is written again after the power is restored, the state of the data management unit and the state of the data storage unit do not match, and there is a problem that the data is written twice in the same region of the data storage unit.

  In general, in a non-volatile memory, the erase unit size is larger than the write unit size, so the data management unit is set in the erase unit size. Therefore, the data management unit is erased at the time of writing data to the data storage unit, and when the data is normally written, the data management unit is written.

  Therefore, by arranging the management data of a plurality of data storage units in the data management unit, even if each data storage unit performs one erasing operation, the data management unit can perform the erasing operation every time data is written in the plurality of data storage units. Will be done.

  As a result, the number of times of writing in the data management unit becomes larger than the number of times of writing in the data storage unit, and the number of times that the data management unit can be rewritten is reached first.

JP, 2005-62981, A

  The present invention has been made in view of the above circumstances, and an object thereof is to reduce the erasing operation of the data management unit accompanying the writing of data to the data storage unit, and to use rewritable nonvolatile memory. It is an object of the present invention to provide a vehicle control device capable of suppressing the number of times.

The vehicle control device according to claim 1, wherein the rewritable nonvolatile memory includes a data storage unit that stores data for controlling the vehicle and a data management unit that indicates whether or not the data has been normally written in the data storage unit. Non-volatile memory and a control circuit for writing data to the non-volatile memory, wherein the control circuit is an unused part of the data management section at the time of writing/updating data to the data storage section of the non-volatile memory. Adopting a method of additionally writing update information in the area, additionally writing data in a state indicating that data is being written at the start of the data writing update, and additionally writing a state indicating that data has been written at the end of the data writing update , and the nonvolatile memory Adopting a list structure as a method of additionally writing update information to an unused area of the data management unit at the time of updating the data write to the data storage unit, and additionally writing the next write address at the start of the data write update to write the data A state indicating that data has been written is added at the end of updating .

  By adopting the above configuration, the control circuit adopts a method of additionally writing the update information to the unused area of the data management section when the data is written and updated in the data storage section of the nonvolatile memory, and the data is updated at the start of the data writing and update. The data indicating the state of being written is added, and the state indicating that the data has been written is added at the end of the data write update. As a result, in the normal data writing process, the block of data is not erased each time the update information is written to the data management unit. Further, even if the power is cut off during writing, when the data is written by turning on the power again, the control circuit does not erase the block of the data management section, which increases the number of times of rewriting of the nonvolatile memory. Can be suppressed.

Block diagram showing the first embodiment Diagram showing the process flow when the power is turned on The figure which shows the flow of program start decision processing Diagram showing the flow of program write processing Illustration of data area of flash memory Change diagram of program writing process (Part 1) Change diagram of program writing process (Part 2) The figure which shows the flow of the program start determination process which shows 2nd Embodiment. Diagram showing the flow of program write processing Illustration of data area of flash memory Change diagram of state of program writing process (1) Change diagram of program writing process (Part 2) The figure which shows the flow of the process at the time of power supply ON which shows 3rd Embodiment Illustration of data area of flash memory

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 shows a schematic block configuration. A vehicle control device 1 is provided in a vehicle and controls other devices (not shown). The vehicle control device 1 mainly includes a control circuit 2 such as a CPU (central processing unit), a communication unit 3, a RAM (random access memory) 4, a flash memory 5 that is a non-volatile memory, and the like. The flash memory 5 is set as an internal storage area in which the data storage section 5a and the data management section 5b are divided.

  The control circuit 2 transmits/receives data to/from an externally provided data transmission/reception device 10 via the communication unit 3 and controls writing to the flash memory 5. The vehicle control device 1 takes in reprogramming data from the outside via the data transmitting/receiving device 10, and rewrites the data in the flash memory 5, for example. At this time, the control circuit 2 controls the writing process to the flash memory 5 based on a program described later.

Next, the operation of the above configuration will be described with reference to FIGS. 2 to 7.
FIG. 2 shows the processing contents executed by the control circuit 2 when the power is turned on. When the power is turned on, the control circuit 2 first executes a program start determination process in step A1. FIG. 3 shows the specific contents of the program activation determination processing in step A1. The control circuit 2 sets the write position of the flash memory 5 to the head of the data management unit 5a in step B1. Next, in step B2, the control circuit 2 confirms whether or not "writing" in the writing position is blank. In step B2, the control circuit 2 determines YES if the "writing in progress" data is blank, determines the writing position, and ends the program activation determination process.

  In step B2, if the data "writing" is other than blank, that is, the judgment value is written, the control circuit 2 judges NO in step B2, proceeds to step B3, and moves the writing position to the next position. Set to the writing position. After that, the control circuit 2 returns to step B2 to determine whether or not the next writing position "writing" is blank, and repeatedly executes steps B2 and B3 until YES.

  When the program activation determination process is completed as described above, the control circuit 2 returns to the process when the power is turned on in FIG. 2 and proceeds to step A2. The control circuit 2 determines in step A2 whether the application can be started. Specifically, when "write complete" at the write position is equal to the determination value, it is determined that the application can be started. Here, if the application can be started, the control circuit 2 determines YES and proceeds to step A3 to execute the main processing in the application. At this time, the control circuit 2 executes the application in step A3 and checks in step A4 whether or not there is an external reprogramming instruction, that is, a program write instruction.

  The control circuit 2 executes steps A3 and A4 to determine YES in step A4 when a program write instruction is issued from the outside while executing the main processing of the application, and proceeds to step A5 to write the program. Execute the process.

  In the above case, the program write instruction from the outside means that a user or the like issues an instruction to write the program from the external data transmitter/receiver 10, and is taken into the control circuit 2 via the communication unit 3.

  When the application is not ready to be started in step A2, the control circuit 2 determines NO and moves to step A6. In step A6, the control circuit 2 stands by until there is a program write instruction from the outside, and if there is a program write instruction, the control circuit 2 determines YES and proceeds to step A5 to execute the program write processing.

  Next, the program writing process described above will be described with reference to FIGS. 4 and 5. FIG. 4 shows a specific flow of the program write processing in step A5 described above. Further, FIG. 5 shows blocks corresponding to addresses inside the flash memory 5.

  First, in FIG. 5, the data storage unit 5a of the flash memory 5 is set corresponding to the area of addresses 0000 0000 to EFFF FFFF, and the data management unit 5b is set corresponding to the area of addresses F0000 to FFFF FFFF. ing. Here, the size of the data management unit 5b corresponds to one block which is the minimum unit of data erasing in the flash memory 5.

  The data management unit 5b is composed of data "writing state n" indicating the writing state. The data indicating the "writing state n" is, for example, 4-byte data "writing" indicating whether the data storage unit 5a is writing, and the 4-byte data "indicating whether the data storage unit 5a has completed writing. It is composed of a pair of "writing completed".

  In addition, in the illustrated example, the size of the “write state n” is shown to be configured with a data length of 8 bytes, but the size and arrangement of the data storage unit 5a and the data management unit 5b are not limited to this. Can be set arbitrarily. Further, the address of the "writing state n" can be set differently from the above setting.

  In this embodiment, as shown in FIG. 5, every time the program writing process to the data storage unit 5a is executed, the data management unit 5b switches from the head address "F000 0000" to "write state 1". The data is written, and subsequently, "write state 2"... Is additionally written at the next address. Then, the data of the "writing state n" is written at the writing position where the writing is performed last.

  Next, the flow of the program writing process will be described with reference to FIG. Since the control circuit 2 has previously executed the program activation determination process of FIG. 3, the write position of the data management unit 5b of the flash memory 5 is fixed. The control circuit 2 first confirms in step C1 whether the data management unit 5b is full. That is, when the write position of the data management unit 5b corresponds to the end of the address, the control circuit 2 is in a full state in which writing cannot be performed as it is.

  Here, when the data management unit 5b is full, the control circuit 2 determines YES in step C1, proceeds to step C2, and erases all the data in the data management unit 5b. Then, in the subsequent step C3, the control circuit 2 sets the writing position at the head of the data management unit 5b.

  In step C1 described above, the "full state" refers to the state of the "1" area in which the "writing" blank area remains in the data management unit 5b. This is because if the "full state" is defined as a blank remaining "0" area, an infinite loop will be formed in step A1 of the program start determination process at the time of power-off and power-on after the completion of program writing. The remaining "1" area is defined to avoid a loop.

  After that, the control circuit 2 proceeds to step C4 to write the determination value in "writing" at the writing position. If the data management unit 5b is not full, the control circuit 2 determines NO in step C1, jumps to step C4, and writes the determination value in the "writing" position at the write position.

  After that, the control circuit 2 proceeds to step C5, erases the data in the area to be written in the data storage unit 5a, and in the next step C6, the data of the program fetched from the outside via the communication unit 3 is converted into data. A process of writing data in the storage unit 5a is executed. Subsequently, in step C7, the control circuit 2 writes the determination value in the "writing complete" of the writing position of the data management unit 5b, and ends the program writing process.

  As described above, after the power is turned on, the operation by the control circuit 2 when the program write instruction is given from the outside is executed. 6 and 7 show specific examples in the case where the above program writing process is executed. In this specific example, the case where the writing state of the data management unit 5b in the flash memory 5 is not executed and the leading address "F000 0000" is blank will be described.

  First, FIG. 6 shows a state of the data management unit 5b when the program writing in the data storage unit 5a is normally completed in the flash memory 5. In the state before the start of the program writing, the control circuit 2 executes the program activation determination processing, and the result is YES because "writing in progress" at the writing position is blank in step B2, and is shown in FIG. 6A. Thus, the address “F00000000” is the writing position.

  In this state, as shown in FIG. 6B, the control circuit 2 executes step C4 to write the determination value to the “writing in progress” at the write position address “F000 0000” at the start of writing. This indicates that the program data is currently being written to the data storage unit 5a.

  After this, when the control circuit 2 executes steps C5 and C6 to complete the program write processing, as shown in FIG. 6C, in step C7, the write position address “F000 0000” “write complete” is completed. The process of writing the judgment value into "" is performed. As a result, the fact that the program writing process has been executed and the writing process has been completed normally is recorded in the data management unit 5b.

  Next, with reference to FIG. 7, a state of the data management unit when the power supply is cut off during program writing and the program writing is executed again will be described. In the state before the start of the program writing, the program start determination process is executed, and the result of step B2 is YES because "writing in progress" at the writing position is blank. As a result, the control circuit 2 sets the address “F000 0000” as the write position, as shown in FIG.

  In this state, as shown in FIG. 7B, the control circuit 2 executes step C4 to write the determination value to the “writing in progress” at the write position address “F000 0000” at the start of writing. This indicates that the program data is currently being written to the data storage unit 5a.

  Then, as described above, the control circuit 2 executes steps C5 and C6 to execute the program writing process in the data storage unit 5a of the flash memory 5. Then, if the power is cut off during the execution of the program writing process, the "writing complete" at the writing position of the data management unit 5b remains blank.

  Then, when the power is turned on again, the control circuit 2 carries out the processing at the time of turning on the power in the same manner as described above, and carries out the program start determination processing of step A1. Here, when the control circuit 2 proceeds from step B1 to step B2, the control circuit 2 determines that the power supply is cut off before the program writing process is completed before the previous program writing process, and thus determines NO.

  That is, as shown in FIG. 7C, the judgment value is written in the “writing in progress” of the address “F00000000” at the writing position, so that the state is not blank. Therefore, the control circuit 2 determines NO in step B2 and proceeds to step B3. Here, the control circuit 2 sets the writing position to the address "F000 0008" which is the next writing position.

  When the control circuit 2 returns to step B2, the address "F00000008", which is newly set as the write position, is "blank", so that the address is set as the write position. After that, the control circuit 2 executes step C4 at the start of writing the program, and writes the determination value in the “writing in progress” at the address “F000 0008” at the writing position, as shown in FIG. 7D.

  Then, when the control circuit 2 executes steps C5 and C6 to complete the program writing process, as shown in FIG. 7E, in step C7, the write position address “F000 0008” “write complete” is completed. The process of writing the judgment value to is performed. As a result, it is recorded in the data management unit 5b that the writing process of the program is executed and the writing process is normally completed after the power is cut off.

  According to the present embodiment as described above, the control circuit 2 sets “writing in progress” as the determination value to the address of the write position of the data management unit 5b at the start of writing the program to the data storage unit 5a of the flash memory 5. I decided to do it.

  As a result, even if the power is cut off during the writing of the program, the data at the writing position of the data management unit 5b is not erased and rewritten, but is set by newly writing during writing of the writing position. By writing, the program writing can be completed normally even after the power failure during the program writing.

  As a result, the block erasing of the data management unit 5b is not performed every time the program writing process is executed, and the number of rewritings of the flash memory 5 can be significantly reduced and the life of the flash memory 5 can be extended.

(Second embodiment)
FIG. 8 to FIG. 12 show the second embodiment, and the portions different from the first embodiment will be described below. In this embodiment, the method of writing processing to the data management unit 5b of the flash memory 5 by the control circuit 2 is changed. While the method of the first embodiment is the “non-list structure”, the “list structure” is adopted in this embodiment.

  In this embodiment, as shown in FIG. 10, the data management unit 5b of the flash memory 5 has a “list structure” configured by data “write state n” indicating the write state. The data indicating the write state is composed of a pair of, for example, 4-byte data “write complete” indicating whether the write to the data storage unit 5a is completed and a “write address” that is an address to the next write state. It

  Also in this embodiment, it is assumed that the address and size in the written state are composed of arbitrary addresses and data lengths, and the size and arrangement of the data storage unit 5a and the data management unit 5b can be set arbitrarily. Note that, in FIG. 10, the "write address" of the "write state n" is set to be continuously set, but as described above, it is not always necessary to set continuously, and the blank is set according to an arbitrary setting condition. A "write address" can be set at any write position.

Next, differences in processing contents by the control circuit 2 in this embodiment will be described.
In FIG. 8 showing the flow of the program start determination process, the control circuit 2 determines whether or not the “write address” of the write position is blank as step B2a instead of step B2.

  In this case, in step B1, the write position to be set first is the start position of the data management unit 5b, that is, the address "F000 0000", so if the "write address" of this address is not set, the write position It can be set as a position.

  In step B2a, if the "write address" is set, that is, if it is not blank, the control circuit 2 moves to step B3a and sets the write position set in the "write address". Hereinafter, the control circuit 2 can determine that the write position of the “write address” set at the last write position is in the blank state by tracing the “write address” of the write position in sequence.

  In FIG. 9 showing the flow of the program writing process, the control circuit 2 executes the process in the same manner as in the first embodiment, but in step C4, instead of this, steps C4a and C4b are executed. In step C4a, the control circuit 2 writes the address indicating the next write position in the "write address" of the current write position. As a result, the state in which the writing process is being performed is indicated, and the state is equivalent to the “judgment value” in the first embodiment. In step C4b, the control circuit 2 sets the current write position to the address written in step C4a.

  11 and 12 show a specific example of the case where the above program writing process is executed. In this specific example, the case where the write state of the data management unit 5b in the flash memory 5 is not executed and the leading address "F000 0000" is blank will be described.

  First, FIG. 11 shows a state of the data management unit 5b when the program writing in the data storage unit 5a is normally completed in the flash memory 5. In the state before the start of the program writing, the control circuit 2 executes the program activation determination process of FIG. As a result, the control circuit 2 determines YES in step B2a because the "write address" of the write position is blank, and determines that the address "F000 0000" is the write position, as shown in FIG. 11(a). it can.

  In this state, as shown in FIG. 11B, the control circuit 2 executes step C4a in FIG. 9 to set the next write address to the “write address” of the write position address “F000 0000” at the start of writing. Write. This indicates that the program data is currently being written to the data storage unit 5a. Next, the control circuit 2 executes step C4b to update the write position.

  After this, when the control circuit 2 executes steps C5 and C6 to complete the program write processing, as shown in FIG. 11(c), in step C7, the write position address “F000 0008” “write complete” is completed. The process of writing the judgment value into "" is performed. As a result, the fact that the program writing process has been executed and the writing process has been completed normally is recorded in the data management unit 5b.

  Next, with reference to FIG. 12, a state of the data management unit when the power supply is cut off during the program writing and the program writing is executed again will be described. In the state before the program writing is started, the program start determination process is executed, and the result is YES because the "write address" of the write position is blank in step B2a. As a result, the control circuit 2 sets the address “F000 0000” as the write position, as shown in FIG.

  In this state, as shown in FIG. 12B, the control circuit 2 executes step C4a to write the next “write address” to the “write address” of the write position address “F00000000” at the start of writing. .. This indicates that the program data is currently being written to the data storage unit 5a. Next, the control circuit 2 executes step C4b to update the write position.

  Then, as described above, the control circuit 2 executes steps C5 and C6 to execute the program writing process in the data storage unit 5a of the flash memory 5. Then, if the power is cut off during the execution of the program writing process, the "writing complete" at the writing position of the data management unit 5b remains blank.

  Then, when the power is turned on again, the control circuit 2 carries out the processing at the time of turning on the power in the same manner as described above, and carries out the program start determination processing of step A1. Here, when the control circuit 2 proceeds from step B1 to B2a, the control circuit 2 determines that the power is cut off during the previous program writing process before the program writing process is completed, and thus determines NO.

  That is, as shown in FIG. 12C, since the next write address is written in the “write address” of the write position address “F0000 0000”, the state is not blank. Therefore, the control circuit 2 determines NO in step B2a, and proceeds to step B3a. Here, the control circuit 2 sets the write position to the address “F000 0008” which is the write position set by the next “write address”.

  When the control circuit 2 returns to step B2a, the "write address" of the address "F00000008" that has been newly set as the write position is blank, so this address is set as the write position. After that, the control circuit 2 executes step C4a at the start of writing the program, and as shown in FIG. 12D, the address to write next to the "write address" of the address "F000 0008" at the write position. Write. Next, the control circuit 2 executes step C4b to update the write position.

  Then, when the program writing process is completed by executing steps C5 and C6, the control circuit 2 at step C7, as shown in FIG. 12(e), "write complete" at the address "F000 0010" at the write position. The process of writing the judgment value to is performed. As a result, it is recorded in the data management unit 5b that the writing process of the program is executed and the writing process is normally completed after the power is cut off.

According to the present embodiment as described above, the same effect as that of the first embodiment can be obtained.
Further, according to the present embodiment, by adopting the “list structure” for the address setting of the write position in the data management unit 5b, it is possible to set the write position of the data so as to be dispersed evenly within the block. it can. As a result, it is possible to further reduce the number of times of rewriting of the flash memory 5 and prolong the life of the flash memory 5.

  In the above embodiment, the "write address" of the "write state n" of the data management unit 5b is sequentially designated as the next address, but the present invention is not limited to this, and any address can be set. .. For example, by setting the next write address under a certain condition, the address in the data management unit 5b can be used evenly, and can be used without partially increasing the number of rewrites. You can also

(Third Embodiment)
FIG. 13 and FIG. 14 show the third embodiment, and the portions different from the first embodiment will be described below. In this embodiment, the setting of the area of the flash memory 20 is applied when a plurality of data storage units 20a and 20b and a plurality of data management units 20c and 20d are provided.

  FIG. 14 shows the data area division of the flash memory 20. The two data storage units 20a and 20b are provided as an application data storage unit 20a and a calibration data storage unit 20b. The application data storage unit 20a is set in the range of addresses "0000 0000" to "BFFF FFFF", and the calibration data storage unit 20b is set in the range of addresses "C000 0000" to "EFFF FFFF".

  Here, the application and the calibration are stored separately because, for example, the control program is an application and is suitable for setting only the calibration data differently according to the vehicle type and the control content. Is. By separately providing the calibration data in this way, there is an advantage that the application can be provided in a generalized state.

  The two data management units 20c and 20d are provided as an application data management unit 20c and a calibration data management unit 20d. The application/data management unit 20c is set in the range of addresses “F000 0000” to “F7FF FFFF”, and the calibration/data management unit 20d is set in the range of addresses “F800 0000” to “FFFF FFFF”.

  The above-mentioned data area is configured such that the application data storage unit 20a is managed by the application data management unit 20c and the calibration data storage unit 20b is managed by the calibration data management unit 20d. Can be rewritten.

  FIG. 13 shows a process executed by the control circuit 2 when the power is turned on in the case of the above configuration. In step A10, the control circuit 2 starts the loop 1 corresponding to the two data management units 20c and 20d provided in the flash memory 5. In this loop 1, the control circuit 2 executes the program activation determination process shown in FIG. 3 in step A11 to determine the write position. At the subsequent step A12, the control circuit 2 determines whether the application can be started.

  The control circuit 2 returns to step A11 in order to repeat loop 1 in step A13 when the application can be started for the first data management section 20c and there is the next data management section 20d, and the next data management is performed. The process is executed for the unit 20d. Then, when the search of all the data management units 20c and 20d is completed, the control circuit 2 executes the main processing in the application in step A14. At this time, the control circuit 2 executes the application in step A14, and checks in step A15 whether or not there is an external program write instruction.

  The control circuit 2 repeatedly executes steps A14 and A15, and while executing the main processing of the application, if there is a program write instruction from the outside, the control circuit 2 determines YES in step A15, proceeds to step A16, and executes the program. The loop 2 (steps A16 to A18) of the writing process is executed.

  If the application is not ready to be activated in step A12, the control circuit 2 makes a negative decision and proceeds to step A19. In step A19, the control circuit 2 stands by until there is a program write instruction from the outside, and if there is a program write instruction, the control circuit 2 determines YES and proceeds to step A16 to execute loop 2 of the program write processing.

  In loop 2 of the program writing process, the control circuit 2 carries out the program writing process of step A17. In this case, the control circuit 2 executes the program write processing of the loop 2 for the number of program write instructions received in step A15, and when these are completed, the processing at power-on is ended (end).

  Further, even when the program writing process as described above is executed, if the power is cut during the writing process, the power-on process is executed as in the first embodiment. By doing so, the data at the writing position of the data management unit 20c or 20d is not block-erased and rewritten, but it is set by additionally writing that the writing position is newly written. Program writing can be completed normally even after power failure.

As a result, it is not necessary to erase the block of the data management unit 20c or 20d each time the program writing process is executed, and the number of times of rewriting of the flash memory 20 can be greatly reduced to prolong the service life.
Further, according to the present embodiment, since only the calibration data can be rewritten separately, there is an advantage that the writing process can be performed in a short time.

(Other embodiments)
The present invention is not limited to the above-described embodiments, but can be applied to various embodiments without departing from the scope of the invention, and can be modified or expanded as follows, for example.

  In the first and second embodiments described above, the case of the program writing process is described as the data writing process, but the data writing process may be performed in order to rewrite only the data included in the program. In this case, for example, the data portion can be set as a previously designated area. Further, only the difference between the program written in the flash memory and the program containing the data to be rewritten can be rewritten.

  The non-volatile memory can be applied to a case where a non-volatile memory such as an EEPROM (Electrically Erasable Programmable Read-Only Memory) other than the flash memory is used.

  As a method of writing the rewrite data in the data management unit of the non-volatile memory, in addition to the method shown in the first and second embodiments, another method may be adopted as long as it is a method of additionally writing each time rewriting. You can

  In the third embodiment, an example in which two data storage units 20a and 20b are set in the flash memory 20 has been shown, but the present invention can be applied to the case where three or more data storage units are set.

  Although the present disclosure has been described with reference to examples, it is understood that the present disclosure is not limited to the examples and structures. The present disclosure also includes various modifications and modifications within an equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more, or less than those, also fall within the scope and spirit of the present disclosure.

  In the drawings, 1 is a vehicle control device, 2 is a control circuit, 3 is a communication unit, 5 and 20 are flash memories (nonvolatile memories), 5a, 20a and 20b are data storage units, 5b, 20c and 20d are data management units. Reference numeral 10 is a data transmission/reception device.

Claims (4)

A rewritable non-volatile memory having a data storage unit in which data for controlling a vehicle is stored and a data management unit indicating whether or not data has been normally written in the data storage unit,
A control circuit for writing data to the nonvolatile memory,
The control circuit employs a method of additionally writing update information to an unused area of the data management unit at the time of updating data writing to the data storage unit of the nonvolatile memory, and indicates that data is being written at the start of the data writing update. State data is added, and a state indicating that data has been written is added at the end of the data write update, and update information is written to an unused area of the data management unit when the data is written to the data storage unit of the nonvolatile memory and updated. A vehicle control device that adopts a list structure as a method of additional writing, additionally writes the next write address at the start of the data write update, and additionally writes a state indicating that data has been written at the end of the data write update . When the power is turned on, the control circuit searches for a write position from the start address of the data management unit of the nonvolatile memory, determines a valid write state, and normally writes data to the data storage unit from the write state. The vehicle control device according to claim 1 , wherein the vehicle control device determines that the fact is satisfied. The control circuit erases the data of the data management unit when the used area of the data management unit is full when writing data to the data storage unit of the nonvolatile memory. Alternatively, the vehicle control device according to item 2 . The vehicle control device according to any one of claims 1 to 3 , wherein the control circuit sets a plurality of the data management units when a plurality of the data storage units is set in the nonvolatile memory.

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