JP6699182B2 - Semiconductor laser and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor laser and a manufacturing method thereof, and more particularly to a semiconductor laser suitable for use in the field of optical communication and a manufacturing method thereof.

  Patent Documents 1 to 3 disclose semiconductor lasers having a mesa portion. The semiconductor laser disclosed in Patent Document 1 includes a crystal growth layer on the surface of the substrate below the bonding pad and at the mesa portion.

JP-A-3-263388 JP 2001-94211 A JP 2004-363147 A

  The crystal growth layer generates stress that warps the substrate. For this reason, in the semiconductor laser provided with the crystal growth layer, the warp of the substrate may occur.

The present invention has been made to solve the above problems, and a first object of the present invention is to obtain a semiconductor laser having a mesa portion that can suppress the warp of the substrate.
The second object is to obtain a method for manufacturing a semiconductor laser capable of suppressing the warp of the substrate.

  What is claimed is: 1. A semiconductor laser comprising a structure including a first-type substrate that is one of an N-type and a P-type, and a mesa portion that is disposed on the surface of the substrate and that includes a crystal growth layer. One side of the mesa portion is a first exposed portion where the substrate is exposed over the entire area, and the other side of the mesa portion of the structure is formed at a position adjacent to the mesa portion and the substrate is exposed. An insulating layer having a second exposed portion that is in a closed state, the semiconductor laser covering the structure, and having an opening on the upper surface of the mesa portion, and the mesa portion on the surface of the insulating layer. A second-type electrode that is the other of the N-type and P-type and is provided so as to cover a continuous region including defined regions on both sides of the mesa portion and to be in contact with the crystal growth layer in the opening; A surface plating layer arranged on the surface of the mold electrode so as to cover the continuous region, a first type electrode arranged on the back surface of the structure, and a back surface arranged on the back surface of the first type electrode. A plating layer, and the front surface plating layer and the back surface plating layer have a thickness that suppresses warpage of the substrate.

  Forming a crystal growth layer on the surface of a first type substrate which is one of N-type and P-type; etching the crystal growth layer to form the mesa portion and the substrate over the entire region on one side of the mesa portion; Forming a first exposed portion that exposes the substrate and a second exposed portion that exposes the substrate at a position adjacent to the mesa portion on the other side of the mesa portion; Forming an insulating layer so as to cover the substrate; forming an opening in the insulating layer on the upper surface of the mesa; and forming a surface of the insulating layer on both sides of the mesa and the mesa. Forming a second type electrode, which is the other of the N type and the P type, so as to cover the continuous region including the prescribed region, and surface plating the surface of the second type electrode so as to cover the continuous region. A surface plating layer forming step of forming a layer, a step of forming a first type electrode on the back surface of the substrate, and a back surface plating layer forming step of forming a back surface plating layer on the lower surface of the first type electrode. The front surface plating layer and the back surface plating layer are formed to have a thickness that suppresses warpage of the substrate.

  In the semiconductor laser according to the present invention, the crystal growth layer is removed over the entire area of at least one side of the mesa portion. Therefore, the stress received by the substrate from the crystal growth layer is reduced. At this time, the ratio of the stress applied to the substrate by the front surface plating layer and the back surface plating layer is large among the stresses applied to the substrate. The front surface plating layer and the back surface plating layer give opposite stresses to the substrate. In the present invention, the thicknesses of the front surface plating layer and the back surface plating layer are adjusted so as to suppress the warp of the substrate. Therefore, according to the present invention, a semiconductor laser with a small warp can be obtained.

  Further, the method for manufacturing a semiconductor laser according to the present invention includes a step of etching the crystal growth layer on at least one side of the mesa portion. Therefore, the crystal growth layer becomes smaller, and the stress received by the substrate from the crystal growth layer is reduced. At this time, the ratio of the stress applied to the substrate by the front surface plating layer and the back surface plating layer is large among the stresses applied to the substrate. The front surface plating layer and the back surface plating layer give opposite stresses to the substrate. In the present invention, the thicknesses of the front surface plating layer and the back surface plating layer are adjusted so as to suppress the warp of the substrate. Therefore, according to the present invention, a semiconductor laser with a small warp can be obtained.

FIG. 3 is a cross-sectional view showing a state in which a crystal growth layer is provided on the surface of the substrate in the first embodiment of the present invention. It is sectional drawing which shows the state which etched FIG. 1 in Embodiment 1 of this invention. FIG. 3 is a cross-sectional view showing a state in which an insulating layer is provided on FIG. 2 in the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a state in which a second type electrode and a surface plating layer are provided in FIG. 3 in the first embodiment of the present invention. FIG. 5 is a plan view showing the state of FIG. 4 in the first embodiment of the present invention. FIG. 3 is a sectional view of the semiconductor laser according to the first embodiment of the present invention. FIG. 3 is a bottom view of the semiconductor laser according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view showing a state in which a crystal growth layer is provided on the surface of a substrate in a comparative example. It is sectional drawing which shows the state which etched FIG. 8 in a comparative example. 10 is a cross-sectional view showing a state in which an insulating film pad is provided on top of FIG. 9 in a comparative example. FIG. 11 is a cross-sectional view showing a state in which an insulating layer, a second-type electrode, and a surface plating layer are provided on top of FIG. 10 in a comparative example. It is sectional drawing of the semiconductor laser in a comparative example. It is a top view of the semiconductor laser in a comparative example. FIG. 6 is a plan view of a semiconductor laser according to a second embodiment of the present invention. FIG. 7 is a plan view of a semiconductor laser according to a third embodiment of the present invention. It is sectional drawing of the semiconductor laser in Embodiment 4 of this invention. It is sectional drawing of the semiconductor laser in Embodiment 5 of this invention. FIG. 13 is a bottom view of the semiconductor laser according to the sixth embodiment of the present invention. It is a bottom view of the semiconductor laser in a comparative example.

  A semiconductor laser and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1.
1 to 7 are views for explaining the method of manufacturing the semiconductor laser 100 according to the first embodiment. In FIG. 1, the crystal growth layer 20 is provided on the surface of the substrate 10. The substrate 10 is a first type InP substrate. Here, the first type indicates one of N type and P type. The second type indicates the other of N type and P type. The crystal growth layer 20 is formed by the steps shown below. First, a first type InP clad layer, an active layer 12, and a second type InP clad layer are laminated in this order by MOCVD (Metal Organic Chemical Vapor Deposition). Next, a stripe pattern in the resonance direction is formed of an insulating film on the surface of the second type InP clad layer. Next, etching is performed by RIE (Reactive Ion Etching) to form the ridge 14 under the insulating film.

  Next, the first-type InP layer, the second-type InP layer 16, and the first-type InP layer are laminated in this order by MOCVD. As a result, the side surface of the ridge 14 is filled. Further, the current can efficiently flow into the active layer 12. Next, the insulating film is removed by etching. Next, a second type InP layer and a second type InGaAs layer are stacked in this order by MOCVD. The InGaAs layer becomes the contact layer 18 with the electrode. Through the above steps, the crystal growth layer 20 is formed on the substrate 10.

  Next, a mesa portion forming step is performed. In the mesa portion forming step, as shown in FIG. 2, the mesa portion 22 is formed by etching. At this time, all the crystal growth layers 20 except the mesa portion 22 are removed by etching. As a result, the first exposed portion 32 and the second exposed portion 34 exposing the substrate 10 are formed on both sides of the mesa portion. From the above, the structure 36 including the substrate 10 and the crystal growth layer 20 is formed.

  Next, as shown in FIG. 3, the insulating layer 24 is formed so as to cover the structure 36. The crystal growth layer 20 is protected by the insulating layer 24. Moreover, the capacitance of the element is reduced. Next, the insulating layer 24 on the upper surface of the mesa portion 22 is removed. As a result, the opening 26 is formed in the insulating layer 24 and the contact layer 18 is exposed. The opening 26 is provided for contact between the contact layer 18 and the electrode.

  Next, as shown in FIG. 4, a second-type electrode 28 is formed on the surface of the insulating layer 24. The second type electrode 28 is an ohmic electrode. The second-type electrode 28 contacts the contact layer 18 in the opening 26. The contact between the contact layer 18 and the second-type electrode 28 in the opening 26 enables an efficient current flow in the active layer 12. Further, since the current is efficiently passed through the active layer 12, the second-type electrode 28 has a low resistance. The second-type electrode 28 is formed so as to cover the bonding wire connection regions 39 on both sides of the mesa portion 22 and the continuous region 48 (see FIG. 5) including the mesa portion 22.

  Next, a surface plating layer forming step is performed. In the present embodiment, the plated layer is formed by electrolytic gold plating. As the plating solution, a non-cyan bright electric field plating solution is used. The liquid temperature at the time of forming the plating is 50° C., stirring is performed, and the current density is 4 mA/cm −2. In electrolytic gold plating, selective plating using a power supply layer and a photoresist pattern is possible. Also, the thickness of plating can be adjusted. In the surface plating layer forming step, first, the first plating layer 30 is formed on the surface of the second type electrode 28. The first plating layer 30 forms the second type electrode 28 as a power feeding layer. The first plating layer 30 is formed using a photoresist pattern so as to cover the connection region 39 of the bonding wire and the continuous region 48 including the mesa portion 22. The first plating layer 30 improves low resistance between the second-type electrode 28 and the active layer 12.

  Next, the second plating layer 38 is formed. The second plating layer 38 is formed by using the first plating layer 30 as a power feeding layer. The second plating layer 38 is formed on the connection area 39 of the bonding wire using a photoresist pattern. The second plating layer 38 becomes a bonding pad for wire bonding. Further, as shown by the arrow 46, the second plating layer 38 is formed so that the upper surface thereof is higher than the upper surface of the mesa portion 22. Therefore, it becomes possible to protect the mesa portion 22 in the subsequent process or at the time of assembly.

  The first plating layer 30 and the second plating layer 38 form a surface plating layer 40. The surface plating layer 40 is provided with a thickness that gives a larger stress to the substrate 10 than the stress that the crystal growth layer 20, the second-type electrode 28, and the insulating layer 24 warp the substrate 10 when the surface plating layer forming step is completed. In the present embodiment, when the surface plating layer forming step is completed, the thickness of surface plating layer 40 is set so that substrate 10 has a convex warp on the surface plating layer 40 forming side.

  Here, the strength of stress that causes the substrate to warp is proportional to the layer thickness. In this embodiment, the crystal growth layer 20 has a thickness of 5 μmt, the insulating layer 24 has a thickness of 0.5 μmt, and the second-type electrode 28 has a thickness of 0.5 μmt. Here, in the present embodiment, the crystal growth layer 20 is etched except for the mesa portion 22. Therefore, the stress applied to the substrate 10 by the crystal growth layer 20 is small. In the present embodiment, in order to convexly warp substrate 10 toward the surface plating layer 40 formation side, first plating layer 30 may be formed to a thickness of 3 μmt or more.

  Although the thickness of the first plating layer 30 is adjusted in the present embodiment, the thickness of the second plating layer 38 may be adjusted so that the substrate 10 is convexly warped toward the front surface side. Further, the thicknesses of both the first plating layer 30 and the second plating layer 38 may be adjusted. In this embodiment, the surface plating layer 40 is set to have a predetermined thickness so that a desired warp can be obtained. On the other hand, a step of measuring the warp of the substrate 10 may be provided, and the thickness of the surface plating layer 40 that causes the substrate 10 to warp convexly may be determined from the measured value.

  FIG. 5 is a plan view showing the state of FIG. As described above, the second-type electrode 28 and the first plating layer 30 are provided so as to cover the connection region 39 of the bonding wire and the continuous region 48 including the mesa portion 22. In the present embodiment, continuous region 48 is a region covered with first plating layer 30. The continuous region 48 has a cross shape in a plan view. The second type electrode 28 is provided so as to include the continuous region 48. The second-type electrode 28 is provided symmetrically with respect to the mesa portion 22 and has a width equal to that of the substrate 10. Further, although the continuous region 48 has a cross shape in the present embodiment, the continuous region 48 may cover the entire area of the substrate 10.

  Next, the back surface of the substrate 10 is processed. As shown in FIG. 6, the substrate 10 is thinned from 400 μmt to 100 μmt or less by grinding or polishing. Next, the first-type electrode 42 is formed on the back surface of the substrate 10. The first type electrode 42 is an ohmic electrode. Next, a back plating layer forming step is performed. In the back surface plating layer forming step, the back surface plating layer 44 is formed on the back surface of the first-type electrode 42. The back surface plating layer 44 is formed by electrolytic gold plating using a photoresist pattern. The thickness of the back plating layer 44 is adjusted so that the warpage of the substrate 10 is canceled when the back plating layer forming step is completed. FIG. 7 is a bottom view of the semiconductor laser 100 according to the present embodiment. The back surface plating layer 44 is formed excluding the outer peripheral portion of the substrate 10.

  In the present embodiment, the area ratio of first plating layer 30 and back plating layer 44 is 30:50. Assuming that the warp of the substrate 10 occurs only by the stress caused by the first plating layer 30 and the back plating layer 44, the thickness of the back plating layer 44 may be set to be 30/50 of that of the first plating layer 30. Good. When the thickness of the first plating layer 30 is 3 μmt, the thickness of the back surface plating layer 44 is 1.8 μmt. In the present embodiment, backside plating layer 44 is set to a predetermined thickness so as to cancel the warpage. On the other hand, as in the case of the surface plating layer forming step, a step of measuring the warp of the substrate 10 may be provided. In this case, the thickness of the back surface plating layer 44 that cancels the warp of the substrate 10 is determined from the measured warp value. This completes the wafer process.

  Next, a method of manufacturing the semiconductor laser 110 according to the comparative example will be described. FIG. 8 shows a state in which the active layer 12 and the crystal growth layer 20 are formed on the surface of the substrate 10. The manufacturing method up to this point is similar to that of the semiconductor laser 100 in the present embodiment. Next, as shown in FIG. 9, the crystal growth layer 20 is etched on portions on both sides of the mesa portion 122. As a result, the crystal growth layers 201 and 202 remain on both sides of the mesa portion 122.

  Next, as shown in FIG. 10, insulating film pads 211 and 212 are formed on the surfaces of the crystal growth layers 201 and 202. Next, as shown in FIG. 11, an insulating layer 124 is formed so as to cover the mesa portion 122, the crystal growth layers 201 and 202, and the substrate 10. An opening 126 is formed in the insulating layer 124 on the upper surface of the mesa 122. Further, the second type electrode 128 and the surface plating layer 130 are formed on the surface of the insulating layer 124. Next, the back surface of the substrate 10 is processed. As shown in FIG. 12, the substrate 10 of 400 μmt is thinned to 100 μmt or less. Next, the first-type electrode 142 and the back surface plating layer 144 are formed on the back surface of the substrate 10. This completes the wafer process. FIG. 13 is a plan view of the semiconductor laser 110 according to the comparative example.

  As described above, the strength of stress that causes the substrate to warp is proportional to the thickness of the layer. In the comparative example, the stress from the crystal growth layer 20 is a main factor, and the substrate 10 is warped. In the thinned state of the substrate 10 shown in FIG. 12, the substrate thickness is about ¼ of that in the state shown in FIG. 11, which is the completion of the surface process. At this time, the substrate 10 is warped about four times as much as when the surface process is completed.

  In the subsequent process of the semiconductor laser, the wafer is divided into bars in order to obtain a single device. Here, the impact may not be transmitted evenly when the wafer is warped during the breaking. For this reason, division failure is likely to occur. In the field of optical communication, the speed of communication is increasing due to the increase in communication volume. Therefore, the resonator length of the element tends to be small. As the resonator length becomes smaller, it is necessary to cut out a thin bar at the end of the cavity. When a thin bar is cut out, the wafer is more likely to cause division defects due to the influence of the warp. Further, in the excitation light source of the processing machine, in order to increase the output and the efficiency, the assembly may be performed in a bar state in which a plurality of elements are arranged. At this time, if the warp of the bar is large, there is a possibility that the solder does not wrap around sufficiently. At this time, assembly failure is likely to occur.

  In the present embodiment, the crystal growth layer 20 is removed over the entire area on both sides of the mesa portion 22. Therefore, the stress caused by the crystal growth layer 20 is reduced. As a result, the ratio of the stress applied to the substrate 10 by the front surface plating layer 40 and the back surface plating layer 44 increases in the stress applied to the substrate 10. Therefore, the front surface plating layer 40 and the back surface plating layer 44 can be main factors of the stress applied to the substrate 10. Therefore, the warp can be suppressed by adjusting the thicknesses of the front surface plating layer 40 and the back surface plating layer 44.

  Each plating layer generates a stress that causes the substrate 10 to be convexly warped toward the plating formation side. In the surface plating layer forming step, the thickness of the surface plating layer 40 is adjusted so that the substrate 10 warps convexly on the surface plating layer 40 forming side. In addition, the back surface plating layer 44 generates stress in the opposite direction to the front surface plating layer 40. Therefore, by forming the back surface plating layer 44, it is possible to suppress the warp of the substrate 10 that is convexly warped in the front surface direction. Further, by adjusting the thickness of the back surface plating layer 44, the warp of the substrate 10 can be offset. Therefore, the warp of the wafer is alleviated when the wafer process is completed. For this reason, it is possible to suppress wafer division defects and assembly defects.

  Further, when the crystal growth layer including the PN junction is sandwiched between the electrodes, the device capacitance becomes large. A large element capacity may hinder high-speed communication. In order to reduce the element capacitance, it is possible to increase the thickness of the insulating layer. In this case, the process may become unstable. Further, as another method for reducing the element capacitance, it is conceivable to reduce the electrode area. In this case, the efficiency of the wire bonding process may decrease.

  On the other hand, in this embodiment, the region of the crystal growth layer 20 is small. Therefore, the element capacitance is reduced. Therefore, the insulating layer 24 can be thinned. At this time, the process can be stabilized. Moreover, the electrode area can be increased. Therefore, the efficiency of the wire bonding process can be improved.

  In the present embodiment, the back surface plating layer 44 is formed after the surface plating layer 40 is formed. As a modified example of the present embodiment, the back surface plating layer may be formed first. In this case, the back surface is processed after the second type electrode 28 is formed. At this time, in the back surface plating layer forming step, the thickness of the back surface plating layer 44 is adjusted so that the substrate 10 is convexly warped toward the back surface plating layer 44 forming side. Then, the surface plating layer forming step is performed. The thickness of the surface plating layer 40 is adjusted so that the warp of the substrate 10 is offset. Further, although the plating is gold plating in the present embodiment, it may be platinum plating.

  Further, in the present embodiment, the continuous area 48 includes the bonding wire connection area 39 and the mesa portion 22. On the other hand, the continuous region 48 may include the defined regions on both sides of the mesa portion 22 and the mesa portion 22. Here, the specified region includes a case other than the bonding wire connection region.

Embodiment 2.
FIG. 14 is a plan view of semiconductor laser 200 according to the second embodiment of the present invention. In this embodiment, the second-type electrode 228 is formed on the surface of the insulating layer 24. The second-type electrode 228 is formed so as to cover the entire area of the insulating layer 24. Further, the first plating layer 230 is formed on the surface of the second-type electrode 228. The first plating layer 230 is formed so as to cover the entire area of the second-type electrode 228. On the surface of the first plating layer 230, the second plating layer 238 is provided in the connection area 39 of the bonding wire. Further, the second plating layer 238 is also provided at the four corners of the first plating layer 230. The second plating layer 238 is formed such that the upper surface thereof is higher than the upper surface of the mesa portion 22.

  In this embodiment, the second plating layer 238 is provided at the four corners of the first plating layer 230. Therefore, it is possible to evenly disperse the shock received by the semiconductor laser 200 during the subsequent process or assembly. Therefore, the impact applied to the mesa portion 22 can be reduced as compared with the first embodiment.

Embodiment 3.
FIG. 15 is a plan view of semiconductor laser 300 according to the third embodiment of the present invention. In the present embodiment, the second plating layer 338 is formed on the surface of the first plating layer 330. The second plating layer 338 is provided only at the four corners of the first plating layer 330. Moreover, in the present embodiment, the first plating layer 330 is used as a bonding pad. Therefore, the first plating layer 330 has a thickness that enables wire bonding. In this embodiment, the step difference on the surface of the semiconductor laser 300 is smaller than that in the second embodiment. Therefore, it becomes possible to stabilize the process.

Fourth Embodiment
FIG. 16 is a sectional view of semiconductor laser 400 according to the fourth embodiment of the present invention. In the present embodiment, the second exposed portion 434 is a partial region of the substrate 10 adjacent to the mesa portion 22. Further, on the surface of the substrate 10, a crystal growth layer 420 is provided in a region facing the mesa portion 22 with the second exposed portion 434 interposed therebetween.

  In addition, the insulating film pad 211 is formed on the upper surface of the crystal growth layer 420 in a region facing the mesa portion 22 with the second exposed portion 434 interposed therebetween. The insulating film pad 211 is provided so that the upper surface of the first plating layer 430 disposed on the insulating film pad 211 is higher than the upper surface of the mesa portion 22.

  In the present embodiment, the stress applied to the substrate 10 by the crystal growth layer 420 can be reduced to about half as compared with the case where the crystal growth layers are provided on both sides of the mesa portion 22. The insulating film pad 211 can protect the mesa portion 22. Therefore, it is possible to protect the mesa portion 22 without providing the second plating layer.

Embodiment 5.
FIG. 17 is a sectional view of semiconductor laser 500 according to the fifth embodiment of the present invention. The present embodiment is the same as the fourth embodiment except that the second plating layer 538 is formed on the surface of the first plating layer 430. The second plating layer 538 is formed on the first exposed portion 32. Further, the second plating layer 538 is provided so that the upper surface thereof is higher than the upper surface of the mesa portion 22. Therefore, the mesa portion 22 is protected by the second plating layer 538 in addition to the insulating film pad 211. Therefore, the protection function of the mesa portion 22 can be improved as compared with the fourth embodiment.

Sixth embodiment.
FIG. 18 is a bottom view of semiconductor laser 600 according to the sixth embodiment of the present invention. In the present embodiment, the back surface plating layer 644 is formed on the back surface of the first-type electrode 42. The back surface plating layer 644 is formed with a certain space 50 vacated from the corresponding portion 52 corresponding to the eccentricity. Here, the eclipse-corresponding portion is a portion to be eclipsed when dividing the wafer into bars. In addition, the back surface plating layer 644 is formed in a state of being divided in parallel with the breaking direction. The area of the portion of the back surface plating layer 644 that is adjacent to the eccentricity corresponding portion 52 is smaller than the area of the portion that is not adjacent.

  FIG. 19 is a bottom view of the semiconductor laser 700 in the comparative example. In FIG. 19, the semiconductor laser 700 is in a wafer state before being broken. The semiconductor laser includes a back surface plating layer 744 on the back surface of the first-type electrode 742. When dividing the wafer into bars, a break is performed. At this time, the backside plating layer 744 is stressed at the portion corresponding to the flattening. Due to this stress, as shown by the broken line 53, the flat surface may be bent, resulting in defective division. The stress from the back surface plating layer 744 increases as the space 54 between the back surface plating layer 744 and the portion corresponding to the eccentricity decreases.

  In this embodiment, a large space 50 is provided in order to suppress the stress from the back surface plating layer 644. In order to ensure the stability during die bonding, the back surface plating layer 644 needs to have a width that is ⅔ of the width of the device. When this width is secured, the space 50 becomes 1/6 of the width of the element at the maximum. From the above, in the present embodiment, the space 50 is set to 1/6 of the element width. When the element size is 300×200 μm, the space 50 is 33 μm. At this time, it is possible to reduce the stress received by the backside plating layer 644 on the backside corresponding portion 52. Therefore, division failure is suppressed. In the present embodiment, the space 50 is set to 1/6 of the element width, but in order to obtain the effect of suppressing the division failure, the space 50 is set to 1/20 to 1/6 of the element width. It may be set to any value.

  Further, in order to reduce the stress generated in the cliff corresponding portion 52, it is effective to reduce the area of the back surface plating layer adjacent to the scribe corresponding portion 52. In this embodiment, the back surface plating layer 644 is divided and provided in parallel with the breaking direction. Furthermore, the area of the portion of the back surface plating layer 644 that is adjacent to the reed-corresponding portion 52 is set to be smaller than the area of the portion that is not adjacent. For this reason, the stress generated in the eclipse corresponding portion 52 is reduced. Therefore, the occurrence of division failure is suppressed.

  In the present embodiment, the space 50 is provided between the backside plating portion 644 and the backside plating layer 644. Further, the back surface plating layer 644 was formed in a state of being divided into a plurality. As a modified example of the present embodiment, the back surface plating layer 644 may be formed after the space 50 is provided, without being divided. In this case, the process of forming the back surface plating layer 644 becomes easy. Further, the back surface plating layer 644 may be formed in a divided state without providing the space 50. In this case, stability during die bonding is improved.

100, 200, 300, 400, 500, 600 semiconductor laser, 10 substrate, 20, 420 crystal growth layer, 22 mesa portion, 24 insulating layer, 26 opening portion, 28, 228 second type electrode, 30, 230, 330 430 1st plating layer, 32 1st exposed part, 34, 434 2nd exposed part, 36 Structure, 38, 238, 338, 538 2nd plating layer, 39 Bonding wire connection area, 40 Surface plating layer, 42 First type electrode, 44, 644 Backside plating layer, 50 space, 52 Corresponding area

Claims (32)

A first-type substrate that is one of N-type and P-type,
A mesa portion arranged on the surface of the substrate and provided with a crystal growth layer,
A semiconductor laser having a structure including:
One side of the mesa portion of the structure is a first exposed portion in which the substrate is exposed over the entire area,
The other side of the mesa portion of the structure has a second exposed portion that is formed in a position adjacent to the mesa portion and in which the substrate is exposed.
The semiconductor laser covers the structure, and an insulating layer having an opening on the upper surface of the mesa portion;
On the surface of the insulating layer, the N type and the P type which are provided so as to cover the continuous region including the mesa portion and the prescribed regions on both sides of the mesa portion and are in contact with the crystal growth layer in the opening portion are formed. A second type electrode,
A surface plating layer arranged on the surface of the second type electrode so as to cover the continuous region;
A first-type electrode disposed on the back surface of the structure,
A back surface plating layer disposed on the back surface of the first type electrode,
Equipped with
The semiconductor laser, wherein the front surface plating layer and the back surface plating layer have a thickness that suppresses warpage of the substrate.   The said surface plating layer is provided with the thickness which gives a stress larger than the stress which the said crystal growth layer, the said 2nd-type electrode, and the said insulating layer warp the said substrate to the said substrate, The claim 1 characterized by the above-mentioned. Semiconductor laser.   The back plating layer has a thickness that cancels the stress exerted on the substrate by the front plating layer, the second type electrode, the insulating layer, the crystal growth layer, and the first type electrode. The semiconductor laser according to claim 2.   The semiconductor laser according to claim 1, wherein the defined region includes a connection region of a bonding wire.   The semiconductor laser according to claim 1, wherein the second-type electrode has a width equal to the width of the substrate.   The semiconductor laser according to claim 1, wherein the second exposed portion exposes the entire area of the substrate on the other side of the mesa portion.   7. The semiconductor laser according to claim 6, wherein the second type electrode is provided symmetrically with respect to the mesa portion. The surface plating layer is
A first plating layer arranged to cover the continuous region,
A second plating layer disposed on a surface of the first plating layer in a region where the substrate and the insulating layer are in contact with each other, and a top surface of the second plating layer is higher than a top surface of the mesa portion;
The semiconductor laser according to claim 6, further comprising:   The semiconductor laser according to claim 8, wherein the second plating layer is provided in the defined region.   The semiconductor laser according to claim 8, wherein the second plating layer is provided at four corners of the first plating layer. The second exposed portion is a partial region of the substrate adjacent to the mesa portion,
The structure includes the crystal growth layer on a surface of the substrate in a region facing the mesa portion with the second exposed portion interposed therebetween,
The semiconductor laser according to claim 1, wherein an upper surface of the surface plating layer is located higher than an upper surface of the mesa portion in the region. The surface plating layer is
A first plating layer arranged to cover the continuous region,
A second plating layer disposed on the surface of the first plating layer in the defined region on the first exposed portion side and having an upper surface at a position higher than an upper surface of the mesa portion;
The semiconductor laser according to claim 11, further comprising:   13. The back surface plating layer is provided with a space of 1/20 to 1/6 of the width of the substrate in the resonance direction from the corresponding portion of the back surface. The semiconductor laser described.   The semiconductor laser according to any one of claims 1 to 13, wherein the back surface plating layer is provided in a divided manner. The back surface plating layer is divided and provided in parallel with the breaking direction,
15. The semiconductor laser according to claim 14, wherein the area of the back surface plating layer adjacent to the location corresponding to the scribed area is smaller than the area of the back surface plating layer not adjacent to the location corresponding to the scribed area. Forming a crystal growth layer on the surface of a first type substrate which is one of N type and P type;
The crystal growth layer is etched to form a mesa portion, a first exposed portion that exposes the substrate over one side of the mesa portion, and a position adjacent to the mesa portion on the other side of the mesa portion. A mesa portion forming step of forming a second exposed portion that exposes the substrate;
Forming an insulating layer so as to cover the crystal growth layer and the substrate,
Forming an opening in the insulating layer on the upper surface of the mesa portion;
Forming a second-type electrode, which is the other of the N-type and the P-type, on the surface of the insulating layer so as to cover the mesa portion and a continuous region including defined regions on both sides of the mesa portion;
A surface plating layer forming step of forming a surface plating layer on the surface of the second type electrode so as to cover the continuous region;
Forming a first type electrode on the back surface of the substrate;
A back plating layer forming step of forming a back plating layer on the lower surface of the first type electrode;
Equipped with
The method for manufacturing a semiconductor laser, wherein the front surface plating layer and the back surface plating layer are formed to have a thickness that suppresses warpage of the substrate.   The front surface plating layer forming step is performed prior to the back surface plating layer forming step, and when the front surface plating layer forming step is completed, the front surface plating layer is formed to a thickness such that the substrate is convexly warped toward the front surface plating layer forming side. The method of manufacturing a semiconductor laser according to claim 16, wherein the method is used. The surface plating layer forming step,
Measuring the warp of the substrate,
A step of forming the surface plating layer so that the warp is in a desired state,
The method of manufacturing a semiconductor laser according to claim 17, further comprising:   19. The back plating layer is formed in a thickness such that the warp of the substrate is canceled at the completion of the back plating layer forming step in the back plating layer forming step. Manufacturing method of semiconductor laser. The back plating layer forming step,
Measuring the warp of the substrate,
A step of forming the back plating layer so that the warp is in a desired state,
The method for manufacturing a semiconductor laser according to claim 19, further comprising:   21. The method of manufacturing a semiconductor laser according to claim 16, wherein the defined region includes a connection region of a bonding wire.   22. The method for manufacturing a semiconductor laser according to claim 16, wherein the second type electrode is formed over a width equal to the width of the substrate.   The said 2nd exposed part is formed in the said mesa part formation process so that the said board|substrate may be exposed over the other side of the said mesa part, The any one of Claims 16-22 characterized by the above-mentioned. Manufacturing method of semiconductor laser.   The method of manufacturing a semiconductor laser according to claim 23, wherein the second-type electrode is formed symmetrically with respect to the mesa portion. The surface plating layer forming step,
Forming a first plating layer so as to cover the continuous region,
Forming a second plating layer on a surface of the first plating layer in a region where the substrate and the insulating layer are in contact with each other so that an upper surface of the second plating layer is higher than an upper surface of the mesa portion;
25. The method of manufacturing a semiconductor laser according to claim 23, further comprising:   26. The method of manufacturing a semiconductor laser according to claim 25, further comprising a step of forming the second plating layer in the defined region.   27. The method of manufacturing a semiconductor laser according to claim 25, further comprising the step of forming the second plating layer at four corners of the first plating layer. In the mesa portion forming step, etching is performed so as to leave the crystal growth layer in a region facing the mesa portion through the second exposed portion,
23. The method of manufacturing a semiconductor laser according to claim 16, further comprising a step of making an upper surface of the surface plating layer in the region higher than an upper surface of the mesa portion. The surface plating layer forming step,
Forming a first plating layer so as to cover the continuous region,
Forming a second plating layer on the surface of the first plating layer in the defined region on the first exposed portion side so that the upper surface is higher than the upper surface of the mesa portion;
29. The method for manufacturing a semiconductor laser according to claim 28, further comprising:   30. In the back surface plating layer forming step, the back surface plating layer is formed with a space of 1/20 to 1/6 of a width of the substrate from a portion corresponding to the eccentricity. The method for manufacturing the semiconductor laser according to any one of items.   31. The method of manufacturing a semiconductor laser according to claim 16, wherein in the back surface plating layer forming step, the back surface plating layer is divided into a plurality of parts.   The back plating is divided and formed in parallel with the heave direction so that the area of the portion adjacent to the heave corresponding portion is smaller than the area of the portion not adjacent to the heave corresponding portion. Item 32. A method for manufacturing a semiconductor laser according to Item 31.

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