JP6694836B2 - Trigger circuit, trigger generation method, sampling oscilloscope, and sampling method - Google Patents

Description

  The present invention relates to a trigger circuit and a trigger generation method for generating sampling timing of a sampler for sampling data, a sampling oscilloscope and a sampling method for displaying a waveform based on sampling data by the sampler.

  For example, Patent Document 1 below discloses a technique in which a pattern signal is sampled by a sampler using a strobe signal generated using a direct digital synthesizer (DDS) and a programmable counter.

U.S. Pat. No. 7,284,141

  By the way, the DDS is a convenient IC that can output a relatively arbitrary frequency by setting an FTW (frequency tuning word), but in principle, an unnecessary wave component such as an image component and a harmonic component is superimposed. Will end up. Therefore, basically, it is general to connect a BPF or an LPF for the purpose of removing unnecessary wave components. The above Patent Document 1 discloses a configuration in which an LPF is connected to the next stage of the DDS.

  Here, when the restriction by the BPF is not taken into consideration, for example, in the configuration in which the LPF is inserted as in the above-mentioned Patent Document 1, if the maximum outputtable frequency is designed to be ¼ of the input frequency, the largest unnecessary wave is obtained. Since the image component can be removed by the LPF under the constraint, only the initially determined maximum frequency is a constraint. Further, if it is decided in advance that the frequency of which the DDS will be, for example, 1/8 or less will be output, the FTW has some flexibility, and it is possible to set a frequency division ratio of, for example, 1/8 × 8191/8192. Met.

  By the way, in a sampling oscilloscope, random sampling and sequential sampling are known as sampling methods for measuring a waveform. Here, in the case of sequential sampling related to the present invention, considering that the residual jitter is improved, in order to remove the unnecessary wave component and extract only the signal wave component, a sharp filter having a high Q value and a steep DDS output is used. Although it is expected to use a BPF having characteristics, it is necessary to fix the DDS output frequency within a certain output range for that purpose. On the other hand, when the sampling clock is supplied from the outside and the corresponding frequency has a range, the DDS input frequency changes, so the DDS output also changes. Therefore, there is a problem that a BPF having a high Q value and a steep filter characteristic and a fixed pass frequency range cannot be used.

  In the above-mentioned conventional device disclosed in Patent Document 1, the DDS setting is fixed and used, and it is necessary to adopt a circuit that allows a certain range for the LPF. As a result, there is a problem that the unnecessary wave component of the DDS output cannot be completely removed and the residual jitter increases.

  Therefore, the present invention has been made in view of the above problems, and uses a bandpass filter having a fixed pass frequency range and is capable of suppressing residual jitter when generating a strobe signal and a trigger generation. Method and sampling It is an object to provide an oscilloscope and a sampling method.

To achieve the above object, the trigger circuit according to claim 1 of the present invention is a direct digital synthesizer 12 that outputs a trigger clock input within an operable frequency range at an arbitrary frequency,
A bandpass filter 13 that limits the passband of the trigger clock output from the direct digital synthesizer;
In the trigger circuit 2 for generating a strobe signal using the phase shift function of the direct digital synthesizer, which includes a variable frequency divider 14 for dividing a trigger clock whose pass band is limited by the band pass filter.
The pass frequency range of the bandpass filter is fixed below octave,
The value of the denominator of the frequency tuning word of the direct digital synthesizer is a power of 2,
Setting the value of the frequency tuning word to approximate the value obtained by dividing the center frequency of the bandpass filter by the input frequency of the direct digital synthesizer,
The division ratio of the variable frequency divider is set to a common multiple of the pattern length and the numerator value of the division ratio set by the direct digital synthesizer.

The trigger generating method according to claim 2 is a direct digital synthesizer 12 that outputs a trigger clock input within an operable frequency range at an arbitrary frequency,
A bandpass filter 13 that limits the passband of the trigger clock output from the direct digital synthesizer;
A variable frequency divider 14 for dividing a trigger clock whose pass band is limited by the band pass filter, and a trigger generating method for generating a strobe signal by using the phase shift function of the direct digital synthesizer of the trigger circuit 2. At
Fixing the pass frequency range of the bandpass filter below an octave;
The value of the denominator of the frequency tuning word of the direct digital synthesizer is a power of 2, and the frequency tuning word is approximated to a value obtained by dividing the center frequency of the bandpass filter by the input frequency of the direct digital synthesizer. The step of setting the value of
Setting the frequency division ratio of the variable frequency divider to a common multiple of the pattern length and the numerator value of the frequency division ratio set by the direct digital synthesizer.

  A sampling oscilloscope described in claim 3 is characterized in that data is sequentially sampled by the sampler 3 at a sampling timing based on the strobe signal output from the trigger circuit 2 of claim 1.

  A sampling method described in claim 4 includes a step of sequentially sampling data by the sampler 3 at a sampling timing based on the strobe signal output from the trigger generating method of claim 2.

  According to the present invention, it is possible to use a bandpass filter having a fixed pass frequency range having a high Q value and steep filter characteristics, which enables optimum filter design and setting and suppresses residual jitter. Since the residual jitter is suppressed, the timing deviation of the switching operation of the sampler can be reduced, and more accurate data sampling can be performed.

It is a block configuration diagram of a sampling oscilloscope including a trigger circuit according to the present invention. In the present invention, it is a diagram showing a relationship between each signal and a bandpass filter characteristic in which the horizontal axis represents frequency and the vertical axis represents amplitude. 6 is a flowchart showing an outline of a trigger generation method and a sampling method according to the present invention.

  Hereinafter, embodiments for implementing the present invention will be described in detail with reference to the accompanying drawings.

  As shown in FIG. 1, the sampling oscilloscope 1 of the present embodiment displays the waveform of a wide-band / high-speed signal to be observed, and includes a trigger circuit 2, a sampler 3, an A / D converter 4, and a display unit. 5 and the control part 6 are comprised roughly.

  The trigger circuit 2 is a circuit that generates a strobe signal used as sampling timing of the sampler 3, and includes a frequency conversion unit 11, a direct digital synthesizer (DDS) 12, a bandpass filter (BPF) 13, and a variable frequency divider 14. It is configured to include.

  The frequency conversion unit 11 is located at the first stage of the trigger circuit 2, includes a variable frequency divider 11a and a frequency multiplication circuit 11b, and can operate the DDS 12 located at the next stage (the input frequency range of the DDS 12 in FIG. 2). The frequency (trigger input frequency Ft of FIG. 2) of the trigger clock (for example, rectangular wave or sine wave) supplied from the outside to H1) is converted.

  The frequency converter 11 can be omitted when the trigger clock in the input frequency range in which the DDS 12 can operate is input from the outside. In this case, the trigger clock is directly input to the DDS 12 from the outside.

  When the operating frequency of the DDS 12 (the DDS12 inputtable range H1 in FIG. 2) is defined as the octave (double) range of 1.25 GHz to 2.5 GHz, the frequency conversion unit 11 behaves as follows.

[Example 1] When the trigger clock is 10 GHz, the frequency division ratio of the variable frequency divider 11a is set to 4, and 2.5 GHz is supplied to the DDS 12.
[Example 2] When the trigger clock is 2.0 GHz, the frequency division ratio of the variable frequency divider 11a is set to 1 and 2.0 GHz is supplied to the DDS 12.
[Example 3] When the trigger clock is 0.1 GHz, the frequency multiplication circuit 11b multiplies the frequency by 16 to supply 1.6 GHz to the DDS 12.

  If the operating frequency range of the DDS 12 is the octave (2 times) range, the frequency division ratio and the multiplication ratio can be supported by powers of 2. Here, it is calculated as a power of 2.

  The DDS 12 is connected to the next stage of the frequency conversion unit 11, and as shown in FIG. 2, the frequency conversion unit 11 adjusts the input frequency Fi to the input possible range H1 and the frequency conversion unit 11 frequency-converts the trigger. An arbitrary waveform or frequency (output frequency Fo) is digitally generated from the clock.

  The BPF 13 is connected to the next stage of the DDS 12 and limits the pass band of the trigger clock output from the DDS 12. As shown in FIG. 2, the BPF 13 has a lower cutoff frequency set to f0 and an upper cutoff frequency set to less than 2f0.

The variable frequency divider 14 is connected to the next stage of the BPF 13 and has a variable frequency division ratio (for example, 2 to 2 ³¹ ). Be done. As shown in FIG. 2, the variable frequency divider 14 adjusts the frequency of the trigger clock that has passed through the BPF 13 within the operable range H2 of the sampler 3.

  Here, the cycle of sampling timing (hereinafter referred to as strobe cycle) at which the sampler 3 can be driven is generally on the order of kHz. Therefore, it is not realistic to directly drive the sampler 3 with the output frequency Fo of the DDS 12 and the BPF 13. Therefore, as shown in FIG. 2, the variable frequency divider 14 at the final stage divides the frequency of the trigger clock passing through the BPF 13 to a frequency at which the sampler 3 can be driven, and the strobe signal (sampling timing of the sampler 3 The strobe frequency Fs) is output.

  The sampler 3 switches the strobe signal (strobe frequency Fs) generated by the trigger circuit 2 at a sampling timing of, for example, several hundred kHz (closed state: 10 to 100 psec) to sample data input from the outside. ..

  The data input from the outside is, for example, a known pattern signal having a periodicity due to a repeating pattern input to the device under test W as a test signal. The known pattern signal includes, for example, a PRBS (Pseudo-random bit sequence) pattern, a fixed pattern, and a programmable pattern of an arbitrary pattern.

  The A / D converter 4 converts the analog output data sampled by the sampler 3 into digital data.

  The display unit 5 is composed of, for example, a liquid crystal display provided in the main body, and under the control of the control unit 6, displays a waveform of data, a statistically processed measurement result and the like.

  The control unit 6 integrally controls the trigger circuit 2, the sampler 3, the A / D converter 4, and the display unit 5 in order to observe a waveform that repeats at a high frequency. For example, the frequency conversion unit 11, the DDS 112, and the variable frequency divider. Frequency division ratio setting of each part of the converter 14, switching control of the variable frequency divider 11a and the frequency multiplication circuit 11b, statistical processing of data converted by the A / D converter 4, display control of the observed waveform on the display 5. And so on.

  Next, the basic operation principle of sequential sampling will be described. In the case of sequential sampling, the DDS 12 is not frequency-detuned as in the case of random sampling, but the phase shift function (phase shift function) is used. The DDS 12 is configured by adding a built-in phase accumulator for FTW, but the phase of the output signal can be changed by changing the value of this phase accumulator by the phase shift function using a value other than FTW. it can. The basic operation is as follows.

(1) The trigger timing is synchronized with the pattern period of the observed waveform by the combination of the frequency conversion unit 11, the DDS 12, and the frequency division ratio of the trigger circuit 2 (hereinafter referred to as pattern lock).
(2) The phase is gradually shifted by using the phase shift function of the DDS 12, and the observed waveform of data is displayed.

  Here, the frequency division ratio of the frequency conversion unit 11 (variable frequency divider 11a) in the first stage, the frequency division ratio of the DDS 12, and the frequency division ratio of the variable frequency divider 14 in the final stage are defined as variables as follows.

Frequency division ratio of the first-stage frequency converter 11 (variable frequency divider 11a) = P (where P = 2 ⁿ : where n = 0, 1, 2, 3, ...)
Dividing ratio of DDS12 = 1/8 (fixed to 1/8)
Frequency division ratio of the variable frequency divider 14 at the final stage = M (M is a multiple of the pattern length)

  When the frequency of the trigger clock input from the outside is I [Hz], the strobe frequency Fs uses P, S, and N, and the strobe frequency Fs [Hz] = Input × (1 / P) × (1/8) It can be written as x (1 / M).

  Therefore, since the strobe period is the reciprocal of the strobe frequency Fs, the strobe period [s] = 1 / (strobe frequency Fs) = (1 / I) × P × 8 × M.

  Here, the observed waveform data signal and the trigger frequency are in synchronization with each other and have a 1: 1 relationship (synchronization is an essential condition). That is, assuming that the signal of I [bit / s] is being observed, the time width of 1 bit is 1 / I. Therefore, from the above equation, the strobe period is 1 × bit multiplied by 8 × P × M.

  Here, M is a multiple of the pattern length according to the precondition. Therefore, the strobe period is also a multiple of the pattern length. That is, it means that a strobe occurs at a specific phase of the periodic pattern.

In this embodiment, since the bit position of the pattern is fixed and the phase is also fixed, the phase is moved using the phase shift function of the DDS 12. The phase shift amount of the DDS 12 can be controlled with a phase resolution of 2 ¹⁴ , for example, based on the output frequency Fo of the DDS 12.

The output signal cycle of the DDS 12 becomes the output signal cycle of the DDS 12 [s] = (1 / I) × P × 8. When the 14-bit phase shift function is used, the phase can be adjusted with a resolution of 2 ¹⁴ times the main cycle, and therefore the minimum resolution is as follows.

Minimum resolution [s] = output signal period of DDS12 / 2 ¹⁴ = (1 / I) × P × 8 × 1/2 ¹⁴
= (1 / I) × P × 1/2048

  Here, (1 / I) is the time of the observation signal 1 bit. Therefore, from the above equation, the phase resolution can be expressed by 2048 / P samples for 1 UI by using the phase shift function of the DDS 12.

  P is a frequency division ratio of the frequency conversion unit 11 (variable frequency divider 11a) in the first stage and is a power of 2. Therefore, if P <2048, 2048 / P can be reduced and 1UI can be expressed by a positive number sample. Therefore, by using the phase shift function of the DDS 12, it becomes possible to display a pattern without a fraction.

  By the way, considering the adaptation of the BPF 13 having a high Q value and a steep filter characteristic and a fixed pass frequency range, the output frequency Fo of the DDS 12 is restricted to less than an octave. On the other hand, the input frequency Fi of the DDS 12 changes in octaves. Therefore, there is no choice but to control the output frequency Fo by adjusting the FTW of the DDS 12.

  Therefore, in the present embodiment, as shown in FIG. 3, the pass frequency range of the BPF 13 is fixed to less than an octave (ST1), and the frequency tuning of the DDS 12 is performed so that the output frequency Fo of the DDS 12 substantially matches the center frequency of the BPF 13. Set a word (FTW). Specifically, the set value of FTW is a denominator value that is a power of 2 (ST2), and the denominator is approximated to a value obtained by dividing the center frequency of the BPF 13 by the input frequency Fi of the DDS 12. And the numerator value is set (ST3). The FTW can be brought closer to the center frequency of the BPF 13 by increasing the value of the denominator, but since the value of the numerator appears as a fraction in the minimum resolution, the denominator and the numerator are set to positive numbers with the smallest digits close to 1. Is preferred. Hereinafter, a specific numerical example will be shown and described. Note that the numerical values described below are examples and are not limited to the numerical values.

Input frequency of DDS12 Fi = 1.74 GHz
Design value of BPF 13 = 1.03 GHz to 1.12 GHz
FTW setting value = 5/8
Output frequency of DDS12 Fo = 1.0875 GHz (second harmonic image component extracted by BPF13)

  Therefore, unlike the above-described basic operation principle, the division ratio of the DDS 12 is 5/8, and thus the strobe period is [s] = 1 / (strobe frequency Fs) = (1 / I) × P × ( 8/5) × M, and even if M is synchronized with the pattern period, it cannot be locked to the pattern. Therefore, consider adding the following condition to the variable M.

  M: a multiple of the pattern length and a multiple of the numerator value of the division ratio set by the DDS 12. That is, the frequency division ratio of the variable frequency divider 11a is set to a multiple of the pattern length and a multiple of the numerator value of the frequency division ratio set by the DDS 12 (ST4), and a strobe signal is generated. Then, the sampler 3 sequentially samples the data at the sampling timing based on the generated strobe signal (ST5).

  Therefore, according to the present embodiment, it is possible to write M = 5 × N as described above, and the strobe period [s] = 1 / (strobe frequency Fs) = (1 / I) × P × (8/5) × M = (1 / I) × P × (8/5) × 5 × N = (1 / I) × P × 8 × N, where N is a multiple of the pattern length. Since there is no change, it operates in the same manner as the operating principle.

The phase shift amount of the DDS 12 can be controlled with a phase resolution of 2 ¹⁴ , for example, based on the output frequency Fo of the DDS 12. The output signal cycle of the DDS 12 is the output signal cycle of the DDS 12 [s] = (1 / I) × P × (8/5).

When the 14-bit phase shift function is used, the phase can be adjusted with a resolution of 2 ¹⁴ times the main cycle, so the minimum resolution is [s] = DDS output signal cycle / 2 ¹⁴ = (1 / I) × P × (8/5) × 1/2 ¹⁴ = (1 / I) × P × 1 / (2048 × 5).

  Therefore, by adding the fraction 5 to the frequency division ratio of the DDS 12, the fraction 5 also appears in the minimum resolution. However, by using the phase shift function of the DDS 12, “1 UI can be expressed by (2048 × 5) / P samples”, and the precondition of P is a power of 2 without change from the operating principle. Therefore, 2048 / P can be reduced, and even if the result is multiplied by 5, it becomes a positive number. Therefore, by using the phase shift function of the DDS 12, 1UI can be represented by a positive sample.

  On the other hand, in general, it is desirable to measure 1 UI with the power of 2 samples. Therefore, it is general to set the phase shift amount of the DDS 12 to 5 times and adjust the power sample number of 2 to 1 UI.

  Thus, according to the present embodiment, even if the BPF performance is made steep and the pass frequency range is fixed, the DDS setting and the frequency division ratio of the variable frequency divider at the final stage can be optimized to operate without problems. You can That is, while following the setting in the conventional sampling oscilloscope, it is possible to use a BPF having a high Q value and a steep filter characteristic and a fixed pass frequency range of less than octave, which enables optimum filter design and setting. Jitter can be suppressed. When the specific numerical values are shown, the residual jitter can be improved from 850 fsrms (0.85 ps) to 400 fsrms (0.4 ps) as compared with the conventional configuration of Patent Document 1.

  Further, since the residual jitter is suppressed, the timing deviation of the switching operation of the sampler 3 can be reduced, and more accurate data sampling can be performed.

  The best modes of the trigger circuit, the trigger generation method, the sampling oscilloscope, and the sampling method according to the present invention have been described above, but the present invention is not limited to the description and the drawings according to this mode. That is, it goes without saying that all other forms, examples, operation techniques, and the like made by those skilled in the art based on this form are included in the scope of the present invention.

1 Sampling oscilloscope 2 Trigger circuit 3 Sampler 4 A / D converter 5 Display section 6 Control section 11 Frequency conversion section 11a Variable frequency divider 11b Frequency multiplication circuit 12 DDS (Direct Digital Synthesizer)
13 BPF (band pass filter)
14 Variable frequency divider Ft Trigger input frequency Fi DDS input frequency Fo DDS output frequency Fs Strobe frequency H1 DDS input possible range H2 Sampler operable range

Claims (4)

A direct digital synthesizer (12) that outputs a trigger clock input within an operable frequency range at an arbitrary frequency,
A band pass filter (13) for limiting a pass band of a trigger clock output from the direct digital synthesizer,
And a variable frequency divider (14) for dividing a trigger clock whose pass band is limited by the band pass filter, and a trigger circuit (2) for generating a strobe signal by using the phase shift function of the direct digital synthesizer. ),
The pass frequency range of the bandpass filter is fixed below octave,
The value of the denominator of the frequency tuning word of the direct digital synthesizer is a power of 2,
Setting the value of the frequency tuning word to approximate the value obtained by dividing the center frequency of the bandpass filter by the input frequency of the direct digital synthesizer,
A trigger circuit , wherein a frequency division ratio of the variable frequency divider is set to a common multiple of a pattern length and a numerator value of the frequency division ratio set by the direct digital synthesizer. A direct digital synthesizer (12) that outputs a trigger clock input within an operable frequency range at an arbitrary frequency,
A band pass filter (13) for limiting a pass band of a trigger clock output from the direct digital synthesizer,
A strobe signal is generated using a phase shift function of the direct digital synthesizer of a trigger circuit (2) including a variable frequency divider (14) that divides a trigger clock whose pass band is limited by the band pass filter. In the trigger generation method,
Fixing the pass frequency range of the bandpass filter below an octave;
The value of the denominator of the frequency tuning word of the direct digital synthesizer is a power of 2, and the frequency tuning word is approximated to a value obtained by dividing the center frequency of the bandpass filter by the input frequency of the direct digital synthesizer. The step of setting the value of
And a step of setting a frequency division ratio of the variable frequency divider to a common multiple of a pattern length and a numerator value of the frequency division ratio set by the direct digital synthesizer. A sampling oscilloscope, wherein data is sequentially sampled by a sampler (3) at a sampling timing based on the strobe signal output from the trigger circuit (2) of claim 1. A sampling method comprising the step of sequentially sampling data by a sampler (3) at a sampling timing based on the strobe signal output from the trigger generating method according to claim 2.

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