JP6681616B2 - A / D converter, image sensor device, and method for generating digital signal from analog signal - Google Patents

Description

  The present invention relates to an A / D converter, an image sensor device and a method for generating a digital signal from an analog signal.

  Patent Document 1 describes an A / D converter. In this A / D converter, an integration type (or folding integration type) A / D conversion operation is performed on the input analog signal, and a cyclic operation is performed on the residual analog signal of the folding integration type A / D conversion. A type A / D conversion operation is performed. In the folding integration type A / D conversion, a digital signal is obtained from an analog signal by performing an operation for A / D conversion while repeating sampling of an input signal and integration of sample values.

International publication 2012/111821

  In the A / D converter described in Patent Document 1, the dynamic range is expanded by the folding operation while reducing noise by integration. The number of integration operations for the input signal affects the performance of the A / D converter such as the dynamic range. Therefore, it has been desired to speed up the integration operation of the A / D converter.

  Therefore, an object of the present invention is to improve the performance of the A / D converter by speeding up the integration operation.

  One aspect of the present invention is a single-ended A / D converter, which has an input for receiving an analog signal converted into a digital value, an output for outputting a first operation value and a second operation value, and Using a gain stage having an operational amplifier circuit including a first input, a second input and an output, one of the first operational value and the second operational value, and the conversion reference voltage, one or more bits An A / D conversion circuit that generates a digital signal including a signal, a logic circuit that generates a control signal using the digital signal, a clock generation circuit that generates a clock signal, and a first output and a second output. Then, a D / A conversion circuit that provides at least one of the first reference voltage and the second reference voltage to the gain stage via the first output and the second output using the control signal. And The gain stage includes a pre-capacitance section including a first capacitance section and a second capacitance section, a second input of the operational amplifier circuit receives a reference potential, and a first reference reference voltage is a second reference voltage. Above the reference voltage, the gain stage includes a switch circuit that utilizes the clock signal to connect one of the first capacitance section and the second capacitance section to the first input of the operational amplifier circuit. , The other of the first capacitance section and the second capacitance section is connected to the reference potential, and the A / D converter generates the first calculation value by the first A / D conversion operation and the second calculation. A second A / D conversion operation for generating a value, and in the first A / D conversion operation, the gain stage performs the first storage operation and the first arithmetic operation in parallel. The first operation and the second operation of performing the second storing operation and the second arithmetic operation in parallel are alternately performed, and the first operation In the storing operation, the analog signal supplied from the input is stored in the first capacitance section, and in the first arithmetic operation, the first arithmetic value based on the second capacitance section is generated at the output of the gain stage. In the second storage operation, the analog signal supplied from the input is stored in the second capacitance section, and in the second calculation operation, the first calculation value based on the first capacitance section is generated at the output of the gain stage. , In the second A / D conversion operation, the gain stage alternately performs the third operation of performing the third storing operation and the fourth operation of performing the fourth arithmetic operation to obtain the third storing operation. In the operation, the first calculated value or the second calculated value is stored in the pre-stage capacitance section, and in the fourth calculation operation, the second calculated value based on the pre-stage capacitance section is generated at the output of the gain stage.

  According to this A / D converter, the first A / D conversion operation for performing the folding integral type A / D conversion and the cyclic type A / D conversion are performed by controlling the operation procedure in the same circuit configuration. A second A / D conversion operation for performing / D conversion is realized. Here, in the first A / D conversion operation, the gain stage performs the first storage operation and the first arithmetic operation in parallel, and the second storage operation and the second arithmetic operation. And the second operation which is performed in parallel are alternately performed. According to this operation, the storing operation and the arithmetic operation are performed in parallel, so that the number of processes per clock increases. Therefore, since the integration operation in the A / D converter is speeded up, the performance of the A / D converter can be improved.

  The first capacitance section includes a first capacitor, the second capacitance section includes a second capacitor, the gain stage includes a third capacitor, and the first storage operation includes the first capacitor. Is connected between the input of the gain stage and the reference potential, whereby the analog signal is stored in the first capacitor, and in the first arithmetic operation, the second capacitor is connected to the second capacitor of the D / A conversion circuit. The second capacitor is connected between the output and the first input of the operational amplifier circuit, and the third capacitor is connected between the output of the operational amplifier circuit and the first input of the operational amplifier circuit. A first calculated value based on the capacitor of is generated at the output of the gain stage, and in the second storing operation, the second capacitor is connected between the input of the gain stage and the reference potential, thereby providing an analog signal. Second capacitor In the second arithmetic operation, the first capacitor is connected between the first output of the D / A conversion circuit and the first input of the operational amplifier circuit, and the third capacitor is operational amplified in the second arithmetic operation. By connecting between the output of the circuit and the first input of the operational amplifier circuit, a first calculated value based on the first capacitor is generated at the output of the gain stage, and in the third storing operation, The first capacitor and the second capacitor are connected between the output of the operational amplifier circuit and the reference potential, and the third capacitor is connected between the output of the operational amplifier circuit and the first input of the operational amplifier circuit. Accordingly, the first calculated value or the second calculated value is stored in the first capacitor and the second capacitor, and in the fourth arithmetic operation, the first capacitor outputs the first output of the D / A conversion circuit. Connected to the first input of the operational amplifier circuit. , The second capacitor is connected between the second output of the D / A conversion circuit and the first input of the operational amplifier circuit, and the third capacitor is the output of the operational amplifier circuit and the first input of the operational amplifier circuit. A second calculated value based on the first capacitor and the second capacitor may be generated at the output of the gain stage by being connected to the input.

  According to this A / D converter, the storage operation and the arithmetic operation are performed in parallel, so that the number of processes per clock increases. Therefore, since the integration operation in the A / D converter is speeded up, the performance of the A / D converter can be improved.

    The first capacitance unit includes a first capacitor and a fourth capacitor, the second capacitance unit includes a second capacitor and a fifth capacitor, the gain stage includes a third capacitor, In the first storage operation, the first capacitor is connected between the input of the gain stage and the second input of the operational amplifier circuit, so that the analog signal is stored in the first capacitor and the first operation operation is performed. Then, the second capacitor is connected between the first output of the D / A conversion circuit and the first input of the operational amplifier circuit, and the third capacitor is the output of the operational amplifier circuit and the first input of the operational amplifier circuit. Is connected to the input of the gain capacitor, a first calculated value based on the second capacitor is generated at the output of the gain stage, and in the second storing operation, the second capacitor is calculated from the input of the gain stage. Second amplifier circuit By being connected to the input, the analog signal is stored in the second capacitor, and in the second arithmetic operation, the first capacitor causes the first output of the D / A conversion circuit and the first output of the operational amplifier circuit to change. The third capacitor connected between the output of the operational amplifier circuit and the first input of the operational amplifier circuit so that the first calculated value based on the first capacitor is connected. Is generated at the output of the gain stage, and the third operation of the second A / D conversion operation further includes a third arithmetic operation performed in parallel with the third storage operation. The fourth operation of the converting operation further includes a fourth storing operation performed in parallel with the fourth arithmetic operation, and in the third storing operation, the first capacitor and the fourth capacitor are the operational amplifier circuit. To be connected between the output and the second input of the operational amplifier circuit Therefore, the first calculated value or the second calculated value is stored in the first capacitor and the fourth capacitor, and in the third calculation operation, the second capacitor becomes the first output of the D / A conversion circuit. A fifth capacitor connected between the first input of the operational amplifier circuit and a fifth capacitor connected between the second output of the D / A conversion circuit and the first input of the operational amplifier circuit; Is connected between the output of the operational amplifier circuit and the first input of the operational amplifier circuit to generate a second operation value at the output of the gain stage, and in the fourth storage operation, the second capacitor And the fifth capacitor is connected between the output of the operational amplifier circuit and the second input of the operational amplifier circuit, whereby the second calculated value is stored in the second capacitor and the fifth capacitor, and In the arithmetic operation of No. 4, the first capacitor is the first capacitor of the D / A conversion circuit. 1 is connected to the first input of the operational amplifier circuit, and a fourth capacitor is connected between the second output of the D / A conversion circuit and the first input of the operational amplifier circuit, The second calculated value may be generated at the output of the gain stage by connecting the third capacitor between the output of the operational amplifier circuit and the first input of the operational amplifier circuit.

  In this A / D converter, in the second A / D conversion operation, the gain stage performs a third storage operation and a third arithmetic operation in parallel, a fourth storage operation, and a third storage operation. The fourth operation, which performs the fourth arithmetic operation in parallel, and the fourth operation are performed alternately. According to this operation, the storage operation and the arithmetic operation in the second A / D conversion operation are performed in parallel, so that the number of processes per clock increases. Therefore, the performance of the A / D converter can be further improved.

  Another aspect of the present invention is an image sensor device. The image sensor device includes a cell array including an array of image sensor cells and a converter array connected to the cell array and including a plurality of A / D converters, each A / D converter being a column of the cell array. Each of the A / D converters is connected to the image sensor cell via a wire, and is the above-mentioned A / D converter. According to this image sensor device, since the A / D converter is a single-ended type, the area of the image sensor device can be reduced.

  Yet another aspect of the present invention is a method of generating a digital signal from an analog signal using the A / D converter described above. According to this method, a first storing step as a first storing operation of storing an analog signal supplied from an input in a first capacitance section, and a gain calculation of a first calculated value based on a second capacitance section And a second storing operation for storing the analog signal supplied from the input in the second capacitance section. Second storage step as a second calculation step and a second calculation step as a second calculation operation for generating a first calculation value based on the first capacitance section at the output of the gain stage. And the integration type A / D conversion step in which the first step and the second step are repeated a predetermined number of times, and the residual analog signal which is the first calculation value in the integration type A / D conversion step Motion to store And a fourth calculation step as a fourth calculation operation for generating a second calculation value based on the preceding capacitance section at the output of the gain stage, and a second calculation A fifth step of performing a third storage step as a third storage operation of storing a value in the preceding-stage capacitance section, and a cyclic A / D conversion step of repeating the fourth step and the fifth step a predetermined number of times. And.

  According to this method, the input analog signal is A / D converted by folding integration and the residual analog signal is cyclic A / D converted using the single-ended A / D converter. , A digital signal corresponding to an analog signal is generated from the results of both A / D conversions. Here, in the A / D conversion by folding integration, the first operation that performs the first storage operation and the first arithmetic operation in parallel, and the second operation that performs the second storage operation and the second arithmetic operation in parallel The operation 2 and the operation 2 are alternately performed. According to this operation, the storing operation and the arithmetic operation are performed in parallel, so that the number of processes per clock increases. Therefore, since the integration operation in the A / D converter is speeded up, the performance of the A / D conversion operation can be improved.

  According to the present invention, the performance of the A / D converter is improved by speeding up the integration operation.

FIG. 1 is a diagram showing a circuit block of an A / D converter according to the first embodiment. FIG. 2 is a diagram showing operations of integral type A / D conversion and cyclic type A / D conversion executed in the A / D converter shown in FIG. FIG. 3 is a diagram showing an operation of integral type A / D conversion in the A / D converter shown in FIG. FIG. 4 is a diagram showing an operation of cyclic A / D conversion in the A / D converter shown in FIG. FIG. 5 is a diagram showing a circuit block of the A / D converter according to the second embodiment. FIG. 6 is a diagram showing operations of integral type A / D conversion and cyclic type A / D conversion executed in the A / D converter shown in FIG. FIG. 7 is a diagram showing an operation of integral type A / D conversion in the A / D converter shown in FIG. FIG. 8 is a diagram showing the operation of cyclic A / D conversion in the A / D converter shown in FIG. FIG. 9 is a diagram showing an image sensor cell.

<First Embodiment>
The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the A / D converter, the image sensor device, and the method for generating a digital signal from an analog signal of the present invention will be described with reference to the accompanying drawings. If possible, the same parts are designated by the same reference numerals.

  FIG. 1 is a circuit diagram of the A / D converter 11 according to the first embodiment. The A / D converter 11 performs a first A / D conversion operation, which is so-called folding integral A / D conversion, and a second A / D conversion operation, which is cyclic A / D conversion, in the same circuit. Implement using the configuration. The A / D converter 11 realizes the first A / D conversion operation and the second A / D conversion operation by changing the time-series control pattern of the switch included in the A / D converter 11.

  The A / D converter 11 includes a gain stage 15, an A / D conversion circuit 17, a logic circuit 19, and a D / A conversion circuit 21. The A / D converter 11 also includes a reference voltage generation circuit 37 and a clock generator (clock generation circuit) 41.

The gain stage 15 includes an input 15a and an output 15b. The input 15a receives the analog signal V _IN which is converted into a digital value. The output 15b provides a first calculated value V _OP1 and a second calculated value V _OP2 . In addition, the gain stage 15 includes the pre-capacitance unit 20, a single end type operational amplifier circuit 23, and a switch circuit 60.

  The pre-stage capacitance section 20 includes a first capacitor 25 as a first capacitance section and a second capacitor 27 as a second capacitance section. The gain stage 15 also includes a third capacitor 29 as a feedback capacitance of the operational amplifier circuit 23.

The first capacitor 25, the second capacitor 27, and the third capacitor 29 are capacitors for storing and calculating various signal values. Here, the capacitance C ₂ of the third capacitor 29 is larger than the capacitance C _1a of the first capacitor 25. The capacitance C ₂ of the third capacitor 29 is larger than the capacitance C _1b of the second capacitor 27. As a result, the analog signal V _OP1 input in the first A / D conversion operation, which is the folding integral type A / D conversion, is attenuated according to the capacitance ratio (C _1a / C ₂ , C _1b / C ₂ ). Integrated. Therefore, the voltage range of the analog signal V _IN output in the folding integral type A / D conversion also becomes smaller according to the capacitance ratio between the first capacitor 25 and the second capacitor 27, so that the A / D is achieved by the single-ended configuration. The converter 11 can be constructed.

The capacity of the third capacitor 29 is twice the capacity of the first capacitor 25 or the capacity of the second capacitor 27. That is, the relationship of C _1a = 1/2 × C ₂ and C _1b = 1/2 × C ₂ is established. According to the A / D converter 11 including the first capacitor 25 and the second capacitor 27, the analog signal V _IN input in the folding integral type A / D conversion is attenuated to ½. Sampled and integrated. Therefore, the voltage range of the first calculation value V _OP1 , which is an analog signal output in the folding integral type A / D conversion, is also halved according to the capacitance ratio between the first capacitor 25 and the second capacitor 27. . Therefore, in the second A / D conversion operation which is the cyclic A / D conversion, the input voltage suitable for the A / D converter having the single end configuration is provided.

The operational amplifier circuit 23 includes a first input 23a, an output 23b, and a second input 23c. The first input 23a is an inverting input terminal. The second input 23c is a non-inverting input terminal. The output 23b is an output terminal. Therefore, the phase of the signal at the output 23b is the inverse of the phase of the signal provided at the first input 23a. The second input 23c is connected to the reference potential line L _COM . The second input 23c receives the reference potential V _COM .

The gain stage 15 includes a plurality of switches 43, 47, 49, 51, 53, 55, 57, 59, 61, 63, 67. The arrangement of the switches 43, 47, 49, 51, 53, 55, 57, 59, 61, 63, 67 shown in FIG. 1 is an example. The clock generator 41 controls the switches 43, 47, 49, 51, 53, 55, 57, 59, 61, 63 and 67. The switch circuit 60 includes switches 47, 49, 55, 57. The switch circuit 60 utilizes the clock signals (φ ₁₁ , φ ₂₁ , φ ₁₂ , and φ ₂₂ ) to connect one of the first capacitor 25 and the second capacitor 27 to the first input 23a of the operational amplifier circuit 23. Then, the other of the first capacitor 25 and the second capacitor 27 is connected to the reference potential line L _COM . Specifically, the switch 47 connects the first capacitor 25 to the reference potential line L _COM . The switch 49 connects the first capacitor 25 to the first input 23a of the operational amplifier circuit 23. The switch 55 connects the second capacitor 27 to the reference potential line L _COM . The switch 57 connects the second capacitor 27 to the first input 23a of the operational amplifier circuit 23.

The reference voltage sources 33 and 35 supply the reference voltage generation circuit 37 with the first reference reference voltage V _RH and the second reference reference voltage V _RL .

The reference voltage generation circuit 37 is based on at least one of the first reference reference voltage V _RH and the second reference reference voltage V _RL , and is at least one of the first conversion reference voltage V _RCH and the second conversion reference voltage V _RCL . To generate.

The A / D conversion circuit 17 receives the converted reference voltage V _RCH provided from the reference voltage generation circuit 37 based on the first calculated value V _OP1 or the second calculated value V _OP2 output from the output 15b of the gain stage 15. , V _RCL to generate a digital signal D. For example, in the first A / D conversion operation, the voltage V _RC1H is provided from the reference voltage generation circuit 37 to the A / D conversion circuit 17 as the first conversion reference voltage V _RCH . Further, in the second A / D conversion operation, the voltage V _RC2H is supplied from the reference voltage generation circuit 37 to the A / D conversion circuit 17 as the first conversion reference voltage V _RCH , and the second conversion reference voltage V _RCL is supplied. As a result, the voltage V _RC2L is supplied from the reference voltage generation circuit 37 to the A / D conversion circuit 17.

The logic circuit 19 generates a control signal V _CONT (for example, φ _DH , φ _DL , φ _DS ) according to the digital signal D.

The D / A conversion circuit 21 includes a first output 21a, a second output 21b, and a switch circuit 31. The D / A conversion circuit 21 operates at least one of the first reference reference voltage V _RH and the second reference reference voltage V _RL by the operation of the switch circuit 31 based on the control signal V _CONT to output the first output 21 a. And to the gain stage 15 via at least one of the second outputs 21b.

Here, the switch circuit 31 supplies the first reference reference voltage V _RH and the second reference reference voltage V _RL to the first output 21a and the second output 21b, respectively, by operating the switches 31a and 31b. . The switch circuit 31 supplies the first reference reference voltage _VRH to both the first output 21a and the second output 21b by operating the switches 31a and 31c. The switch circuit 31 supplies the second standard reference voltage V _RL to both the first output 21a and the second output 21b by operating the switches 31b and 31c. The first output 21a of the D / A conversion circuit 21 is connected to the one end 25a of the first capacitor 25 via the switch 63. The second output 21b of the D / A conversion circuit 21 is connected to the one end 27a of the second capacitor 27 via the switch 67. Since the opening and closing of the switches 31a, 31b, 31c are controlled by the control signals φ _DH , φ _DS , φ _DL from the logic circuit 19, the values of the digital signals B ₁ , B ₀ are the control signals φ _DH , φ. Determine which of _DS or φ _DL is active.

  As shown in FIG. 2, the gain stage 15 includes a first storage operation ST1a and a first arithmetic operation ST1b that are performed in parallel, a second storage operation ST2a, and a second arithmetic operation ST1b. The second operation ST2 in which ST2b is performed in parallel is alternately performed. Further, the gain stage 15 alternately performs the third operation ST3 that performs the third storage operation ST3a and the fourth operation ST4 that performs the fourth arithmetic operation ST4b.

In the first arithmetic operation ST1b and the second arithmetic operation ST2b, the operational amplifier circuit 23, the first capacitor 25, the second capacitor 27, and the third capacitor 29 generate the first arithmetic value V _OP1 .

In the first storage operation ST1a, the first capacitor 25 stores the analog signal V _IN supplied from the input 15a of the gain stage 15.

In the second storage operation ST2a, the second capacitor 27 stores the analog signal V _IN supplied from the input 15a of the gain stage 15.

In the first arithmetic operation ST1b, when the analog signal V _IN is stored in the second capacitor 27 in the second storage operation ST2a, the second capacitor 27 outputs the second output of the D / A conversion circuit 21. 21b and the first input 23a of the operational amplifier circuit 23 are connected. In the first arithmetic operation ST1b, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. By connecting the second capacitor 27, the third capacitor 29, and the operational amplifier circuit 23 described above, the first operational value V _OP1 is generated at the output 15b of the gain stage 15.

In the second arithmetic operation ST2b, the first capacitor 25 is connected between the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. In the second arithmetic operation ST2b, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23, as in the first arithmetic operation ST1b. It By connecting the first capacitor 25 and the third capacitor 29 described above to the operational amplifier circuit 23, the first operational value V _OP1 is generated at the output 15b of the gain stage 15.

  The gain stage 15 alternately performs the third operation ST3 for performing the third storage operation ST3a and the fourth operation ST4 for performing the fourth arithmetic operation ST4b.

In the third storage operation ST3a, the first calculated value V _OP1 or the second calculated value V _OP2 is stored in the first capacitor 25 and the second capacitor 27. In the fourth arithmetic operation ST4b, the operational amplifier circuit 23, the first capacitor 25, the second capacitor 27, and the third capacitor 29 generate the second arithmetic value V _OP2 . That is, in the fourth arithmetic operation ST4b, the first capacitor 25 is connected between the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23, and the second capacitor 25 is connected. 27 is connected between the second output 21b of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23, and the third capacitor 29 is connected to the output 23b of the operational amplifier circuit 23 and the operational amplifier circuit 23. Is connected to the first input 23a. With this circuit configuration, the second calculated value V _OP2 is generated at the output 15b of the gain stage 15.

  Next, with reference to FIGS. 2, 3 and 4, the first A / D conversion operation as the integral A / D conversion step performed in the A / D converter 11 and the cyclic A / D conversion The second A / D conversion operation as a step will be described.

  First, the first A / D conversion operation in the A / D converter 11 will be described. As shown in part (a) of FIG. 2, the first A / D conversion operation includes a first operation ST1 using the first capacitor 25 and a second operation ST2 using the second capacitor 27. Including ST2. That is, according to the A / D converter 11 shown in FIG. 1, the storage process and the arithmetic process included in the first A / D conversion operation are performed in parallel by the first capacitor 25 and the second capacitor 27. It is processed. Therefore, since the number of processes per clock can be increased, the integration operation in the A / D converter 11 can be speeded up.

  The storage operation and the arithmetic operation in each step described below are realized by the switch circuit 31 and the switches 43, 47, 49, 51, 53, 55, 57, 59, 61, 63, 67.

First, the A / D converter 11 performs the first initial storage step STf1. In this operation, clock signals (φ ₁₁ = 1, φ ₂₁ = 0, φ ₁₂ = 1, φ ₂₂ = 0, φ ₃ = 0, φ _R = 1 and φ _S = 1 and φ _Sl1 = 1 and φ _S12 = 0, φ _P1 = 0, φ _N1 = 1) makes the switches 43, 47, 55, 57, 59, 67 conductive and the switches 49, 51, 57, 61, 63 non-conductive.

According to the above clock signal, the gain stage 15 constitutes a circuit as shown in part (a) of FIG. Specifically, the first capacitor 25 is connected between the input 15a of the gain stage 15 and the reference potential line L _COM . The output 23b of the operational amplifier circuit 23 is connected to the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the analog signal V _IN received via the input 15 a of the gain stage 15 is stored in the first capacitor 25. Further, the second capacitor 27 is connected between the second output 21b of the D / A conversion circuit 21 and the reference potential line L _COM . According to this circuit configuration, the second reference reference voltage V _RL supplied from the second output 21 b of the D / A conversion circuit 21 is stored in the second capacitor 27. The third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23.

The charge (Q _1a ) accumulated in the first capacitor 25 (capacitance C _1a ) in the first initial storage step STf1 is represented by the equation (1).

Then, the A / D converter 11 performs the second operation ST2 as the second step. The second operation ST2 includes a second operation ST2b as a second operation step and a second storage operation ST2a as a second storage step. In this second step, clock signals (φ ₁₁ = 0, φ ₂₁ = 1, φ ₁₂ = 1, φ ₂₂ = 0, φ ₃ = 0, φ _R = 0, φ _S = 1, φ _S1 1 = 0, φ _S12 = 1, φ _P1 = 1, φ _N1 = 0), the switches 43, 49, 55, 61, 63 are made conductive, and the switches 47, 51, 53, 57, 59, 67 are made non-conductive. .

According to the above clock signal, the gain stage 15 constitutes a circuit as shown in part (b) of FIG. Specifically, the first capacitor 25 is connected between the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. The third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the first operation value V _OP1 corresponding to the analog signal V _IN stored in the first capacitor 25 is generated at the output 15b of the gain stage 15. That is, the second arithmetic operation ST2b as the second arithmetic step is performed.

In the second arithmetic operation ST2b performed following the first initial storage step STf1, D / A conversion circuit 21, the second standard reference voltage _{V RL} via the first output 21a and switching 63 1 The capacitor 25 is provided at one end 25a thereof. Note that such an operation is performed only in the second arithmetic operation ST2b performed subsequent to the first initial storage operation STf1. In the second and subsequent arithmetic operations, the D / A conversion circuit 21 operates based on the digital value generated by the A / D conversion circuit 17. This operation will be described later.

Then, the first calculation value V _OP1 generated in the second calculation operation ST2b is expressed by Expression (2A), and when the relationship between C _1a and C ₂ is Expression (2B), it is expressed by Expression (2C). Be done.

In the second step, the second capacitor 27 is connected between the input 15a of the gain stage 15 and the reference potential line L _COM . According to this circuit configuration, the analog signal V _IN received via the input 15 a of the gain stage 15 is stored in the second capacitor 27. That is, the second storage operation ST2a as the second storage step is performed. Charge stored in the second capacitor 27 (capacitance _{C 1b) (Q 1b)} is represented by the formula (3).

Then, the A / D converter 11 performs the first operation ST1 as the first step according to the value of the digital signal D (= B ₁ ). The first operation ST1 includes a first calculation operation ST1b as a first calculation step and a first storage operation ST1a as a first storage step. In this first step, clock signals (φ ₁₁ = 1, φ ₂₁ = 0, φ ₁₂ = 0, φ ₂₂ = 1 and φ ₃ = 0, φ _R = 0, φ _S = 1 and φ _S11 = 1, φ _Sl2 = 0, φ _P1 = 0, φ _N1 = 1), the switches 43, 47, 57, 59, 67 are made conductive, and the switches 49, 51, 53, 55, 61, 63 are made non-conductive. .

According to the above clock signal, the gain stage 15 constitutes a circuit as shown in part (c) of FIG. Specifically, the first capacitor 25 is connected between the input 15a of the gain stage 15 and the reference potential line L _COM . According to this circuit configuration, the analog signal V _IN received via the input 15 a of the gain stage 15 is stored in the first capacitor 25. That is, the first storage operation ST1a as the first storage step is performed.

The second capacitor 27 is connected between the second output 21b of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. Further, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the first operation value V _OP1 corresponding to the analog signal V _IN stored in the second capacitor 27 is generated at the output 15b of the gain stage 15. That is, the first calculation operation ST1b as the first calculation step is performed.

In the first arithmetic operation ST1b, the A / D conversion circuit 17 uses one comparator 17a to generate the digital signal D. In this case, the digital signal D has only 1 bit (B ₁ ) and can represent two values. The signal used as a reference in the comparator 17a is the conversion reference voltage V _RC1H . The comparator 17a operates as follows.
When V _OP1 , V _OP2 > V _RC1H , B ₁ = 1
When V _OP1 and V _OP2 ≦ V _RC1H B ₁ = 0

The D / A conversion circuit 21 performs the following control according to the control signal V _CONT based on the digital signal B ₁ from the comparator 17a.
When B ₁ = 1: V _DA1 = V _RH , V _DA2 = V _RL
When B ₁ = 0: V _DA1 = V _DA2 = V _RL

The first calculation value V _OP1 generated in the first calculation operation ST1b is expressed by Expression (4A), and is expressed by Expression (4C) when the relationship between C _1b and C ₂ is Expression (4B). ΔV _R in formula (4C) is shown by the following formula (4D).

  Then, according to the value of the digital signal D (2), the A / D converter 11 performs the second operation ST2 as the second step shown in part (b) of FIG. That is, the A / D converter 11 performs the integral type A / D conversion step in which the first step and the second step are repeated a predetermined number of times. Specifically, in the integration type A / D conversion step, the second step is executed after the first initial storage operation STf1. In this second step, the second storage operation ST2a is executed simultaneously with the second arithmetic operation ST2b. After the second step, the first step is executed. In this first step, the first storage operation ST1a is executed at the same time as the first arithmetic operation ST1b. Then, the second step is executed again. In this second step, the second storage operation ST2a is executed simultaneously with the second arithmetic operation ST2b. As described above, in the integration type A / D conversion step, the first step ST1 and the second step ST2 are repeated.

In the first A / D conversion operation, the first calculation step V _OP1 when the first calculation step and the first storage step are repeated M times to perform sampling and integration are shown by the equation (5A). Be done. ΔV _R in formula (5A) is shown by the following formula (5B).

The above description is an example in which the second reference voltage V _RL is adopted as the reference voltage V _RI in the second arithmetic operation performed subsequent to the first initial storage operation STf1. On the other hand, the first standard reference voltage V _RH may be adopted as the reference voltage V _RI in the second arithmetic operation performed subsequent to the first initial storage operation STf1.

  Next, with reference to FIG. 2 and FIG. 4, a second A / D conversion operation as a cyclic A / D conversion step in the A / D converter 11 will be described. As shown in part (b) of FIG. 2, the second A / D conversion operation includes a third operation ST3 as a third step using the first capacitor 25 and the second capacitor 27, and It includes a fourth operation ST4 as a fourth step.

First, the A / D converter 11 performs the third operation ST3 as the third step. The third operation ST3 includes a third storage operation ST3a as the second initial storage step STf2. In the third step, clock signals (φ ₁₁ = 1, φ ₂₁ = 0, φ ₁₂ = 1, φ ₂₂ = 0, φ ₃ = 1, φ _R = 0, φ _S = 0, φ _S1 1 = 1, φ _Sl2 = 1, φ _P1 = 0, φ _N1 = 0), the switches 47, 51, 55, 59, 61 are made conductive, and the switches 43, 49, 53, 57, 63, 67 are made non-conductive. .

According to the above clock signal, the gain stage 15 constitutes a circuit as shown in part (a) of FIG. Specifically, the first capacitor 25 is connected between the output 23b of the operational amplifier circuit 23 and the reference potential line L _COM . The second capacitor 27 is connected between the output 23b of the operational amplifier circuit 23 and the reference potential line L _COM . The third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. One end 29a of the third capacitor 29 is connected to one end 25a of the first capacitor 25 via the switches 51 and 59. One end 29a of the third capacitor 29 is also connected to one end 27a of the second capacitor 27 via the switches 51 and 61. According to this circuit configuration, the first calculated value V _OP1 which is the residual analog signal accumulated in the third capacitor 29 is stored in the first capacitor 25 and the second capacitor 27. That is, the third storage operation ST3a as the third storage step is performed.

Further, the first calculation value V _OP1 is provided to the comparators 17a and 17b via the output 15b of the gain stage 15. The comparators 17a and 17b generate digital signals B ₁ and B ₀ based on the provided first operation value V _OP1 . The generation of the digital values B ₁ and B ₀ will be described later.

Then, following the third operation ST3, the A / D converter 11 performs the fourth operation ST4 as the fourth step in accordance with the value of the digital signal D (= B ₁ + B ₀ ). The fourth operation ST4 includes a fourth operation ST4b as a fourth operation step. In the fourth step, clock signals (φ ₁₁ = 0, φ ₂₁ = 1, φ ₁₂ = 0, φ ₂₂ = 1 and φ ₃ = 0, φ _R = 0, φ _S = 0, φ _{S1 1} = 0, φ _S12 = 0, φ _P = 1, φ _N = 1), the switches 49, 57, 63, 67 are made conductive, and the switches 43, 47, 51, 53, 55, 59, 61 are made non-conductive. .

According to the above clock signal, the first capacitor 25, the second capacitor 27, the third capacitor 29, and the operational amplifier circuit 23 constitute a circuit as shown in part (b) of FIG. . Specifically, the first capacitor 25 is connected between the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. The second capacitor 27 is connected between the second output 21b of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. The third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the operational amplifier circuit 23, the first capacitor 25, the second capacitor 27, and the third capacitor 29 generate the second operation value V _OP2 . That is, the fourth arithmetic operation ST4b as the fourth arithmetic step is performed.

Here, the switch circuit 31 is controlled by the first output 21a and the second output 21b of the D / A conversion circuit 21 in accordance with the digital signal D (= B ₁ + B ₀ ) from the comparators 17a and 17b. Reference voltage V _RH or second reference voltage V _RL .

The comparators 17a and 17b are included in the A / D conversion circuit 17. The comparator 17a provides the comparison result signal B ₁ by comparing the input analog signal (for example, the first calculated value V _OP1 or the second calculated value V _OP2 ) with the first conversion reference voltage V _RC2H . The comparator 17b also provides the comparison result signal B ₀ by comparing the input analog signal with the second conversion reference voltage V _RC2L . The converted reference voltages V _RC2H and V _RC2L are provided from the reference voltage generation circuit 37. The digital signal D indicates an A / D converted value. The digital signal D has, for example, 2 bits (B ₀ , B ₁ ) and each bit (B ₀ , B ₁ ) can take “1” or “0”. The digital signal D is represented by (D = B ₀ + B ₁ ). In the A / D converter 11, depending on the combination of bits (B ₀ , B ₁ ), the digital value for each one-time integration operation or one cycle is the first value (D = 0) and the second value (D = 1). ) And a third value (D = 2). That is, the comparators 17a and 17b operate as follows.
When V _OP1 and V _OP2 > V _RC2H , D = 2 (B ₁ = 1 and B ₀ = 1)
When V _RC2L <V _OP1 , V _OP2 ≤ V _RC2H , D = 1 (B ₁ = 0, B ₀ = 1)
When V _OP1 and V _{OP2 ≤V RC2L} D = 0 (B ₁ = 0, B ₀ = 0)

When the digital signal is “D = 2”, the first output 21a and the second output 21b of the D / A conversion circuit 21 are controlled so as to provide the first reference reference voltage V _RH, while the control signal of FIG. The operation shown in part (b) is performed. On the other hand, when the digital signal is “D = 0”, it is controlled so that the first output 21a and the second output 21b of the D / A conversion circuit 21 provide the second reference voltage V _RL . The operation shown in part (b) of 4 is performed. Furthermore, when the digital signal is “D = 1”, the first reference reference voltage V _RH and the second reference reference voltage V _RL are output from the first output 21a and the second output 21b of the D / A conversion circuit 21, respectively. The operation shown in part (b) of FIG.

When one comparator 17a is used in the first A / D conversion operation, the reference voltage generation circuit 37 outputs the voltage V _RC1H based on the first reference reference voltage V _RH and the second reference reference voltage V _RL. To generate. Further, when the two comparators 17a and 17b are used in the second A / D conversion operation, the reference voltage generation circuit 37 determines the reference voltage _VRH and the second reference voltage _VRL based on the first reference voltage _VRH and the second reference voltage _VRL . The voltages V _RC2H and V _RC2L are generated. The reference voltage generation circuit 37 includes a first reference reference voltage V _RH and a second reference reference voltage V _RL , a first converted reference voltage V _RC1H in the first A / D conversion operation, and a second A / D. a first conversion reference voltage _{V RC2H} and second conversion reference voltage _{V RC2L,} is related to the operation as shown below in D conversion operation. Thus the first conversion reference voltage _{V RC1H} at the first A / D conversion operation, first conversion reference voltage _{V RC2H} and second conversion reference voltage _{V RC2L} in the second A / D conversion operation generated Therefore, the first A / D conversion operation and the second A / D conversion operation are appropriately performed.
V _RC1H = (V _RH + V _RL ) / 2
(V _RH + V _RL ) / 2 <V _RC2H <V _RH
V _RL <V _RC2L <(V _RH + V _RL ) / 2

When the two comparators 17a and 17b are used, the switch circuit 31 of the D / A conversion circuit 21 is responsive to the control signal V _CONT to output the first reference reference voltage V _RH and the second reference voltage V _RH to the first output 21a. Of the reference reference voltage V _RL . In addition, the switch circuit 31 provides either the first reference reference voltage V _{RH or} the second reference reference voltage V _{RL to} the second output 21b in response to the control signal V _CONT .

When the voltage provided to the first output 21a is V _DA1 and the voltage provided to the second output 21b is V _DA2 , the D / A conversion circuit 21 responds to the control signal V _CONT from the logic circuit 19. Then, for example, the following control is performed.
When the first condition (D = 2) is satisfied: V _DA1 = V _DA2 = V _RH
When the second condition (D = 1) is satisfied: V _DA1 = V _RH , V _DA2 = V _RL
When the third condition (D = 0) is satisfied: V _DA1 = V _DA2 = V _RL

Subsequently, the gain stage 15 performs the third storage operation ST3a as the third storage step shown in part (a) of FIG. 4 subsequent to the fourth calculation operation ST4b. In the third storage operation ST3a, the second operation value V _OP2 in the fourth operation operation ST4b is stored in the first capacitor 25 and the second capacitor 27.

  Then, the gain stage 15 repeats the third operation ST3 and the fourth operation ST4 a predetermined number of times as a cyclic A / D conversion operation.

According to this A / D converter 11, the analog signal V _IN is alternately sampled (stored) by the first capacitor 25 and the second capacitor 27, so that the integration operation is performed for the same A / D conversion time. By increasing the number of times to about twice and doubling the gain in the cyclic A / D conversion operation, a faster and lower noise A / D conversion operation can be realized.

<Second Embodiment>
Next, an A / D converter according to the second embodiment and a method of generating a digital signal from an analog signal using the A / D converter will be described.

  FIG. 5 is a circuit diagram of the A / D converter 11A according to the second embodiment. Similar to the A / D converter 11 according to the first embodiment, the A / D converter 11A includes a first A / D conversion operation that is a so-called folding integral A / D conversion and a cyclic A / D conversion operation. The second A / D conversion operation, which is D conversion, is performed using the same circuit configuration. The pre-stage capacitance section 20A of the gain stage 15A includes a first capacitance section including a first capacitor 25 and a fourth capacitor 26, a second capacitance section including a fourth capacitor 26 and a fifth capacitor 28, Have. The gain stage 15A of the A / D converter 11A further includes switches 67, 69, 71, 73. According to the gain stage 15A including such a configuration, the storage operation and the arithmetic operation in the integration type A / D conversion operation can be performed in parallel. Further, according to the gain stage 15A, the storage operation and the arithmetic operation in the cyclic A / D conversion operation can be performed in parallel.

  The arrangement of the added switches 67, 69, 71, 73 shown in FIG. 5 is an example. The control of these switches 67, 69, 71, 73 is performed by the clock generator 41. The switch 63 connects the first capacitor 25 to the first output 21a of the D / A conversion circuit 21. The switch 67 connects the second capacitor 27 to the first output 21a of the D / A conversion circuit 21. The switch 65 connects the fourth capacitor 26 to the second output 21b of the D / A conversion circuit 21. The switch 69 connects the fifth capacitor 28 to the second output 21b of the D / A conversion circuit 21. The switch 71 connects one end 25a of the first capacitor 25 to one end 26a of the fourth capacitor 26. The switch 73 connects one end 27a of the second capacitor 27 to one end 28a of the fifth capacitor 28.

  As shown in part (b) of FIG. 6, in the operation performed by the gain stage 15A, the third operation ST3 further includes a third arithmetic operation ST3b that is performed in parallel with the third storage operation ST3a. The fourth operation ST4 further includes a fourth storage operation ST4a performed in parallel with the fourth arithmetic operation ST4b.

In the first arithmetic operation ST1b and the second arithmetic operation ST2b, the operational amplifier circuit 23, the first capacitor 25, the second capacitor 27, and the third capacitor 29 generate the first arithmetic value V _OP1 .

In the first storage operation ST1a, the first capacitor 25 is connected between the input 15a of the gain stage 15A and the reference potential line L _COM . According to this circuit configuration, the analog signal V _IN supplied from the input 15a of the gain stage 15A is stored in the first capacitor 25.

In the first arithmetic operation ST1b performed in parallel with the first storage operation ST1a, the second capacitor 27 is connected to the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. Connected between. In the first storing operation ST1a, the third capacitor 29 is connected to the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the first calculated value V _OP1 is generated at the output 15b of the gain stage 15A.

In the second storage operation ST2a, the second capacitor 27 is connected between the input 15a of the gain stage 15A and the reference potential line L _COM . According to this circuit configuration, the analog signal V _IN supplied from the input 15a of the gain stage 15A is stored in the second capacitor 27.

In the second arithmetic operation ST2b performed in parallel with the second storage operation ST2a, the first capacitor 25 is connected to the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. Connected between. In the second arithmetic operation ST2b, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23, as in the first arithmetic operation ST1b. It According to this circuit configuration, the first calculated value V _OP1 is generated at the output 15b of the gain stage 15A.

In the third storage operation ST3a, the first capacitor 25 is connected between the output 23b of the operational amplifier circuit 23 and the reference potential line L _COM . In addition, the fourth capacitor 26 is connected between the output 23b of the operational amplifier circuit 23 and the reference potential line L _COM . According to this circuit configuration, the first calculated value V _OP1 or the second calculated value V _OP2 is stored in the first capacitor 25 and the fourth capacitor 26.

In the third arithmetic operation ST3b performed in parallel with the third storage operation ST3a, the second capacitor 27 connects the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. Connected between. Further, the fifth capacitor 28 is connected between the second output 21b of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. Further, in the third arithmetic operation ST3b, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the second calculated value V _OP2 is generated at the output 15b of the gain stage 15A.

In the fourth storage operation ST4a, the second capacitor 27 is connected between the output 23b of the operational amplifier circuit 23 and the reference potential line L _COM . Further, the fifth capacitor 28 is connected between the output 23b of the operational amplifier circuit 23 and the reference potential line L _COM . According to this circuit configuration, the second calculated value V _OP2 is stored in the first capacitor 25 and the fourth capacitor 26.

In the fourth arithmetic operation ST4b performed in parallel with the fourth storage operation ST4a, the first capacitor 25 is connected to the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. Connected between. Further, the fourth capacitor 26 is connected between the second output 21b of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. Further, in the fourth arithmetic operation ST4b, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the second calculated value V _OP2 is generated at the output 15b of the gain stage 15A.

  Next, with reference to FIG. 7, a first A / D conversion operation as an integral A / D conversion step performed in the A / D converter 11A and a second A / D conversion step as a cyclic A / D conversion step. The A / D conversion operation will be described.

  First, the first A / D conversion operation in the A / D converter 11A will be described. Part (a) of FIG. 6 shows the first A / D conversion operation performed in the gain stage 15A. The storing operation and the arithmetic operation in each step described below are realized by the switches 43, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73.

The A / D converter 11A performs a first operation ST1 as a first step. Specifically, the A / D converter 11A performs the first storage operation STf1 as the first initial storage step. The gain stage 15A includes clock signals (φ ₁₁ = 1, φ ₂₁ = 0, φ ₁₂ = 0, φ ₂₂ = 0, φ ₃ = 0, φ _R = 1 and φ _S = 1 and φ _S11 = 1 and φ _S12 = 0, φ _P1 = 0, φ _N1 = 0, φ _P2 = 0, φ _N2 = 0, φ _M1 = 0, φ _M2 = 0) are input. According to this clock signal, the switches 43, 47, 53, 59 are rendered conductive, and the switches 49, 51, 55, 57, 61, 63, 65, 67, 69, 71, 73 are rendered non-conductive.

According to the clock signal described above, the gain stage 15A constitutes a circuit as shown in part (a) of FIG. Specifically, the first capacitor 25 is connected between the input 15a of the gain stage 15A and the reference potential line L _COM . The output 23b of the operational amplifier circuit 23 is connected to the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the analog signal V _IN received via the input 15a of the gain stage 15A is stored in the first capacitor 25.

The charge (Q _1a ) accumulated in the first capacitor 25 (capacitance C _1aa ) forming the first capacitance section in the first initial storage step STf1 is represented by the equation (6).

Then, the A / D converter 11A performs the second operation ST2 as the second step according to the value of the digital signal D (= B ₁ ). The second operation ST2 includes a second operation ST2b as a second operation step and a second storage operation ST2a as a second storage step. The gain stage 15A includes clock signals (φ ₁₁ = 0, φ ₂₁ = 1, φ ₁₂ = 1, φ ₂₂ = 0, φ ₃ = 0, φ _R = 0, φ _S = 1, φ _S1 1 = 0, φ _S12 = 1, φ _P1 = 1, φ _N1 = 0, φ _P2 = 0, φ _N2 = 0, φ _M1 = 0, φ _M2 = 0) is input. According to this clock signal, the switches 43, 49, 55, 61, 63 are rendered conductive, and the switches 47, 51, 57, 53, 59, 65, 67, 69, 71, 73 are rendered non-conductive.

According to the above clock signal, the gain stage 15A constitutes a circuit as shown in part (b) of FIG. Specifically, the first capacitor 25 is connected between the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. In addition, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the first operation value V _OP1 corresponding to the analog signal V _IN stored in the first capacitor 25 is generated at the output 15b of the gain stage 15A. That is, the second arithmetic operation ST2b as the second arithmetic step is performed.

Further, according to the above clock signal, the second capacitor 27 is connected between the input 15a of the gain stage 15A and the reference potential line L _COM . According to this circuit configuration, the analog signal V _IN received via the input 15a of the gain stage 15A is stored in the second capacitor 27. That is, the second storage operation ST2a as the second storage step is performed.

Then, the A / D converter 11A performs the first operation ST1 as the first step according to the value of the digital signal D (= B ₁ ). The first operation ST1 includes a first calculation operation ST1b as a first calculation step and a first storage operation ST1a as a first storage step. The gain stage 15A includes clock signals (φ ₁₁ = 1, φ ₂₁ = 0, φ ₁₂ = 0, φ ₂₂ = 1 and φ ₃ = 0, φ _R = 0, φ _S = 1 and φ _Sl1 = 1 and φ _S12 = 0, φ _P1 = 0, φ _N1 = 0, φ _P2 = 1, φ _N2 = 0, φ _M1 = 0, φ _M2 = 0) are input. According to this clock signal, the switches 43, 47, 57, 59, 67 are made conductive, and the switches 49, 51, 53, 55, 61, 63, 65, 69, 71, 73 are made non-conductive.

According to the above clock signal, the gain stage 15A constitutes a circuit as shown in part (c) of FIG. Specifically, the first capacitor 25 is connected between the input 15a of the gain stage 15A and the reference potential line L _COM . According to this circuit configuration, the analog signal V _IN received via the input 15a of the gain stage 15A is stored in the first capacitor 25. That is, the first storage operation ST1a as the first storage step is performed.

Further, the second capacitor 27 is connected between the first output 21 a of the D / A conversion circuit 21 and the first input 23 a of the operational amplifier circuit 23. The third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the first operation value V _OP1 corresponding to the analog signal V _IN stored in the second capacitor 27 is generated at the output 15b of the gain stage 15A. That is, the first calculation operation ST1b as the first calculation step is performed.

Then, according to the value of the digital signal D (= B ₁ ), the A / D converter 11A performs the second operation ST2 as the second step shown in part (b) of FIG. That is, the A / D converter 11A is an integral A / D converter that repeats the first step (see section (c) of FIG. 7) and the second step (see section (b) of FIG. 7) a predetermined number of times. Perform a conversion step.

In the first A / D conversion operation, the first operation value V _OP1 when the first operation step and the first storage step are repeated M times to perform sampling and integration is represented by the expression (7A). Be done. Further, C _1aa and C _1ba are represented by the following formulas (7B) and (7C). The folding integral type A / D conversion operation in the second embodiment is exactly the same as the folding integral type A / D conversion operation in the first embodiment. Therefore, the equation (7A) is exactly the same as the equation (5A).

  Next, the second A / D conversion operation as the cyclic A / D conversion step in the A / D converter 11A will be described. As shown in part (b) of FIG. 6, the second A / D conversion operation includes a third operation ST3 as a third step and a fourth operation ST4 as a fourth step.

First, the A / D converter 11A performs the third operation ST3 as the third step. The third operation ST3 includes a third storage operation ST3a as the second initial storage step STf2. The gain stage 15A includes clock signals (φ ₁₁ = 1, φ ₂₁ = 0, φ ₁₂ = 0, φ ₂₂ = 0, φ ₃ = 1, φ _R = 0, φ _S = 0, φ _Sl1 = 1 and φ _S12 = 0, φ _P1 = 0, φ _N1 = 0, φ _P2 = 0, φ _N2 = 0, φ _M1 = 1, φ _M2 = 0) are input. According to this clock signal, the switches 47, 51, 59, 71 are rendered conductive, and the switches 43, 49, 53, 55, 57, 61, 63, 65, 67, 69, 73 are rendered non-conductive.

According to the above clock signal, the gain stage 15A constitutes a circuit as shown in part (a) of FIG. Specifically, the first capacitor 25 and the fourth capacitor 26 are connected between the output 23b of the operational amplifier circuit 23 and the reference potential line L _COM . According to this circuit configuration, the first calculation value V _OP1 which is the residual analog signal is stored in the first capacitor 25 and the fourth capacitor 26. That is, the third storage operation ST3a as the third storage step is performed.

Then, the A / D converter 11A performs the fourth operation ST4 as the fourth step according to the value of the digital signal D (= B ₁ + B ₀ ). The fourth operation ST4 includes a fourth operation ST4b as a fourth operation step and a fourth storage operation ST4a as a fourth storage step. In the gain stage 15A, clock signals (φ ₁₁ = 0, φ ₂₁ = 1, φ ₁₂ = 1, φ ₂₂ = 0, φ ₃ = 1, φ _R = 0, φ _S = 0, φ _{S1 1} = 0, φ _S12 = 1, φ _P1 = 1, φ _N1 = 1, φ _P2 = 0, φ _N2 = 0, φ _M1 = 0, φ _M2 = 1) is input. According to this clock signal, the switches 49, 51, 55, 61, 63, 65, 73 are rendered conductive, and the switches 43, 47, 53, 57, 59, 67, 69, 71 are rendered non-conductive.

According to the above clock signal, the gain stage 15A constitutes a circuit as shown in part (b) of FIG. Specifically, the first capacitor 25 is connected between the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. Further, the fourth capacitor 26 is connected between the second output 21b of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. In addition, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the second calculated value V _OP2 is generated at the output 15b of the gain stage 15A. That is, the fourth arithmetic operation ST4b as the fourth arithmetic step is performed.

Further, the second capacitor 27 and the fifth capacitor 28 are connected between the output 23b of the operational amplifier circuit 23 and the reference potential line L _COM . According to this circuit configuration, the second calculated value V _OP2 is stored in the second capacitor 27 and the fifth capacitor. That is, the fourth storage operation ST4a as the fourth storage step is performed.

Then, the A / D converter 11A performs the third operation ST3 as the fifth step according to the value of the digital signal D (= B ₁ + B ₀ ). The third operation ST3 includes a third operation ST3b as a third operation step and a third storage operation ST3a as a third storage step. The gain stage 15A includes clock signals (φ ₁₁ = 1, φ ₂₁ = 0, φ ₁₂ = 0, φ ₂₂ = 1 and φ ₃ = 1 and φ _R = 0, φ _S = 0, φ _Sl1 = 1 and φ _S12 = 0, φ _P1 = 0, φ _N1 = 0, φ _P2 = 1, φ _N2 = 1, φ _M1 = 1, φ _M2 = 0) are input. According to this clock signal, the switches 47, 51, 57, 59, 67, 69, 71 are rendered conductive, and the switches 43, 49, 53, 55, 61, 63, 65, 73 are rendered non-conductive.

According to the clock signal described above, the gain stage 15A constitutes a circuit as shown in part (c) of FIG. Specifically, the first capacitor 25 and the fourth capacitor 26 are connected between the output 23b of the operational amplifier circuit 23 and the reference potential line L _COM . According to this circuit configuration, the second calculation value V _OP2 generated in the fourth calculation operation ST4b is stored in the first capacitor 25 and the fourth capacitor 26. That is, the third storage operation ST3a as the third storage step is performed.

The second capacitor 27 is connected between the first output 21a of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. Further, the fifth capacitor 28 is connected between the second output 21b of the D / A conversion circuit 21 and the first input 23a of the operational amplifier circuit 23. Further, the third capacitor 29 is connected between the output 23b of the operational amplifier circuit 23 and the first input 23a of the operational amplifier circuit 23. According to this circuit configuration, the second calculated value V _OP2 is generated at the output 15b of the gain stage 15A. That is, the third calculation operation ST3b as the third calculation step is performed.

  Then, the gain stage 15A repeats the third operation ST3 and the fourth operation ST4 a predetermined number of times as the cyclic A / D conversion operation.

<Third Embodiment>

  Another aspect of the present invention is an image sensor device. FIG. 9 is a view showing pixels of the image sensor. This image sensor device includes a cell array including an array of image sensor cells 2a and a converter array including a plurality of A / D converters 11 connected to the cell array. Each of the A / D converters 11 is connected to the image sensor cell 2a via the column line 8 of the cell array. According to the image sensor device including the A / D converter 11, high sensitivity and high speed operation are possible, and a wide dynamic range can be realized.

The image sensor cell 2a has, for example, a CMOS image sensor cell structure. The photodiode DF receives the light L for one pixel related to the image. The gate of the selection transistor M _S is connected to the row selection line S extending in the row direction. The gate of the reset transistor M _R is connected to the reset line R. The gate of the transfer transistor M _T is connected to the transfer selection line extending in the row direction. One end of the photodiode DF is connected to the floating diffusion layer FD via the transfer transistor M _T. The floating diffusion layer FD is connected to the reset potential line Reset through the reset transistor M _R, and is also connected to the gate of the transistor M _A. One current terminal (for example, drain) of the transistor M _A is connected to the column line 8 via the selection transistor M _S. The transistor M _A supplies a potential according to the charge amount of the floating diffusion layer FD to the column line via the selection transistor M _S.

The image sensor cell 2a having this structure can generate a first signal indicating a reset level and a second signal indicating a signal level superimposed on the reset level. That is, the image sensor cell 2a first provides the reset control signal to the reset transistor M _R to reset the floating diffusion layer FD. This reset level is read out via the transistor M _A. Next, the charge transfer control signal TX is supplied to the transfer transistor M _T , and the photo-induced signal charge is transferred from the photodiode DF to the floating diffusion layer. After that, this signal level is read out through the transistor M _A. As described above, the image sensor cell 2a, which is a pixel, can generate the first signal S1 indicating the reset level and the second signal S2 indicating the signal level superimposed on the reset level.

  Here, the converter array may include the A / D converter 11A according to the second embodiment instead of the A / D converter 11 according to the first embodiment. That is, one A / D converter 11A may be connected to one image sensor cell 2a. According to such a configuration, since one A / D converter 11A can perform the integral A / D conversion operation and the cyclic A / D conversion operation, the circuit area of the A / D converter 11A in the image sensor device. Can be made smaller.

  It is also possible to have a configuration in which the A / D converter 11 and the A / D converter 11A are connected to one image sensor cell 2a. Specifically, the input 15a of the gain stage 15A of the A / D converter 11 is connected to the output line of the image sensor cell 2a. The output 15b of the gain stage 15A of the A / D converter 11 is connected to the input 15a of the gain stage 15A of the A / D converter 11A. According to this configuration, the integral A / D conversion operation is performed by the A / D converter 11, and the cyclic A / D conversion operation is performed by the A / D converter 11A. Therefore, since the integral A / D conversion operation and the cyclic A / D conversion operation can be performed in parallel (pipeline processing), the performance of the A / D converter can be further improved.

  The present invention has been described in detail above based on the embodiments. However, the present invention is not limited to the above embodiment. The present invention can be variously modified without departing from the gist thereof.

  For example, the A / D converters 11 and 11A may apply the correlated double sampling (CDS) processing to the signal from the image sensor cell 2a. This processing may be performed in the analog domain (analog CDS) or the digital domain (digital CDS).

2a ... Image sensor cell, 11, 11A ... A / D converter, 15, 15A ... Gain stage, 15a ... Input, 15b ... Output, 17 ... A / D conversion circuit, 17a, 17b ... Comparator, 19 ... Logic circuit, 20 ... Preceding capacity part, 21 ... D / A conversion circuit, 21a ... 1st output, 21b ... 2nd output, 23 ... Operation amplification circuit, 23a ... 1st input, 23c ... 2nd input, 23b ... Output, 25 ... First capacitor (first capacitance section), 27 ... Second capacitor (second capacitance section), 33, 35 ... Reference voltage source, 37 ... Reference voltage generation circuit, 41 ... Clock generator , 60 ... Switch circuit, D ... Digital value, ST1 ... First operation, ST1a ... First storing operation, ST1b ... First arithmetic operation, ST2 ... Second operation, ST2b ... Second storing operation, ST2a ... second arithmetic operation, T3 ... third operation, ST3a ... third store operation, ST3b ... third arithmetic operation, ST4 ... fourth operation, ST4b ... fourth arithmetic operation, ST4a ... fourth storage operation, V _{IN ...} Analog Signal, V _OP1 ... First operation value, V _OP2 ... Second operation value, V _RH ... First reference reference voltage, V _RL ... Second reference reference voltage, V _COM ... Reference potential.

Claims (4)

A single-ended A / D converter,
A gain stage having an input for receiving an analog signal converted into a digital value, an output for outputting a first calculated value and a second calculated value, and an operational amplifier circuit including a first input, a second input and an output When,
An A / D conversion circuit that generates a digital signal including one or more bits by using one of the first operation value and the second operation value and the conversion reference voltage,
A logic circuit that generates a control signal using the digital signal;
A clock generation circuit for generating a clock signal,
A first output and a second output, and using the control signal, at least one of a first reference voltage and a second reference voltage, the first output and the second reference voltage. A D / A conversion circuit that provides the gain stage through an output,
The gain stage includes a pre-capacitance unit including a first capacitance unit and a second capacitance unit,
The first capacitance section includes a first capacitor,
The second capacitance section includes a second capacitor,
The second input of the operational amplifier circuit receives a reference potential,
The first reference voltage is higher than the second reference voltage,
The gain stage includes a switch circuit and a third capacitor ,
The switch circuit uses the clock signal to connect one of the first capacitance section and the second capacitance section to the first input of the operational amplifier circuit, and to connect the first potential to the reference potential. And the other of the second capacitance portion and
The A / D converter performs a first A / D conversion operation for generating the first operation value and a second A / D conversion operation for generating the second operation value,
In the first A / D conversion operation, the gain stage performs a first storage operation and a first arithmetic operation in parallel, and a second storage operation and a second arithmetic operation. Alternately perform the second operation performed in parallel,
In the first storing operation, the analog signal supplied from the input is stored in the first capacitance section,
In the first storing operation, the first capacitor is connected between the input of the gain stage and the second input of the operational amplifier circuit so that the analog signal is transferred to the first capacitor. Stored in
In the first arithmetic operation, the first arithmetic value based on the second capacitance section is generated at the output of the gain stage,
In the first arithmetic operation, the second capacitor is connected between the second output of the D / A conversion circuit and the first input of the operational amplifier circuit, and the third capacitor is connected. A capacitor is connected between the output of the operational amplifier circuit and the first input of the operational amplifier circuit so that the first calculated value based on the second capacitor is the output of the gain stage. Is generated in
In the second storing operation, the analog signal supplied from the input is stored in the second capacitance section,
In the second storing operation, the second capacitor is connected between the input of the gain stage and the second input of the operational amplifier circuit so that the analog signal is transferred to the second capacitor. Stored in
In the second arithmetic operation, the first arithmetic value based on the first capacitance section is generated at the output of the gain stage,
In the second arithmetic operation, the first capacitor is connected between the first output of the D / A conversion circuit and the first input of the operational amplifier circuit, and the third capacitor is connected. A capacitor is connected between the output of the operational amplifier circuit and the first input of the operational amplifier circuit so that the first calculated value based on the first capacitor is the output of the gain stage. Is generated in
In the second A / D conversion operation, the gain stage alternately performs a third operation of performing a third storing operation and a fourth operation of performing a fourth arithmetic operation,
In the third storing operation, the first calculated value or the second calculated value is stored in the preceding stage capacitance section,
In the third storing operation, the first capacitor and the second capacitor are connected between the output of the operational amplifier circuit and the second input of the operational amplifier circuit, and the third capacitor is By connecting between the output of the operational amplifier circuit and the first input of the operational amplifier circuit, the first calculated value or the second calculated value is changed to the first capacitor and the second capacitor. Stored in the capacitor of
In the fourth arithmetic operation, the second arithmetic value based on the pre-capacitance unit is generated at the output of the gain stage,
In the fourth arithmetic operation, the first capacitor is connected between the first output of the D / A conversion circuit and the first input of the operational amplifier circuit, and the second capacitor is The third capacitor is connected between the second output of the D / A conversion circuit and the first input of the operational amplification circuit, and the third capacitor is connected to the output of the operational amplification circuit and the output of the operational amplification circuit. An A / D converter that is connected to a first input to generate the second calculated value based on the first capacitor and the second capacitor at the output of the gain stage; . A single-ended A / D converter,
A gain stage having an input for receiving an analog signal converted into a digital value, an output for outputting a first calculated value and a second calculated value, and an operational amplifier circuit including a first input, a second input and an output When,
An A / D conversion circuit that generates a digital signal including one or more bits by using one of the first operation value and the second operation value and the conversion reference voltage,
A logic circuit that generates a control signal using the digital signal;
A clock generation circuit for generating a clock signal,
A first output and a second output, and using the control signal, at least one of a first reference voltage and a second reference voltage, the first output and the second reference voltage. A D / A conversion circuit that provides the gain stage through an output,
The gain stage includes a pre-capacitance unit including a first capacitance unit and a second capacitance unit,
The first capacitance unit includes a first capacitor and a fourth capacitor,
The second capacitance unit includes a second capacitor and a fifth capacitor,
The second input of the operational amplifier circuit receives a reference potential,
The first reference voltage is higher than the second reference voltage,
The gain stage includes a switch circuit and a third capacitor ,
The switch circuit uses the clock signal to connect one of the first capacitance section and the second capacitance section to the first input of the operational amplifier circuit, and to connect the first potential to the reference potential. And the other of the second capacitance portion and
The A / D converter performs a first A / D conversion operation for generating the first operation value and a second A / D conversion operation for generating the second operation value,
In the first A / D conversion operation, the gain stage performs a first storage operation and a first arithmetic operation in parallel, and a second storage operation and a second arithmetic operation. Alternately perform the second operation performed in parallel,
In the first storing operation, the analog signal supplied from the input is stored in the first capacitance section,
In the first storing operation, the first capacitor is connected between the input of the gain stage and the second input of the operational amplifier circuit so that the analog signal is transferred to the first capacitor. Stored in
In the first arithmetic operation, the first arithmetic value based on the second capacitance section is generated at the output of the gain stage,
In the first arithmetic operation, the second capacitor is connected between the first output of the D / A conversion circuit and the first input of the operational amplifier circuit, and the third capacitor is The first calculated value based on the second capacitor is generated at the output of the gain stage by being connected between the output of the operational amplifier circuit and the first input of the operational amplifier circuit. Is
In the second storing operation, the analog signal supplied from the input is stored in the second capacitance section,
In the second storing operation, the second capacitor is connected between the input of the gain stage and the second input of the operational amplifier circuit so that the analog signal is transferred to the second capacitor. Stored in
In the second arithmetic operation, the first arithmetic value based on the first capacitance section is generated at the output of the gain stage,
In the second arithmetic operation, the first capacitor is connected between the first output of the D / A conversion circuit and the first input of the operational amplifier circuit, and the third capacitor is The first calculated value based on the first capacitor is generated at the output of the gain stage by being connected between the output of the operational amplifier circuit and the first input of the operational amplifier circuit. Is
In the second A / D conversion operation, the gain stage alternately performs a third operation of performing a third storing operation and a fourth operation of performing a fourth arithmetic operation,
In the third storing operation, the first calculated value or the second calculated value is stored in the preceding stage capacitance section,
In the fourth arithmetic operation, the second arithmetic value based on the pre-capacitance unit is generated at the output of the gain stage,
The third operation of the second A / D conversion operation further includes a third arithmetic operation performed in parallel with the third storage operation,
The fourth operation of the second A / D conversion operation further includes a fourth storage operation performed in parallel with the fourth arithmetic operation,
In the third storing operation, the first capacitor and the fourth capacitor are connected between the output of the operational amplifier circuit and the second input of the operational amplifier circuit, whereby the first capacitor and the fourth capacitor are connected. 1 calculated value or said 2nd calculated value is stored in said 1st capacitor and said 4th capacitor,
In the third arithmetic operation, the second capacitor is connected between the first output of the D / A conversion circuit and the first input of the operational amplifier circuit, and the fifth capacitor is connected. The third capacitor is connected between the second output of the D / A conversion circuit and the first input of the operational amplification circuit, and the third capacitor is connected to the output of the operational amplification circuit and the output of the operational amplification circuit. Connecting to a first input to generate the second computed value at the output of the gain stage,
In the fourth storing operation, the second capacitor and the fifth capacitor are connected between the output of the operational amplifier circuit and the second input of the operational amplifier circuit, whereby the second capacitor and the fifth capacitor are connected. A calculated value of 2 is stored in the second capacitor and the fifth capacitor,
In the fourth arithmetic operation, the first capacitor is connected between the first output of the D / A conversion circuit and the first input of the operational amplifier circuit, and the fourth capacitor is The third capacitor is connected between the second output of the D / A conversion circuit and the first input of the operational amplification circuit, and the third capacitor is connected to the output of the operational amplification circuit and the output of the operational amplification circuit. An A / D converter in which the second calculated value is generated at the output of the gain stage by being connected to a first input . An image sensor device,
A cell array including an array of image sensor cells,
A converter array connected to the cell array and including a plurality of A / D converters;
Each of the A / D converters is connected to the image sensor cell via a column line of the cell array,
An image sensor device, wherein each of the A / D converters is as described in claim 1 or 2 . A method for generating a digital signal from an analog signal using the A / D converter according to claim 1 or 2 .
A first storing step as the first storing operation for storing the analog signal supplied from the input in the first capacitance section, and the first calculated value based on the second capacitance section. A first step of performing in parallel a first operation step as the first operation, which is generated at the output of the gain stage,
A second storing step as the second storing operation of storing the analog signal supplied from the input in the second capacitance section, and the first operation value based on the first capacitance section. A second step of performing in parallel a second operation step as the second operation that is generated at the output of the gain stage;
An integration type A / D conversion step in which the first step and the second step are repeated a predetermined number of times;
A third step of performing an operation of storing the residual analog signal, which is the first calculated value in the integration type A / D conversion step, in the preceding stage capacitance section;
A fourth step of performing a fourth arithmetic step as the fourth arithmetic operation for generating the second arithmetic value based on the preceding stage capacitance section at the output of the gain stage;
A fifth step of performing a third storing step as the third storing operation of storing the second calculated value in the front-stage capacitance section;
A method of generating a digital signal from an analog signal, comprising: a cyclic A / D conversion step in which the fourth step and the fifth step are repeated a predetermined number of times.

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