JP6666776B2 - Error protection circuit - Google Patents

Description

  The present invention relates to an abnormality protection circuit.

  2. Description of the Related Art Conventionally, various devices have been provided with an abnormality protection circuit. For example, Patent Document 1 discloses an overcurrent protection circuit provided in a motor driving device (motor driver).

  The overcurrent protection circuit of Patent Document 1 includes an OCP mute counter and a combination logic unit. The OCP mute counter starts pulse counting of the internal clock signal when the overcurrent detection signal is set to the abnormal logic level. Then, the OCP mute counter outputs a counter signal indicating whether the count value has reached a predetermined threshold value. When the counter signal indicating that the count value has reached the predetermined threshold is output, the combinational logic unit outputs an overcurrent protection signal indicating an abnormality. The count value of the OCP mute counter is reset when the overcurrent detection signal is set to a normal logic level.

  Accordingly, if the overcurrent detection signal maintains the logic level at the time of abnormality during the mute period (mask period) of the value obtained by multiplying the cycle of the internal clock signal by the threshold value of the count value, the overcurrent protection signal indicating abnormality is output. Is done. On the other hand, if the overcurrent detection signal returns to the normal logic level before the mute period has elapsed, the overcurrent protection signal indicating an abnormality is not output.

JP 2012-222869 A (Page 20, FIG. 22, etc.)

  However, in Patent Document 1, when the oscillator that is the source of the internal clock signal fails and the generation of the internal clock signal is stopped, the OCP mute counter cannot count the internal clock signal and the overcurrent detection signal Cannot be generated when an abnormal logic level is reached. Therefore, there occurs a problem that the overcurrent protection function does not operate.

  For example, when the overcurrent protection circuit is for use in a vehicle, in a situation where ISO26262, which is an international standard for functional safety related to electric / electronics of a vehicle, has been formulated, safety is emphasized. It is important to avoid the failure that the protection function does not operate.

  In view of the above situation, an object of the present invention is to provide an abnormality protection circuit that enables the operation of the abnormality protection function even when the oscillator fails.

In order to achieve the above object, an abnormality protection circuit according to one embodiment of the present invention includes:
A first output signal generation unit that outputs a first output signal indicating that the abnormality detection state has continued for a predetermined period based on the count of the clock signal;
A second output signal generation unit that outputs a second output signal indicating the abnormality without using the clock signal when an abnormality is detected;
A selection unit that selects one of the first output signal and the second output signal according to a clock stop detection signal,
When the clock stop detection signal indicates that the clock is normally generated, the second output signal generation unit is disabled, and the selection unit selects the first output signal,
When the clock stop detection signal indicates that the clock is stopped, the second output signal generation unit is enabled, and the selection unit selects the second output signal,
It is configured to output an abnormality protection signal based on the output signal selected by the selection unit (first configuration).

  In the first configuration, the second output signal generation unit may include a D input terminal to which a signal of a predetermined logic level is input, a clock terminal to which an abnormality detection signal is input, and output the second output signal. (A second configuration).

  In the second configuration, an AND circuit may be further provided, the output of which is input to a reset terminal of the D flip-flop, and the clock stop detection signal may be input to one input terminal of the AND circuit. Good (third configuration).

  In the third configuration, a signal based on a reset signal may be input to the other input terminal of the AND circuit (fourth configuration).

  In any one of the first to fourth configurations, the first output signal generation unit may include a counter to which the abnormality detection signal and the clock signal are input and a D to which a signal based on the output of the counter is input. A D flip-flop having an input terminal, a clock terminal to which the clock signal is input, and an output terminal to output the first output signal may be included (fifth configuration).

  Further, in the fifth configuration, a signal based on a reset signal for resetting the D flip-flop included in the second output signal generation unit may be input to a reset terminal of the D flip-flop. 6).

  Further, a driving device according to another aspect of the present invention is a driving device having a multi-channel output, comprising: an oscillator; a clock stop detection unit that monitors the oscillator and outputs a clock stop detection signal; (Seventh configuration).

  Further, in the seventh configuration, the abnormality protection circuit further includes an AND circuit, and an output signal selected by the selection unit is input to one input terminal of the AND circuit, and the other of the AND circuit A control signal for controlling the on / off of a channel may be input to an input terminal of the first circuit, and the abnormality protection signal may be output from the AND circuit (eighth configuration).

The drive device according to any one of the seventh and eighth configurations, further comprising a POR (power-on reset) circuit and performing communication with an external microcomputer,
In the abnormality protection circuit, the second output signal generation unit includes a D input terminal to which a signal of a predetermined logic level is input, a clock terminal to which an abnormality detection signal is input, and an output terminal to output the second output signal And a D flip-flop having
The abnormality protection circuit further includes a first AND circuit and a second AND circuit,
A reset signal output from the POR circuit is input to one input terminal of the first AND circuit, and a reset signal from the microcomputer is input to the other input terminal of the first AND circuit.
The second AND circuit receives the clock stop detection signal at one input terminal, and receives the output of the first AND circuit at the other input terminal,
The output of the second AND circuit may be input to a reset terminal of the D flip-flop (a ninth configuration).

  Further, an in-vehicle electronic device according to another aspect of the present invention includes a driving device having any one of the above configurations.

  According to the present invention, it is possible to operate the abnormality protection function even when the oscillator fails.

It is a figure showing composition of a motor drive device concerning one embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration of an overcurrent protection circuit according to one embodiment of the present invention. 6 is a timing chart regarding an operation (in the case of an oscillator failure) in the overcurrent protection circuit according to one embodiment of the present invention. FIG. 1 is an external view illustrating an example of a vehicle including an electronic device. FIG. 4 is a diagram illustrating a configuration of a motor drive device according to a comparative example. FIG. 9 is a diagram illustrating a configuration of an overcurrent protection circuit according to a comparative example. 5 is a timing chart illustrating an operation of the overcurrent protection circuit when an overcurrent detection period is relatively long. 5 is a timing chart illustrating an operation of the overcurrent protection circuit when an overcurrent detection period is relatively short.

  An embodiment of the present invention will be described below with reference to the drawings. Note that, here, an overcurrent protection circuit will be described as an example of the abnormality protection circuit, and a motor drive device will be described as an example to which the overcurrent protection circuit is applied.

<Configuration of motor drive device>
First, before describing an embodiment of the present invention, a comparative example with respect to the embodiment of the present invention will be described. FIG. 5 is a diagram illustrating a configuration of a motor drive device 200 according to a comparative example with respect to the embodiment of the present invention. The motor driving device 200 shown in FIG. 5 is configured as a motor driver IC having a multi-channel output.

  The motor driving device 200 shown in FIG. 5 includes motor driving units 1 to 8, a logic control unit 9, a POR (power on reset) circuit 10, an oscillator 11, an interface 12, and a UVLO (under voltage lock out). It is provided with a circuit 13, an overvoltage protection circuit 14, and a TSD (thermal shutdown) circuit 15, and is an IC (semiconductor device) in which these components are integrated on one chip.

  The motor drive device 200 includes input terminals T1 and T2 for establishing a connection with the outside and output terminals OUT1 and OUT8. A power supply voltage VS for the motor driving units 1 to 8 is externally applied to the input terminal T1. The power supply voltage VCC for the logic control unit 9 is externally applied to the input terminal T2.

  The motor driving units 1 and 2 correspond to the driving of the motor M1, similarly, the motor driving units 3 and 4 correspond to the driving of the motor M2, and the motor driving units 5 and 6 correspond to the driving of the motor M3. , Motor driving units 7 and 8 correspond to driving of the motor M4. The motors M1 to M4 are DC brush motors. That is, the motor drive device 200 has four channels of output.

  Each of the motor driving units 1 to 8 has the same configuration, and includes an upper switching element Q1, a lower switching element Q2, an upper switching element Q3, a lower switching element Q4, a resistor R1, a resistor R2, a pre-driver PR, It is configured to include a comparator CP1 and a comparator CP2.

  The source of the upper switching element Q1 composed of a P-channel MOSFET (MOS field effect transistor) is connected to the application terminal of the power supply voltage VS via the resistor R1. The drain of upper switching element Q1 is connected to the drain of lower switching element Q2 formed of an N-channel MOSFET. The source of the lower switching element Q2 is connected to the ground terminal via the resistor R2. That is, the upper switching element Q1 and the lower switching element Q2 are connected in series between the resistors R1 and R2 to form a bridge.

  The source of the upper switching element Q3 is connected to the power supply voltage VS application terminal. The drain of the upper switching element Q3 is connected to the drain of the lower switching element Q4. The source of the lower switching element Q4 is connected to the ground terminal. That is, the upper switching element Q3 and the lower switching element Q4 are connected in series to form a bridge.

  In each of the motor driving units 1 to 8, a connection point between the upper switching element Q1 and the lower switching element Q2 and a connection point between the upper switching element Q3 and the lower switching element Q4 are commonly connected to the output terminals OUT1 to OUT8. Is done. The output terminals OUT1 and OUT2 are connected to the positive and negative electrodes of the motor M1, respectively. Similarly, output terminals OUT3 and OUT4 are respectively connected to the positive and negative electrodes of motor M2, output terminals OUT5 and OUT6 are respectively connected to the positive and negative electrodes of motor M3, and output terminals OUT7 and OUT8 are respectively connected to motor M4. Connected to positive and negative electrodes.

  The gate of the upper switching element Q1 and the gate of the upper switching element Q3 are connected to one output terminal of the pre-driver PD, and the gate of the lower switching element Q4 and the gate of the lower switching element Q2 are connected to the other of the pre-driver PD. Connected to output end. The pre-driver PD drives each of the switching elements Q1 to Q4 by outputting a drive signal from each output terminal based on a command from the logic control unit 9. Thus, the motor driving units 1 to 8 can perform PWM (pulse width modulation) driving of the motors M1 to M4 and forward / reverse rotation driving.

  The connection point between the resistor R1 and the upper switching element Q1 is connected to the non-inverting end (+) of the comparator CP1. A predetermined reference voltage is applied to the inverting end (-) of the comparator CP1. The comparator CP1 compares the current detection voltage obtained by current / voltage conversion by the resistor R1 with the reference voltage, and outputs an overcurrent detection signal DET1 to the logic control unit 9 as a comparison result.

  The connection point between the lower switching element Q2 and the resistor R2 is connected to the non-inverting end (+) of the comparator CP2. A predetermined reference voltage is applied to the inverting end (-) of the comparator CP2. The comparator CP2 compares the current detection voltage obtained by current / voltage conversion by the resistor R2 with the reference voltage, and outputs an overcurrent detection signal DET2 to the logic control unit 9 as a comparison result.

  The comparator CP1 and the comparator CP2 as such overcurrent detection units can detect an overcurrent generated due to a ground fault and a power short to the output terminal OUT1 or OUT2, or a short circuit between the output terminals OUT1 and OUT2. The same applies to the output terminals OUT3 to OUT8.

  The overcurrent detection signals DET1 and DET2 are output to an overcurrent protection circuit (not shown) included in the logic control unit 9. Details of the overcurrent protection circuit will be described later.

  When the power supply voltage VCC rises, the POR circuit 10 outputs a reset signal PRST of a logic level (for example, low level) at the time of reset to the logic control unit 9, and a certain period after UVLO [Under Voltage Lockout] is released. After the lapse of time, a reset signal PRST having a logic level (for example, High level) at the time of reset release is output to the logic control unit 9. When the power supply voltage VCC falls below a predetermined threshold, the POR circuit 10 outputs to the logic control unit 9 a reset signal PRST having a logic level at the time of reset.

  The oscillator 11 generates an internal clock signal CK and outputs the signal to the logic control unit 9. For the multi-channel output (four-channel output), one oscillator 11 is used in common, thereby suppressing timing variations between channels.

  The UVLO circuit 13 monitors the power supply voltage VS, generates an undervoltage protection signal, and outputs this to the logic control unit 9. When the power supply voltage VS falls below the protection set value (for example, 5 V), the undervoltage protection signal becomes a logic level (for example, High level) at the time of abnormality, and the logic control unit 9 receiving this signal outputs each output via the pre-driver PD. The terminals OUT1 to OUT8 are opened. On the other hand, when the power supply voltage VCC rises to a protection release value (for example, 6 V) or more, the undervoltage protection signal becomes a normal logic level (for example, Low level), and the logic control unit 9 receiving this receives a normal operation.

  The overvoltage protection circuit 14 monitors the power supply voltage VS, generates an overvoltage protection signal, and outputs the signal to the logic control unit 9. For example, when the power supply voltage VS rises to 32 V, the overvoltage protection signal becomes a logic level (for example, High level) at the time of an abnormality, and the logic control unit 9 receiving the signal opens the output terminals OUT1 to OUT8 via the predriver PD. And

  The TSD circuit 15 monitors the chip temperature of the motor drive device 200, generates an overheat protection signal, and outputs this to the logic control unit 9. When the chip temperature of the motor driving device 200 rises to a protection set value (for example, 175 ° C.) or more, the overheat protection signal becomes a logic level at the time of abnormality (for example, High level). The respective output terminals OUT1 to OUT8 are opened via this. On the other hand, when the chip temperature of the motor drive device 200 falls below the protection release value (for example, 150 ° C.), the overheat protection signal becomes the normal logic level (for example, Low level), and the logic control unit 9 receiving this receives the normal operation. Move to

  The interface 12 transmits various signals received from the microcomputer 25 provided outside the motor driving device 200 to the logic control unit 9.

<About the overcurrent protection circuit>
Next, the overcurrent protection circuit will be described. FIG. 6 is a diagram illustrating a configuration of the overcurrent protection circuit 160 included in the logic control unit 9. The overcurrent protection circuit 160 is provided for each of the motor driving units 1 to 8 so as to correspond to each of the comparators CP1 and CP2. That is, a total of 16 overcurrent protection circuits 160 are provided.

  The overcurrent protection circuit 160 includes a counter 1601, an inverter 1602, a D flip-flop 1603, an AND circuit 1604, and an AND circuit 1605.

  The counter 1601 receives the overcurrent detection signal DET1 or DET2 and the clock signal clk. The clock signal clk is generated by dividing the frequency of the internal clock signal CK output from the oscillator 11 by a frequency divider (not shown) included in the logic control unit 9. The counter 1601 counts the clock signal clk and outputs a count result signal CNT.

  Inverter 1602 inverts input count result signal CNT to generate inverted signal INV. An inverted signal INV is input to a D input terminal of the D flip-flop 1603. A clock signal clk is input to a clock terminal of the D flip-flop 1603.

  A reset signal PRST output from the POR circuit 10 is input to one input terminal of the AND circuit 1604, and a reset signal XRST is input to the other input terminal of the AND circuit 1 from the microcomputer 25 via the interface 12. The output of the AND circuit 1604 is input to the reset terminal (R bar terminal) of the D flip-flop 1603.

  The Q output signal Qout output from the Q output terminal of the D flip-flop 1604 is input to one input terminal of the AND circuit 1605, and the ON / OFF control signal CRS is input to the other input terminal. The ON / OFF control signal CRS is a signal indicating ON / OFF of each channel of the motor driving device 200, and is a signal transmitted from the microcomputer 25 and stored in a register (not shown in FIG. 5) via the interface 12.

  When both the reset signal PRST and the reset signal XRST are at the logical level (High level) at the time of reset release, the output from the AND circuit 1604 becomes High level, and the D flip-flop 1603 responds to the input to the D input terminal and the clock terminal. To perform a normal operation of outputting from the Q output terminal. On the other hand, when at least one of the reset signal PRST and the reset signal XRST becomes a logic level (Low level) at the time of reset, the output from the AND circuit 1604 becomes Low level, and the D flip-flop 1603 is reset.

  When the ON / OFF control signal CRS is at the ON logic level (High level), the AND circuit 1605 is enabled. When the ON / OFF control signal CRS is at the OFF logic level (Low level), AND is applied. The circuit 1605 becomes invalid.

  Here, the operation in the normal operation in which the reset signal PRST and the reset signal XRST are at the logical level (High level) at the time of reset release and the ON / OFF control signal CRS is the logical level (High level) at the time of ON, This will be described with reference to the timing charts shown in FIGS.

  FIG. 7 is a timing chart showing examples of various signal waveforms when an overcurrent is detected for a relatively long period. At timing t1 in FIG. 7, an overcurrent occurs in the current flowing through the resistor R1 or the resistor R2, and the overcurrent detection signal DET1 or DET2 rises from a low level to a high level.

  Then, using this as a trigger, the counter 1601 starts counting the clock signal clk. The counter 1601 continues counting while the overcurrent detection signal DET1 or DET2 is at a high level, and outputs a count result signal CNT of a logical level according to whether or not the count value has reached a predetermined threshold. When the count value has not reached the threshold value, the count result signal CNT is Low level, and when the count value has reached the threshold value, the count result signal CNT has High level.

  In FIG. 7, the threshold value is set to 10 as an example, and the overcurrent detection signal DET1 or DET2 maintains the High level until after the timing t2 when the count value reaches 10, so that the count result signal CNT becomes Low at the timing t2. Switching from level to high level.

  Accordingly, the inverted signal INV output from the inverter INV1602 switches from the High level to the Low level slightly after the timing t2. At the timing t2, the clock clk rises. At this point, the inverted signal INV is at the high level, so that the Q output signal Qout output from the D flip-flop 1603 is maintained at the high level. When the clock signal CLK rises at the timing t3, the inverted signal INV is at the low level, so that the Q output signal Qout switches from the high level to the low level. As a result, the overcurrent protection signal Socp output from the AND circuit 1605 switches from the high level to the low level.

  When the overcurrent protection signal Socp is switched to the low level, the logic control unit 9 opens the output terminals OUT1 and OUT2 via the pre-driver PD, for example. Accordingly, it is possible to prevent the motor drive device 200 from being burned out due to the overcurrent.

  On the other hand, FIG. 8 shows a timing chart when an overcurrent is detected for a relatively short period such as a moment. When an overcurrent is detected at timing t11 in FIG. 8 and the overcurrent detection signal DET1 or DET2 switches from a low level to a high level, the counter 1601 starts counting the clock signal clk.

  In the case of FIG. 8, the overcurrent detection period is short, and at the timing t12 when the count value of the clock signal clk does not reach the threshold value (here, 10), the overcurrent detection signal DET1 or DET2 falls to the Low level. When the overcurrent detection signal DET1 or DET2 falls to a low level, the counter 1601 stops counting, resets the count value, and sets the count result signal CNT to a low level.

  As a result, the count result signal CNT is maintained at a low level, and the inverted signal INV, the Q output signal Qout, and the overcurrent protection signal Socp are maintained at a high level. In this case, the logic control unit 9 does not perform overcurrent protection.

  Therefore, when the overcurrent detection period (the period during which the overcurrent detection signal DET1 or DET2 is at a high level) is shorter than the mask period determined by the cycle of the clock signal clk and the threshold value of the count value, the overcurrent protection signal Socp is masked. Is done. For example, when the cycle of the clock signal clk is 1 μs and the threshold value of the count value is 10, the mask period is about 10 μs.

  Thus, even when an overcurrent for a short period occurs due to a rush current flowing into the parasitic capacitance of the upper switching element Q1 and the parasitic capacitance of the lower switching element Q2 when the power supply voltage VS is activated, overcurrent protection is performed. Can be avoided.

  However, with the configuration of the overcurrent protection circuit 160 according to such a comparative example, when the oscillator 11 fails, the generation of the internal clock signal CK and thus the generation of the clock signal clk is stopped. Can't count. Therefore, even if an overcurrent is detected and the overcurrent detection signal DET1 or DET2 rises to a high level, the count result signal CNT is maintained at a low level, and overcurrent protection is not performed. That is, the malfunction of the overcurrent protection function due to the failure of the oscillator 11 occurs.

<Motor drive device and overcurrent protection circuit according to embodiment of the present invention>
Therefore, as an embodiment of the present invention, the motor drive device and the overcurrent protection circuit are configured as described below.

  FIG. 1 is a diagram showing a configuration of a motor drive device 20 according to the embodiment of the present invention. The difference between the motor driving device 20 and the motor driving device 200 (FIG. 5) according to the comparative example is that a watchdog timer 17 is further provided. In addition, an overcurrent protection circuit (not shown) included in the logic control unit 91 of FIG. 1 (an overcurrent protection circuit 16 of FIG. 2 described later) included in the logic control unit 91 of FIG. And different.

  The watchdog timer 17 (clock stop detection unit) monitors the internal clock signal CK generated by the oscillator 11, and when the internal clock signal CK is normally generated, the logical level (Low level) corresponding to the generation is monitored. The internal clock stop detection signal CKDT is output. On the other hand, the watchdog timer 17 stops the generation of the internal clock signal CK and, when the time is up, outputs an internal clock stop detection signal CKDT of a logical level (High level) corresponding to that. The internal clock stop detection signal CKDT is input to an overcurrent protection circuit included in the logic control unit 91.

  FIG. 2 is a diagram showing a configuration of the overcurrent protection circuit 16 included in the logic control unit 91. The overcurrent protection circuit 16 includes a counter 161, an inverter 162, a D flip-flop 163, AND circuits 164 to 166, a D flip-flop 167, and a selector 168. Note that a first output signal generator is configured by the counter 161, the inverter 162, and the D flip-flop 163, and a second output signal generator is configured by the D flip-flop 167.

  Of the overcurrent protection circuit 16, the counter 161, the inverter 162, the D flip-flop 163, the AND circuit 164, and the AND circuit 165 have the same configuration as that of the overcurrent protection circuit 160 according to the comparative example.

  The difference between the configuration of the overcurrent protection circuit 160 and that of the overcurrent protection circuit 160 will be described. The AND circuit 166 receives the internal clock stop detection signal CKDT at one input terminal, and receives the output of the AND circuit 164 at the other input terminal. . The output of the AND circuit 166 is input to the reset terminal (R bar terminal) of the D flip-flop 167.

  The D input terminal of the D flip-flop 167 receives a low-level signal Slow, and the clock terminal receives the overcurrent detection signal DET1 or DET2. The selector 168 receives the Q output signal Qout (first output signal) output from the D flip-flop 163 and the Q output signal Qout2 (second output signal) output from the D flip-flop 167. The selector 168 selects one of the Q output signal Qout and the Q output signal Qout2 according to the logic level of the internal clock stop detection signal CKDT, and outputs the selected output signal Sout. To the AND circuit 165, the selection output signal Sout is input to one input terminal, and the ON / OFF control signal CRS is input to the other input terminal. The overcurrent protection signal Socp is output from the AND circuit 165.

  When at least one of the reset signal PRST and the reset signal XRST becomes a logic level (Low level) at the time of reset, the output of the AND circuit 164 becomes Low level, so that the D flip-flop 163 is reset. At this time, since the output of the AND circuit 166 becomes Low level, the D flip-flop 167 is also reset.

  When both the reset signal PRST and the reset signal XRST are at the logic level (High level) at the time of reset release, the output of the AND circuit 164 becomes High level, and the D flip-flop 163 can operate normally (hereinafter, ON). It is assumed that the / OFF control signal CRS is at the high level when ON.) At this time, if the oscillator 11 operates normally and the internal clock signal CK is normally generated, the internal clock stop detection signal CKDT goes to the low level, and the output of the AND circuit 166 goes to the low level. 167 is reset. The selector 168 selects the Q output terminal Qout of the D flip-flop 163 and outputs the selected output signal Qout as the selected output signal Sout.

  In this state, as shown in the timing chart of FIG. 7 described above, when an overcurrent is detected for more than the mask period (when the overcurrent detection signal DET1 or DET2 is at High level), the count result signal CNT output from the counter 161 is output. Is switched from the Low level to the High level, and as a result, the Q output signal Qout of the D flop 163 switches from the High level to the Low level. At this time, the selection output signal Sout output from the selector 168 also switches from the High level to the Low level, so that the overcurrent protection signal Socp output from the AND circuit 165 switches from the High level to the Low level. Thereby, the logic control unit 91 can perform overcurrent protection.

  On the other hand, as shown in the timing chart of FIG. 8 described above, when an overcurrent shorter than the mask period is detected, the count result signal CNT is maintained at the Low level, and the Q output signal Qout is maintained at the High level. Therefore, the selection output signal Sout also maintains the High level. As a result, the overcurrent protection signal Socp maintains the High level, and the overcurrent protection is not performed.

  It is also assumed that the oscillator 11 fails and the generation of the internal clock signal CK stops, and the watchdog timer 17 detects this and outputs the internal clock stop detection signal CKDT at a high level. At this time, when both the reset signal PRST and the reset signal XRST are at the logic level (High level) at the time of reset release, the output of the AND circuit 164 becomes High level, the output of the AND circuit 166 becomes High level, and the D flip-flop 167 Allows normal operation. Further, the selector 168 selects the Q output signal Qout2, which is the output of the D flip-flop 167, and outputs it as the selected output signal Sout.

  In this state, as shown in the timing chart of FIG. 3, if an overcurrent is detected and the overcurrent detection signal DET1 or DET2 rises from the Low level to the High level at the timing t21, the D flip-flop 167 at that timing is switched on. Since the logic level (Low level) applied to the input terminal is output from the Q output terminal, the Q output signal Qout2 switches from the High level to the Low level. Then, the selection output signal Sout output from the selector 168 also switches to the low level, so that the overcurrent protection signal Socp output from the AND circuit 165 also switches to the low level. As a result, the logic control unit 91 performs overcurrent protection.

  As described above, according to the present embodiment, the overcurrent protection function can be operated even when the oscillator 11 fails and the generation of the internal clock signal CK is stopped.

<Application to vehicles>
FIG. 4 is an external view illustrating a configuration example of a vehicle equipped with various electronic devices. The vehicle X of this configuration example includes various electronic devices X11 to X18 that operate by receiving the supply of the power supply voltage VS from the battery X10. The mounting positions of the electronic devices X11 to X18 in FIG. 4 may be different from the actual positions for convenience of illustration.

  The electronic device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, and the like).

  The electronic device X12 is a lamp control unit that performs lighting control such as a high intensity discharged lamp (HID) or a daytime running lamp (DRL).

  The electronic device X13 is a transmission control unit that performs control related to the transmission.

  The electronic device X14 is a body control unit that performs control related to the motion of the vehicle X (ABS (anti-lock brake system) control, EPS (electric power steering) control, electronic suspension control, and the like).

  The electronic device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The electronic device X16 is incorporated into the vehicle X at the factory shipment stage as standard equipment and manufacturer options such as air conditioners, wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, and electric seats. Electronic equipment.

  The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].

  The electronic device X18 is an electronic device provided with a high pressure-resistant motor such as a vehicle-mounted blower, an oil pump, a water pump, and a battery cooling fan.

  Of the electronic devices X11 to X18 described above, the electronic device including the DC motor with a brush can appropriately adopt the configuration of the motor driving device 20 described above. In particular, in a situation in which ISO26262 or the like is formulated, the overcurrent protection function of the motor drive device 20 is important in terms of safety.

<Other modifications>
Various technical features disclosed in this specification can be modified in various ways in addition to the above-described embodiment without departing from the spirit of the technical creation. For example, the application target of the overcurrent protection circuit is not limited to the motor drive device, but may be, for example, an LED drive device (including an in-vehicle drive device).

  Further, the abnormality protection circuit of the present invention is not limited to an overcurrent protection circuit, but can be applied to, for example, an overvoltage protection circuit, a temperature abnormality protection circuit, and the like.

  Thus, the above-described embodiment is to be considered in all respects as illustrative and not restrictive, and the technical scope of the present invention is not limited to the description of the above-described embodiment but to the claims. , And should be understood to include all modifications that fall within the meaning and range equivalent to the claims.

  INDUSTRIAL APPLICABILITY The present invention can be used, for example, in a vehicle-mounted motor drive device.

1-8 Motor drive unit 9, 91 Logic control unit 10 POR circuit 11 Oscillator 12 Interface 13 UVLO circuit 14 Overvoltage protection circuit 15 TSD circuit 16 Overcurrent protection circuit 161 Counter 162 Inverter 163 D flip-flop 164-166 AND circuit 167 D flip-flop 168 Selector 17 Watchdog timer 20 Motor driving device 25 Microcomputer 160 Overcurrent protection circuit 1601 Counter 1602 Inverter 1603 D flip-flop 1604 AND circuit 1605 AND circuit 200 Motor driving device R1, R2 Resistance Q1, Q3 Upper switching element Q2, Q4 Lower Side switching element PD Pre-driver CP1, CP2 Comparator T1, T2 Input terminal OUT1-OUT8 Output terminal

Claims (10)

A first output signal generation unit that outputs a first output signal indicating that the abnormality detection state has continued for a predetermined period based on the count of the clock signal;
A second output signal generation unit that outputs a second output signal indicating the abnormality without using the clock signal when an abnormality is detected;
A selection unit that selects one of the first output signal and the second output signal according to a clock stop detection signal,
When the clock stop detection signal indicates that the clock is normally generated, the second output signal generation unit is disabled, and the selection unit selects the first output signal,
When the clock stop detection signal indicates that the clock is stopped, the second output signal generation unit is enabled, and the selection unit selects the second output signal,
An abnormality protection circuit that outputs an abnormality protection signal based on the output signal selected by the selection unit.   The second output signal generation unit includes a D flip-flop having a D input terminal to which a signal of a predetermined logic level is input, a clock terminal to which an abnormality detection signal is input, and an output terminal to output the second output signal. The abnormality protection circuit according to claim 1, further comprising a loop. And further comprising an AND circuit whose output is inputted to a reset terminal of the D flip-flop,
The abnormality protection circuit according to claim 2, wherein the clock stop detection signal is input to one input terminal of the AND circuit.   4. The abnormality protection circuit according to claim 3, wherein a signal based on a reset signal is input to the other input terminal of the AND circuit. The first output signal generation unit includes:
A counter to which an abnormality detection signal and the clock signal are input;
A D input terminal to which a signal based on the output of the counter is input, a clock terminal to which the clock signal is input, and a D flip-flop having an output terminal to output the first output signal. The abnormality protection circuit according to any one of claims 1 to 4, characterized in that:   6. The abnormality protection circuit according to claim 5, wherein a signal based on a reset signal for resetting the D flip-flop included in the second output signal generator is input to a reset terminal of the D flip-flop. A drive device having a multi-channel output,
An oscillator,
A clock stop detection unit that monitors the oscillator and outputs a clock stop detection signal;
A drive device comprising: the abnormality protection circuit according to any one of claims 1 to 6. The abnormality protection circuit further includes an AND circuit,
An output signal selected by the selection unit is input to one input terminal of the AND circuit,
A control signal for controlling on / off of a channel is input to the other input terminal of the AND circuit,
The driving device according to claim 7, wherein the abnormality protection signal is output from the AND circuit. 9. The driving device according to claim 7, further comprising a POR (power-on reset) circuit for communicating with an external microcomputer.
In the abnormality protection circuit, the second output signal generation unit includes a D input terminal to which a signal of a predetermined logic level is input, a clock terminal to which an abnormality detection signal is input, and an output terminal to output the second output signal And a D flip-flop having
The abnormality protection circuit further includes a first AND circuit and a second AND circuit,
A reset signal output from the POR circuit is input to one input terminal of the first AND circuit, and a reset signal from the microcomputer is input to the other input terminal of the first AND circuit.
The second AND circuit has one input terminal receiving the clock stop detection signal and the other input terminal receiving an output of the first AND circuit.
The drive device according to claim 1, wherein an output of the second AND circuit is input to a reset terminal of the D flip-flop.   An in-vehicle electronic device comprising the driving device according to any one of claims 7 to 9.

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