JP6642188B2 - Nonvolatile storage device, integrated circuit device, electronic device, and method of controlling nonvolatile storage device - Google Patents

Description

  The present invention relates to a nonvolatile storage device, an integrated circuit device, an electronic device, a method for controlling a nonvolatile storage device, and the like.

  There is known a technology (ECC: Error Check and Correct or Error Correction Code) for detecting whether data read from a memory is correct and correcting erroneous data to correct data. In this technique, data to which error correction data is added is stored in a memory, and the data is read to perform an error correction process. Even if there is an error in the data read from the memory, the error is corrected by the error correction processing to obtain correct data. There is an upper limit on the number of bits that can be corrected by the error correction process, and the upper limit is determined by the number of bits of the added error correction data.

  Conventional techniques of such ECC are disclosed in Patent Documents 1 to 3, for example. In Patent Documents 1 to 3, the existence of an error bit is permitted in an erasing operation or a writing operation on the assumption that an error is corrected by an error correction process in reading. That is, in Patent Literatures 1 and 2, when the number of error bits detected in the write verify is equal to or less than the number of bits that can be corrected by the error correction process, it is considered that the writing has succeeded even if the error bit is detected. . In Patent Literature 3, when the number of error bits detected in the erase verify is equal to or less than the number of bits that can be corrected by the error correction process, the erasure is regarded as successful even if the error bit is detected.

JP 06-131884 A JP-A-06-131886 JP-A-10-222959

  As described above, in the related art, the existence of the error bit is permitted in either the erasing or the writing. However, it is desirable that the existence of the error bit can be permitted in both the erasing and the writing in view of extending the life of the memory. .

  However, if an attempt is made to permit the presence of an error bit in both erasing and writing, error correction data is required for erasing and writing, and the memory capacity increases. On the other hand, if an attempt is made to permit the presence of error bits in both erasing and writing without increasing the data amount of the error correction data, a problem may occur due to the influence of margin reading. That is, in the erase verify, the write verify, and the normal read operation, the criteria for determining whether the read bit is “0” or “1” are different. Therefore, the existence of error bits exceeding the number of bits that can be corrected in the error correction processing may be permitted, and erroneous data may be output in the error correction processing.

  According to some embodiments of the present invention, a nonvolatile memory device, an integrated circuit device, an electronic device, and a nonvolatile memory that allow the presence of an error bit in both erasing and writing and that can correct correct data in an error correction process An apparatus control method and the like can be provided.

  One embodiment of the present invention includes a non-volatile memory, a memory control unit that controls an erasing operation, a reading operation, and a writing operation to the non-volatile memory, and the memory control unit includes: Erase verify is performed, bit comparison processing is performed to compare the erase verify result data, which is the result data of the erase verify, with the write data in bit units, and whether an error in the write verify is permitted as being correctable by the error correction processing is permitted or not. The non-volatile storage device determines whether or not to perform the determination based on the result of the bit comparison process.

  According to one embodiment of the present invention, by performing the bit comparison process between the erase verification result data and the write data, the existence of an error bit may be permitted beyond the number of bits that can be corrected by the error correction process. The case can be detected. Then, by determining whether or not to permit an error in the write verification based on the result of the bit comparison processing, it is possible to make a determination according to the above case. As a result, the presence of an error bit is permitted in both erasing and writing, and correct data can be corrected in error correction processing.

  In one aspect of the present invention, the memory control unit may perform the bit comparison process when an error is determined in the erase verify.

  When an error in write verification is permitted, there is a possibility that the number of error bits that can be corrected in read data may exceed the number of error bits in erase verification. According to one embodiment of the present invention, the bit comparison process is performed in such a case. Therefore, when an error is determined in the erase verification, it is possible to determine not to permit an error in the write verification. This makes it possible to reduce the number of error bits in the read data to the number of error-correctable bits or less.

  In one aspect of the present invention, the memory control unit may include, in the bit comparison processing, an erase error bit determined as an error in the erase verify result data, and a write bit of the write data corresponding to the erase error bit. May be compared.

  If an error in the write verification is permitted when the erase error bit and the write bit of the corresponding write data are at different logical levels, the number of error bits in the read data may exceed the number of error bits that can be corrected. According to one embodiment of the present invention, the above-described case can be detected by comparing the erase error bit and the write bit.

  Further, in one aspect of the present invention, when it is determined in the bit comparison process that the erasure error bit and the write bit are at the same first logical level, the memory control unit determines whether the write verification result data is the same. A write error bit determined as an error in certain write verify result data may be determined as a bit that can be corrected by the error correction processing, and it may be determined that the write data has been successfully written to the nonvolatile memory.

  As described above, when the erase error bit and the write bit are at different logical levels, there is a possibility that the number of error bits in the read data that can be corrected is exceeded. According to one aspect of the present invention, the write error bit is permitted when it is determined that the erase error bit and the write bit are at the same first logical level. Thus, when there is no possibility that the number of error bits that can be corrected is exceeded, a write error bit can be permitted.

  In one aspect of the present invention, the memory control unit, when it is determined in the bit comparison process that the erase error bit and the write bit are at the same first logical level, removes an error in the write verify. An error correction enable / disable flag indicating whether or not to allow is set to active to allow an error.If the error correction enable / disable flag is active, whether or not the write error bit can be corrected by the error correction processing is determined. If it is determined that the write error bit can be corrected by the error correction process, it may be determined that the write data has been successfully written to the nonvolatile memory.

  In this way, the logic level of the error correction enable / disable flag is set in the bit comparison process according to whether the erase error bit and the write bit have the same first logic level. Then, when the error correction enable / disable flag is active, it is determined whether or not the write error bit can be corrected by the error correction process. In this way, when the erase error bit and the write bit are at the same first logical level in the bit comparison processing, the write error bit can be permitted.

  In one embodiment of the present invention, the nonvolatile memory device includes a read circuit that performs the read operation, and the read circuit reads data from the nonvolatile memory based on an erase verify determination criterion in the erase verify, In the write verification, data may be read from the nonvolatile memory according to a write verification criterion different from the erase verification criterion.

  In one embodiment of the present invention, the criterion for erasure verification used in erase verification is different from the criterion for write verification used in write verification. By performing such a margin read, it is possible to provide a margin to data (guaranteed data) in erasing or writing. On the other hand, when error bits are allowed on the premise of error correction processing, there is a problem that errors may not be correctly corrected due to the influence of margin reading. According to one embodiment of the present invention, such a problem is solved. Solvable.

  In one embodiment of the present invention, a nonvolatile memory device includes an erase and write circuit that performs the erase operation and the write operation, and a read circuit that performs the read operation. A bit comparison unit that performs processing, a control unit that controls the erase / write circuit and the read circuit, and determines whether or not the read / write circuit is enabled, and performs the error correction process on data read by the read circuit. An error correction unit and an error correction data generation unit that generates error correction data used for the error correction processing may be provided.

  With this configuration, the bit comparison unit performs a bit comparison process between the erase verification result data and the write data, and the control unit determines whether or not to permit the write error bit. This makes it possible to obtain correct result data in the error correction processing performed by the error correction unit.

  Another embodiment of the present invention relates to an integrated circuit device including the nonvolatile memory device described in any of the above.

  Still another embodiment of the present invention relates to an electronic device including the nonvolatile memory device described in any of the above.

  Still another aspect of the present invention is a method of controlling a nonvolatile memory device including a nonvolatile memory, wherein in a write operation to the nonvolatile memory, an erase verify is performed, and an erase as data resulting from the erase verify is performed. A bit comparison process of comparing the verification result data and the write data in a bit unit is performed, and whether or not to permit an error in the write verification as being correctable by the error correction process is determined based on the result of the bit comparison process. The present invention relates to a method of controlling the nonvolatile memory device based on the control method.

FIG. 1 is a configuration example of a nonvolatile storage device according to the present embodiment. FIG. 2 is a flowchart of the erasing operation of the present embodiment. FIG. 3 is a flowchart of the write operation of the comparative example. FIG. 4 is an example of a histogram showing the relationship between the number of times of erasure of stored data of bits and the number of bits. FIG. 5 shows a specific example in which error correction cannot be performed even though the erase verify and the write verify have been passed. FIG. 6A is an explanatory diagram of the error correction processing in the specific example of FIG. FIG. 6B is an explanatory diagram of the error correction processing in the specific example of FIG. FIG. 6C is an explanatory diagram of the error correction processing in the specific example of FIG. FIG. 7 is a diagram schematically illustrating margin reading. FIG. 8 is a flowchart of the write operation of the present embodiment. FIG. 9 is a specific example in which the error correction enable / disable flag becomes “1” by the bit comparison process. FIG. 10 is a specific example in a case where the error correction enable / disable flag becomes “0” by the bit comparison process. FIG. 11 is a detailed configuration example of the nonvolatile memory device according to the present embodiment. FIG. 12 is a detailed configuration example of the readout circuit and the nonvolatile memory. FIG. 13A is an explanatory diagram of the generation processing of the error correction data. FIG. 13B is an explanatory diagram of the generation processing of the error correction data. FIG. 13C is an explanatory diagram of the generation processing of the error correction data. FIG. 14A is an explanatory diagram of the error correction processing. FIG. 14B is an explanatory diagram of the error correction processing. FIG. 14C is an explanatory diagram of the error correction processing. FIG. 14D is an explanatory diagram of the error correction processing. FIG. 15 shows a specific example in which an error bit permitted in an erasing operation is corrected. FIG. 16 shows a specific example of correcting an error bit permitted in a write operation. FIG. 17 is a configuration example of an electronic device of the present embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail. Note that the present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are essential as solving means of the present invention. Not necessarily.

1. 1. Configuration FIG. 1 is a configuration example of a nonvolatile storage device 200 according to the present embodiment. The nonvolatile memory device 200 includes a nonvolatile memory 10, an erasing and writing circuit 20, a reading circuit 30, and a memory control unit 100 (memory control circuit). The nonvolatile storage device 200 is configured as, for example, an integrated circuit device.

  The nonvolatile memory 10 is a memory that retains stored data even when power is not supplied. In the present embodiment, it is assumed that the nonvolatile memory 10 is capable of electrically rewriting (erasing and writing) the stored data a plurality of times, such as an electrically erasable programmable read-only memory (EEPROM) or a flash memory. It is. For example, the nonvolatile memory 10 includes a memory cell array arranged in a matrix, word lines provided along each row of the memory cell array, and bit lines provided along each column of the memory cell array. Each memory cell of the memory cell array is provided at the intersection of a word line and a bit line, and the physical address of the memory cell is specified by the word line and the bit line. The memory cell is, for example, a floating gate type MOS transistor that holds data by charge injected into a floating gate, or a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) transistor that holds data by charge injected into an insulating film. And so on.

  The erasing and writing circuit 20 is a circuit that performs an erasing operation for erasing data stored in the nonvolatile memory 10 and a writing operation for writing data to the nonvolatile memory 10. Specifically, in the erase operation, "1" (high level, in a broad sense, the second logic level) is written to all the target memory cells. In the write operation, among the memory cells that are all “1” due to the erase operation, the memory cell corresponding to the bit of the write data “0” (low level, first logical level in a broad sense) is “ Write "0". The erase and write circuit includes, for example, a write amplifier circuit that drives a bit line and a selection circuit that selects a word line. Note that the selection circuit may be included in the memory control unit 100.

  The read circuit 30 is a circuit that performs a read operation for reading data stored in the nonvolatile memory 10. The read circuit 30 is configured by, for example, a sense amplifier that compares a cell current output from a memory cell to a bit line with a reference current and detects read data (logic level of a bit) based on the comparison result.

  The memory control unit 100 controls each unit of the nonvolatile storage device 200. For example, the memory control unit 100 decodes a logical address into a physical address and controls an erase operation, a write operation, and a read operation for the physical address. In addition, a process for generating error correction data (ECC data) from user data and an error correction process (ECC process) for read data are performed. Here, the erasing operation is an operation including erasing of stored data, erasing verification, and determination of success (pass) and failure (fail) of erasing. The write operation is an operation including writing of write data, write verification, and determination of success or failure of writing. In the present embodiment, the write operation further includes an erase verify, and a bit comparison process between the data read by the erase verify and the write data (expected value). Then, based on the result of the bit comparison processing, the success or failure of the writing is determined. The read operation is an operation including reading of stored data. The memory control unit 100 can be realized by a logic circuit generated by an automatic placement and routing method such as a gate array, or various processors such as a microcomputer and a DSP (Digital Signal Processor). When implemented by a processor, for example, the non-volatile storage device 200 further includes a memory, in which a program or the like describing the function of the memory control unit 100 is stored. Then, the function of the memory control unit 100 is realized by the processor executing the program.

  Now, there is a method of permitting (permitting) the existence of an error bit in an erasing operation or a writing operation on the assumption that the error bit can be corrected by an error correction process at the time of reading. However, as will be described later with reference to FIGS. 2 to 7, when error bits are permitted in both the erasing operation and the writing operation, there is a possibility that even if error correction processing is performed on read data, correct data cannot be corrected.

  That is, since different margins are set for the judgment criterion (reference current IE in FIG. 7) used for erase verification and the judgment criterion (reference current IW) used for write verification, a bit determined as an error in the erase verification is set. May be determined as a pass in the write verify. In this case, a new error bit is permitted in the write verify. Since the margin read is not performed in the read operation (reference current IR), there is a possibility that a bit determined as an error in the erase verify and a pass in the write verify becomes an error bit in the read data. Then, there is a possibility that the maximum number of bits that can be error-corrected, together with the error bits newly permitted in the write verification, will be exceeded.

  In this regard, the non-volatile storage device 200 of the present embodiment includes the non-volatile memory 10 and the memory control unit 100 that controls an erasing operation, a reading operation, and a writing operation for the non-volatile memory 10. In the write operation, the memory control unit 100 performs an erase verify, and performs a bit comparison process of comparing the erase verify result data, which is the result data of the erase verify, with the write data on a bit basis. The memory control unit 100 determines whether or not to permit an error in the write verification as being correctable by the error correction processing based on the result of the bit comparison processing.

  For example, in the flow of a write operation described later with reference to FIG. 8, erase verify is performed in step S21, and bit comparison is performed in step S25. In steps S26, S24, and S27, an error correction enable / disable flag is set based on the result of the bit comparison. In steps S31 to S34, based on the error correction enable / disable flag, it is determined that an error in the write verify can be corrected by an error correction process. A decision is made as to whether to permit.

  As will be described later with reference to FIG. 5, when the bit of the write data corresponding to the bit (B1) determined as an error in the erase verify is “1”, there is a possibility that the error cannot be corrected. According to the present embodiment, such a case can be detected by performing a bit comparison process between the erase verification result data and the write data. By deciding whether or not to permit a write-verify error based on the result of the bit comparison process, it is possible to make a decision corresponding to the above case (decision not to permit a write-verify error), The number of error bits can be reduced to the number of error-correctable bits or less.

  In the present embodiment, the memory control unit 100 performs a bit comparison process when an error is determined in the erase verify.

  For example, as shown in FIG. 8, when an error bit is detected in the erase verify in step S21, the process branches to YES in step S23, and performs a bit comparison process in step S25.

  The criterion (reference current IE in FIG. 7) used in the erase verify has a margin for strictly determining “1” with respect to the criterion (reference current IR) used in the normal read operation. That is, a correct value is read out from a bit that has passed the erase verify even in a normal read operation. From this, there is a possibility that the number of error bits may exceed the number of error bits that can be corrected if the erase verification determines that an error has occurred.In such a case, the bit comparison process is performed to reduce the number of error bits. The number of correctable bits can be reduced.

  Further, in the present embodiment, the memory control unit 100 determines, in the bit comparison processing, the erase error bit (for example, B1 in FIG. 5) determined as an error in the erase verify result data and the write data corresponding to the erase error bit. A comparison process with the write bit (B2) is performed.

  As described above, when the write bit of the write data corresponding to the erase error bit is “1”, there is a possibility that the number of error bits that can be corrected is exceeded. According to the present embodiment, the above-described case can be detected by performing the comparison processing of those bits.

  Further, in the present embodiment, when it is determined in the bit comparison process that the erase error bit and the write bit are at the same first logical level (“0”), the memory control unit 100 is the data of the write verify. A write error bit determined as an error in the write verification result data is determined as a bit that can be corrected by an error correction process, and it is determined that the write data has been successfully written to the nonvolatile memory.

  For example, as shown in FIG. 8, if it is determined in step S26 that the erase error bit and the write bit match, the process branches to YES, and the error correction enable / disable flag is set to 1 in step S24. Then, the process branches to YES in step S32, and if it is determined in step S33 that the number of write error bits is equal to or less than the number of bits in which error correction is possible, the process branches to YES and determines that the write was successful.

  As for the criterion (reference current IW in FIG. 7) used in the write verify, a margin for strictly determining “0” (first logical level) is set with respect to the criterion (reference current IR) used in the normal read operation. ing. That is, a correct value is read out even in a normal read operation for a bit of “0” that has passed the write verify. As shown in FIG. 9, in the erase verify, the bit of "0" is determined as an error bit (D1). That is, when it is determined that the erase error bit and the write bit are at the same first logical level (“0”), the bit does not become an error bit in a normal read operation. As a result, the number of error bits can be made equal to or less than the number of error-correctable bits even if the bits determined as errors in the write verification are permitted.

  Further, in the present embodiment, when it is determined in the bit comparison process that the erase error bit and the write bit are at the same first logic level (S26, YES in FIG. 8), an error in the write verify is performed. An error correction enable / disable flag indicating whether or not the error is permitted is set to be active for permitting the error (S24). When the error correction enable / disable flag is active (S32, YES), the memory control unit 100 determines whether the write error bit can be corrected by the error correction process (S33). Then, when it is determined that the write error bit can be corrected by the error correction process (S33, YES), the memory control unit 100 determines that the writing of the write data to the nonvolatile memory 10 has succeeded (passed).

  In this way, the logic level of the error correction enable / disable flag is set in the bit comparison process according to whether the erase error bit and the write bit have the same first logic level. Then, when the error correction enable / disable flag is active, it is determined whether a bit determined as an error in the write verify can be corrected by the error correction process. In this way, when the erase error bit and the write bit are at the same first logical level in the bit comparison processing, the write error bit can be permitted in the write operation.

  Further, the nonvolatile memory device 200 of the present embodiment includes a read circuit 30 that performs a read operation. Then, the read circuit 30 reads data from the nonvolatile memory 10 using the erase verify criterion (the reference current IE in FIG. 7) in the erase verify, and the write verify criterion different from the erase verify criterion in the write verify. The data is read from the nonvolatile memory 10 by (reference current IW).

  As shown in FIG. 7, a criterion for strictly determining “1” is used in erase verification, and a criterion for strictly determining “0” is used in write verification. By performing such a margin read, it is possible to provide a margin to data (guaranteed data) in erasing or writing. On the other hand, if the error bit is allowed on the premise of the error correction processing, the above-described problem may occur due to the influence of the margin read as described above. In the present embodiment, such a problem can be solved.

  In the present embodiment, as described later with reference to FIG. 11, the nonvolatile memory device 200 includes an erasing and writing circuit 20 for performing an erasing operation and a writing operation, and a reading circuit 30 for performing a reading operation. The memory control unit 100 includes a bit comparison unit 130 that performs a bit comparison process, a control unit 110 that controls the erase / write circuit 20 and the read circuit 30 and determines whether or not the data is read, and an error of data read by the read circuit 30. It has an error correction unit 150 that performs a correction process, and an error correction data generation unit 140 that generates error correction data used for the error correction process.

  With this configuration, the bit comparison unit 130 performs a bit comparison process between the erase verification result data and the write data, and the control unit 110 determines whether to permit the write error bit (permission determination). . Accordingly, it is possible to obtain correct result data in the error correction processing performed by the error correction unit 150.

  Although the configuration and operation of the nonvolatile storage device 200 have been described above, the following control method of the nonvolatile storage device 200 may be executed. That is, in the method of controlling the nonvolatile memory device 200 including the nonvolatile memory 10, the erase verify is performed in the write operation to the nonvolatile memory 10, and the erase verify result data and the write data, which are the result data of the erase verify, are bit-separated. A bit comparison process for comparing in units is performed, and a determination as to whether or not to permit an error in the write verification as being correctable by the error correction process is made based on the result of the bit comparison process.

  With such a control method of the nonvolatile memory device 200, it is possible to permit a detected error as being correctable by an error correction process in both the erase verify and the write verify. This makes it possible to extend the life of the nonvolatile memory 10 and the like.

2. Problems When Error Bits Are Allowed in Erase Operation and Write Operation Hereinafter, the erase operation of the present embodiment and the write operation of the comparative example will be described, and the problem that occurs when both of them are executed will be described. Then, details of the method of the present embodiment that can solve the problem will be described.

  FIG. 2 is a flowchart of the erasing operation of the present embodiment. When the erasing operation is started, the erasing and writing circuit 20 writes all “1” data (erasing data) to the address (word or page) specified by the memory control unit 100 and erases the stored data ( S1). Next, the read circuit 30 reads the data of the address erased in step S1 by the margin read for erasing, and the memory control unit 100 performs the erase verify (S2). That is, the read circuit 30 determines whether the data of each bit is “0” or “1” based on the criterion for erasure verification, and reads the data. Then, the memory control unit 100 compares the read data with the expected value (all “1”), and determines (detects) a bit (“0” bit) different from the expected value as an error bit. Next, the memory control unit 100 counts the number of error bits determined in step S2 (S3).

  Next, the memory control unit 100 determines whether or not the number of error bits is equal to or less than the number of bits that can be corrected by the error correction process (S4). If the number of error bits is equal to or smaller than the number of bits that can be corrected by the error correction process, the memory control unit 100 determines that the erasing has been successful (passed), and ends the erasing operation. On the other hand, when the number of error bits is not less than the number of bits that can be corrected by the error correction process, the memory control unit 100 determines whether the number of erasures is less than a specified value (S5). The number of times of erasing is the number of times that the erasing in step S1 is executed in the current erasing operation. If the erase count is less than the specified value, the memory control unit 100 counts up (increments) a variable indicating the erase count, and returns to step S1 (S6). On the other hand, if the erase count is not less than the specified value, the memory control unit 100 determines that the erase operation has failed (failed), and ends the erase operation.

  As described above, in the erasing operation of the present embodiment, basically, erasing is repeatedly performed until data stored in the nonvolatile memory 10 is correctly erased. On the other hand, if the number of bits is equal to or less than the number of bits that can be corrected by the error correction process at the time of reading, it is regarded that the erasure was possible even if there were error bits.

  FIG. 3 is a flowchart of the write operation of the comparative example. When the writing operation is started, the erasing and writing circuit 20 writes the writing data to the address (word or page) specified by the memory control unit 100 (S41). Next, the read circuit 30 reads the data written in step S41 by a write margin read, and the memory control unit 100 performs write verification (S42). That is, the read circuit 30 determines whether the data of each bit is “0” or “1” based on the determination criteria for write verification, and reads the data. Then, the memory control unit 100 compares the read data with an expected value (write data), and determines a bit different from the expected value as an error bit. Next, the memory control unit 100 counts the number of error bits determined in step S42 (S43).

  Next, the memory control unit 100 determines whether or not the number of error bits is equal to or less than the number of bits that can be corrected by the error correction processing (S44). If the number of error bits is equal to or smaller than the number of bits that can be corrected by the error correction process, the memory control unit 100 determines that the writing has succeeded (passed), and ends the writing operation. On the other hand, when the number of error bits is not less than the number of bits that can be corrected by the error correction process, the memory control unit 100 determines whether the number of times of writing is less than a specified value (S45). The number of times of writing is the number of times of executing the writing in step S41 in the current writing operation. When the number of times of writing is less than the specified value, the memory control unit 100 counts up (increments) a variable indicating the number of times of writing, and returns to step S41 (S46). On the other hand, if the number of times of writing is not less than the specified value, it is determined that the writing operation has failed (failed), and the writing operation is terminated.

  As described above, in the write operation of the comparative example, basically, the write operation is repeatedly performed until the write data is correctly written in the nonvolatile memory 10. On the other hand, if the number of bits is equal to or less than the number of bits that can be corrected by the error correction processing at the time of reading, it is considered that writing was possible even if there were error bits.

  As described above, if the number of error bits is equal to or less than the number of error-correctable bits in the erasing operation or the writing operation, error bits are permitted for the following reason.

  FIG. 4 is an example of a histogram showing the relationship between the number of erases and the number of bits in which stored data of bits is erased (that is, the erase verify is passed).

  As indicated by A1 in FIG. 4, there may be a case where there is a bit that is more prominent than the average number of times of erasure and has a higher number of times of erasure. Suppose that erasure is repeated without permitting error bits until all bits are determined to be "1" by erase verify. In this case, erasure is repeated until "1" is written to the bit indicated by A1. As a result, erasure (writing of “1”) is repeated more than necessary for the bit that should be completed with the average number of erasures as indicated by A2. When such overwriting is performed, the memory cells may be damaged, and the life of the nonvolatile memory 10 may be shortened.

  In this regard, even if a bit such as A1 is determined to be an error in the erase verification, by permitting the error and terminating the erase operation, it is possible to reduce the number of erases as indicated by A3. As a result, the life of the nonvolatile memory 10 can be extended.

  In the above description, erasing is described as an example. However, a histogram having similar characteristics is obtained for the number of times of writing, and the same argument holds. That is, in a write operation, “0” is written to a bit that has been set to “1” by erasure, but by permitting an error bit in write verification, the number of times of writing (overwriting of “0”) can be suppressed.

  By the way, when the error bit is permitted only in the erasing operation and the error bit is not permitted in the writing operation, or when the error bit is permitted only in the writing operation and the error bit is not permitted in the erasing operation, the error correction processing corrects the error bit. The data can be corrected (for example, see FIGS. 13A to 16 described later). However, in the above-described erase operation of the present embodiment and the write operation of the comparative example, the error bit is permitted in both of the operations. When error bits are permitted in both the erasing operation and the writing operation, correct data may not be corrected by error correction processing. Hereinafter, this point will be described with reference to FIGS.

  FIG. 5 shows a specific example in which error correction cannot be performed even though the erase verify and the write verify have been passed.

  As shown in FIG. 5, data stored in the non-volatile memory 10 includes data originally to be stored in the non-volatile memory 10 (hereinafter, referred to as user data) and a user data for performing error correction of write data. And error correction data generated from the data. Here, the user data is, for example, data transferred from a processing device (CPU or the like), data generated by a process of the memory control unit 100 or the like, and only data prepared by a specific user or the like is assumed. Not something.

  For example, in the case of a paging method in which a memory is divided into pages of a predetermined size and controlled, user data corresponds to data of one page. Then, error correction data is generated from the one page of data. Alternatively, in the case of the method of controlling in word units, the user data corresponds to one word data. Then, error correction data is generated from the one word data.

FIG. 5 shows an example of adding error correction data using a Hamming code. In this method, up to 1 error bit can be corrected from the combined data of user data and error correction data by associating N + 1 bits of error correction data with ^2N bits of user data. It is. Details of the error correction method will be described later with reference to FIGS. FIG. 5 shows that 4 (= 2 ² ) bits of user data (x1, x2, x3, x4) are added with 3 (= 2 + 1) bits of error correction data (p1, p2, p3) by Hamming code. This is an example in which one error bit can be corrected at a maximum of 7 bits of write data. Note that the maximum number of correctable bits may be two or more. Further, the method of generating the error correction data is not limited to the Hamming code.

  As shown in FIG. 5, the expected value of the data for erasure is “1111111”. In the erase operation, if the data read by the erase verify (referred to as erase verify result data) is “1101111”, the bit x3 indicated by B1 is an error bit. Since the number of error bits is 1 or less, it is determined that the erasing operation has been successful.

  Next, a write operation is performed. Assume that the expected value of the write data is “0110001”. In the writing operation, writing is performed only on the bits x1, x4, p1, and p2 of “0”. That is, since the bit x3 (write bit) shown in B2 is "1", writing is not performed, and the state (charge accumulated in the memory cell in the erase operation) determined to be "0" by the erase verify in the erase operation is maintained. You. At this time, it is expected that the bit x3 becomes “0” in the data read by the write verify (referred to as write verify result data). However, as indicated by B3, the bit x3 may be determined to be “1” due to the influence of the margin read. The effect of the margin read will be described later with reference to FIG.

  Since the expected value of the bit x3 is "1", the bit x3 is determined to be a pass in the write verify unlike the erase verify. Then, since bit x3 is not counted as an error bit, it is determined that writing has succeeded even if there is one error bit other than bit x3. As shown in B4, it is assumed that the bit x1 whose expected value is "0" is determined to be "1" in the write verify, and is determined to be an error bit.

  At this time, as shown in B5, in the read data (data before error correction) in the normal read operation, the bit x3 may be read as “0” because the margin read is not performed. In this case, two bits x1 and x3 differ from the expected value, and exceed the number of error bits that can be corrected. When error correction processing is performed on such read data, the data resulting from the error correction processing becomes “1101001”, which is different from the expected value “0110001” of the write data.

  Specifically, as shown in FIG. 6A, the syndromes (s1, s2, s3) are obtained from the read data “1100001”. Then, as shown in FIG. 6B, the syndrome (s1, s2, s3) is converted into an error vector (e1, e2, e3, e4, e5, e6, e7). In the error vector in FIG. 6B, e4 = 1, indicating that bit x4 is an error bit. As shown in FIG. 6C, an exclusive OR (xor) of the read data and the error vector is obtained. By this processing, the logical level of the bit x4, which is an error bit, is inverted from “0” to “1”, and “1101001” is obtained as the result data of the error correction processing. As described above, when error bits exceeding the number of error-correctable bits exist in the read data, even if the error correction processing is performed on the read data, the data cannot be restored to the same value as the expected value of the write data. .

  FIG. 7 is a diagram schematically illustrating margin reading. In the nonvolatile memory 10, data is read by comparing the current from the memory cell (cell current) with a reference current by a sense amplifier. As shown in FIG. 7, a margin is provided for a reference current IE (> IR) in erase verification and a reference current IW (<IR) in write verification with respect to a reference current IR in a normal read operation.

  In the erase verify, when the cell current is larger than the reference current IE, it is determined to be “1”. That is, the histogram DSE in which the number of bits that have passed the erase verify is counted for each cell current has a distribution above the reference current IE. On the other hand, if the cell current is smaller than the reference current IE, it is determined to be “0”, so that the cell current of the memory cell corresponding to the bit x3 of B1 in FIG. 5 is smaller than the reference current IE. Here, as shown by C1, it is assumed that the cell current is near the reference current IR in a normal read operation (eg, a slightly smaller value).

  In the write verify, when the cell current is smaller than the reference current IW, it is determined to be “0”. That is, the histogram DSW in which the number of bits passing the write verify is counted by each cell current has a distribution below the reference current IW. On the other hand, when the cell current is larger than the reference current IW, it is determined to be “1”, so that the bit of the cell current indicated by C1 is determined to be “1”. In this manner, as shown by B3 in FIG. 5, the bit x3 is determined to be "1" in the write verify, and the determination result is different from that of the erase verify.

  When the bit x3 is read by the normal read operation, the bit x3 is determined to be "0" because the cell current is slightly smaller than the reference current IR as indicated by C1. In this way, as indicated by B5 in FIG. 5, the bit x3 is read as "0" in the normal read operation, and has a value different from the expected value "1" of the bit x3 of the write data.

3. Hereinafter, a method according to the present embodiment that can solve the above-described problem will be described. FIG. 8 is a flowchart of the write operation of the present embodiment.

  When the write operation is started, the read circuit 30 reads the data at the address where the write data is to be written (data written in the erase operation before the write operation) by the erase margin read, and the memory control unit 100 erases the data. Verify is performed (S21). That is, the memory control unit 100 compares the read data with the expected value (all “1”), and determines a bit (bit “0”) different from the expected value as an error bit. Next, the memory control unit 100 counts the number of error bits determined in step S21 (S22).

  Next, the memory control unit 100 determines whether or not use of the error correction processing is permitted in the erasing operation (S23). That is, it is determined whether or not the number of error bits counted in step S22 is 1 or more (1 in the present embodiment). When the use of the error correction process is not permitted in the erasing operation (the number of error bits is 0), the memory control unit 100 sets the error correction enable / disable flag to “1” (active) (S24).

  On the other hand, when the use of the error correction processing is permitted in the erasing operation (the number of error bits is 1 or more), the memory control unit 100 determines whether the erasure verification result data and the write data read in the erasure verification in step S21. A bit comparison process with (expected value) is performed (S25). Specifically, an error bit in the erase verify result data is compared with a bit of write data of the same digit (position) as the error bit.

  Next, the memory control unit 100 determines whether or not the error bit matches the bit of the write data corresponding to the error bit (S26). If the error bit matches the corresponding bit of the write data, the error correction enable / disable flag is set to "1" in step S24. Since the error bit in the erase verify is “0”, it is determined that they match when the bit of the corresponding write data is “0”. On the other hand, if the error bit does not match the corresponding write data bit, the memory control unit 100 sets the error correction enable / disable flag to “0” (inactive) (S27). When the number of error bits for which error correction is possible is two or more, for example, when even one bit does not match, the error correction enable / disable flag is set to “0”.

  Next, the erase and write circuit 20 writes the write data to the address where the erase verify was performed in step S21 (S28). Next, the read circuit 30 reads the data written in step S28 by a write margin read, and the memory control unit 100 performs write verification (S29). That is, the memory control unit 100 compares the read data with an expected value (write data), and determines a bit different from the expected value as an error bit. Next, the memory control unit 100 counts the number of error bits determined in step S29 (S30). At this time, the number of error bits is counted for bits other than the bits determined to be error bits in the erase verify in step S21.

  Next, the memory control unit 100 determines whether or not the number of error bits counted in step S30 is 0 (S31). If the number of error bits is 0, the memory control unit 100 determines that the writing has succeeded (passed), and ends the writing operation. If the number of error bits is not 0, the memory control unit 100 determines whether or not the error correction enable / disable flag is "1" (S32). If the error correction enable / disable flag is “1”, the memory control unit 100 determines whether the number of error bits counted in step S30 is equal to or less than the number of bits that can be corrected by the error correction process (S33). . If the number of error bits is equal to or less than the number of bits that can be corrected by the error correction processing, the memory control unit 100 determines that the writing has succeeded (passed), and ends the writing operation.

  On the other hand, when the number of error bits is not smaller than the number of bits that can be corrected by the error correction process, the memory control unit 100 determines whether the number of times of writing is less than a specified value (S34). If the number of times of writing is less than the specified value, the memory control unit 100 counts up (increments) a variable indicating the number of times of writing, and returns to step S28 (S35). On the other hand, if the number of times of writing is not less than the specified value, the memory control unit 100 determines that the writing operation has failed (failed), and ends the writing operation. In this case, a flag indicating a failure (defective product) may be stored in a register (not shown) or may be notified to a user (for example, the CPU or the like may use an interface (not shown) of the nonvolatile storage device 200). The CPU may read a flag from the register via the CPU, and perform processing for notifying the user based on the flag). Alternatively, the nonvolatile memory 10 may have a redundant memory area, and write data for which a write operation has failed may be written to the redundant memory area.

  If the error correction enable / disable flag is “0” in step S32, the memory control unit 100 proceeds to step S34 without determining whether the error bit can be corrected. That is, when the error correction enable / disable flag is “0”, the error bit in the write verify is not permitted (writing is repeated until the number of error bits becomes 0 or the number of times of writing exceeds a specified value).

  The write operation according to the above flow will be described in a specific example with reference to FIGS. FIG. 9 is a specific example in which the error correction enable / disable flag becomes “1” by the bit comparison process.

  As shown in FIG. 9, the expected value of the erase verification result data is “1111111”. Assuming that the erase verify result data read by the erase verify is “1101111”, the bit x3 of “0” is determined as an error bit (erase error bit) as indicated by D1. Since an error bit is detected, the process branches to YES in step S23 in FIG. 8, and a bit comparison process between the erase verification result data and the write data is performed.

  Assuming that the expected value of the write data is "0101100", the bit x3 of the write data corresponding to the error bit x3 of the erase verify is "0" as indicated by D2. That is, since it is determined that they match in the bit comparison process, the process branches to YES in step S26 in FIG. 8, and the error correction enable / disable flag is set to "1" in step S24.

  It is assumed that, after writing the write data “0101100”, the write verify result data read by the write verify is “1101100”. In this case, as indicated by D3, the bit x1 is "1", which is different from the expected value "0", so that it is detected as an error bit (write error bit). Since the error correction enable / disable flag is "1", the flow branches to YES in step S32 of FIG. 8, and the flow branches to YES in step S33 because the number of error bits is 1 or less. That is, the error bit x1 is permitted, and the write operation ends.

  When the write data is read by a normal read operation, the read data is, for example, “1101100”. As indicated by D4, the error bit x1 in the write verify may be read as "1" even in the read data. In this case, bit x1 is an error bit. On the other hand, it is checked whether the error bit x3 in the erase verify matches the expected value "0" in the write verify. That is, as described in FIG. 7, it is determined that the cell current of the bit x3 is smaller than the reference current IW. Since the reference current in the normal read operation is IR> IW, the bit determined to be “0” in the write verify is read as “0” also in the normal read operation as indicated by D5. That is, the bit does not become an error bit.

  As described above, only the bit x1 determined to be an error bit in the write verify operation may become an error bit in the read operation, and does not exceed the number of error-correctable bits. As a result, the result data of the error correction processing becomes “0101100”, and the expected value of the write data is restored.

  FIG. 10 is a specific example in a case where the error correction enable / disable flag becomes “0” by the bit comparison process.

  As shown in FIG. 10, assuming that bit x3 is determined to be an error bit (erase error bit) in the erase verify as indicated by E1, the process branches to YES in step S23 in FIG. 8, and the erase verify result data and the write data are erased. A bit comparison process is performed.

  Assuming that the expected value of the write data is “0111010”, the bit x3 of the write data corresponding to the error bit x3 of the erase verify is “1” as indicated by E2. That is, since it is determined that the bits do not match in the bit comparison process, the process branches to NO in step S26 in FIG.

  After writing the write data “0111010”, the write verify result data read by the write verify may be “0101010”. That is, as described with reference to FIG. 7, the bit x3 determined to be an error bit ("0") in the erase verify and the expected value of the write data is "1" is "0" in the write verify as indicated by E3. (That is, a write error bit). Since the error correction enable / disable flag is "0", the process branches to NO in step S32 in FIG. 8, and it is not permitted to generate a new error bit other than the bit x3 in the write verification. That is, the read data in the normal read operation may be “0101010” having an error in the bit x3, but no error bit is generated other than the bit x3.

  As described above, only the bit x3 determined to be an error bit in the erase verify operation may become an error bit in the read operation, and does not exceed the number of error-correctable bits. As a result, the result data of the error correction processing becomes “0111010”, and the expected value of the write data is restored.

4. Detailed Configuration FIG. 11 is a detailed configuration example of the nonvolatile storage device 200 of the present embodiment. In FIG. 11, the nonvolatile memory 10 includes a user data memory cell array 11 and an error correction data memory cell array 12. Further, the memory control unit 100 includes a control unit 110, a verify determination unit 120, a bit comparison unit 130, an error correction data generation unit 140, and an error correction unit 150. The bit comparison unit 130 includes a write data register 131 and a read data register 132.

  The user data memory cell array 11 is a memory cell array that stores user data among erase data and write data. The error correction data memory cell array 12 is a memory cell array that stores error correction data among erase data and write data. For example, these memory cell arrays are obtained by dividing one memory cell array into regions. When erasing, writing, and reading are performed, the user data and the error correction data associated therewith are accessed.

  The error correction data generator 140 generates error correction data from the user data DIN. The error correction data and the user data DIN are held in the write data register 131 as write data. The erasing and writing circuit 20 performs writing to the nonvolatile memory 10 based on the write data held in the write data register 131.

  Data read from the nonvolatile memory 10 by the read circuit 30 is held in the read data register 132 as read data. The error correction unit 150 performs an error correction process based on the read data held in the read data register 132, and outputs result data DOUT of the error correction process.

  The verify determination unit 120 performs erase verify in the erase operation (S2 in FIG. 2), erase verify in the write operation (S21 in FIG. 8), and write verify in the write operation (S29 in FIG. 8). That is, the data read by these verifications is compared with an expected value to detect an error bit.

  The bit comparison unit 130 performs a bit comparison process (S25 in FIG. 8) in the write operation. That is, the write data held in the write data register 131 and the erase verify result data held in the read data register 132 are compared for each bit.

  The control unit 110 controls an erasing operation, a writing operation, and a reading operation. That is, the control unit 110 performs the processing of steps S3 to S6 in FIG. 2 in the erasing operation. In step S1, an address is designated and an erase instruction is given to the erase / write circuit 20. Further, the control unit 110 executes the processing of steps S22 to S24, S26, S27, and S30 to S35 in FIG. 8 in the writing operation. In step S28, an address designation and a write instruction are issued to the erase / write circuit 20. Further, the control unit 110 instructs the read circuit 30 to specify an address and read in the read operation.

  FIG. 12 is a detailed configuration example of the readout circuit 30 and the nonvolatile memory 10. The read circuit 30 includes a current mirror circuit 31 and a sense amplifier 32. The nonvolatile memory 10 includes a reference cell 14 and a memory cell array 13. Although one sense amplifier 32 is shown in FIG. 12, a plurality of sense amplifiers are actually provided corresponding to a plurality of bit lines.

  The reference cell 14 has basically the same structure as a normal memory cell, but the threshold voltage is adjusted by writing to the reference cell 14 in the inspection step, thereby adjusting the reference cell current to a predetermined current. Irc is output. The memory cell array 13 corresponds to the user data memory cell array 11 and the error correction data memory cell array 12 in FIG. Icel is a cell current output from the memory cell selected by the word line to the bit line.

  The current mirror circuit 31 mirrors the reference cell current Irc output from the reference cell 14 of the nonvolatile memory 10 and outputs a reference current Iref. The sense amplifier 32 compares the reference current Iref with the cell current Icel, and outputs “0” or “1” as data.

  The current mirror circuit 31 can select a plurality of mirror ratios. Then, by switching the mirror ratio based on the control signal from the control unit 110, the switching of the reference currents IW, IR, and IE in FIG. 7 is realized.

  Note that the method of switching the reference current is not limited to this. For example, a plurality of reference cells having different reference cell currents may be provided, and the reference current may be switched by selecting the reference cells based on a control signal from the control unit 110.

5. Error Correction Data Generation Processing and Error Correction Processing Hereinafter, details of the error correction data generation processing and the error correction processing will be described. FIG. 13A to FIG. 13C are explanatory diagrams of the generation processing of the error correction data. Hereinafter, an example will be described in which error correction data is generated by a Hamming code and an error bit of up to one bit can be corrected.

  The data is represented as "0011", and when it is considered as a vector, it is represented as (0, 0, 1, 1), but the data is substantially different only in the notation. The content is the same.

  As shown in FIG. 13A, when the user data is 4 bits, 3-bit error correction data is generated. Then, the combined 7-bit data becomes the write data w. The bits p1, p2, and p3 of the error correction data are obtained by the equations shown in FIG. 13B. Here, “xor” is an exclusive OR. FIG. 13C shows the expression of FIG. 13B as a truth table. When the user data is "1111", the error correction data is "111", and all "1" s are written in the erasing operation.

  14A to 14D are explanatory diagrams of the error correction processing. As shown in FIG. 14A, the read data y has the same 7 bits as the write data w. The syndrome (s1, s2, s3) is obtained from the read data y by the equation shown in FIG. 14B. An error vector (e1, e2, e3, e4, e5, e6, e7) is obtained from the syndromes (s1, s2, s3) according to the syndrome pattern (correspondence between the syndrome and the error vector) shown in FIG. 14C. When the component (bit) ei = 1 of the error vector, it indicates that the bit yi of the read data y is an error bit. Here, i is an integer of 1 or more and 7 or less. When the syndrome is (0,0,0), the error vector is (0,0,0,0,0,0,0), indicating that there is no error bit. As shown in FIG. 14D, the exclusive OR of the error vector and the read data is obtained, and the result is output as result data (final read data) of the error correction process.

  FIG. 15 shows a specific example in which an error bit permitted in an erasing operation is corrected. When the erase verify result data is “1101111”, if a normal read operation is performed as it is, “1101111” may be read as the read data. In this read data, the bit x3 has an error. In this case, the syndrome is (1,1,0) from the equation in FIG. 14B, and the error vector is (0,0,1,0,0,0,0) from the syndrome pattern in FIG. 14C. When the result data is obtained from the equation of FIG. 14D, the logical level of bit x3 is inverted to “1111111”, and the error of bit x3 has been corrected.

  FIG. 16 shows a specific example of correcting an error bit permitted in a write operation. If the write data is “0110001” and the write verify result data is “1110001”, “1110001” may be read as the read data. In this read data, the bit x1 has an error. The syndrome is (1, 0, 1) from the equation in FIG. 14B, and the error vector is (1, 0, 0, 0, 0, 0, 0) from the syndrome pattern in FIG. 14C. When the result data is obtained from the equation of FIG. 14D, the logical level of bit x1 is inverted to “0110001”, and the error of bit x1 has been corrected.

In the above, the case where the user data is 4 bits has been described as an example, but the present invention is not limited to this. That is, when error correction data is generated by a Hamming code, up to 1 error bit can be corrected by adding n + 1 bit error correction data to 2 ⁿ bits of user data. . In the above description, the case where the user data has an error has been described as an example. However, even when the error correction data has an error, the error correction data is corrected by the same method. In other words, if the error correction data is equal to or less than the maximum number of bits that can be corrected in the data obtained by combining the user data and the error correction data, the data is corrected to correct data.

6. Electronic Device FIG. 17 is a configuration example of an electronic device 400 according to the present embodiment. As the electronic device 400 of the present embodiment, various electronic devices such as a printer, a printer ink cartridge, an oscillator, a gyro sensor, a projector, a television device, an information processing device (computer), and a portable information terminal can be assumed.

  The electronic device 400 includes a processing unit 310 (for example, a processor such as a CPU or a gate array), a storage unit 320 (memory), an operation unit 330 (operation device), an interface unit 340 (interface circuit, interface device), and a display unit 350 ( Display).

  The display unit 350 is, for example, a liquid crystal display device or an EL (Electro-Luminescence) display device using a self-luminous element. The operation unit 330 is a user interface that receives various operations from the user. For example, it is a button, a mouse, a keyboard, a touch panel attached to the display unit 350, or the like. The interface unit 340 is a data interface that inputs and outputs image data and control data. For example, a wired communication interface such as a USB or a wireless communication interface such as a wireless LAN. The storage unit 320 stores data input from the interface unit 340. Alternatively, the storage unit 320 functions as a working memory of the processing unit 310. The non-volatile storage device 200 stores setting data for setting operation of the electronic device, data used for various processes performed by the processing unit 310, and the like. The processing unit 310 performs control processing of various parts of the electronic device and various data processing based on the data stored in the nonvolatile storage device 200.

  Note that the configuration of the electronic device 400 is not limited to FIG. 17, and various modifications can be made, such as omitting some of the components or adding other components. For example, when the electronic device is an oscillator or a gyro sensor, the electronic device includes the processing unit 310, the nonvolatile storage device 200, an analog circuit (for example, a drive circuit, a detection circuit, and the like), and a vibrator. The processing unit 310, the non-volatile memory device 200, and the drive circuit are configured as one integrated circuit device, a vibrator is connected to the analog circuit, and the integrated circuit device and the vibrator are stored in a package.

  Although the present embodiment has been described in detail as described above, those skilled in the art can easily understand that many modifications that do not substantially depart from the novel matter and effects of the present invention are possible. Therefore, such modifications are all included in the scope of the present invention. For example, in the specification or the drawings, a term described at least once together with a broader or synonymous different term can be replaced with the different term in any part of the specification or the drawing. In addition, all combinations of the present embodiment and the modifications are also included in the scope of the present invention. The configuration and operation of the nonvolatile memory, the erasing and writing circuit, the reading circuit, the memory control unit, the nonvolatile storage device, and the electronic device are not limited to those described in the present embodiment, and various modifications can be made. is there.

10: nonvolatile memory, 11: user data memory cell array,
12 data memory cell array for error correction, 13 memory cell array
14: reference cell, 20: erase and write circuit, 30: read circuit,
31: current mirror circuit, 32: sense amplifier, 100: memory control unit,
110: control unit, 120: verify determination unit, 130: bit comparison unit,
131: write data register, 132: read data register,
140: an error correction data generation unit; 150: an error correction unit;
200: nonvolatile storage device, 310: processing unit, 320: storage unit, 330: operation unit,
340: interface unit, 350: display unit, 400: electronic device,
IE: reference current (criterion for erasure verification), IR: reference current,
IW: reference current (criterion for write verification),
p1 to p3: bits of error correction data, x1 to x4: bits of user data

Claims (10)

A non-volatile memory;
A memory control unit that controls erase operation, read operation, and write operation to the nonvolatile memory,
Including
The memory control unit includes:
In the write operation, an erase verify is performed, and a bit comparison process of comparing the erase verify result data, which is the result data of the erase verify, with the write data in a bit unit is performed, and an error in the write verify can be corrected by an error correction process. A non-volatile storage device characterized in that the determination as to whether or not to permit is made based on the result of the bit comparison process. In claim 1,
The memory control unit includes:
The nonvolatile memory device according to claim 1, wherein the bit comparison process is performed when an error is determined in the erase verify. In claim 1 or 2,
The memory control unit includes:
In the bit comparison process, a comparison process is performed between an erase error bit determined as an error in the erase verify result data and a write bit of the write data corresponding to the erase error bit. apparatus. In claim 3,
The memory control unit includes:
When it is determined in the bit comparison process that the erase error bit and the write bit are at the same first logical level, a write error determined to be an error among write verify result data that is the write verify result data. A non-volatile memory device, wherein a bit is a bit that can be corrected by the error correction processing, and it is determined that writing of the write data to the non-volatile memory is successful. In claim 4,
The memory control unit includes:
When it is determined in the bit comparison process that the erase error bit and the write bit are at the same first logical level, an error correction enable / disable flag indicating whether an error in the write verify is permitted is set to an error. Set to Active to allow
If the error correction enable / disable flag is active, determine whether the write error bit is correctable by the error correction process,
When it is determined that the write error bit can be corrected by the error correction processing, it is determined that the write data has been successfully written to the nonvolatile memory. In any one of claims 1 to 5,
Including a read circuit for performing the read operation,
The read circuit,
In the erase verify, data is read from the non-volatile memory based on an erase verify determination criterion,
The nonvolatile memory device according to claim 1, wherein in the write verification, data is read from the nonvolatile memory according to a write verification criterion different from the erase verification criterion. In any one of claims 1 to 6,
An erase and write circuit for performing the erase operation and the write operation;
A read circuit for performing the read operation;
Including
The memory control unit includes:
A bit comparison unit that performs the bit comparison process;
A control unit for controlling the erasing and writing circuit and the reading circuit, and determining whether or not the erasing and writing circuit is read, and
An error correction unit that performs the error correction process on the data read by the read circuit;
An error correction data generation unit that generates error correction data used for the error correction processing,
A nonvolatile storage device, comprising:   An integrated circuit device comprising the nonvolatile memory device according to claim 1.   An electronic apparatus comprising the nonvolatile storage device according to claim 1. A method for controlling a nonvolatile storage device including a nonvolatile memory,
In the write operation to the nonvolatile memory, erase verify is performed,
Performing a bit comparison process of comparing the erase verify result data, which is the result data of the erase verify, with the write data in bit units;
A method for controlling a nonvolatile memory device, comprising determining whether or not to permit an error in write verification as being correctable by an error correction process based on a result of the bit comparison process.