CN113707208B - Method for controlling verification operation for error correction of nonvolatile memory device and nonvolatile memory device - Google Patents
Method for controlling verification operation for error correction of nonvolatile memory device and nonvolatile memory device Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1208—Error catch memory
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Abstract
The present invention provides a method of controlling a verification operation for error correction of a nonvolatile memory device, the method comprising the following; the fault tolerant bit value for error correction of the non-volatile memory device is set to a first value to control a plurality of verify operations in dependence upon the fault tolerant bit value. After at least a portion of the non-volatile storage device is programmed a specified number of times, the fault tolerant bit value is updated from the first value to a second value to control the plurality of verify operations in accordance with the fault tolerant bit value, wherein the second value is greater than the first value and less than or equal to a fault tolerant bit threshold. The method may be performed during at least a portion of the nonvolatile memory device is programmed and verified.
Description
Technical Field
The present invention relates to a nonvolatile memory device, and more particularly, to a method for controlling a verification operation for error correction of a nonvolatile memory device and a nonvolatile memory device using the same.
Background
Generally, a nonvolatile memory, such as a flash memory, uses an error correction code (error correction code, ECC) to repair a soft error (soft error) or a physical error (physical fault) of a memory cell (hereinafter, the soft error and the physical error are collectively referred to as an error). However, it is limited to repair data using the error correction code, for example, a single error correction-double error detection (SEC-DED) algorithm can repair only a single error bit. If more than one bit needs to be repaired, it is necessary to apply other algorithms and apply more storage space to the algorithms, which reduces the available storage space.
In the prior art, when a portion of a non-volatile memory (e.g., a particular page) is programmed, a verify operation is performed on programmed bits (e.g., bits of the page) of the non-volatile memory to determine whether the programmed bits include error bits and the number of error bits exceeds a reference value representing the error correction capability of the non-volatile memory. If the number of erroneous bits is below the reference value, the programmed bits are determined to be verified. If the number of erroneous bits exceeds the reference value, the programming bits are determined to be verification failure, and the page is programmed again, and so on.
Disclosure of Invention
It is an object of the present invention to propose a technique of controlling a verification operation for error correction of a nonvolatile memory device.
To achieve the above object, the present invention provides a method of controlling a verification operation for error correction of a nonvolatile memory device, the method comprising: setting a fault tolerant bit (tolerated error bit, TEB) value for error correction of the non-volatile storage to a first value to control a plurality of verify operations in accordance with the fault tolerant bit value, wherein the first value is less than a fault tolerant bit threshold for error correction of the non-volatile storage. After at least a portion of the non-volatile storage device is programmed a specified number of times, the fault-tolerant bit value is updated from the first value to a second value to control the plurality of verify operations in accordance with the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold.
In one embodiment, the fault tolerant bit value is set to the first value when the number of pulses is less than a pulse number threshold.
In an embodiment, the first value is zero or less than the fault tolerance bit threshold.
In an embodiment, the fault tolerant bit value is updated from the first value to the second value when the pulse number is equal to or greater than the pulse number threshold.
In some embodiments, the method includes progressively increasing the fault tolerant bit value from the second value at least once to control the plurality of verify operations in accordance with the fault tolerant bit value, wherein the increased fault tolerant bit value is less than or equal to the fault tolerant bit threshold.
In some embodiments, the method is performed during the programming and verification of at least a portion of the non-volatile storage device.
In order to achieve the above object, the present invention further provides a nonvolatile memory device, which includes a nonvolatile memory cell array, a page buffer circuit, and a control logic circuit. The page buffer circuit is coupled to the nonvolatile memory cell array. The control logic circuit is coupled to the non-volatile memory cell array and the page buffer circuit. The control logic circuit is to control the non-volatile memory device. During programming and verifying of at least a portion of the array of non-volatile memory cells controlled by the control logic, the control logic sets a tolerance bit value to a first value to control the plurality of verify operations in accordance with the tolerance bit value, wherein the first value is less than a fault tolerance bit threshold for error correction of the non-volatile memory device; after at least a portion of the array of non-volatile memory cells is programmed a specified number of times, the control logic updates the fault-tolerant bit value from the first value to a second value to control the plurality of verify operations in accordance with the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold.
In one embodiment, the control logic progressively increases the fault tolerant bit value from the second value at least once to control the plurality of verify operations in accordance with the fault tolerant bit value, wherein the increased fault tolerant bit value is less than or equal to the fault tolerant bit threshold.
As described above, the present invention provides a method embodiment of controlling a verification operation for error correction of a nonvolatile memory device, and a nonvolatile memory device embodiment using the method. Therefore, the method can improve the probability of correctly compiling the data. Therefore, the method can avoid the error correction performance of the nonvolatile memory device from being impaired because the data to be written is smaller than or equal to the tolerance bit value, thereby enhancing the reliability of the nonvolatile memory device.
For a further understanding of the nature and the technical aspects of the present invention, reference should be made to the following detailed description of the invention and to the accompanying drawings, which are included to illustrate and not to limit the scope of the claims.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the description below are only some embodiments of the invention and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of controlling a verify operation for error correction of a non-volatile memory according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an example of an implementation of the method of FIG. 1;
FIG. 3 is a flow chart of a method of controlling a verify operation for error correction of a non-volatile memory according to some embodiments of the present invention;
FIG. 4 is a schematic diagram showing an example of an implementation of the method of FIG. 3;
FIG. 5 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention;
FIG. 6 is a flow chart of a program for programming and verifying the non-volatile memory while the method according to an embodiment of the present invention is being performed; and
FIG. 7 is a schematic diagram of an example of programming voltage increases during performance of the method of FIG. 6.
Reference numerals illustrate:
1. Nonvolatile memory device
10. Memory cell array
20 X-ray decoder
30. Voltage generator
40. Page buffer circuit
45 Y-line decoder
50. Input/output buffer
60. Control logic circuit
600. Bit detector
610. Tolerance dislocation detector
620. Pulse counting circuit
A. number of pulses A1, A2, A3, A4
B. Numerical values of B1, B2, B3 and B4
S10, S20, S30, S110, S120, S130, S140, S145, S150, S155, S160 steps
Detailed Description
For a fuller understanding of the objects, features and advantages of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings.
Hereinafter, embodiments of techniques for controlling verify operations to enable error correction of a non-volatile memory are presented, wherein a fault-tolerant bit (tolerated error bit, TEB) value for error correction of the non-volatile memory device may be updated during verify operations related to a program operation. In some embodiments, the fault-tolerant bit value will be determined in some manner so that the non-volatile storage device will be more reliable and avoid particular programming data from impairing the ability to correct errors.
Practical application of this technique assumes that in certain application scenarios, a computing device (e.g., a smart phone, a laptop, or a server, etc.) needs to write a small number of bits of data to a non-volatile storage (e.g., a flash memory device) that needs to have the ability to have X bits (bit) error correction codes (error correction code, ECC) per Y bits (bytes), for example, 8 bits error correction codes per 512 bits. When a portion of the non-volatile memory device (e.g., a particular page) is programmed, a verify operation is performed with respect to programming bits of the non-volatile memory device (e.g., a plurality of bits of the page), wherein a determination is made as to whether the programming bits include a number of error bits that exceeds the fault-tolerant bit value. If the number of error bits is less than or equal to the fault tolerant bit value, the programmed bits are determined to pass verification. If the number of erroneous bits exceeds the fault-tolerant bit value, it is determined that the programming bits failed to verify, and the page is programmed again, and so on. Typically, the fault tolerant bit value is a fixed value that is used to indicate the error correction capability of the non-volatile memory. For example, in this application scenario, the page is 512 bytes and the fault tolerant bit value is 8.
The inventors have obtained a specific case for the above application scenario. In this case, data from the computing device having a bit number less than or equal to the fault tolerant bit value is written to a blank area in the non-volatile memory, wherein all bits in the blank area have the same value prior to writing the data. Each time a verify operation is performed, because the written data is less than or equal to the fault-tolerant bit value, the verify operation for the data is always verified. In this case, even though the data may not be correctly organized, no organization operation is performed. Thus, the data that is considered to have been compiled will consume error correction capability. In a worst case scenario, the computing device may crash or cease functioning if the data is corrupted by incorrect programming. This is critical for the non-volatile memory.
Referring to fig. 1, fig. 1 is a flowchart of a method of controlling a verification operation for error correction of a nonvolatile memory device according to an embodiment of the present invention. The method comprises steps S10 and S20.
As shown in step S10, a fault-tolerant bit value for error correction of the nonvolatile memory device is set to a first value to control a plurality of verification operations according to the fault-tolerant bit value, wherein the first value is smaller than a fault-tolerant bit threshold for error correction of the nonvolatile memory device.
After at least a portion of the non-volatile storage device is programmed a certain number of times, the fault-tolerant bit value is updated from the first value to a second value to control a plurality of verification operations according to the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold.
Thus, the method can avoid the impairment of the error correction capability caused by the written data being less than or equal to the fault-tolerant bit value. For ease of illustration, in the application scenario discussed above, when a verification operation is performed, the verification operation will fail by setting the tolerance bit value to a first value (e.g., 0,1, or 2) that is less than the fault tolerance bit threshold (e.g., 8) by step S10, since the data to be written (e.g., a small number of bits, such as 8, 7 bits, or less) is substantially greater than the fault tolerance bit value (e.g., 0,1, or 2). In the case of an incremental pulsing (INCREMENTAL STEP pulse programming, ISPP) technique applied to the non-volatile memory, a programming operation will be performed, regardless of whether the data has been properly programmed, since the verification operation of the fault-tolerant bit value with respect to the first value has failed. In the delta pulse programming, the verify operation may repeatedly fail during a period when at least a portion of the non-volatile memory (e.g., a small number of bits written, such as 8, 7, or less bits of data) is programmed a certain number of times (e.g., 3 or 4). By step S20, the fault tolerant bit value is updated from the first value (e.g. 0) to a second value (e.g. 5, 6, 7 or 8) greater than the first value, so as to control the plurality of verification operations according to the fault tolerant bit value after the nonvolatile memory device is programmed the specific number of times (e.g. 3 or 4), wherein the second value is less than or equal to the fault tolerant bit threshold. Thereby, even if the number of bits of the data to be written is less than the fault tolerance bit threshold, the data to be written will be programmed a certain number of times, thus increasing the probability that the data is correctly programmed. The method can avoid the defect that the error correction capability of the nonvolatile memory device is weakened because the data to be written is smaller than or equal to the fault-tolerant bit value, thereby improving the reliability of the nonvolatile memory device. In contrast, in the prior art, the fault-tolerant bit value is fixedly set to the fault-tolerant bit threshold, i.e., the maximum error correction capability is used, and this results in the programming operation not being performed when the number of bits of data to be written is less than the fault-tolerant bit threshold.
In one embodiment, the fault tolerant bit value is set to the first value when the number of pulses is less than a threshold number of pulses. For example, in the incremental pulse programming process, the number of pulses is increased every time a programming operation is performed. Referring to fig. 2, when the number of pulses is less than the threshold number of pulses, as indicated by symbol a (e.g., 3 or 4) in fig. 2, the fault-tolerant bit value is set to the first value, which may be zero or less than the fault-tolerant bit threshold.
Referring to fig. 2, in one embodiment, when the pulse number is equal to or greater than the pulse number threshold, the fault tolerant bit value is updated from the first value (e.g., 0) to the second value, as indicated by reference character B (e.g., 3 or 4) in fig. 2.
Referring to fig. 3, fig. 3 is a method of controlling a verification operation for error correction of a nonvolatile memory device according to some embodiments of fig. 1.
As shown in fig. 3, the method includes steps S10 and S20 identical to those of fig. 1, and the second value is smaller than the fault tolerance threshold, and further includes step S30. The fault tolerant bit value is progressively increased from the second value at least one or more times to control the verify operation in accordance with the fault tolerant bit value, wherein the increased fault tolerant bit value is less than or equal to the fault tolerant bit threshold, as shown in step S30.
In some embodiments of step S30, the fault tolerant bit values may be incremented multiple times with the same increment (e.g., 1,2, or 3) or with individual increments.
In one embodiment of the method of fig. 3, for example, during incremental pulsing of a portion of the non-volatile memory, when the number of pulses is less than a pulse value A1, as represented by symbol A1 (e.g., 4) in fig. 4, the tolerance bit value is set to the first value, which may be zero or less than the tolerance bit threshold, by step S10 of fig. 3. When the number of pulses is equal to the pulse value A1 (e.g., 4), the fault tolerant bit value is updated from the first value (e.g., 0) to the second value (e.g., 1) in step S20 in fig. 3, for example, indicated by the fault tolerant bit value B1 (e.g., 1) in fig. 4. Then, by means of step S30 of fig. 3, the fault tolerant bit value is progressively increased from the second value at least one or more times. Referring to FIG. 4, when the number of pulses is equal to a pulse value A2 (e.g., 5), the fault tolerant bit value is updated from the second value (e.g., fault tolerant bit value B1) to a fault tolerant bit value B2 (e.g., 3). When the number of pulses is equal to the pulse value A3 (e.g., 6), the fault tolerant bit value is updated from the fault tolerant bit value B2 (e.g., 3) to a fault tolerant bit value B3 (e.g., 4). When the number of pulses is equal to the pulse value A4 (e.g., 8), the fault tolerant bit value is eventually updated from the fault tolerant bit value B3 (e.g., 4) to a fault tolerant bit value B4 (e.g., 6). In this way, for the example of incremental pulsing of a portion of the non-volatile memory, the error correction capability may be preserved until after the number of pulses meets a determination criterion, e.g., the number of pulses equals the pulse value A1, and the data to be written will be programmed a certain number of times even if the number of bits of the data to be written is less than the fault-tolerant bit threshold, and therefore the probability that the data will be programmed correctly is improved. Furthermore, the error correction capability may be progressively released after the decision criterion is met. Therefore, the method can avoid the error correction capability of the nonvolatile memory device from being weakened because the data to be written is smaller than or equal to the fault-tolerant bit value, thereby improving the reliability of the nonvolatile memory device.
Embodiments for implementing the method according to the previous examples of fig. 1,2, 3 or 4 are provided below.
In one embodiment, a nonvolatile memory device is provided that includes a nonvolatile memory cell array, a page buffer circuit, and a control logic circuit. The non-volatile storage device may be, for example, a flash memory device.
The page buffer circuit is coupled to the non-volatile memory cell array, and the control logic circuit is coupled to the non-volatile memory cell array and the page buffer circuit. The control logic circuit is to control the non-volatile memory device.
For example, the control logic may be configured to implement the method according to the examples of fig. 1, 2, 3 or 4 described above. When the control logic circuit controls at least one part of the nonvolatile memory cell array to be programmed and verified, the control logic circuit sets the tolerance bit value to be a first numerical value so as to control verification operation according to the tolerance bit value, wherein the first numerical value is smaller than a fault tolerance bit threshold value for error correction of the nonvolatile memory device; and after programming at least a portion of the array of non-volatile memory cells a certain number of times, the control logic updates the fault-tolerant bit value from the first value to a second value to control a verification operation in accordance with the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold.
In one embodiment, the control logic sets the fault tolerant bit value to the first value when the number of pulses is less than a threshold number of pulses.
In an embodiment, the control logic sets the first value to zero or a value less than the fault tolerance bit threshold.
In one embodiment, the control logic updates the fault tolerant bit value from the first value to the second value when the pulse number is equal to or greater than the pulse number threshold.
In an embodiment, the control logic progressively increases the fault tolerant bit value from the second value at least once to control a verification operation in dependence upon the fault tolerant bit value, wherein the increased fault tolerant bit value is less than or equal to the fault tolerant bit threshold.
Referring to fig. 5, fig. 5 is a block diagram of a nonvolatile memory device according to the foregoing embodiment. As shown in fig. 5, the nonvolatile memory device 1 includes a memory cell array 10, an X-ray decoder 20, a voltage generator 30, a page buffer circuit 40, a Y-line decoder 45, an input/output buffer 50, and a control logic circuit 60. For ease of illustration, the non-volatile storage device 1 may be a flash memory device, such as a NAND flash memory device. Of course, the implementation of the present invention is not limited to the above examples.
The memory cell array 10 includes a plurality of memory cells arranged in columns connected to word lines (word lines) and rows connected to bit lines (bit lines). Each memory cell stores 1bit of data or M bits of data, where M is an integer greater than 1. Each memory cell may utilize a charge storage layer to store data, such as a floating gate or charge trapping layer, a variable resistor, or other type of memory cell.
The X-ray decoder 20 is used for performing selection and driving operations of a plurality of columns of the memory cell array 10.
The voltage generator 30 is controlled by the control logic 60 and generates a plurality of voltages (e.g., programming, pass, erase, and read voltages) for programming, erase, and read operations.
The page buffer circuit 40 and the Y-line decoder 45 are controlled by the control logic circuit 60 and act as sense amplifiers or write drivers depending on the different modes of operation of the flash memory device. For example, in a read operation, the page buffer circuit 40 and the Y-line decoder 45 act as sense amplifiers to sense data from selected memory cells of a selected column. For example, in a programming operation, the page buffer circuit 40 and the Y-line decoder 45 function as a write driver for driving selected memory cells of selected columns according to programming data. The page buffer circuit 40 includes a plurality of page buffers corresponding to respective bit lines or bit line pairs.
The input/output buffer 50 receives read data from the page buffer circuit 40 and the Y-line decoder 45 and transmits the read data to an external destination, such as a computing device. The input/output buffer 50 typically operates in conjunction with an external device, such as a memory controller or host.
The control logic 60 is arranged to control the operation of the non-volatile memory device 1. The control logic 60 may be implemented to include a bit detector 600, a fault tolerant bit detector 610, and a pulse counting circuit 620.
For example, the control logic circuit 60 may be configured to receive data with a bit detector 600, which is read by the page buffer circuit 40 and the Y-line decoder 45 in a verify operation. The control logic 60 may determine whether the at least one selected memory cell is successfully programmed, for example, by determining whether the threshold voltage of the at least one selected memory cell is greater than or equal to the associated verify level based on the data read by the page buffer 40 using the bit detector 600.
The fault-tolerant bit detector 610 is responsive to the fault-tolerant bit value and is operable to detect whether the data read by the page buffer 40 includes a number of error bits less than or equal to the fault-tolerant bit value. The fault tolerant bit detector 610 may be implemented in analog and/or digital circuitry, such as suitable current sense amplifiers, counters, and logic.
The pulse counting circuit 620 is used to count the number of pulses, for example, in incremental pulse programming. The pulse counting circuit 620 may be implemented in digital circuitry, such as a suitable counter and sequential and/or combinational logic circuits. The number of pulses may be a program number of pulses or an erase number of pulses.
The control logic 60 may also include one or more registers that store success or failure information during programming. For example, the control logic circuit 60 determines whether all selected memory cells have been successfully programmed based on the read data from the page buffer circuit 40 and the Y-line decoder 45 during a verify operation.
In some embodiments, the control logic 60 may be configured to implement steps S10 and S20 of fig. 1 or steps S10-S30 of fig. 3, as described in accordance with the foregoing examples of fig. 1,2, 3, or 4. For example, the control logic 60 may be configured to read the number of pulses of the pulse counting circuit 620 and determine a timing to progressively set the fault-tolerant bit value of the fault-tolerant bit detector 610 to the first value, the second value, or another value based on the number of pulses received from the pulse counting circuit 620.
In other embodiments, the fault tolerant bit detector 610 may be configured to couple with the pulse counting circuit 620 to accommodate a skew value, and the pulse counting circuit 620 may be configured to include logic to store a number of pulses and control the fault tolerant bit detector based at least on the number of pulses. The logic of the pulse counting circuit 620 may be configured to read the number of pulses stored in the pulse counting circuit 620 and determine a timing to progressively set the fault-tolerant bit value of the fault-tolerant bit detector 610 to the first value, the second value, or another value based on the number of pulses stored in the pulse counting circuit 620. Of course, the implementation of the present invention is not limited to the above examples.
In some embodiments, the method of FIG. 1 or FIG. 3 may be performed when a program of programming and verifying operations is executed on at least a portion of the non-volatile memory. Referring to FIG. 6, an example of a program for programming and verifying operations, such as incremental pulse programming, is shown. The procedure of fig. 6 includes steps S110 to S160.
In step S110, the programming voltage V PGM is initially set to the starting programming voltage, with the loop indicator K set to 1 and the pass flag set to 0.
In step S120, a programming operation of a portion (e.g., a page) of the nonvolatile memory is performed.
In step S130, a verification operation is performed. In step S140, it is determined whether the number of error bits is less than or equal to the fault tolerant bit value. If yes, it represents the verification operation as passing verification, wherein the passing flag is set to 1; and the programming is stopped as shown in step S145. If not, the process further proceeds to step S150 to confirm whether the cycle indicator K is greater than a cycle indication threshold.
In step S150, when the determination is yes, the programming fails, as shown in step S155. If the determination of step S150 is negative, the process further proceeds to step S160, wherein the programming voltage V PGM is increased by an increment and the cycle indicator K is increased, and then the process proceeds to step S120 to execute the next cycle.
In one embodiment, the fault-tolerant bit value of step S140 may be set according to the method described in the examples of fig. 1,2, 3 or 4.
Referring to fig. 6 and 7, the programming voltage V PGM is progressively increased over a plurality of cycles of the program. In some embodiments, the method according to fig. 1 or 3 may be performed when the compiling and verifying operations shown in fig. 6 are alternately performed.
The following tables 1 and 2 are two examples of the method according to fig. 1 and 3, i.e. examples in which the programming voltage, i.e. ISPP voltage, is gradually increased when a program such as an example of delta pulse programming is performed.
Table 1 shows that the fault-tolerant bit value is initially set to 0 and is set to 7 when the number of pulses is equal to 4, i.e. the maximum fault-tolerant bit value in this example.
TABLE 1
Table 2 shows that the tolerance bit value is initially set to 0 and progressively increases, and when the number of pulses is equal to 4, the tolerance bit value is set to 7.
TABLE 2
In some embodiments, the fault-tolerant bit value may be set to the fault-tolerant bit threshold when the number of pulses equals or exceeds a pulse number threshold. The threshold number of pulses may be determined based on performance or characteristics of the nonvolatile memory device. For example, the threshold number of pulses may be determined based on a disturb value (disturb value) of the non-volatile storage device (e.g., a program disturb, a pass voltage (Vpass) disturb, and/or a design voltage (Vpp) disturb) and/or a time required for programming.
In some embodiments, the verification operation may be determined to be verified when two or more consecutive passes of verification are detected.
Accordingly, the present invention proposes embodiments of a method for controlling a verification operation of a non-volatile memory device and a non-volatile memory device thereof. Therefore, even if the bit number of the data to be written is smaller than the fault-tolerant bit threshold, the data to be written is programmed for a specific number of times, so that the probability of correctly programming the data can be improved. The method can avoid that the error correction capability of the nonvolatile memory device is impaired because the data to be written is less than or equal to the fault-tolerant bit value, thereby improving the reliability of the nonvolatile memory device.
The present invention has been disclosed in the foregoing in terms of preferred embodiments, however, it will be understood by those skilled in the art that the embodiments are merely illustrative of the present invention and should not be construed as limiting the scope of the present invention. It should be noted that all changes and substitutions equivalent to the described embodiments are intended to be included in the scope of the present invention. Accordingly, the scope of the invention is defined by the appended claims.
Claims (11)
1. A method of controlling a verification operation for error correction of a non-volatile memory device, the method comprising:
Setting a fault-tolerant bit value for error correction of the non-volatile storage device to a first value to control a plurality of verify operations in accordance with the fault-tolerant bit value, wherein the first value is less than a fault-tolerant bit threshold for error correction of the non-volatile storage device; and
After at least a portion of the non-volatile storage device is programmed a specified number of times, the fault-tolerant bit value is updated from the first value to a second value to control the plurality of verify operations in accordance with the fault-tolerant bit value, wherein the specified number of times is at least 3 and the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold.
2. The method of claim 1, wherein the fault tolerant bit value is set to the first value when the number of pulses is less than a pulse number threshold.
3. The method of claim 2, wherein the first value is zero or less than the fault tolerance bit threshold.
4. The method of claim 2, wherein the fault tolerant bit value is updated from the first value to the second value when the pulse number is equal to or greater than the pulse number threshold.
5. The method according to claim 1, wherein the method further comprises:
Progressively increasing the fault tolerant bit value from the second value at least once to control the plurality of verify operations in accordance with the fault tolerant bit value, wherein the increased fault tolerant bit value is less than or equal to the fault tolerant bit threshold.
6. The method of claim 1, wherein the method is performed during programming and verification of at least a portion of the non-volatile storage device.
7. A nonvolatile memory device, comprising:
An array of non-volatile memory cells;
A page buffer circuit coupled to the nonvolatile memory cell array; and
Control logic coupled to the array of non-volatile memory cells and the page buffer circuit for controlling the non-volatile memory device,
Wherein during a period when the control logic circuit controls at least a portion of the non-volatile memory cell array to be programmed and verified, the control logic circuit sets a tolerance bit value to a first value to control a plurality of verification operations in accordance with the tolerance bit value, wherein the first value is less than a fault tolerance bit threshold for error correction of the non-volatile memory cell array; after at least a portion of the non-volatile memory cell array is programmed a specific number of times, the control logic updates the error tolerant bit value from the first value to a second value to control the plurality of verification operations according to the error tolerant bit value, wherein the specific number of times is at least 3, and the second value is greater than the first value and less than or equal to the error tolerant bit threshold.
8. The non-volatile storage device of claim 7, wherein the control logic is to set the fault tolerant bit value to the first value when the number of pulses is less than a pulse number threshold.
9. The non-volatile storage device of claim 8, wherein the control logic sets the first value to a value of zero or less than the fault tolerance bit threshold.
10. The non-volatile storage device of claim 8, wherein the control logic is to update the fault tolerant bit value from the first value to the second value when the number of pulses is equal to or greater than the number of pulses threshold.
11. The non-volatile storage device of claim 7, wherein the control logic progressively increases the fault tolerant bit value from the second value at least once to control the plurality of verify operations in accordance with the fault tolerant bit value, wherein the increased fault tolerant bit value is less than or equal to the fault tolerant bit threshold.
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