JP2017111849A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage capable of saving unqualified memory cells while ameliorating a yield deteriorated by program failure.SOLUTION: A method of programming a NAND type flash memory comprises: a step of applying a program pulse to a selected page; a step of determining whether a program in the selected page is qualified; and a step of further applying the program pulse to the selected page if the number of applied program pulses has not reached an optimal number when determined to be unqualified, and determining that the page is quasi-qualified if the selected page has a predetermined number of unqualified bits when the number of applied program pulses has reached the optimal number.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a method for programming a semiconductor memory device, particularly a NAND flash memory.

  In NAND flash memory, repeated programming and erasing of data deteriorates the charge retention characteristics due to deterioration of the tunnel insulating film, or threshold fluctuations occur due to charges trapped in the tunnel insulating film, resulting in bit errors. cause. Patent Document 1 is equipped with an error checking and correcting circuit (ECC) as a countermeasure against such a bit error. Patent Document 2 discloses an error correction scheme for multi-bit data in a NAND flash memory that stores multi-bit data in one memory cell. Further, Patent Document 3 discloses a flash memory in which physical blocks having a corrected number of errors equal to or greater than a threshold value are registered in the table as warning blocks, and the priority of selection of warning blocks is lowered when data is written.

JP 2010-152989 A JP 2008-165805 A JP 2010-79486 A

  FIG. 1 shows a main part of a NAND flash memory on which an ECC circuit is mounted on-chip. Program data input from the external input / output terminal is loaded into the page buffer / sense circuit 10, and the loaded program data is transferred to the ECC circuit 30 via the transfer circuit 20. The transfer circuit 20 includes a plurality of transistors capable of bidirectional data transfer, and each transistor is driven by a control signal TG commonly connected to the gates. The ECC circuit 30 calculates the transferred program data, generates an error correction code for error detection / correction, and writes the error correction code back to a predetermined area of the page buffer / sense circuit 10. Next, the program data and error correction code held in the page buffer / sense circuit 10 are programmed into the selected page of the memory array.

  FIG. 2 is a flowchart of a conventional program operation. A program pulse is applied to the word line of the selected page, a voltage corresponding to the program data is set to the bit line, and a program pulse is applied to the selected page (S10). Next, program verification of the selected page is performed (S20), and it is determined whether the program of all the memory cells of the selected page has passed (S30). If it is determined that all the memory cells have been successfully programmed, the program is terminated. If there is a memory cell in which the program has failed, it is determined whether the number of application times of the program pulse has reached NMAX (S40). Here, NMAX means the maximum time allowed for programming or the maximum number of program pulses allowed for programming. When NMAX is reached, the program failure status is notified to the external controller, and the block is managed as a bad block. On the other hand, if NMAX has not been reached, a program pulse having a step voltage larger by ΔV than the previous program pulse is generated according to ISPP (Incremental Step Program Pulse) (S50), and this program pulse is applied to the selected page. .

  In a flash memory that does not use the ECC function installed in an external controller or the like, or does not have an ECC installed, it is premised that the program verify passes all bits. On the other hand, in a flash memory that uses an ECC function mounted on an external controller or the like or that has an ECC mounted on-chip, some of the fail bits (“0” program is rejected in the memory cell in verify). ), It is possible to make a pseudo-pass by relieving this with ECC. For example, if m-bit error detection / correction is possible by ECC, it is theoretically possible to rescue up to m failed bits. When Ncc is the maximum number of bits that can be relieved by ECC, Np is the maximum number of failed bits that can be pseudo-passed in verification, and Nf is the actual number of failed bits, Np is Ncc ≧ Np Preferably, Ncc> Np is set. When Np ≧ Nf, the selected page includes a fail bit. However, since the fail bit can be relieved by ECC, the verification is determined to be a false pass. Then, when the selected page is read, a fail bit included in the selected page is detected as an error, and this data is corrected.

  By determining the pseudo-pass, program failures and bad blocks can be reduced, yield can be improved, and program disturb can be reduced by suppressing the number of program pulses applied.

  However, the conventional programming method using pseudo-pass has the following problems. For example, when fail bits up to k bits are regarded as pseudo-pass (Np = k), if the number of program pulse applications is before reaching NMAX, the actual number of fail bits Nf is pseudo-pass during verification. The program is automatically terminated when it becomes smaller than the maximum number of failed bits Np. In other words, even if the number of application times of the program pulse is sufficiently smaller than NMAX and there is still a margin for the number of application times, if Nf ≦ Np, it is determined as a pseudo-pass and the program ends. However, some memory cells that have failed to be programmed can be passed by the application of the next program pulse, and such a memory cell is determined to be a failed bit. It is desirable to determine that the bit is not a pass bit. If the number of rejected bits increases due to pseudo-pass, functions other than ECC are greatly limited.

  An object of the present invention is to solve such a conventional problem and to provide a semiconductor memory device capable of repairing a failed memory cell while improving the yield of a program failure.

  The NAND flash memory programming method according to the present invention includes a step of applying a program pulse to a selected page, a step of determining pass / fail of the program of the selected page, and application of a program pulse when it is determined to be unacceptable. If the number of times has not reached the optimum value smaller than the maximum allowable value of the program, further program pulses are applied to the selection page, and if the number of application times of the program pulses has reached the optimum value, the selection is made. And determining that the page is a pseudo-pass if the page has a predetermined number of failed bits.

  Preferably, the programming method further determines whether or not the number of application times of the program pulse has reached the allowable maximum value when the selected page is larger than a predetermined number of failed bits, and the allowable maximum value If not reached, a program pulse is further applied to the selected page, and if the allowable maximum value is reached, the program is terminated as a program failure. Preferably, the allowable maximum value is the maximum number of application times of the program pulse allowed for the program of the selected page. Preferably, the predetermined number of failed bits is less than or equal to the number of bits that can be relieved by error detection / correction. Preferably, the optimum value can be set by an external controller. Preferably, the program method further includes generating an error correction code of data to be programmed, and the selected page is programmed with program data and the error correction code.

  In the NAND flash memory programming method according to the present invention, the step of receiving data to be programmed and the number of bits programmed by the data to be programmed are equal to or less than the number of rescue bits that can be relieved by the error detection / correction means. Determining whether or not, a step of generating an error correction code of the data to be programmed by the error detection / correction means, and a number of bits programmed by the data to be programmed is less than or equal to the number of relief bits When the determination is made, there is a step of ending the program to the selected page by programming the error correction code in the spare area without programming in the regular area of the selected page.

  Preferably, the programming method further includes a step of programming the data to be programmed in the regular area of the selected page when it is determined that the number of bits programmed by the data to be programmed is larger than the number of relief bits.

  A semiconductor memory device according to the present invention includes a memory array, error detection / correction means for generating an error correction code for data to be programmed, and the data to be programmed and the error correction code in a selected page of the memory array. The program means applies a program pulse to the selected page, and when it is determined that the program of the selected page is unsuccessful, the number of times the program pulse is applied is less than the maximum allowable value of the program. If the value has not reached the value, a program pulse is further applied to the selected page, and if the number of application times of the program pulse has reached the optimum value, the selected page has a predetermined number of failed bits. If there is, a process for determining that it is a pseudo-pass is executed.

  A semiconductor device according to the present invention includes a memory array, error detection / correction means for generating an error correction code for data to be programmed, and a program for programming data to be programmed and the error correction code to a selected page of the memory array. The program means does not program the regular area of the selected page when the number of bits programmed by the data to be programmed is less than or equal to the number of relief bits that can be relieved by the error detection / correction means. The program for the selected page is completed by programming the error correction code in the spare area. Preferably, the semiconductor memory device includes means for reading data of a selected page of the memory array, and the error detection / correction means performs error detection / correction of the read data based on the read error correction code. .

  According to the present invention, when it is determined that the program verification is unsuccessful, the program pulse is further applied when the number of application times of the program pulse has not reached the optimum value smaller than the allowable maximum value. When the number of times of application has reached the optimal value, if the selected page has a predetermined number of rejected bits, the process of determining pseudo pass is executed, so at least the program pulse reaches the optimal value. Until this is done, pass / fail judgment of all bits is guaranteed. Thereby, a memory cell that can pass normally can be relieved from the failure determination.

It is a figure explaining ECC operation | movement of the conventional flash memory. It is a flowchart explaining the program operation | movement of the conventional flash memory. 1 is a diagram showing an overall schematic configuration of a NAND flash memory according to an embodiment of the present invention. 3 is a circuit diagram showing a configuration of a NAND string of a memory cell array according to an embodiment of the present invention. FIG. It is a figure which shows an example of the voltage applied to each part at the time of the program of the flash memory based on the Example of this invention. 3 is a flowchart illustrating a program operation of the flash memory according to the first example of the present invention. It is a figure explaining the ECC process of the regular area at the time of program operation by the 1st example of the present invention. It is a figure explaining the ECC process of the spare area at the time of the program operation | movement by 1st Example of this invention. 3 is a flowchart illustrating a read operation according to the first exemplary embodiment of the present invention. 7 is a flowchart illustrating a program operation of a flash memory according to a second example of the present invention. It is a flowchart explaining the program operation | movement of the flash memory based on 3rd Example of this invention.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. Here, a NAND flash memory is illustrated as a preferred form. It should be noted that in the drawings, each part is highlighted for easy understanding, and is different from an actual device scale.

  A typical configuration of a flash memory according to an embodiment of the present invention is shown in FIG. However, the configuration of the flash memory shown here is an exemplification, and the present invention is not necessarily limited to such a configuration. The flash memory 100 of this embodiment includes a memory array 110 in which a plurality of memory cells are arranged in a matrix, an input / output buffer 120 connected to an external input / output terminal I / O and holding input / output data, and the memory array 110. ECC circuit 130 for error detection / correction of data to be programmed into the data and data read therefrom, address register 140 for receiving address data from the input / output buffer 120, command data from the input / output buffer 120 and externally A control unit 150 for controlling each unit, a row address information Ax from the address register 140, a word for decoding the row address information Ax, and selecting a block and a word line based on the decoding result Selection by the line selection circuit 160 and the word line selection circuit 160 The column address information Ay is received from the page buffer / sense circuit 170 that holds the data read from the read page and the write data to the selected page and the address register 140, and the column address information Ay is decoded. The column selection circuit 180 for selecting data in the page buffer / sense circuit 170 based on the decoding result, and various voltages (write voltage Vpgm, pass voltage, etc.) necessary for data reading, programming, erasing, etc. Vpass, read pass voltage Vread, erase voltage Vers, and the like).

  The memory array 110 has m memory blocks BLK (0), BLK (1),..., BLK (m−1) arranged in the column direction. A page buffer / sense circuit 170 is disposed adjacent to the block BLK (0). In addition to this configuration, the page buffer / sense circuit 170 may be disposed at the other end of the block or at both ends.

  As shown in FIG. 4, a plurality of NAND string units NU in which a plurality of memory cells are connected in series are formed in one memory block, and n + 1 string units NU are arranged in the row direction in one memory block. ing. The cell unit NU includes a plurality of memory cells MCi (i = 0, 1,..., 31) connected in series, and a selection transistor TD connected to the drain side of the memory cell MC31 which is one end. , The selection transistor TS connected to the source side of the memory cell MC0 which is the other end, the drain of the selection transistor TD is connected to the corresponding one bit line GBL, and the source of the selection transistor TS is common Connected to the source line SL.

  The control gate of the memory cell MCi is connected to the word line WLi, and the gates of the selection transistors TD and TS are connected to selection gate lines SGD and SGS parallel to the word line WL. When the word line selection circuit 160 selects a block based on the row address Ax or the converted address, the word line selection circuit 160 selectively drives the selection transistors TD and TS via the block selection gate signals SGS and SGD. Although FIG. 4 shows a typical cell unit configuration, the cell unit may include one or more dummy cells in the NAND string.

  A memory cell is typically formed on a source / drain which is an N type diffusion region formed in a P-well, a tunnel oxide film formed on a channel between the source / drain, and a tunnel oxide film. The MOS structure includes a floating gate (charge storage layer) and a control gate formed on the floating gate via a dielectric film. When charge is not accumulated in the floating gate, that is, when data “1” is written, the threshold value is in a negative state, and the memory cell is normally on. When electrons are accumulated in the floating gate, that is, when data “0” is written, the threshold value is shifted to positive, and the memory cell is normally off. However, the memory cell may be an SLC type that stores 1 bit (binary data) or an MLC type that stores multiple bits.

  FIG. 5 is a table showing an example of the bias voltage applied during each operation of the flash memory. In a read operation, a certain positive voltage is applied to the bit line, a certain voltage (for example, 0 V) is applied to the selected word line, and a pass voltage Vpass (for example, 4.5 V) is applied to the unselected word line. A positive voltage (for example, 4.5 V) is applied to the selection gate lines SGD and SGS, the bit line selection transistor TD and the source line selection transistor TS are turned on, and 0 V is applied to the common source line. In the program (write) operation, a high voltage program voltage Vprog (15 to 20 V) is applied to the selected word line, an intermediate potential (for example, 10 V) is applied to the non-selected word line, and the bit line selection transistor TD is turned on. The source line selection transistor TS is turned off, and a potential corresponding to data “0” or “1” is supplied to the bit line GBL. In the erasing operation, 0 V is applied to the selected word line in the block, a high voltage (for example, 20 V) is applied to the P well, and electrons in the floating gate are extracted to the substrate, thereby erasing data in units of blocks.

  When the input data Di is loaded into the page buffer / sense circuit 170 via the input / output buffer 120 during the program operation, the ECC circuit 130 calculates the input data Di transferred from the page buffer / sense circuit 170, and the input data An error correction code or a parity bit necessary for error detection and correction of Di is generated. The ECC calculation is performed by a known method such as a Hamming code or Reed-Solomon, and converts the input k-bit or k-byte input data Di into p = k + q. In this specification, “q” is referred to as an error correction code or parity bit necessary for error detection and correction of the input data Di. In one preferred example, the ECC circuit 130 sets the error correction code in the spare area of the page buffer / sense circuit 170. Thus, the input data Di and the error correction code set in the page buffer / sense circuit 170 are programmed into the selected page of the memory array 110.

  When the data read from the selected page of the memory array 110 during the read operation is held in the page buffer / sense circuit 170, the ECC circuit 130 reads the read data based on the error correction code transferred from the page buffer / sense circuit 170. The error is detected and corrected. If an error is detected, the corrected data is set in the page buffer / sense circuit 170. Then, the data held in the page buffer / sense circuit 170 is output via the input / output buffer 120.

  Next, the program operation according to the first embodiment of the present invention will be described with reference to the flowchart of FIG. When the control unit 150 receives a program command via the input / output buffer 120, the control unit 150 starts a sequence for the program. The input data Di is loaded into the page buffer / sense circuit 170 via the input / output buffer 120, and then ECC processing of the input data Di is performed by the ECC circuit 130 (S100).

  FIG. 7 shows an example of ECC processing. When the flash memory 100 has × 8 external input / output terminals, data is loaded from the external input / output terminals P0 to P7 to the page buffer / sense circuit 170 via the I / O buffers 120-1 to 120-7. . For example, the page buffer / sense circuit 170 includes a regular area 300 divided into eight sectors, sector 0 to sector 7, and a spare area 310 divided into four sectors, spare 0, spare 1, spare 2, and spare 3. And have.

  One sector of the regular area 300 is composed of, for example, 256 bytes. In this case, the eight sectors of the regular area 300 can hold about 2 Kbytes of program data as a whole. One sector of the spare area 310 is composed of, for example, 16 bytes. In this case, four sectors (spare 0 to spare 3) can hold data of 64 bytes in total. One sector of the spare area 310 includes, for example, an area 311 for storing information for identifying a bad block including a defective memory cell, an area 312 for storing information on user data, and an error correction code for two sectors of the regular area 300. Areas 313 and 314 for storing (parity bits) and an area 315 for storing error correction codes (parity bits) when the spare area 310 is subjected to ECC calculation. Spare 0 areas 313 and 314 of the spare area 310 store error correction codes (parity bits) of the sector 0 and sector 1 of the regular area 300, respectively. Spare 1 areas 313 and 314 of the spare area 310 are regular areas. 300 error correction codes (parity bits) of sector 2 and sector 3 are stored. Similarly, the spare 2 of the spare area 310 stores the parity bits of the sectors 4 and 5 of the regular area 300, and the spare 3 of the spare area 310 stores the parity bits of the sectors 6 and 7 of the regular area 300. .

  Input / output buffers 120-0 to 120-7 are allocated to one sector of the regular area 300, that is, 256 bits are allocated to one external input / output terminal (256 bits × 8 = 1 sector). The column selection circuit 180 decodes the column address information Ay received during the program operation, and selects a sector to which data input to the external input / output terminals P-0 to P7 is loaded based on the decoding result. FIG. 7 shows an example in which data received at the external input / output terminals P-0 to P-7 is loaded into the sector 0 according to the column address information Ay.

  In the example shown here, the ECC circuit 130 includes a writing circuit for writing an error correction code. Preferably, the ECC circuit 130 can perform an ECC operation on data having a number of bytes equal to one sector in the regular area 300. If one sector of the regular area 300 is 256 bytes, the ECC circuit performs an ECC operation on 256-byte data and generates an error correction code for correcting a 4-bit error.

  The ECC circuit 130 writes the generated error correction code in the corresponding sector area 313 or 314 of the spare area 310. In the example shown in FIG. 7, since the program data is loaded into sector 0 of regular area 300, the error correction code is written into area 313 storing the parity of sector 0 of spare 0.

  FIG. 8 illustrates an ECC process for data in the spare area 310. When the ECC process is completed for each sector in the regular area 300, the ECC process is performed for each sector in the spare area 310. Although it is arbitrary which ECC processing is performed in one sector of the spare area 310, in this example, the ECC processing is performed on data in the areas 312 to 314. Therefore, the data in the spare 3 areas 312 to 314 is transferred to the ECC circuit 130, and the error correction code generated by the ECC processing is written into the spare 0 area 315 by the ECC circuit 130. The same processing is performed for the other spares 1 to 3.

  Referring to FIG. 6 again, when the ECC process ends (S100), the program to the memory array 110 is started. A word line in the memory array 110 is selected by the word line selection circuit 160, a voltage corresponding to the data held by the page buffer / sense circuit 170 is supplied to the bit line, and a program pulse is applied to the selected page ( S110). Next, program verification is performed (S120), and it is checked whether or not the threshold value of the memory cell in which data “0” is programmed is equal to or greater than a certain value. If all bits of the selected page pass as a result of the verification, the program is terminated. On the other hand, when all the bits have not passed, the control unit 150 determines whether or not the number of application times of the program pulse has reached the optimum number Nop (S130).

  Here, the optimum number of times Nop is a value smaller than NMAX, which is the maximum number of application times or the maximum program time of the program pulse allowed in the program, and preferably, when determining that the memory cell is a program failure. The number of program pulses to be applied to the minimum. For example, when the maximum time allowed for programming is 700 μs and the time required to apply one program pulse is 50 μs, NMAX = 700 μs or NMAX = 14 times. The optimum number Nop can be determined based on the number of program pulses applied when a typical memory cell is successfully passed. For example, when the average number Nav of program pulses applied to a memory cell that passes the program is calculated by a statistical method, the optimum number Nop can be set to Nop = Nav. The optimum number Nop can be set by, for example, a command received from an external controller, and the set value is held in a register of the control unit 150 or the like.

  When the number of application times of the program pulse has not reached the optimum number Nop (S140), the control unit 150 applies a program pulse larger by ΔV than the previous time to the selected page according to ISPP (S150). On the other hand, when the number of application times of the program pulse has reached the optimum number Nop (S140), the control unit 150 performs a step of determining whether or not the selected page is pseudo-passed (S160). As described above, the maximum number of failed bits Np that is regarded as pseudo-pass is equal to or less than the maximum number of bits Ncc that can be remedied by ECC, and the number of failed bits at the time of verification, that is, the number of bits actually generated in the selected page. If the number of accepted bits Nf is equal to or less than the maximum number of failed bits Np for pseudo-pass (Nf ≦ Np), it is determined as pseudo-pass (S160). If it is determined to be pseudo-pass, the program operation is terminated, and the reject bit of “0” failure is stored as it is in the selected page.

  On the other hand, when it is determined that the pseudo-pass has not been achieved (S160), the control unit 150 determines whether or not the number of application times of the program pulse has reached NMAX (S170). A program pulse is applied to the selected page (S150, S110). When the number of application times of the program pulse reaches NMAX, the program failure status is notified to the external controller, and the block including the selected page is managed as a bad block. In this case, identification information that is a bad block is stored in the area 311 of the spare area.

  Next, an operation for reading data from a page programmed by pseudo-pass will be described with reference to the flow of FIG. First, a page of the memory array 110 is selected, and data of the selected page is read to the page buffer / sense circuit 170 (S200). Next, the data held in the spare area of the page buffer / sense circuit 170 is transferred to the ECC circuit 130 (S210). For example, when error detection / correction of sector 0 is performed, the data of spare 0 shown in FIG. 7 is transferred to the ECC circuit 130. The ECC circuit 130 first performs error detection / correction of data held in the areas 313 and 314 based on the error correction code (parity) held in the area 315.

  Next, the data in the regular area of the page buffer sense circuit 170 is transferred to the ECC circuit 130 (S220). For example, the data of sector 0 shown in FIG. 7 is transferred to the ECC circuit 130. The ECC circuit 130 detects an error in the data of sector 0 based on the error correction code stored in the spare 0 area 313 (S230). If sector 0 contains a failure bit when it is falsely passed, the failure bit is detected as an error. If an error is detected, the ECC circuit 130 corrects the error to correct data, and sets the corrected data in the page buffer / sense circuit 170 (S240). Such processing is performed in units of sectors (S250).

  As described above, according to the present embodiment, since it is determined whether or not the pseudo pulse is passed when the number of application times of the program pulse reaches the optimum number Nop, the pseudo pass is not performed until the optimum number Nop. Judgment of passing all bits of the selected page is guaranteed. As a result, a memory cell that has been determined to be rejected in the past is more likely to be repaired as a pass, and a margin for the number of bits that can be relieved by other processing by the ECC processing can be secured, and at the same time, the program succeeds. Yield can be improved.

  Next, the program operation of the second embodiment of the present invention will be described with reference to the flow of FIG. In the second embodiment, steps S300, S310, and S320 are newly added to the flow of FIG. The controller 150 determines whether or not the pseudo-pass is based on the input program data during the program operation (S300). Here, it is assumed that programming of the selected page is performed on memory cells (all data is “1”) in an erased state. When the number of bits of the data “0” included in the program data of one sector is equal to or less than the maximum number of failed bits Np that can be pseudo-passed, the control unit 150 determines that it is pseudo-passed, otherwise In that case, the same processing as the flow of FIG. 2 is executed.

  If it is determined to be pseudo-pass, the program data held in the page buffer / sense circuit 170 is transferred to the ECC circuit 130, where ECC processing is performed (S310). The ECC circuit 130 writes the error correction code generated by the operation in the spare area of the page buffer / sense circuit. Next, the error correction code held in the page buffer / sense circuit 170 is programmed in the spare area of the selected page. At this time, all the memory cells in the regular area of the selected page hold data “1”, and a program inhibit voltage is supplied to the bit lines in the regular area of the selected page. When the error correction code is programmed in the spare area, the program operation is terminated. Since all the regular regions are prohibited from being programmed, the influence of coupling between adjacent bit lines is eliminated, and the program disturb characteristic is improved as compared with a normal program in which a programmed bit line exists.

  Reading a page that has been falsely accepted is performed in the same manner as in the first embodiment. That is, data read from the selected page is held in the page buffer / sense circuit 170. The data in the regular area is all “1”, and the program data has data “0” having a number of rejected bits Np or less. The ECC circuit 130 receives data in the spare area of the page buffer / sense circuit 170, and should program error bits, that is, data “0” from all “1” data in the regular area based on the error correction code included therein. The bit is detected, data “1” is corrected to data “0”, and this is set in the page buffer / sense circuit 170.

  As described above, according to the second embodiment, when the data to be programmed is less than or equal to the number of bits that can be relieved by the ECC circuit 130, the program data is programmed in the regular area unlike the normal program sequence. Instead, by programming only the error correction code in the spare area, the program disturb characteristic in the regular area can be improved, and at the same time, the programming time can be shortened. When an error correction code is programmed in the spare area in step S320 in FIG. 10, a verify step is also executed in the same way as a normal program. In this case, a program routine by ISPP is executed as shown by a broken line K in FIG. It is also possible.

  Next, a third embodiment of the present invention will be described. The third embodiment is a combination of the first embodiment and the second embodiment, and its operation flow is shown in FIG. The flow of FIG. 11 is obtained by adding steps S300, S310, and S320 of the second embodiment to the flow of FIG. 6, and the operation thereof is the same as in the first and second embodiments. Therefore, the description is omitted. In step S320 of FIG. 11, when an error correction code is programmed in the spare area, it is possible to perform a program sequence by ISPP as in the case of FIG. 10, and in this case, it is desired to pass all error correction codes. It is also possible to set the optimum number Nop to be larger than the optimum number Nop when the pseudo-pass is not made, to increase the possibility of determining that all bits are passed, and to make the pseudo-pass in step S160 difficult.

  Note that NAND-type flash memory is programmed in units of pages, but the size of program data to be input must always be equal to the size of one page, that is, the eight sectors of the regular area 300 shown in FIG. do not do. For example, the size of the program data can be the size of one sector. Usually, from the viewpoint of program disturb, there is a limit to the number of times (NOP (Number of Program)) allowed to be continuously programmed on the same page, and one page data is divided and programmed according to the NOP. It is possible. When the NOP is 4, one page data can be input to the flash memory 10 divided into, for example, 2 sectors, 1 sector, 3 sectors, and 2 sectors.

  Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the invention described in the claims. Is possible.

DESCRIPTION OF SYMBOLS 100: Flash memory 110: Memory array 120: Input / output buffer 130: ECC circuit 140: Address register 150: Control part 160: Word line selection circuit 170: Page buffer / sense circuit 180: Column selection circuit 190: Internal voltage generation positive circuit 300: Regular area 310: Spare area

Claims (7)

A NAND flash memory programming method comprising:
Receiving data to be programmed;
Determining whether the number of bits programmed by the data to be programmed is less than or equal to the number of rescue bits that can be relieved by the error detection / correction means;
Generating an error correction code of the data to be programmed by the error detection / correction means;
When it is determined that the number of bits programmed by the data to be programmed is equal to or less than the number of relief bits, the error correction code is selected by programming the spare area without programming the regular area of the selected page. Steps to exit the program to the page;
A programming method comprising: The programming method further comprises a step of programming data to be programmed in a regular area of a selected page when it is determined that the number of bits programmed by the data to be programmed is larger than the number of relief bits. The program method described. A NAND flash memory programming method comprising:
Receiving data to be programmed;
Determining whether the number of bits programmed by the data to be programmed is less than or equal to the number of rescue bits that can be relieved by the error detection / correction means;
Generating an error correction code of the data to be programmed by the error detection / correction means;
When it is determined that the number of bits programmed by the data to be programmed is equal to or less than the number of relief bits, the error correction code is selected by programming the spare area without programming the regular area of the selected page. Steps to exit the program to the page;
Programming the data to be programmed into the regular area of the selected page when it is determined that the number of bits programmed by the data to be programmed is greater than the number of relief bits,
The step of programming further comprises:
Applying a program pulse to the selected page;
Determining pass / fail of the program on the selected page;
When it is determined that the program has failed, if the number of program pulse applications has not reached the optimum value smaller than the maximum allowable value of the program, the program pulse is further applied to the selected page, and the number of program pulse applications Is determined to be a pseudo-pass if the selected page has a predetermined number of failed bits. A memory array;
Error detection / correction means for generating an error correction code for data to be programmed;
Programming means for programming data to be programmed and the error correction code to a selected page of the memory array;
The program means includes
When the number of bits programmed by the data to be programmed is less than or equal to the number of rescue bits that can be relieved by the error detection / correction means, the error correction code is programmed in the spare area without programming in the regular area of the selected page This completes the program of the selected page. 5. The semiconductor memory device according to claim 4, wherein said program means further programs data to be programmed in a regular area of a selected page when the number of bits programmed by said data to be programmed is larger than the number of relief bits. The program means further applies a program pulse to the selected page, and when it is determined that the program of the selected page is unsuccessful, the number of application times of the program pulse does not reach an optimum value smaller than the allowable maximum value of the program. In this case, a program pulse is further applied to the selected page, and if the number of application times of the program pulse has reached the optimum value, if the selected page has a predetermined number of failed bits, it is determined as a pseudo-pass. The semiconductor memory device according to claim 5, wherein the processing is performed. The semiconductor memory device includes means for reading data of a selected page of the memory array,
The semiconductor memory device according to claim 4, wherein the error detection / correction unit performs error detection / correction on the read data based on the read error correction code.

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