CN113707208A - Method of controlling verify operation for error correction of nonvolatile memory device and nonvolatile memory device - Google Patents
Method of controlling verify operation for error correction of nonvolatile memory device and nonvolatile memory device Download PDFInfo
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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Abstract
The present invention provides a method of controlling a verify operation for error correction of a nonvolatile memory device, the method including the following; a fault-tolerant bit value for error correction of the non-volatile storage device is set to a first value to control a plurality of verify operations in accordance with the fault-tolerant bit value. After at least a portion of the non-volatile storage device is programmed a certain number of times, the fault-tolerant bit value is updated from the first value to a second value to control the plurality of verify operations according to the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to a fault-tolerant bit threshold. The method may be performed during programming and verification of at least a portion of the non-volatile storage device.
Description
Technical Field
The present invention relates to a nonvolatile memory device, and more particularly, to a method of controlling a verify operation for error correction of a nonvolatile memory device and a nonvolatile memory device using the same.
Background
Generally, a nonvolatile memory, such as a flash memory, uses an Error Correction Code (ECC) to repair a soft error (soft error) or a physical error (physical fault) of a memory cell (hereinafter, the soft error and the physical error are collectively referred to as an error). However, there are limitations to repairing data using the error correction code, for example, a single error correction-double error detection (SEC-DED) algorithm can only repair a single error bit. If more than one bit needs to be repaired, it is necessary to apply other algorithms and to apply more storage space to the algorithms, which reduces the available storage space.
In the prior art, when a portion (e.g., a specific page) of a non-volatile memory is programmed, a verification operation is performed on programmed bits (e.g., bits of a page) of the non-volatile memory to determine whether the programmed bits include error bits and the number of error bits exceeds a reference value representing the error correction capability of the non-volatile memory. If the number of error bits is lower than the reference value, the programmed bits are determined to be verified. If the number of error bits exceeds the reference value, the program bits are judged to fail verification, and the page is programmed again, and so on.
Disclosure of Invention
It is an object of the present invention to provide a technique for controlling a verify operation for error correction of a nonvolatile memory device.
To achieve the above object, the present invention provides a method for controlling a verify operation for error correction of a nonvolatile memory device, the method comprising: setting a free error bit (TEB) value for error correction of the non-volatile storage device to a first value to control a plurality of verify operations according to the TEB value, wherein the first value is less than a TEB threshold for error correction of the non-volatile storage device. Updating the fault-tolerant bit value from the first value to a second value after at least a portion of the non-volatile storage device is programmed a specified number of times to control the plurality of verification operations in accordance with the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold.
In one embodiment, the fault tolerant bit value is set to the first value when the number of pulses is less than a pulse number threshold.
In one embodiment, the first value is zero or less than the fault-tolerant bit threshold.
In one embodiment, the fault tolerant bit value is updated from the first value to the second value when the number of pulses is equal to or greater than the number of pulses threshold.
In some embodiments, the method comprises progressively increasing the fault tolerant bit value at least once from the second value to control the plurality of verification operations in dependence on the fault tolerant bit value, wherein the increased fault tolerant bit value is less than or equal to the fault tolerant bit threshold.
In some embodiments, the method is performed during programming and verification of at least a portion of the non-volatile storage device.
To achieve the above objective, the present invention further provides a nonvolatile memory device, which includes a nonvolatile memory cell array, a page buffer circuit, and a control logic circuit. The page buffer circuit is coupled to the array of non-volatile memory cells. The control logic circuit is coupled to the array of non-volatile memory cells and the page buffer circuit. The control logic is to control the non-volatile storage device. During the time that the control logic controls at least a portion of the array of non-volatile memory cells to be programmed and verified, the control logic sets a fault-tolerant bit value to a first value to control the plurality of verify operations in accordance with the fault-tolerant bit value, wherein the first value is less than a fault-tolerant bit threshold for error correction of the non-volatile memory device; after at least a portion of the array of non-volatile memory cells is programmed a specified number of times, the control logic updates the fault-tolerant bit value from the first value to a second value to control the plurality of verify operations according to the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold.
In one embodiment, the control logic circuit incrementally increments the fault tolerant bit value at least once from the second value to control the plurality of verify operations in accordance with the fault tolerant bit value, wherein the incremented fault tolerant bit value is less than or equal to the fault tolerant bit threshold value.
As described above, the present invention provides embodiments of a method of controlling verify operations for error correction of a non-volatile memory device, and non-volatile memory device embodiments using the same. Therefore, the method can improve the probability of correctly compiling the data. Therefore, the method can prevent the error correction performance of the nonvolatile memory device from being weakened because the data to be written is less than or equal to the fault-tolerant bit value, thereby enhancing the reliability of the nonvolatile memory device.
For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for illustration purposes only and are not intended to limit the scope of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.
FIG. 1 is a flow diagram of a method of controlling verify operations for error correction of a non-volatile memory in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram of an example of an implementation of the method of FIG. 1;
FIG. 3 is a flow diagram of a method of controlling verify operations for error correction of non-volatile memory according to some embodiments of the invention;
FIG. 4 is a schematic diagram showing an example of an implementation of the method of FIG. 3;
FIG. 5 is a block diagram of a non-volatile memory device according to an embodiment of the present invention;
FIG. 6 is a flow chart of a procedure for programming and verifying the non-volatile memory while the method according to an embodiment of the present invention is performed; and
FIG. 7 is a schematic diagram of an example of programming voltage increase during performance of the method of FIG. 6.
Description of reference numerals:
1 nonvolatile memory device
10 memory cell array
20X-ray decoder
30 voltage generator
40-page buffer circuit
45Y line decoder
50 input/output buffer
60 control logic circuit
600 bit detector
610 fault-tolerant bit detector
620 pulse counting circuit
A. Number of pulses A1, A2, A3 and A4
B. B1, B2, B3 and B4 numerical values
S10, S20, S30, S110, S120, S130, S140, S145, S150, S155, S160 steps
Detailed Description
For a fuller understanding of the objects, features and advantages of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings.
In the following, the present invention proposes embodiments of techniques for controlling verify operations to implement error correction of non-volatile memory, wherein a freed error bit (TEB) value for error correction of the non-volatile storage device may be updated during a verify operation associated with a program operation. In some embodiments, the fault-tolerant bit value will be determined in some manner so that the non-volatile storage device will be more reliable and avoid certain programming data impairing the ability to correct errors.
The practical application of this technology assumes that, in a particular application scenario, a computing device (e.g., a smartphone, laptop or server, etc.) needs to write a small number of bits of data to a non-volatile storage device (e.g., a flash memory device) that needs to have the capability of X-bit (bit) Error Correction Codes (ECC) for every Y bits (bytes), e.g., 8 bits per 512 bits. When a portion (e.g., a particular page) of the non-volatile storage device is programmed, a verify operation is performed for programmed bits (e.g., bits of the page) of the non-volatile storage device, wherein it is determined whether the programmed bits include more error bits than the number of fault tolerant bit values. If the number of error bits is less than or equal to the fault-tolerant bit value, the programmed bits are determined to be verified. If the number of the error bits exceeds the fault-tolerant bit value, the verification of the program bits is judged to fail, and the page is programmed again, and so on. Generally, the fault-tolerant bit value is a fixed value used to represent the error-correcting capability of the non-volatile memory. For example, in this application scenario, the page is 512 bytes and the fault-tolerant bit value is 8.
The inventors have obtained a particular situation for the above application scenario. In this case, data from the computing device having a number of bits less than or equal to the fault-tolerant bit value is written to a blank area in the non-volatile memory, wherein all bits in the blank area have the same value prior to writing the data. Whenever a verify operation is performed, the verify operation for the data is always verified because the data written is less than or equal to the fault-tolerant bit value. In this case, no programming operation is performed any more, even though the data may not be programmed correctly. Thus, the data that is considered programmed will consume the ability to correct errors. In the worst case, the computing device may crash or cease functioning if the data is corrupted because it was not properly programmed. This is critical for the non-volatile memory.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method of controlling a verify operation for error correction of a nonvolatile memory device according to an embodiment of the present invention. The method includes steps S10 and S20.
As shown in step S10, a fault-tolerant bit value for error correction of the non-volatile memory device is set to a first value to control a plurality of verification operations according to the fault-tolerant bit value, wherein the first value is smaller than a fault-tolerant bit threshold for error correction of the non-volatile memory.
After at least a portion of the non-volatile memory device is programmed a certain number of times, the fault-tolerant bit value is updated from the first value to a second value to control a plurality of verification operations according to the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold value, as shown in step S20.
Thus, the method may avoid impairment of error correction capability due to written data being less than or equal to the fault-tolerant bit value. For illustration, in the application scenario discussed above, when undergoing a verification operation, the fault-tolerant bit value is set to a first value (e.g., 0, 1 or 2) smaller than the fault-tolerant bit threshold (e.g., 8) via step S10, and the verification operation will fail because the data to be written (e.g., a small number of bits, such as 8, 7 bits or less) is substantially larger than the fault-tolerant bit value (e.g., 0, 1 or 2). In the case where an incremental pulse programming (ISPP) technique is applied to the nonvolatile memory, since the verification operation of the fault-tolerant bit value with respect to the first value has failed, a programming operation will be performed regardless of whether the data has been programmed correctly. In the incremental pulse programming, the verify operation may repeatedly fail to verify during at least a portion of the non-volatile memory (e.g., a small number of bits written, such as 8, 7, or less bits of data) is programmed a particular number of times (e.g., 3 or 4 times). By step S20, the fault-tolerant bit value is updated from the first value (e.g. 0) to a second value (e.g. 5, 6, 7 or 8) greater than the first value, so as to control the plurality of verification operations according to the fault-tolerant bit value after the nonvolatile memory device is programmed the specific number of times (e.g. 3 or 4), wherein the second value is less than or equal to the fault-tolerant bit value. Therefore, even if the number of bits of the data to be written is less than the fault-tolerant bit threshold, the data to be written is programmed for a specific number of times, thereby increasing the probability that the data is programmed correctly. The method can prevent the error correction capability of the nonvolatile memory device from being weakened because the data to be written is less than or equal to the fault-tolerant bit value, thereby improving the reliability of the nonvolatile memory device. In contrast, in the prior art, the fault-tolerant bit value is fixedly set to the fault-tolerant bit threshold, i.e., the maximum error correction capability is used, which results in the programming operation not being performed when the number of bits of data to be written is less than the fault-tolerant bit threshold.
In one embodiment, the fault tolerant bit value is set to the first value when the number of pulses is less than a pulse number threshold. For example, in the incremental pulse programming process, a number of pulses is incremented for each programming operation performed. Referring to fig. 2, when the number of pulses is less than the pulse number threshold, as indicated by symbol a (e.g., 3 or 4) in fig. 2, the fault-tolerant bit value is set to the first value, which may be zero or less than the fault-tolerant bit threshold.
Referring to fig. 2, in an embodiment, when the pulse number is equal to or greater than the pulse number threshold, the fault-tolerant bit value is updated from the first value (e.g., 0) to the second value, as indicated by reference symbol B (e.g., 3 or 4) in fig. 2.
Referring to fig. 3, fig. 3 is a method of controlling a verify operation for error correction of a non-volatile memory device according to some embodiments of fig. 1.
As shown in fig. 3, the method includes steps S10 and S20 which are the same as those in fig. 1, and the second value is smaller than the fault-tolerant bit threshold, and further includes step S30. As shown in step S30, the fault-tolerant bit value is incrementally increased at least one or more times from the second value to control the verification operation according to the fault-tolerant bit value, wherein the increased fault-tolerant bit value is less than or equal to the fault-tolerant bit threshold.
In some embodiments of step S30, the fault tolerant bit value may be incremented by the same increment (e.g., 1, 2, or 3) or by individual increments multiple times.
In one embodiment of the method of FIG. 3, for example, during incremental pulsing of a portion of the non-volatile memory, when the number of pulses is less than a pulse value A1, as indicated by symbol A1 (e.g., 4) in FIG. 4, the fault-tolerant bit value is set to the first value by step S10 of FIG. 3, wherein the first value may be zero or less than the fault-tolerant bit threshold. When the pulse number is equal to the pulse value A1 (e.g., 4), the fault-tolerant bit value is updated from the first value (e.g., 0) to the second value, as represented by the fault-tolerant bit value B1 (e.g., 1) in FIG. 4, via step S20 in FIG. 3. Then, by step S30 of fig. 3, the fault tolerant bit value is incrementally increased at least one or more times from the second value. Referring to FIG. 4, when the pulse number is equal to a pulse value A2 (e.g., 5), the fault tolerant bit value is updated from the second value (e.g., fault tolerant bit value B1) to a fault tolerant bit value B2 (e.g., 3). When the pulse number is equal to the pulse number A3 (e.g., 6), the fault tolerant bit value is updated from the fault tolerant bit value B2 (e.g., 3) to a fault tolerant bit value B3 (e.g., 4). When the pulse number is equal to the pulse number A4 (e.g., 8), the fault-tolerant bit value is finally updated from the fault-tolerant bit value B3 (e.g., 4) to a fault-tolerant bit value B4 (e.g., 6). In this manner, for the example of an incremental pulse programming process performed on a portion of the non-volatile memory, the error correction capability may be preserved until after the number of pulses meets a criterion, such as the number of pulses equal to pulse value A1, and the data to be written will be programmed a certain number of times even if the number of bits of the data to be written is less than the fault-tolerant bit threshold, so that the probability of the data being programmed correctly is increased. Furthermore, the error correction capability may be progressively released upon satisfaction of the decision criterion. Therefore, the method can prevent the error correction capability of the nonvolatile memory device from being weakened because the data to be written is less than or equal to the fault-tolerant bit value, thereby improving the reliability of the nonvolatile memory device.
The following provides an example of the implementation of the method according to the previous examples of fig. 1, 2, 3 or 4.
In one embodiment, a non-volatile memory device is provided that includes an array of non-volatile memory cells, a page buffer circuit, and a control logic circuit. The non-volatile storage device may be, for example, a flash memory device.
The page buffer circuit is coupled to the non-volatile memory cell array, and the control logic circuit is coupled to the non-volatile memory cell array and the page buffer circuit. The control logic is to control the non-volatile storage device.
For example, the control logic may be configured to implement the methods according to the foregoing examples of fig. 1, 2, 3, or 4. When the control logic circuit controls at least a portion of the non-volatile memory cell array to be programmed and verified, the control logic circuit sets a fault-tolerant bit value to a first value to control a verification operation according to the fault-tolerant bit value, wherein the first value is less than a fault-tolerant bit threshold for error correction of the non-volatile memory device; and after programming at least a portion of the array of non-volatile memory cells a specified number of times, the control logic updates the fault-tolerant bit value from the first value to a second value to control a verify operation based on the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold.
In one embodiment, the control logic sets the fault tolerant bit value to the first value when the number of pulses is less than a pulse number threshold.
In one embodiment, the control logic sets the first value to zero or a value less than the tolerance bit threshold.
In one embodiment, the control logic updates the fault tolerant bit value from the first value to the second value when the number of pulses is equal to or greater than the pulse number threshold.
In one embodiment, the control logic circuit incrementally increases the fault tolerant bit value from the second value at least once to control a verification operation in dependence upon the fault tolerant bit value, wherein the increased fault tolerant bit value is less than or equal to the fault tolerant bit threshold.
Referring to fig. 5, fig. 5 is a block diagram of a nonvolatile memory device according to the foregoing embodiments. As shown in fig. 5, the nonvolatile memory device 1 includes a memory cell array 10, an X-line decoder 20, a voltage generator 30, a page buffer circuit 40, a Y-line decoder 45, an input/output buffer 50, and a control logic circuit 60. For convenience of description, the non-volatile memory device 1 may be a flash memory device, such as a NAND flash memory device. Of course, the implementation of the present invention is not limited to the above examples.
The memory cell array 10 includes a plurality of memory cells arranged in a row connected to word lines (word lines) and a column connected to bit lines (bit lines). Each memory cell stores 1-bit data or M-bit data, where M is an integer greater than 1. Each memory cell may utilize a charge storage layer to store data, such as a floating gate or charge trapping layer, a variable resistance, or other type of memory cell.
The X-ray decoder 20 is used for selecting and driving a plurality of columns of the memory cell array 10.
The voltage generator 30 is controlled by the control logic 60 and generates a plurality of voltages (e.g., programming voltage, pass voltage, erase voltage, and read voltage) for programming, erase, and read operations.
The page buffer circuit 40 and the Y-line decoder 45 are controlled by the control logic circuit 60 and act as sense amplifiers or write drivers depending on the different operating modes of the flash memory device. For example, in a read operation, the page buffer circuit 40 and the Y-line decoder 45 function as sense amplifiers for sensing data from a selected memory cell of a selected column. For example, in a programming operation, the page buffer circuit 40 and the Y-line decoder 45 function as a write driver for driving selected memory cells of a selected column according to programming data. The page buffer circuit 40 includes a plurality of page buffers corresponding to respective bit lines or bit line pairs.
The input/output buffer 50 receives read data from the page buffer circuit 40 and the Y-line decoder 45 and transmits the read data to an external destination, such as a computing device. The I/O buffer 50 typically operates in conjunction with an external device, such as a memory controller or host.
The control logic 60 is used to control the operation of the non-volatile memory device 1. The control logic 60 may be implemented to include a bit detector 600, a fault tolerant bit detector 610, and a pulse counting circuit 620.
For example, the control logic circuit 60 may be configured to receive data with the bit detector 600, which is read by the page buffer circuit 40 and the Y-line decoder 45 in a verify operation. The control logic 60 can determine whether the at least one selected memory cell is successfully programmed, for example, by determining whether the threshold voltage of the at least one selected memory cell is greater than or equal to the associated verify level according to the data read by the page buffer circuit 40 by the bit detector 600.
The fault-tolerant bit detector 610 is responsive to a fault-tolerant bit value for detecting whether data read by the page buffer 40 includes a number of error bits less than or equal to the fault-tolerant bit value. The fault-tolerant bit detector 610 may be implemented with analog circuits and/or digital circuits, such as suitable current sense amplifiers, counters, and logic circuits.
The pulse counting circuit 620 is used to count the number of pulses, for example, for incremental pulse programming. The pulse counting circuit 620 may be implemented in digital circuitry, such as a suitable counter and sequential and/or combinational logic circuitry. The number of pulses may be a program pulse number or an erase pulse number.
The control logic 60 may also include one or more registers that store success or failure information during programming. For example, the control logic circuit 60 determines whether all selected memory cells have been successfully programmed based on the read data from the page buffer circuit 40 and the Y-line decoder 45 during verify operations.
In some embodiments, the control logic 60 may be configured to implement steps S10 and S20 of fig. 1 or steps S10-S30 of fig. 3, as described in accordance with the foregoing examples of fig. 1, 2, 3, or 4. For example, the control logic 60 may be configured to read the number of pulses of the pulse counting circuit 620 and determine the timing for progressively setting the fault-tolerant bit value of the fault-tolerant bit detector 610 to the first value, the second value or other values according to the number of pulses received from the pulse counting circuit 620.
In other embodiments, the fault-tolerant bit detector 610 may be configured to be coupled to the pulse counting circuit 620 to receive a fault-tolerant bit value, and the pulse counting circuit 620 may be configured to include logic to store a number of pulses and to control the fault-tolerant bit detector based at least on the number of pulses. The logic circuit of the pulse counting circuit 620 may be configured to read the number of pulses stored in the pulse counting circuit 620 and determine a timing for progressively setting the fault-tolerant bit value of the fault-tolerant bit detector 610 to the first value, the second value or other values according to the number of pulses stored in the pulse counting circuit 620. Of course, the implementation of the present invention is not limited to the above examples.
In some embodiments, the method of FIG. 1 or 3 may be performed when a program of the program and verify operations is executed in at least a portion of the non-volatile memory. Referring to FIG. 6, an example of programming and verification operations, such as incremental pulse programming, is shown. The routine of fig. 6 includes steps S110 to S160.
In step S110, a voltage V is programmedPGMInitially set to the starting programming voltage with the cycle indicator K set to 1 and the pass flag set to 0.
In step S120, a program operation of a portion (e.g., a page) of the non-volatile memory is performed.
In step S130, a verification operation is performed. In step S140, it is determined whether the number of error bits is less than or equal to the fault-tolerant bit value. If yes, the verification operation is represented as passing verification, wherein the passing flag is set to be 1; and the programming is stopped as shown in step S145. If not, the process further proceeds to step S150 to determine whether the loop indicator K is greater than the loop indicator threshold.
In step S150, if the determination is positive, it represents that the compilation has failed, as shown in step S155. If the judgment in the step S150 is NO, the program further proceeds to a step S160 in which the programming voltage V is programmedPGMAn increment amount is added and the loop indicator K is increased, and then the procedure proceeds to step S120 to execute the next loop.
In one embodiment, the fault tolerant bit value of step S140 may be set by the method described in the example according to fig. 1, 2, 3 or 4.
Referring to fig. 6 and 7, the programming voltage V is programmed through a plurality of cycles of the programPGMWill be progressively increased. In some embodiments, the method according to FIG. 1 or FIG. 3 may be performed when the compilation and verification operations shown in FIG. 6 are performed alternately.
Tables 1 and 2 below are two examples of the method according to fig. 1 and 3, i.e., an example in which the programming voltage (i.e., ISPP voltage) is gradually increased when a program such as an example of incremental pulse programming is performed.
Table 1 shows that the fault-tolerant bit value is initially set to 0 and is set to 7 when the pulse number is equal to 4, i.e., the maximum fault-tolerant bit value of this example.
TABLE 1
Table 2 shows that the fault-tolerant bit value is initially set to 0 and progressively increased, and when the number of pulses is equal to 4, the fault-tolerant bit value is set to 7.
TABLE 2
In some embodiments, the fault tolerant bit value may be set to the fault tolerant bit threshold when the number of pulses equals or exceeds a pulse number threshold. The pulse number threshold may be determined according to performance or characteristics of the nonvolatile memory device. For example, the pulse number threshold may be determined according to a disturb value (disturb value) of the nonvolatile memory device, such as a programming disturb, a pass voltage (Vpass) disturb and/or a design voltage (Vpp) disturb, and/or a time required for programming.
In some embodiments, the verification operation may be determined to be verified when two or more consecutive passes of verification are detected.
Accordingly, embodiments of a method for controlling a verify operation of a nonvolatile memory device and a nonvolatile memory device thereof are provided. Therefore, even though the number of bits of the data to be written is smaller than the fault-tolerant bit threshold value, the data to be written is still programmed for a certain number of times, and therefore the probability of correctly programming the data can be improved. The method can prevent the error correction capability of the nonvolatile memory device from being weakened because the data to be written is less than or equal to the fault-tolerant bit value, thereby improving the reliability of the nonvolatile memory device.
The present invention has been disclosed in terms of preferred embodiments, however, it will be understood by those skilled in the art that the embodiments are illustrative only and should not be construed as limiting the scope of the invention. It is noted that equivalent variations and substitutions for the illustrated embodiments are intended to be included within the scope of the present invention. Therefore, the protection scope of the present invention is defined by the claims.
Claims (11)
1. A method of controlling a verify operation for error correction of a non-volatile memory device, the method comprising:
setting a fault-tolerant bit value for error correction of the non-volatile storage device to a first value to control a plurality of verify operations in dependence on the fault-tolerant bit value, wherein the first value is less than a fault-tolerant bit threshold for error correction of the non-volatile storage device; and
updating the fault-tolerant bit value from the first value to a second value after at least a portion of the non-volatile storage device is programmed a specified number of times to control the plurality of verification operations in accordance with the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold.
2. The method of claim 1, wherein the fault tolerant bit value is set to the first value when a number of pulses is less than a pulse number threshold.
3. The method of claim 2, wherein the first value is zero or less than the fault-tolerant bit threshold.
4. The method of claim 2, wherein the fault tolerant bit value is updated from the first value to the second value when the number of pulses is equal to or greater than the pulse number threshold.
5. The method of claim 1, further comprising:
progressively incrementing the fault tolerant bit value at least once from the second value to control the plurality of verification operations in accordance with the fault tolerant bit value, wherein the incremented fault tolerant bit value is less than or equal to the fault tolerant bit threshold.
6. The method of claim 1, wherein the method is performed during programming and verification of at least a portion of the non-volatile storage device.
7. A non-volatile storage device, comprising:
a non-volatile memory cell array;
a page buffer circuit coupled to the array of non-volatile memory cells; and
a control logic circuit coupled to the array of non-volatile memory cells and the page buffer circuit for controlling the non-volatile memory device,
wherein, during a time that the control logic controls at least a portion of the array of non-volatile memory cells to be programmed and verified, the control logic sets a fault-tolerant bit value to a first value to control a plurality of verification operations as a function of the fault-tolerant bit value, wherein the first value is less than a fault-tolerant bit threshold for error correction of the array of non-volatile memory cells; after at least a portion of the array of non-volatile memory cells is programmed a specified number of times, the control logic updates the fault-tolerant bit value from the first value to a second value to control the plurality of verify operations according to the fault-tolerant bit value, wherein the second value is greater than the first value and less than or equal to the fault-tolerant bit threshold.
8. The non-volatile memory device of claim 7, wherein the control logic circuit sets the fault tolerant bit value to the first value when a number of pulses is less than a pulse number threshold.
9. The non-volatile memory device of claim 8, wherein the control logic circuit sets the first value to zero or a value less than the tolerance bit threshold.
10. The non-volatile memory device of claim 8, wherein the control logic circuit updates the fault tolerant bit value from the first value to the second value when the number of pulses is equal to or greater than the number of pulses threshold.
11. The non-volatile memory device of claim 7, wherein the control logic circuit incrementally increments the fault tolerant bit value from the second value at least once to control the plurality of verify operations as a function of the fault tolerant bit value, wherein the incremented fault tolerant bit value is less than or equal to the fault tolerant bit threshold.
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