JP6632416B2 - Shared memory control circuit and shared memory control method - Google Patents

Description

  The present invention relates to a shared memory control circuit and a shared memory control method, and more particularly, to a multiprocessor system having a shared memory accessible from a plurality of processors.

In a multiprocessor system having a shared memory, a semaphore (an exclusive control variable) is used for exclusive control when a plurality of processors (CPUs) access the shared memory. The shared memory is divided into a plurality of areas, and semaphore registers corresponding to the divided memory areas are provided. At the time of shared memory access, by reading that the semaphore register corresponding to the area to be accessed is "0", it is confirmed that the semaphore has not been acquired by another processor, and then "1" to indicate that the semaphore is in use. To perform exclusive control by acquiring a semaphore. By accessing the shared memory after acquiring the semaphore and reading or writing, simultaneous access from multiple processors is prohibited, preventing data corruption due to simultaneous writing and rewriting data during data reading. I have. Therefore, when the semaphore acquisition fails, that is, when the value read from the semaphore register is “1”, it is necessary to wait for the semaphore release by polling or the like.
At the time of semaphore acquisition, exclusive control cannot be realized if reading or writing occurs from another processor between the state reading operation of the semaphore register and the acquisition state writing operation. For this reason, it is necessary to prohibit access from another processor from the state reading of the semaphore register to the writing of the acquired state, and it is necessary to perform a state read called a read-modify-write and simultaneously perform a process of writing the acquired state. .

  Therefore, if multiple semaphore registers are read at the same time, multiple semaphores accessed may be acquired. In order to avoid acquiring unnecessary semaphores, only one semaphore register is accessed in one access. Can not. Therefore, it is not possible to know a plurality of semaphore states at the same time, and it is necessary to access the registers one by one in order to acquire the semaphore, and the throughput has decreased due to an increase in access time.

  Further, when communication is performed using the shared memory, it is impossible to determine an address range in which valid communication data is stored in the divided shared memory area. Therefore, it is necessary to read all the addresses in the divided shared memory area, and it is necessary to read data even from an address where data used for communication is not stored, and the communication throughput is reduced. Also, it is not possible to distinguish between the area where data used for communication is stored and the area where data is not stored, and it is necessary to keep all shared memory areas, including unused memory areas, always running. , Causing power consumption to increase.

  To cope with such a problem, Japanese Patent Application Laid-Open No. 2004-178374 monitors data and addresses flowing on a shared bus and copies them to a cache for the own processor, thereby reducing access to a semaphore register and suppressing bus tightness. I do. As described above, a technique is disclosed in which the same contents as the shared memory data and the semaphore register data are copied to the cache of the own processor to reduce the bus usage rate.

  However, in Japanese Patent Application Laid-Open No. 2004-178374, it is necessary to wait for semaphore release by polling or the like when semaphore acquisition fails. In addition, it is not possible to know the state of a plurality of semaphores at the same time, and it is necessary to access the registers one by one in order to acquire the semaphore. Therefore, the access time, the communication throughput, and the power consumption by the shared memory cannot be improved. Further, a large-capacity cache capable of storing the shared memory data and the semaphore register data is required, which causes a problem of high cost.

  In Japanese Patent Application Laid-Open No. 2001-222466, the shared memory is divided into small blocks, and an identifier storage area indicating the identifier of the CPU updated last is installed in each block. Instead, a technique using data in a CPU-only memory is disclosed.

  However, in Japanese Patent Application Laid-Open No. 2001-222466, when semaphore acquisition fails, it is necessary to wait for semaphore release by polling or the like. In addition, it is not possible to know the state of a plurality of semaphores at the same time, and it is necessary to access the registers one by one in order to acquire the semaphore. Therefore, the access time, the communication throughput, and the power consumption by the shared memory cannot be improved.

JP 2004-178374 A JP 2001-222466 A

As described above, in a system in which a shared memory is accessed from a plurality of processors, exclusion control using a semaphore is performed, but when acquisition of a semaphore fails, it is necessary to wait for semaphore release by polling or the like. Further, it is not possible to know a plurality of semaphore states at the same time, and it is necessary to access the registers one by one in order to acquire the semaphore, so that the access time increases and the throughput decreases.
In addition, when performing communication using the shared memory, it is not possible to determine an address at which data to be communicated is stored or a memory area not used as a system, and a communication throughput by accessing an area not used for communication. There was a problem that declined.
Also. There has been a problem in that power consumption is increased by constantly operating all shared memory areas including unused memory areas.

  An object of the present invention is to improve communication throughput using a shared memory accessible from a plurality of processors.

The shared memory control circuit of the present invention includes:
In a shared memory control circuit accessed by a plurality of processors,
Multiple memory areas,
A plurality of semaphore registers provided corresponding to the plurality of memory areas, a plurality of semaphore registers for recording semaphores used for exclusive control of the memory area,
A semaphore state summary register for recording states of the plurality of semaphore registers.

  According to the present invention, since a semaphore status summary register that can check the status of a plurality of semaphore registers by one access is provided, it is possible to shorten the access time to the shared memory and improve the communication throughput.

FIG. 3 is a diagram illustrating a shared memory control circuit 50 according to the first embodiment of the present invention. FIG. 5 is a diagram for explaining a method for implementing a plurality of semaphore state reads in the first embodiment of the present invention. FIG. 3 is a diagram illustrating an operation of a processor on a transmission side according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating an operation of a processor on the receiving side according to the first embodiment of the present invention. FIG. 7 is a diagram illustrating a shared memory control circuit 50 according to a second embodiment of the present invention. FIG. 13 is a diagram for explaining a method of realizing use state reading of a plurality of shared memory areas according to the second embodiment of the present invention. FIG. 9 is a diagram illustrating an operation of a processor on a transmission side according to a second embodiment of the present invention. FIG. 8 is a diagram illustrating an operation of a processor on a receiving side according to a second embodiment of the present invention. FIG. 10 is a diagram for explaining a shared memory control circuit 50 according to Embodiment 3 of the present invention. FIG. 14 is a diagram for explaining a method of reading availability information of a plurality of shared memory areas in Embodiment 3 of the present invention. FIG. 13 is a diagram for explaining a memory area stop operation in the third embodiment of the present invention. FIG. 14 is a diagram illustrating a memory area starting operation according to Embodiment 3 of the present invention. FIG. 14 is a diagram illustrating a memory area starting operation according to Embodiment 3 of the present invention.

Embodiment 1 FIG.
*** Configuration description ***
FIG. 1 is a diagram showing a configuration of a multiprocessor system 100 including a shared memory control circuit 50 according to the first embodiment of the present invention.
In FIG. 1, a processor 10, a processor 20, and a processor 30 are connected to a bus 40. The shared memory control circuit 50 is also connected to the bus 40. The shared memory control circuit 50 includes a shared memory 520 and an access control unit 541 that controls access to the shared memory 520.
The shared memory 520 is managed by being divided into N pieces. The shared memory control circuit 50 has a plurality of memory areas. In FIG. 1, the shared memory 520 is divided into memory areas 521, 522, 523 and 524. ing. The shared memory control circuit 50 has a plurality of semaphore registers corresponding to a plurality of memory areas. The semaphore register is a register that records a semaphore used for exclusive control of a memory area. In FIG. 1, semaphore registers 501, 502, 503, and 504 corresponding to the respective memory areas 521, 522, 523, and 524 are provided. In FIG. 1, “RG” means “register”. Hereinafter, the semaphore registers 501, 502, 503, and 504 are simply referred to as the semaphore registers 500 when it is not necessary to distinguish them.
In addition, the shared memory control circuit 50 includes a semaphore state summary register 531 for recording states of a plurality of semaphore registers.

As shown in FIG. 2, the semaphore register 500 is a register composed of a plurality of bits, and the least significant bit of the semaphore register 500 is a semaphore status bit 509 for recording a semaphore composed of one bit. When the semaphore status bit 509 is "0", it indicates that the semaphore has not been acquired, and when it is "1", it indicates that the semaphore has been acquired. The semaphore status bit 509 is a bit indicating that a semaphore is being acquired in a semaphore register corresponding to a memory area obtained by dividing the shared memory 520.
Further, as shown in FIG. 2, the semaphore state summary register 531 is an N-bit register in which the value of the semaphore state bit 509 is extracted and arranged. Each bit of the semaphore status summary register 531 is connected to the corresponding semaphore status bit 509 via a signal line, and is reflected in the value of each bit of the semaphore status summary register 531 at the same time as the semaphore status bit 509 changes. As a result, the same value as the value of the semaphore state bit 509 of the semaphore registers 501, 502, 503, and 504 is sequentially recorded from the least significant bit of the semaphore state summary register 531 to the most significant bit. The semaphore state summary register 531 can be read by a single access from the processor, and the processor can know the N semaphore states in one access, eliminating the need to individually access a plurality of semaphore registers. . At this time, the semaphore status summary register 531 is not connected to the semaphore status bit 509 but is made an independent register. Even when the value of the semaphore status bit 509 changes, the processor or the access control unit 541 rewrites the semaphore status summary register 531. good.

*** Explanation of operation ***
The method of controlling the shared memory by the shared memory control circuit 50 will be described with reference to FIGS. Here, an operation when data communication using a shared memory is performed between different processors will be described by taking a case where data is transmitted from the processor 1 to the processor 2 as an example.

<< Data transmission operation >>
Step 11: Step of reading semaphore state summary register FIG. 3 shows an operation flowchart of the processor 1 on the data transmission side. When accessing the memory storage area, the processor 1 on the data transmitting side reads the value of the semaphore state summary register 531.

Step 12: Semaphore Acquisition Step and Semaphore State Recording Step Next, the processor 1 looks for a bit whose value of the semaphore state summary register 531 is “0” and detects a semaphore register for which no semaphore has been acquired. The processor 1 accesses the semaphore register whose memory area is not used, and acquires the semaphore. That is, the processor 1 accesses the semaphore register corresponding to the bit of the value of 0 of the semaphore state summary register 531, reads the value of the semaphore register, and rewrites the semaphore state bit 509 to “1”. From the state reading of the semaphore register to the writing of the acquisition state, it is necessary to prohibit access from another processor.
At this time, the value of the semaphore status bit 509 is reflected on the value of the corresponding bit of the semaphore status summary register 531 connected to the semaphore status bit 509 by a signal line. When the semaphore status summary register 531 is an independent register without being connected to the semaphore status bit 509, the processor 1 sets the semaphore status summary corresponding to the semaphore register whose semaphore status bit 509 is rewritten to “1”. The bit of the register 531 is rewritten to “1”. The process of rewriting the bit of the semaphore status summary register 531 to “1” may be performed not by the processor 1 but by the access control unit 541. In this case, the access control unit 541 detects that the semaphore status bit 509 is rewritten to “1” and rewrites the corresponding bit of the semaphore status summary register 531 to “1”.
As described above, the semaphore acquisition step is a step of recording a semaphore used for exclusive control of the memory area in a plurality of semaphore registers provided corresponding to the plurality of memory areas.
The semaphore state recording step is a step of recording the state of the semaphore register in the semaphore state summary register.

Step 13: Semaphore Acquisition Check Step At the time of semaphore acquisition, the semaphore acquisition fails because another processor acquires the same semaphore between the time when the semaphore status summary register 531 is read and the time when the semaphore register status is read. That is, the value read from the semaphore register may be “1”. In this case, another semaphore register is selected from the read value of the semaphore state summary register, and a semaphore is acquired by accessing a semaphore register for which no semaphore has been acquired.

Step 14: Data writing step (memory area access step)
Next, the processor 1 on the data transmission side writes the transmission data to a memory area corresponding to the acquired semaphore.

Step 15: Semaphore Release Step When writing of all communication data is completed, the processor 1 releases the semaphore by writing “0” to the semaphore register corresponding to the accessed memory area. At this time, the value of the semaphore status bit 509 is reflected on the value of the corresponding bit of the semaphore status summary register 531 connected to the semaphore status bit 509 by a signal line. When the semaphore status summary register 531 is an independent register without being connected to the semaphore status bit 509, the processor 1 rewrites the corresponding bit of the semaphore status summary register 531 to “0”.
Thereby, the data transmission from the processor 1 is completed.

<< Data reception operation >>
Next, an operation in which the processor 2 on the data receiving side reads data written by the processor 1 will be described. FIG. 4 shows an operation flowchart of the processor 2 on the data receiving side.

Step S21: Notification Signal Waiting Step The processor 1 notifies the processor 2 of the read timing of reading communication data from the shared memory by a notification signal such as an interrupt signal or polling. The processor 2 waits for a notification signal from the processor 1.

Step S22: Read Start Step Upon receiving the notification signal, the processor 2 starts the read operation.

Step S23: Semaphore Acquisition Step and Semaphore State Recording Step The processor 2 analyzes the notification signal, specifies the memory area where the communication data is recorded, accesses the corresponding semaphore register, and acquires the semaphore. The operation of accessing the semaphore register and the operation of acquiring the semaphore are the same as those in step 12 described above except that the semaphore state summary register 531 is not accessed. The reason why the access to the semaphore state summary register 531 is unnecessary is that the memory area in which the communication data is recorded has already been notified to the processor 2, and the processor 2 already knows the semaphore register to be accessed.

Step 24: Semaphore acquisition check step At the time of semaphore acquisition, semaphore acquisition may fail. That is, when the value read from the semaphore register is “1”, the processor 2 or the access control unit 541 waits for the release of the semaphore from the semaphore register by polling.

Step S25: Data read step (memory area access step)
After acquiring the semaphore, the processor 2 reads the communication data from the memory area where the communication data is recorded.

Step S26: Release Semaphore Step When the reading of communication data by the processor 2 ends, the processor 2 writes "0" into the semaphore register corresponding to the accessed memory area, and releases the semaphore. At this time, the value of the semaphore status bit 509 is reflected on the value of the corresponding bit of the semaphore status summary register 531 connected to the semaphore status bit 509 by a signal line. When the semaphore status summary register 531 is not connected to the semaphore status bit 509 but is an independent register, the processor 2 or the access control unit 541 sends the semaphore status summary register 531 corresponding to the semaphore register whose semaphore is released. Is rewritten to “0”.
Thereby, the receiving process of the processor 2 is completed.

*** Explanation of effect of embodiment ***
According to the embodiment of the present invention, since the shared memory control circuit 50 includes the semaphore state summary register 531, it is possible to improve communication throughput using a shared memory that can be accessed from a plurality of processors. That is, since the semaphore status summary register 531 that can confirm the status of the plurality of semaphore registers by one access is provided, the access time to the shared memory can be reduced.

Embodiment 2 FIG.
In this embodiment, points different from the first embodiment will be mainly described.
*** Configuration description ***
FIG. 5 is a diagram showing a configuration of a system including the shared memory control circuit 50 according to the second embodiment of the present invention.
The shared memory control circuit 50 has a plurality of memory management registers corresponding to a plurality of memory areas. The plurality of memory management registers are registers that record the use state of the memory area. In FIG. 5, memory management registers 511, 512, 513, and 514 corresponding to the memory areas 521, 522, 523, and 524 are provided. Hereinafter, when it is not necessary to distinguish the memory management registers 511, 512, 513, and 514, they are simply referred to as memory management registers 510.
In addition, the shared memory control circuit 50 includes a memory status summary register 532 that records the status of a plurality of memory areas.

As shown in FIG. 6, the memory management register 510 is a register composed of a plurality of bits. The least significant bit of the memory management register 510 is a memory use state bit 517 consisting of one bit. When the memory use status bit 517 is “0”, the corresponding memory area is unused, and when “1”, it indicates that the corresponding memory area is in use. The memory use status bit 517 is a flag bit indicating whether the memory area obtained by dividing the shared memory 520 is unused or in use.
As shown in FIG. 6, the memory status summary register 532 is an N-bit register in which the values of the memory usage status bits 517 are extracted and arranged. Each bit of the memory status summary register 532 is connected to the corresponding memory usage status bit 517 by a signal line, and is reflected in the value of each bit of the memory status summary register 532 at the same time as the memory usage status bit 517 changes. As a result, the same value as the value of the memory use state bit 517 of the memory management registers 511, 512, 513, 514 is recorded in order from the least significant bit to the most significant bit of the memory state summary register 532. The memory status summary register 532 can be read by a single access from the processor, and the processor can know the N memory usage status in one access, and need to individually access a plurality of memory management registers. Disappears.

The memory management register 510 is a register that stores information on a corresponding memory storage area. The memory management register 510 has the above-mentioned memory use state bit 517 in the least significant bit, and has a memory access state bit 518 in addition to the least significant bit.
The memory use state bit 517 stores the use state (presence or absence of valid communication data) of the memory area.
The memory access status bit 518 includes at least one of the following bits, and stores the following information of the memory storage area.
1. Last access type bit (1 bit)
Final access type to memory area (0: read or 1: write),
The state of memory access can be known.
2. Last access processor bits (multiple bits)
The processor number of the processor that last accessed the memory area,
3. Communication ID bits (multiple bits)
The processor number of the communication destination processor that is the destination of the communication data,
4. Data identification bit (multiple bits)
The data identification number of the communication data indicating the order of the transmission data is recorded.
5. Address bits (multiple bits)
The start address and end address of the memory area where the transmission data is recorded.
Also, the start address and the end address of the memory area from which the reading was performed.

  When accessing the memory area, the information of the memory management register 510 is stored in the memory management register by hardware or software. Specifically, the processor or the access control unit 541 stores such information in the memory management register when accessing the memory area. By accessing the memory management register 510, all processors in the system can know the use state of the shared memory.

*** Explanation of operation ***
The method of controlling the shared memory by the shared memory control circuit 50 will be described with reference to FIGS.

<< Data transmission operation >>
Step 11: Step of reading semaphore state summary register and memory state summary register When accessing the shared memory, the processor 1 on the data transmission side reads the values of the semaphore state summary register 531 and the memory state summary register 532.

Step 12: Semaphore Acquisition Step and Semaphore State Recording Step The processor 1 searches the semaphore state summary register 531 for a bit having a value of “0”, detects a semaphore register for which a semaphore has not been acquired, and detects the value of the memory state summary register 532. Looks for a bit of "0" and detects an unused memory area. Then, the processor 1 accesses the semaphore register of the unused memory area where the semaphore has not been acquired, and acquires the semaphore. Thereafter, by the same operation as in the first embodiment, the processor 1 records the semaphore used for exclusive control of the memory area in the semaphore register, and the semaphore state summary register connected to the semaphore state bit by a signal line. The value of the semaphore state bit is reflected in the value of the corresponding bit of. When the semaphore status summary register is an independent register without being connected to the semaphore status bit, the processor 1 records the status of the semaphore register in the semaphore status summary register.

Step 13: Semaphore Acquisition Check Step At the time of semaphore acquisition, the semaphore acquisition fails because another processor acquires the same semaphore between the time when the semaphore status summary register 531 is read and the time when the semaphore register status is read. there is a possibility. In this case, another semaphore register is selected from the read values of the semaphore status summary register 531 and the memory status summary register 532, and the semaphore is acquired by accessing a semaphore register for which no semaphore has been acquired.

Step 14-1: Data writing step (memory area access step)
Next, the processor 1 on the data transmission side writes the transmission data to a memory area corresponding to the acquired semaphore.

Step 14-2: Use State Recording Step At this time, the access control unit 541 writes “1” to the memory use state bit of the memory management register corresponding to the write destination memory area, and the corresponding memory area is used for inter-processor communication. Record that it is in use. Here, that the memory area is being used means that communication data is stored and is not read out. In addition, the memory area is unused when there is no communication data in use, that is, the communication data is not stored or the communication data is stored by the communication destination processor. It means that it has been read. At this time, the value of the memory use state bit is reflected on the value of the corresponding bit of the memory state summary register connected to the memory use state bit by a signal line.
At the same time, the access control unit 541 writes “1” to the last access type bit to indicate that the immediately preceding access was a write. Further, the access control unit 541 writes “1” in the last access processor bit, indicating that the last access processor is the processor 1. Further, the access control unit 541 specifies the processor of the transmission destination by writing “2” which is the processor ID of the data transmission destination to the communication ID bit. In addition, the access control unit 541 may write a communication data identification number indicating the order of transmission data in the data identification bit.
The access control unit 541 writes the write start address and the write end address of the data to the start address and the end address of the address bits of the memory management register when writing data, and stores at which address in the memory area the data is written.
As described above, the use state recording step is a step of recording the use state of the memory area in a plurality of memory management registers provided corresponding to the plurality of memory areas.

Step 14-3: Management Status Recording Step If the memory status summary register is not connected to the memory use status bit but is an independent register, the access control unit 541 sets the corresponding bit of the memory status summary register 532 to the corresponding bit. Write "1". The access control unit 541 writes “1” to the corresponding bit of the memory status summary register 532 corresponding to the write destination memory area, and records that the corresponding memory area is being used for inter-processor communication.
As described above, the management state recording step is a step of recording the use state of the memory area in the memory state summary register 532.

Step 15: Semaphore Release Step When writing of all communication data is completed, the processor 1 releases the semaphore by writing “0” to the semaphore register corresponding to the accessed memory boundary.
At this time, the value of the semaphore status bit is reflected on the value of the corresponding bit of the semaphore status summary register connected to the semaphore status bit by a signal line. When the semaphore status summary register is not connected to the semaphore status bit but is an independent register, the processor 1 or the access control unit 541 determines the bit of the semaphore status summary register 531 corresponding to the semaphore register whose semaphore is released. Is rewritten to “0”.
Thereby, the data transmission from the processor 1 is completed.

<< Data reception operation >>
Next, an operation in which the processor 2 on the data receiving side reads data written by the processor 1 will be described. FIG. 8 shows an operation flowchart of the processor 2 on the data receiving side.

Step S21: Polling Step or Notification Signal Waiting Step The timing at which the processor 2 reads communication data from the shared memory is determined by the processor 2 polling the memory status summary register 532. When the processor 2 detects that “1” has been written to a certain bit of the memory status summary register 532, the communication destination processor ID recorded in the communication ID bit of the corresponding memory management register 510 is “2”. It is determined whether or not. Instead of polling the memory status summary register 532, the processor 2 may poll the memory management register.
Alternatively, as in the first embodiment, the read timing at which the processor 2 reads communication data from the shared memory may be notified by a notification signal from the processor 1 to the processor 2.

Step S22: Read Start Step The processor 2 reads the memory management register corresponding to the memory area in which the communication data has been written, and the memory use state is “1” and the communication processor ID is “2” which is its own processor ID. If they match and the final access type is write, it is determined that there is unreceived data. If it is determined that there is unreceived data, reading of communication data from the shared memory is started.
Alternatively, the processor 2 starts the reading operation when receiving the notification signal.

Step S23: Semaphore Acquisition Step and Semaphore State Recording Step When the processor 2 determines that there is unreceived data, it accesses the corresponding semaphore register, acquires the semaphore, and stores it in the semaphore register, as in the first embodiment. The semaphore acquisition is recorded, and the value of the semaphore register is reflected in the semaphore status summary register.

Step 24: Semaphore acquisition check step At the time of semaphore acquisition, semaphore acquisition may fail. That is, when the value read from the semaphore register is “1”, the processor 2 or the access control unit 541 waits for the release of the semaphore from the semaphore register by polling.

Step S25: Data read step (memory area access step)
After acquiring the semaphore, the processor 2 reads the communication data from the memory area where the communication data is recorded.
The processor 2 determines an address range in which valid data is stored based on the read start address and the write end address recorded in the read start address and end address of the address bits of the memory management register, and converts the data in this address range into data. read out. As a result, unnecessary access to a memory area in which writing has not been performed can be prevented, so that communication throughput can be improved.
When the data read by the processor 2 is completed, the processor 2 writes the read address to the read start address and the end address of the address bits of the memory management register, indicating that all the transmission data has been received. For example, it is determined that the start address and the end address where the data is recorded match the read start address and the end address, indicating that all the transmission data has been received.

Step S26: Semaphore Release Step When the reading of communication data by the processor 2 ends, the processor 2 writes "0" in the memory use state bit 517 of the memory management register, indicating that the inter-processor communication has been completed.
Further, the processor 2 writes “0” into the semaphore register corresponding to the accessed memory area, and releases the semaphore.
At this time, the value of the semaphore status bit is reflected on the value of the corresponding bit of the semaphore status summary register connected to the semaphore status bit by a signal line. When the semaphore status summary register is not connected to the semaphore status bit but is an independent register, the processor 2 or the access control unit 541 determines the bit of the semaphore status summary register 531 corresponding to the semaphore register whose semaphore is released. Is rewritten to “0”.
If the memory status summary register is an independent register without being connected to the memory use status bit, the processor 2 or the access control unit 541 rewrites the bit of the memory status summary register 352 to “0”.
Thereby, the receiving process of the processor 2 is completed.

*** Explanation of effect of embodiment ***
According to the present embodiment, since the memory status summary register 532 that can confirm the status of a plurality of semaphore registers by one access is provided, the access time to the shared memory can be reduced.
In addition, a memory management register that records the access history and state of the memory area from the processor to the memory area by software or hardware is provided, and by enabling access from a plurality of processors, it is possible to confirm and control the access status of the communicating processor. The communication throughput can be improved using a shared memory that can be accessed from a plurality of processors.

Embodiment 3 FIG.
In this embodiment, points different from Embodiments 1 and 2 will be mainly described.

*** Configuration description ***
A system including the shared memory control circuit 50 according to the third embodiment of the present invention will be described with reference to FIG.
As in the first embodiment, as shown in FIG. 9, semaphore registers 501, 502, 503, and 504 and semaphore state summary registers 531 corresponding to memory areas 521, 522, 523, and 524 are provided.
Further, the shared memory control circuit 50 includes a memory control summary register 533 that records whether a plurality of memory areas can be used and a memory control unit 542 that stops the operation of the memory area recorded as unusable in the memory control summary register 533. Are provided.

As shown in FIG. 10, a memory control status bit 519 indicating whether a memory area is available is provided in the least significant bit of the memory management register. When the memory control status bit 519 is “0”, the corresponding memory area is unusable, and when the bit is “1”, the corresponding memory area is usable. The memory use status bit 517 is a flag bit indicating whether the memory area obtained by dividing the shared memory 520 can be used. Here, that the memory area is usable means that the power and the clock are normally supplied to the corresponding memory area, and the memory area can be written and read.
As shown in FIG. 10, the memory control summary register 533 is an N-bit register in which the values of the memory use state bits 517 are extracted and arranged. The same value as the value of the memory control status bit 519 of the memory management registers 511, 512, 513, 514 is recorded in order from the least significant bit to the most significant bit of the memory control summary register 533. The memory control summary register 533 can be read by a single access from the processor, and the processor can know the N memory usage states in one access, and need to access a plurality of memory management registers individually. Disappears.

  The memory control unit 542 controls availability of the memory area. The memory control unit 542 controls the operation or stop of the clock and the power supply / non-supply for each divided memory area. The memory control unit 542 may control only one of the operation or stop of the clock and the supply of power, or may control both of them.

*** Explanation of operation ***
A method of stopping operation of an unused memory area will be described with reference to FIG.
Step S31: Unused determination step The processor reads the memory status summary register 532 to indicate that the processor is unused, ie, there is no communication data in use (communication data is not stored or is stored. The memory area in which the communication data has been read by the communication destination processor is determined. Alternatively, the access control unit 541 or the memory control unit 542 may determine an unused memory area from the value of the memory status summary register 532 without using the processor.
This determination may be performed periodically, or may be performed each time the reception processing of the processor is completed.
Instead of referring to the memory status summary register 532, an unused memory area may be determined by referring to the memory control status bit 519 of the memory management register 510.

Step S32: Stop Step When the processor detects an unused memory area, the processor stops the clock of the unused memory area or shuts off the power supply via the memory control unit 542. Further, the access control unit 541 may stop the clock of the unused memory area or cut off the power supply via the memory control unit 542. Alternatively, the memory control unit 542 may stop the clock of the unused memory area or cut off the power. Thus, the operation of the unused memory area can be stopped, and the power consumption can be reduced.

Step S33: Stop Recording Step Further, the processor or the access control unit 541 writes “0” to the memory control status bit 519 of the memory management register corresponding to the memory area where the clock is stopped or the power supply is shut off. Further, the processor or the access control unit 541 writes “0” to a corresponding bit of the memory control summary register 533. This allows all processors to read from the memory control summary register 533 that the corresponding memory area is unusable, thereby preventing access to the unusable memory area.

  The memory area in which the processor or the access control unit 541 stops the operation may be a part or all of the unused memory areas. Alternatively, the number of unused memory areas may be a fixed number or a fixed rate.

A method of activating the stopped memory area will be described.
The memory area whose operation has been stopped can be restarted and made usable by supplying power and a clock.

<< Restart when all unused memory areas are stopped >>
A method of activating a memory area when all unused memory areas are stopped will be described with reference to FIG.
Step S41: Starting Step When an access to the semaphore register occurs while all the unused memory areas are stopped, the processor or the access control unit 541 restarts the memory area corresponding to the accessed semaphore register. And make it usable.
Step S42: Start Recording Step The processor or the access control unit 541 writes “1” in the memory control status bit 519 of the corresponding memory management register, and writes the memory control summary register of the memory control summary register connected to the memory control status bit by a signal line. The value of the memory control status bit is reflected in the value of the corresponding bit. When the memory control summary register is an independent register without being connected to the memory control status bit, the processor or the access control unit 541 writes “1” to a corresponding bit of the memory control summary register 533. Thus, the processor can read from the memory control summary register 533 that the corresponding memory area has become available, and the processor can start the operations described in the first and second embodiments.

<< Restart when a part of unused memory area is stopped >>
A method of activating a memory area when a part of the unused memory area is stopped will be described with reference to FIG.
Step S51: Step of selecting usable memory area When an access to the semaphore register occurs in a state where only a part of the unused memory area is stopped, the available memory being operated by the processor from the memory control summary register 533. Determine the existence of the area. If there is an available memory area, the processor starts using the shared memory by selecting an available and unused memory area from the memory status summary register 532.
As described above, the processor specifies the memory area by sequentially reading the values of the memory control summary register 533, the memory status summary register 532, and the semaphore status summary register 531. The processor specifies a memory area where power and clock are normally supplied, there is no communication data in use, and the semaphore is released, and the corresponding semaphore is obtained. As a result, the accessing processor can access the shared memory without controlling the clock operation and power supply of the shared memory.

Step S52: Startup Step Further, when the processor selects an available memory area and an unused memory area from the memory status summary register 532, the available memory area and the unused memory area Disappears or falls below a certain number. In this case, the processor or the access control unit 541 secures an unused memory area by restarting the stopped memory area.

Step S53: Start Recording Step The processor or the access control unit 541 writes “1” into the memory control status bit 519 of the corresponding memory management register, and writes the memory control summary bit of the memory control summary register connected to the memory control status bit by a signal line. The value of the memory control status bit is reflected in the value of the corresponding bit. When the memory control summary register is an independent register without being connected to the memory control status bit, the processor or the access control unit 541 writes “1” to a corresponding bit of the memory control summary register 533. Thus, the processor can read from the memory control summary register 533 that the corresponding memory area has become available, and the processor can start the operations described in the first and second embodiments.

*** Explanation of effect of embodiment ***
According to the present embodiment, since the memory state summary register 532 capable of controlling the operation of the shared memory is provided and the operation of the unused memory area is stopped, it is possible to reduce the power consumption. That is, by providing the memory status summary register 532 that stores the memory usage status determined from the access status to the memory, it is possible to determine the unused memory area and stop the power supply or stop the clock supply. Will be possible.

  According to the present embodiment, since the memory control summary register 533 capable of confirming the memory usage state of a plurality of memory areas by one access is provided, it is possible to reduce the access time to the shared memory.

*** Description of other configurations ***
The access control unit 541 is a unit that receives a processor instruction and processes the instruction. Therefore, in the first, second, and third embodiments, the operation of the processor can be regarded as the operation of the access control unit 541. All operations of the access control unit 541 of the first, second, and third embodiments may be executed by the processor.
The access control unit 541 and the memory control unit 542 can be realized by a processor, and can be realized by a combination of hardware, firmware, and software.
The shared memory can be realized by a random access memory, a cache memory, a fixed disk, an optical disk, or the like.
The registers described in the first, second, and third embodiments are storage elements that are used in the shared memory control circuit 50 to hold data, hold operation results, and hold execution states. The registers store data. A memory that can be read and written by a processor at high speed and with a small number of accesses may be used.

In the second embodiment, the semaphore state summary register 531 described in the first embodiment may not be provided. That is, the shared memory control circuit 50 may include only the semaphore register 500, the access control unit 541, the memory status summary register 532, the memory management register 510, and the shared memory 520.
Alternatively, only the semaphore register 500, the access control unit 541, the memory status summary register 532, and the shared memory 520 may exist.
Further, since the memory status summary register 532 has the same information as the memory usage status bit 517 of the memory management register 510, if the memory status summary register 532 is present, the memory usage status bit 517 of the memory management register 510 is not present. Is also good. Conversely, if the memory use status bit 517 of the memory management register 510 is present, the memory status summary register 532 may not be provided.

In the third embodiment, the semaphore status summary register 531, the semaphore register 500, and the memory management register 510 described in the first and second embodiments may not be provided. That is, the shared memory control circuit 50 may include only the access control unit 541, the memory status summary register 532, the memory control summary register 533, the memory control unit 542, and the shared memory 520.
Further, since the memory control summary register 533 has the same information as the memory control status bit 519 of the memory management register 510, if the memory control summary register 533 exists, the memory control status bit 519 of the memory management register 510 does not exist. Is also good. Conversely, if there is a memory control status bit 519 of the memory management register 510, the memory control summary register 533 may not be provided.

  Any two or all of the semaphore state summary register 531, the memory state summary register 532, and the memory control summary register 533 may be combined into one integrated summary register.

  10 processors, 20 processors, 30 processors, 40 buses, 50 shared memory control circuits, 100 multiprocessor systems, 500, 501, 502, 503, 504 semaphore registers, 509 semaphore status bits, 510, 511, 512, 513, 514 memory Management register, 517 memory use status bit, 518 memory access status bit, 519 memory control status bit, 520 shared memory, 521, 522, 523, 524 memory area, 531 semaphore status summary register, 532 memory status summary register, 533 memory control Summary register, 541 access control unit, 542 memory control unit.

Claims (6)

In a shared memory control circuit accessed by a plurality of processors,
Multiple memory areas,
A plurality of memory management registers provided corresponding to the plurality of memory areas and recording a use state of the memory area;
A memory status summary register for recording usage status of the plurality of memory areas ,
A shared memory control circuit , wherein the processor detects an unused memory area from the memory status summary register and accesses a semaphore register corresponding to the detected unused memory area to acquire a semaphore . In a shared memory control circuit accessed by a plurality of processors,
Multiple memory areas,
A plurality of memory management registers provided corresponding to the plurality of memory areas, the plurality of memory management registers recording a use state of the memory area;
With
The memory management register has, for a corresponding memory area, a memory access state bit for recording a use state of whether the memory area is in use or unused,
1. A last access type bit for recording the last access type to the memory area,
2. A last access processor bit that records the processor number of the processor that last accessed the memory area,
3. A communication ID bit for recording a processor number of a communication destination processor which is a destination of communication data;
4. A data identification bit for recording a data identification number of communication data,
5. Start address and end address of the memory area where the communication data is recorded, and, shared memory that have a least any one or more bits of the address bits to record the start address and end address of the memory area was read Control circuit.   In a shared memory control circuit accessed by a plurality of processors,
  Multiple memory areas,
  A plurality of memory management registers provided corresponding to the plurality of memory areas and recording a use state of the memory area;
  A memory status summary register for recording usage status of the plurality of memory areas;
With
  The memory management register has, for a corresponding memory area, a memory access state bit for recording a use state of whether the memory area is in use or unused,
1. A last access type bit for recording the last access type to the memory area,
2. A last access processor bit that records the processor number of the processor that last accessed the memory area,
3. A communication ID bit for recording a processor number of a communication destination processor which is a destination of communication data;
4. A data identification bit for recording a data identification number of communication data,
5. A shared memory control circuit having at least one of an address bit for recording a start address and an end address of a memory area in which communication data is recorded, and an address bit for recording a start address and an end address of a memory area from which data is read. In a shared memory control circuit accessed by a plurality of processors,
Multiple memory areas,
A memory status summary register for recording a usage status of the plurality of memory areas;
A memory control unit for stopping the operation of the memory area recorded as unused in the memory status summary register;
A memory control summary register that records a memory area stopped operating by the memory control unit ,
A shared memory control circuit , wherein the processor detects an unused memory area from the memory status summary register and accesses a semaphore register corresponding to the detected unused memory area to acquire a semaphore . In a shared memory control method in which a plurality of processors access a shared memory having a plurality of memory areas,
A use state recording step of recording a use state of a memory area in a plurality of memory management registers provided corresponding to the plurality of memory areas;
A management state recording step of recording a use state of the memory area in a memory state summary register;
Detecting an unused memory area from the memory status summary register, and accessing a semaphore register corresponding to the detected unused memory area to acquire a semaphore. An unused determination step of determining an unused memory area that is not used among the plurality of memory areas;
A stopping step of stopping the operation of the unused memory area determined in the unused determining step,
A stop recording step of recording, in the memory control summary register, a memory area whose operation has been stopped;
A selecting step of determining an available memory area by referring to the memory control summary register and selecting an available memory area;
The shared memory control method according to claim 5, further comprising: a starting step of determining a stopped memory area with reference to the memory control summary register and starting the stopped memory area.

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