JP6627916B2 - Multilayer ceramic capacitors - Google Patents

Description

  The present invention relates to a multilayer ceramic capacitor.

  In recent years, large-capacity and small-sized multilayer ceramic capacitors have been demanded. Such a multilayer ceramic capacitor is formed in a rectangular parallelepiped shape, for example, in which an inner ceramic layer (dielectric ceramic layer) and internal electrodes are alternately stacked, and an outer ceramic layer is disposed on the upper surface and the lower surface. And an external electrode is formed on both end surfaces of the ceramic body. Side margins are formed on both side surfaces of the ceramic body to prevent connection with external electrodes.

  As a method for manufacturing a multilayer ceramic capacitor as described above, a manufacturing method described in Patent Document 1 is disclosed. That is, in the method for manufacturing a multilayer ceramic capacitor, a plurality of ceramic green sheets each having a conductive film serving as an internal electrode formed on the surface are laminated to form a mother laminate. Is cut so that the conductive film is exposed on the side surface where no is formed. Then, a ceramic slurry to be a side margin portion is applied to both side surfaces to form a uniform side margin portion with little variation.

JP-A-61-248413

  However, in the manufacturing method of the multilayer ceramic capacitor described in Patent Document 1, the ceramic slurry used for forming the side margin portion is made of the same dielectric ceramic material as the ceramic slurry used for forming the inner ceramic layer. Have been. In the firing step of the method for manufacturing a multilayer ceramic capacitor, when firing is performed under the conditions for forming the ceramic layer for the inner layer, the voids increase inside the side margins, so that the moisture from the side margins passes through the voids. There is a problem that intrusion cannot be prevented and the reliability of the multilayer ceramic capacitor is reduced.

  Therefore, a main object of the present invention is to provide a multilayer ceramic capacitor in which a multilayer chip having a side margin portion can be sintered more densely and reliability is improved.

A multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor including a multilayer body including a plurality of stacked dielectric layers and a plurality of internal electrodes, and external electrodes electrically connected to the internal electrodes. The laminate has a first main surface and a second main surface facing each other in the laminating direction, a first side surface and a second side surface facing each other in a width direction perpendicular to the laminating direction, and a direction perpendicular to the laminating direction and the width direction. The plurality of internal electrodes are formed in a rectangular parallelepiped shape including a first end surface and a second end surface facing each other in the length direction, and the first internal electrode exposed at the first end surface, the first internal electrode, and a dielectric material. A second internal electrode exposed at the second end face so as to face through the body layer, wherein the plurality of external electrodes are formed so as to cover the first end face, and are electrically connected to the first internal electrode. First externally connected A second external electrode formed so as to cover the second end face and connected to the second internal electrode; When the region extending along the first side surface and the second side surface up to the main surface of the stacked body and where the first internal electrode and the second internal electrode are not present is defined as a side margin portion, the side margin portion is formed by the first margin of the stacked body. And a multilayer ceramic capacitor having an outer layer located on the second side surface and an inner layer located on the first and second internal electrode sides, wherein the thickness of the outer layer is larger than the thickness of the inner layer. It is.
Further, a multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor including a multilayer body including a plurality of stacked dielectric layers and a plurality of internal electrodes, and external electrodes electrically connected to the internal electrodes. Thus, the laminated body has a first main surface and a second main surface facing each other in the laminating direction, a first side surface and a second side surface facing each other in a width direction orthogonal to the laminating direction, and the laminating direction and the width direction. The plurality of internal electrodes are formed in a rectangular parallelepiped shape including a first end face and a second end face that are opposed to each other in an orthogonal length direction, and the plurality of internal electrodes are: a first internal electrode exposed at the first end face; And a second internal electrode exposed at the second end face so as to face through the dielectric layer, wherein the plurality of external electrodes are formed so as to cover the first end face, and the first internal electrode The first electrically connected to An external electrode and a second external electrode formed so as to cover the second end face and connected to the second internal electrode. If the region extending along the first side surface and the second side surface to the main surface of No. 2 and the first internal electrode and the second internal electrode do not exist is defined as a side margin portion, the side margin portion is It is composed of two layers, an outer layer located on each of the first and second side surfaces, and an inner layer located on the first and second internal electrode sides, and the thickness of the outer layer is larger than the thickness of the inner layer. , A multilayer ceramic capacitor.

According to the multilayer ceramic capacitor of the present invention, when a region where the first internal electrode and the second internal electrode are not present is defined as a side margin portion when the ceramic body is viewed from the laminating direction, the side margin portion has a multi-layer structure. By doing so, the infiltration of moisture from the side margin portion toward the inside of the ceramic body can be suppressed, so that the moisture resistance of the multilayer ceramic capacitor can be improved. Therefore, a multilayer ceramic capacitor having improved reliability can be provided.
Further, even when the side margin portion is formed in two layers, the inner portion on the internal electrode side and the outer portion on the side surface side of the ceramic body, the infiltration of moisture from the side margin portion toward the inside of the ceramic body is performed. Therefore, the moisture resistance of the multilayer ceramic capacitor can be improved.

  According to the present invention, a multilayer chip having a side margin portion can be sintered more densely, and a multilayer ceramic capacitor with improved reliability can be provided.

  The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments for carrying out the invention with reference to the drawings.

1 is a schematic perspective view showing an example of the appearance of a multilayer ceramic capacitor according to the present invention. FIG. 2 is an illustrative sectional view showing a section along line AA in FIG. 1. FIG. 2 is an illustrative sectional view showing a section along line BB in FIG. 1; It is explanatory drawing for demonstrating the manufacturing method of a laminated ceramic capacitor, (a) is the perspective view which showed typically the state which formed the conductive film on the ceramic green sheet, (b) is the conductive film. It is the perspective view which showed typically the state which piles up the ceramic green sheet in which was formed. FIG. 5 is a schematic perspective view illustrating an example of an appearance of a multilayer chip manufactured by the method for manufacturing a multilayer ceramic capacitor illustrated in FIG. 4.

  An example of the multilayer ceramic capacitor according to the present invention will be described. FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor as an example of the appearance of a multilayer ceramic capacitor including a ceramic body and external electrodes, and FIG. 2 is a cross-sectional view illustrating a cross section taken along line AA of FIG. FIG. FIG. 3 is an illustrative sectional view showing a section taken along line BB of FIG.

  The multilayer ceramic capacitor 10 according to the present embodiment generally includes a ceramic body 12 and external electrodes 40 and 42 formed on both end surfaces of the ceramic body 12, respectively.

  The size of the laminated ceramic capacitor 10 according to the present invention is such that the dimension in the length (L) direction, the dimension in the width (W) direction, and the dimension in the laminated (T) direction are, for example, 1.6 mm × 0.8 mm × 0. There are combinations of 0.8 mm, 1.0 mm × 0.5 mm × 0.5 mm, 0.6 mm × 0.3 mm × 0.3 mm, 0.4 mm × 0.2 mm × 0.2 mm.

  The ceramic body 12 is formed in a rectangular parallelepiped shape, and has a first end face 13 and a second end face 14 extending along the width (W) direction and the lamination (T) direction, and the length (L) direction and the lamination (T) direction. ) Direction, a first side surface 15 and a second side surface 16 extending along the direction, and a first main surface 17 and a second main surface 18 extending along the length (L) direction and the width (W) direction. Have. In the ceramic body 12, the first end face 13 and the second end face 14 face each other, the first side face 15 and the second side face 16 face each other, and the first main face 17 and the second Are opposed to each other. Further, the first side face 15 and the second side face 16 are orthogonal to the first end face 13 and the second end face 14, and the first main face 17 and the second main face 18 are formed by the first end face 13 And the first side surface 16. Further, it is preferable that the corners and the ridges of the ceramic body 12 are rounded.

  The ceramic body 12 includes a plurality of inner ceramic layers (dielectric ceramic layers) 20 and a plurality of first inner electrodes 22 and second inner electrodes 24 disposed at interfaces between the plurality of inner ceramic layers 20. The outer layer portions 28 and 30 in which the outer layer ceramic layers are disposed so as to sandwich the inner layer portion 26 in the laminating (T) direction, and the inner layer portion 26 and the outer layer portions 28 and 30 have widths ( Side margin portions 32 and 34 in which ceramic layers for side margins are disposed so as to be sandwiched in the direction W). In other words, the inner layer portion 26 is a region sandwiched between the first and second internal electrodes 22 and 24 disposed closest to the first main surface 17 or the second main surface 18. The side margin portions 32 and 34 are regions where the first internal electrode 22 and the second internal electrode 24 do not exist when the ceramic body 12 is viewed from the lamination (T) direction.

  The inner ceramic layer 20 is composed of, for example, a dielectric ceramic particle having a perovskite structure containing a perovskite compound containing Ba and Ti as a main component. Further, at least one of Si, Mg, and Ba is added as an additive to these main components, and the additive exists between the ceramic particles. The thickness of the inner ceramic layer 20 after firing is preferably 0.3 μm or more and 10 μm or less.

  The upper and lower outer layers 28, 30 are made of the same dielectric ceramic material as the inner ceramic layer 20, respectively. Note that the outer layer portions 28 and 30 may be made of a dielectric ceramic material different from the inner ceramic layer 20. It is preferable that the thickness of the outer layer portions 28 and 30 after firing is 15 μm or more and 40 μm or less.

  The first internal electrode 22 and the second internal electrode 24 face each other with the ceramic layer for inner layer 20 therebetween in the thickness direction. Capacitance is formed at a portion where the first internal electrode 22 and the second internal electrode 24 face each other with the ceramic layer for internal layer 20 interposed therebetween.

  The left end of the first internal electrode 22 is drawn out to the first end face 13 of the ceramic body 12 and is electrically connected to the external electrode 40. The right end of the second internal electrode 24 is drawn out to the second end face 14 of the ceramic body 12 and is electrically connected to the external electrode 42.

  The first and second internal electrodes 22, 24 are made of, for example, Ni, Cu, or the like. It is preferable that the thickness of the first and second internal electrodes 22 and 24 is 0.3 μm or more and 2.0 μm or less.

The side margin portions 32 and 34 have a two-layer structure including outer portions 32a and 34a located on the side surface of the ceramic body 12 and inner portions 32b and 34b located on the first and second internal electrodes 22 and 24 sides. is there. The side margins 32 and 34 are made of a dielectric ceramic material having a perovskite structure made of a main component such as BaTiO ₃ , for example. Further, at least one of Si, Mg, and Ba is added as an additive to these main components, and the additive exists between the ceramic particles. The thickness of the side margin portions 32 and 34 after firing is preferably 5 μm or more and 40 μm or less. In particular, the present invention works effectively when the thickness is 20 μm or less. Preferably, the thickness of the inner portions 32b and 34b is smaller than that of the outer portions 32a and 34a. Specifically, the thickness of the outer portions 32a and 34a is preferably 5 μm or more and 20 μm or less, and the thickness of the inner portions 32b and 34b is , And 0.1 μm or more and 20 μm or less. In addition, due to the difference in sinterability between the outer portions 32a and 34a and the inner portions 32b and 34b, it can be easily understood that the side margin portions 32 and 34 have a two-layer structure by using an optical microscope. Further, the side margin portions 32 and 34 may be not only two layers of the outer portions 32a and 34a and the inner portions 32b and 34b, but may be a plurality of layers.

  The thickness of the outer layer portions 28 and 30 or the thickness of the side margin portions 32 and 34 is set so that the ceramic body 12 is perpendicular to the plane composed of the lamination (T) direction and the width (W) direction. Polish so that the length becomes about 1/2, measure the length from the end of the internal electrode (including the end where the ceramic dielectric is diffused) to the outside every 10 layers, and from the average value Desired.

In the side margins 32 and 34, the gaps decrease from the inner part 32b to the outer part 32a and from the inner part 34b to the outer part 34a.
As described above, when sintering the laminated chip on which the side margin portions 32 and 34 are formed, even if the conditions for sintering the inner layer portion of the ceramic body 12 provided with the internal electrodes are provided, Since the voids can be reduced from the inside to the outside of the margins 32, 34, the infiltration of moisture from the side margins 32, 34 toward the inside of the ceramic body 12 is suppressed. The moisture resistance of the multilayer ceramic capacitor can be improved. Therefore, a multilayer ceramic capacitor having improved reliability can be provided.
Here, the void portion is a state where the space portion is mixed with a space or a portion where the glass is buried. The number of voids can be confirmed by taking an image of an area of 30 μm × 30 μm with a SEM at a magnification of 5,000 and counting.

  Further, the grain size, which is the particle size of the ceramic particles in the inner portions 32b and 34b of the side margin portions 32 and 34, is smaller than the grain size in the outer portions 32a and 34a, and the denseness is increased. In particular, at the ends of the first and second internal electrodes 22, 24 near the side margins 32, 34, the grain size is smaller than the grain size at the outer portions 32a, 34a.

The gap is formed by polishing the ceramic body 12 in the same manner as when measuring the thicknesses of the side margins 32 and 34, so that the outer dimensions of the multilayer ceramic capacitor 10 are, for example, 0.6 mm × 0.3 mm × 0.3 mm. In the case of, it can be observed by taking a SEM image at a magnification of 5,000 and counting points regarded as voids.
Further, SEM images are taken at a magnification of 20000 to 50,000 times, and the grains in the imaging range are selected and the average (for example, 50) of the sizes is calculated, thereby obtaining the grain sizes in the outer portions 32a and 34a and the inner portions 32b and 34b. The difference in size can be understood.

The amount of Ba as an additive between the inner ceramic layer 20 of the inner layer portion 26 and the ceramic particles of the outer portions 32a, 34a and the inner portions 32b, 34b of the side margin portions 32, 34 is as follows.
The inner ceramic layer 20 of the inner layer part 20 <the outer parts 32a, 34a <the inner parts 32b, 34b,
It is.
As described above, it is preferable that the side margin portion is formed in two layers of the inner portion on the internal electrode side and the outer portion on the side surface, and that the Ba content of the inner portion is larger than the Ba content of the outer portion. By doing so, the reliability of the multilayer ceramic capacitor having a side margin portion can be improved.
In other words, the content of Ba between the ceramic particles made of the ceramic dielectric decreases from the inside to the outside of the side margin portion of the ceramic body 12. Therefore, when sintering the laminated chip on which the side margin portions 32 and 34 are formed, even if the conditions for sintering the inner layer portion provided with the internal electrode in the ceramic body 12 are the side margin portion 32 , 34, by promoting the grain growth of the dielectric ceramic particles, it is possible to sinter more densely, so that the number of voids in the dielectric ceramic layer constituting the outside of the side margin portion is reduced. Therefore, intrusion of moisture from the side margin portions 32 and 34 toward the inside of the ceramic body 12 can be prevented.
The content of Ba as an additive between the ceramic particles of the side margin portions 32 and 34 is different. The difference in Ba content can be found by TEM analysis.

The content of Ba in the outer portions 32a, 34a and the inner portions 32b, 34b of the side margin portions 32, 34 is such that the molar ratio with respect to Ti: 1 mol is a center value,
The outer portions 32a and 34a have Ba greater than 1.000 and less than 1.020;
The inner portions 32b and 34b are larger than Ba: 1.020 and smaller than 1.040,
It is preferable that the ingredients are blended so that By doing so, the reliability of the multilayer ceramic capacitor having a side margin portion can be improved.

  Further, the ceramic body 12 is polished from the side margin portions 32, 34 side, and the respective powders obtained by polishing the outer portions 32a, 34a and the inner portions 32b, 34b are dissolved with acid to perform ICP emission spectroscopy. Thus, it can be confirmed that the above molar ratio is obtained in the outer portions 32a and 34a and the inner portions 32b and 34b.

  Further, in these ranges, it is preferable that the content of Ba between the ceramic particles of the inner portions 32b and 34b is more than 100% and less than 140% more than the outer portions 32a and 34a. By doing so, the reliability of the multilayer ceramic capacitor having a side margin portion can be improved.

  The external electrodes 40 and 42 are composed of electrode layers 40a and 42a containing Cu formed by baking and a first plating layer containing Ni for preventing solder erosion formed on the surfaces of the electrode layers 40a and 42a. It has a triple structure composed of 40b and 42b and second plating layers 40c and 42c containing Sn formed on the surfaces of the first plating layers 40b and 42b.

  In the multilayer ceramic capacitor 10 shown in FIG. 1, the gap decreases from the inside to the outside of the side margins 32 and 34. That is, in the multilayer ceramic capacitor shown in FIG. 1, the gaps in the outer portions 32a and 34a are smaller than those in the inner portions 32b and 34b of the side margins 32 and 34. Intrusion of moisture from 32, 34 toward the inside of the ceramic body 12 is suppressed, and the moisture resistance of the multilayer ceramic capacitor 10 can be improved.

  In the multilayer ceramic capacitor 10 shown in FIG. 1, the ceramic particles between the inner portions 32 b and 34 b of the side margin portions 32 and 34 extend from the inner portions 32 a and 34 a (that is, from the inside to the outside of the side margin portions 32 and 34). Ba has decreased. Further, Ba is diffused from the inner portions 32b and 34b to the inner ceramic layer 20 between the inner portions 32b and 34b and the ends of the first and second internal electrodes 22 and 24, so that the first and second inner layers are formed. In the vicinity of the side margin portions 32, 34 of the second internal electrodes 22, 24, the amount of Ba is large. Therefore, the grain growth of the ceramic particles at the end portions of the first and second internal electrodes 22 and 24 can be suppressed, and the reliability between the internal electrodes can be improved.

  On the other hand, in the multilayer ceramic capacitor 10 shown in FIG. 1, since Ba is small in the outer portions 32a and 34a of the side margin portions 32 and 34, the grain growth of the ceramic particles is promoted and the ceramic particles can be sintered more densely. Therefore, it becomes strong against the invasion of moisture from the outside.

  Next, a method for manufacturing the multilayer ceramic capacitor will be described. 4A and 4B are explanatory views for explaining a method for manufacturing a multilayer ceramic capacitor, and FIG. 4A is a perspective view schematically showing a state in which a conductive film is formed on a ceramic green sheet, and FIG. FIG. 3 is a perspective view schematically showing a state in which ceramic green sheets on which conductive films are formed are stacked. FIG. 5 is a schematic perspective view showing an example of an overview of a multilayer chip manufactured by the method for manufacturing a multilayer ceramic capacitor shown in FIG. The details will be described below.

(1) Formation of Ceramic Element First, a perovskite compound containing Ba and Ti is prepared as a dielectric ceramic material. A dielectric powder obtained from this dielectric ceramic material is mixed with at least one of Si, Mg, and Ba, an organic binder, an organic solvent, a plasticizer, and a dispersant in a predetermined ratio as an additive. A rally is created. The ceramic slurry is formed into a plurality of ceramic green sheets 50a (50b) on a resin film (not shown). The molding of the ceramic green sheet 50a (50b) is performed using, for example, a die coater, a gravure coater, a micro gravure coater, or the like.

  Next, as shown in FIG. 4A, a conductive paste for internal electrodes is printed in a stripe shape in the X direction on the surface of the ceramic green sheet 50a (50b), and dried to form the internal electrodes 22 (24). ) Is formed. As a printing method, various methods such as screen printing, inkjet printing, and gravure printing are used. The thickness of the conductive film 52a (52b) is preferably 1.5 μm or less.

  Subsequently, as shown in FIG. 4B, the plurality of ceramic green sheets 50a and 50b on which the conductive films 52a and 52b are printed are perpendicular to the printing direction (X direction) of the conductive films 52a and 52b. The layers are shifted in the direction (the width direction of the conductive films 52a and 52b: the Y direction) and stacked. Further, if necessary, a predetermined number of ceramic green sheets on which the conductive layers serving as the outer layer portions 28 and 30 are not formed on the upper and lower surfaces of the ceramic green sheets 50a and 50b serving as the inner layer portions 26 thus laminated. Stacked to obtain a mother laminate.

  Next, the obtained mother laminate is pressed. As a method for pressing the mother laminate, a method such as a rigid press or an isostatic press is used.

  Subsequently, the pressed mother laminate is cut into a chip shape, and a laminate chip 60 as shown in FIG. 5 is obtained. As a method for cutting the mother laminate, various methods such as press cutting, dicing, and laser are used.

Through the above steps, only one conductive surface 52a of the ceramic green sheet 50a is exposed on one end surface which is both end surfaces of the multilayer chip 60, and only the conductive film 52b of the ceramic green sheet 50b is exposed on the other end surface. It is an exposed surface.
The conductive film 52a of the ceramic green sheet 50a and the conductive film 52b of the ceramic green sheet 50b are exposed on both side surfaces of the multilayer chip 60.

(2) Formation of Side Margin Section Next, a side margin ceramic green sheet to be the side margin sections 32 and 34 is prepared. Hereinafter, this will be described in more detail.

  First, a perovskite compound containing Ba and Ti is prepared as a dielectric ceramic material. A dielectric powder obtained from this dielectric ceramic material is mixed with at least one of Si, Mg, and Ba, a binder resin, an organic solvent, a plasticizer, and a dispersant in a predetermined ratio as an additive. A rally is created.

  Here, the ceramic slurry to be the outer portions 32a, 34a of the side margin portions 32, 34 is adjusted such that the molar ratio of Ba is greater than Ba: 1.000 and less than 1.020 with respect to Ti: 1 mol. The ceramic slurry used as the inner portions 32b and 34b of the side margin portions 32 and 34 is adjusted such that the molar ratio of Ba is greater than Ba: 1.020 and less than 1.040 with respect to 1 mol of Ti.

  The amount of polyvinyl chloride (PVC) contained in the ceramic slurry that becomes the outer portions 32a and 34a of the side margin portions 32 and 34 is included in the ceramic slurry that becomes the inner portions 32b and 34b of the side margin portions 32 and 34. It is contained more than the amount of polyvinyl chloride (PVC).

  Further, as the solvent contained in the ceramic slurry that becomes the inner portions 32b and 34b of the side margin portions 32 and 34, an optimal solvent is appropriately selected in order to prevent a sheet attack on the ceramic green sheet for the outer portion. Further, the ceramic green sheet for the inner portion has a role of bonding to the multilayer chip 60.

  Then, the prepared ceramic slurry for forming the outer portions 32a and 34a of the side margin portions 32 and 34 is applied on the resin film, and dried to form a ceramic green sheet for the outer portion.

  Next, on the surface of the outer ceramic green sheet, the prepared ceramic slurry for forming the inner portions 32b and 34b of the side margin portions 32 and 34 is applied and dried to form an inner ceramic green sheet. As a result, a ceramic green sheet for a side margin having a two-layer structure is manufactured.

  Here, the thickness of the ceramic green sheet for the inner portion is formed to be smaller than the thickness of the ceramic green sheet for the outer portion. For example, the thickness of the outer ceramic green sheet is formed so that the thickness after firing is 5 μm or more and 20 μm or less, and the thickness of the inner ceramic green sheet is 0.1 μm or more and 20 μm or less after firing. It is formed so that it becomes. It is preferable that the ceramic green sheet for the outer part is thicker than the ceramic green sheet for the inner part. Further, an interface exists between the outer portions 32a, 34a and the inner portions 32b, 34b, and the stress applied to the multilayer ceramic capacitor 10 can be reduced by the interface.

  The ceramic green sheet for the side margin having the two-layer structure described above was produced by printing the ceramic green sheet for the inner portion on the surface of the ceramic green sheet for the outer portion. The ceramic green sheets for side margin having a two-layer structure may be manufactured by forming ceramic green sheets for use in advance and then bonding them together.

  Next, the ceramic green sheet for side margin is peeled from the resin film.

  Subsequently, one side or the other side of the laminated chip 60 where the conductive films 52a and 52b are exposed is pressed and punched toward the inner portion ceramic green sheet of the peeled side margin ceramic green sheet. Then, layers to be side margin portions 32 and 34 are formed. At this time, it is preferable that an organic solvent serving as an adhesive is applied to the side surface of the stacked chip 60 in advance.

  Next, the laminated chip 60 on which the layers to be the side margin portions 32 and 34 are formed is degreased under a predetermined condition in a nitrogen atmosphere, and then is subjected to a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere. And the sintered ceramic body 12 is formed.

  Next, external electrode paste containing Cu as a main component is applied and baked on both ends of the sintered ceramic body 12, respectively, and electrically connected to the first and second internal electrodes 22 and 24, respectively. The electrode layers 40a and 42a are formed. Furthermore, first plating layers 40b and 42b formed by Ni plating are formed on the surfaces of the electrode layers 40a and 42a, and second plating layers 40c and 42c formed by Sn plating are formed on the surfaces of the first plating layers 40b and 42b. Thus, external electrodes 40 and 42 are formed.

  As described above, the multilayer ceramic capacitor 10 shown in FIG. 1 is manufactured.

  The side margin portions 32 and 34 can also be formed by applying ceramic slurry for side margin to both side surfaces of the laminated chip 60 where the conductive films 52a and 52b are exposed.

  That is, the ceramic slurry to be the inner portions 32b and 34b is applied to both sides of the laminated chip 60 where the conductive films 52a and 52b are exposed, dried, and further, the ceramic slurry to be the outer portions 32a and 34a is applied. Is done.

  In this case, the thickness of the ceramic slurry that becomes the inner portions 32b and 34b or the thickness of the ceramic slurry that becomes the outer portions 32a and 34a can be adjusted by adjusting the amount of resin contained in each ceramic slurry. .

  Further, the side margin portions 32 and 34 are formed by masking both end surfaces of the laminated chip 60 with a resin or the like, dipping the laminated chip 60 as a whole into a ceramic slurry to be the inner portions 32b and 34b, and drying. Then, it may be formed by dipping in a ceramic slurry to be the outer portions 32a and 34a. In this case, the side margin portions 32 and 34 are formed in a two-layer structure so as to cover the outer layer portions 28 and 30.

(Experimental example)
1. Examples and Comparative Examples In the experimental examples, samples of the multilayer ceramic capacitors of the following examples and comparative examples were manufactured, and the multilayer ceramic capacitors were evaluated by a moisture resistance load test.

(Example)
In the example, the multilayer ceramic capacitor 10 shown in FIG. 1 was manufactured by the above-described method. In this case, the external dimensions of the multilayer ceramic capacitor 10 were 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height. In the embodiment, with respect to Ba as an additive in the side margin portions 32 and 34, the molar ratio of Ba to Ti: 1 mol is 1.020 for the outer portions 32a and 34a and 1.028 for the inner portions 32b and 34b. . The thickness of the side margin portions 32 and 34 was 20 μm, the thickness of the outer portions 32a and 34a was 16 μm, and the thickness of the inner portions 32b and 34b was 4 μm. The thickness of the inner ceramic layer 20 is 0.83 μm per layer, the thickness of each of the first and second internal electrodes 22 and 24 is 0.40 μm, and the outer layer portion 28 and the outer layer portion 30 have a thickness of 0.40 μm. Were each 25 μm in thickness. The numerical values of the thickness are all numerical values after firing. The number of laminated ceramic layers 20 for the inner layer was 280.

(Comparative example)
In the comparative example, a multilayer ceramic capacitor was manufactured under the same conditions as in the example except that the molar ratio of Ba to Ti: 1 mol was uniformly set to 1.020 for Ba as an additive in the side margin portion.

(Moisture load test)
Each sample of the example and the comparative example was subjected to a moisture resistance load test. The conditions of the humidity resistance load test were a relative humidity of 95%, a temperature of 40 degrees, and a rated voltage of 6.3 V. Then, the insulation resistance value of each sample was measured, and when the insulation resistance was degraded within 1.0 × 10 ⁶ [Ω], it was determined to be defective. For this moisture resistance load test, 36 samples of each of the example and the comparative example were prepared.

  As a result of the humidity resistance load test, 36 out of 36 samples were determined to be defective in the multilayer ceramic capacitor of the comparative example.

On the other hand, in the multilayer ceramic capacitor of the example, the number of samples determined to be defective was 0 out of 36 samples.
Therefore, in all of the examples, highly reliable multilayer ceramic capacitors were obtained for all the samples.

  It should be noted that the present invention is not limited to the above-described embodiment, but may be variously modified within the scope of the invention. Further, the thickness, the number of layers, the counter electrode area, and the outer dimensions of the ceramic layer of the ceramic electronic component are not limited to these.

DESCRIPTION OF SYMBOLS 10 Multilayer ceramic capacitor 12 Ceramic body 13 1st end surface 14 2nd end surface 15 1st side surface 16 2nd side surface 17 1st main surface 18 2nd main surface 20 Inner ceramic layer 22 1st inside Electrode 24 Second inner electrode 26 Inner layer part 28, 30 Outer layer part 32, 34 Side margin part 32a, 34a Outer part 32b, 34b Inner part 40, 42 External electrode 40a, 42a Electrode layer 40b, 42b First plating layer 40c , 42c Second plating layer 50a, 50b Ceramic green sheet 52a, 52b Conductive film 60 Laminated chip

Claims (12)

A multilayer ceramic capacitor including a stacked body including a plurality of stacked dielectric layers and a plurality of internal electrodes, and an external electrode electrically connected to the internal electrodes,
The laminate has a first main surface and a second main surface facing each other in the laminating direction, a first side surface and a second side surface facing each other in a width direction perpendicular to the laminating direction, and a direction perpendicular to the laminating direction and the width direction. Formed in a rectangular parallelepiped shape including a first end face and a second end face opposed in the length direction
The plurality of internal electrodes are a first internal electrode exposed on the first end face, and a second internal electrode exposed on the second end face so as to face the first internal electrode via a dielectric layer. Including an internal electrode,
The plurality of external electrodes are formed so as to cover the first end face, and are formed so as to cover a first external electrode electrically connected to the first internal electrode and the second end face. And a second external electrode connected to the second internal electrode,
In a cross section of the stacked body viewed from the stacking direction, the stacked body extends from the first main surface to the second main surface along the first side surface and the second side surface, and the first internal electrode and the second If the area where the internal electrode does not exist is the side margin part,
The side margin portion includes an outer layer located on the first and second side surfaces of the laminate, and an inner layer located on the first and second internal electrode sides, and a thickness dimension of the outer layer. Is a multilayer ceramic capacitor having a thickness larger than the thickness of the inner layer. A multilayer ceramic capacitor including a stacked body including a plurality of stacked dielectric layers and a plurality of internal electrodes, and an external electrode electrically connected to the internal electrodes,
The laminate has a first main surface and a second main surface facing each other in the laminating direction, a first side surface and a second side surface facing each other in a width direction perpendicular to the laminating direction, and a direction perpendicular to the laminating direction and the width direction. Formed in a rectangular parallelepiped shape including a first end face and a second end face opposed in the length direction
The plurality of internal electrodes are a first internal electrode exposed on the first end face, and a second internal electrode exposed on the second end face so as to face the first internal electrode via a dielectric layer. Including an internal electrode,
The plurality of external electrodes are formed so as to cover the first end face, and are formed so as to cover a first external electrode electrically connected to the first internal electrode and the second end face. And a second external electrode connected to the second internal electrode,
In a cross section of the stacked body viewed from the stacking direction, the stacked body extends from the first main surface to the second main surface along the first side surface and the second side surface, and the first internal electrode and the second If the area where the internal electrode does not exist is the side margin part,
The side margin portion includes two layers, an outer layer located on the first and second side surfaces of the laminate, and an inner layer located on the first and second internal electrode sides,
A multilayer ceramic capacitor, wherein a thickness dimension of the outer layer is larger than a thickness dimension of the inner layer.   3. The multilayer ceramic capacitor according to claim 1, wherein a dimension of the outer layer in a width direction is 5 μm or more and 20 μm or less. 4.   The multilayer ceramic capacitor according to claim 1, wherein a dimension of the inner layer in a width direction is 0.1 μm or more and 20 μm or less.   The multilayer ceramic capacitor according to claim 1, wherein a thickness of the dielectric layer is 0.3 μm or more and 10 μm or less.   3. The multilayer ceramic capacitor according to claim 1, wherein a thickness of the internal electrode is 0.3 μm or more and 2.0 μm or less. 4. 3. The side margin portion according to claim 1, wherein a ceramic slurry or a ceramic green sheet is attached to both side surfaces of the multilayer chip where the conductive film for the internal electrode is exposed. 4. Multilayer ceramic capacitors.
An inner layer portion including a plurality of the first internal electrodes and a plurality of the second internal electrodes disposed at an interface between the plurality of dielectric layers and the plurality of dielectric layers;
An outer layer portion disposed so as to sandwich the inner layer portion in the stacking direction,
The multilayer ceramic capacitor according to claim 1, comprising:   The multilayer ceramic capacitor according to claim 8, wherein the thickness of the outer layer portion is 15 µm or more.   The multilayer ceramic capacitor according to claim 8, wherein the thickness of the outer layer portion is 40 µm or less.   9. The multilayer ceramic capacitor according to claim 8, wherein the outer layer portion is made of the same dielectric ceramic material as a dielectric layer forming the inner layer portion.   The multilayer ceramic capacitor according to claim 8, wherein the outer layer portion is made of a dielectric ceramic material different from a dielectric layer forming the inner layer portion.

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