JP6614348B2 - Solar cell evaluation substrate and solar cell evaluation method - Google Patents

Description

  The present invention relates to a solar cell evaluation substrate and a solar cell evaluation method for evaluating the impurity diffusion concentration of an impurity diffusion layer in a solar cell.

  Conventionally, as a structure of a solar battery cell that achieves high photoelectric conversion efficiency, Patent Document 1 includes a p-type diffusion layer that is a p-type emitter layer on the light-receiving surface side of an n-type silicon substrate, and a BSF (Back There is disclosed a solar cell including a surface field layer in which the impurity concentration in the lower region of the electrode in the p-type diffusion layer is higher than the impurity concentration in other regions in the p-type diffusion layer. In the solar battery cell having the structure disclosed in Patent Document 1, the contact resistance between the lower region of the electrode and the electrode in the p-type diffusion layer can be reduced.

  On the other hand, in recent years, the grid electrode is also required to be thinned to 150 μm or less from the viewpoint of high photoelectric conversion efficiency. And in the photovoltaic cell which has a selective impurity diffused layer structure like the photovoltaic cell disclosed by patent document 1, in order to improve photoelectric conversion efficiency, the sheet resistance of the impurity diffused layer from which impurity concentration differs is evaluated. It is important to optimize it.

Japanese Patent No. 5379767

  However, when the electrode is thinned to about 150 μm or less, the impurity diffusion layer below the electrode also needs to be thinned. Due to the mechanism of the measuring instrument, the impurity diffusion below the electrode is required in the structure of the solar cell. There was a problem that it was difficult to measure the sheet resistance of the layer.

  The present invention has been made in view of the above, and it is possible to obtain a solar cell evaluation substrate capable of accurately measuring the sheet resistance of an impurity diffusion layer even when the impurity diffusion layer is thinned. Objective.

In order to solve the above-described problems and achieve the object, a solar cell evaluation substrate according to the present invention is provided on a first conductivity type semiconductor substrate, a first surface of the semiconductor substrate, and an evaluation target. A plurality of elongated grid impurity regions having a second conductivity type impurity at a first impurity concentration and a region corresponding to the shape of the grid electrode of the solar battery cell, and the first surface of the semiconductor substrate; A region between grid impurity regions adjacent in the width direction is provided with an inter-grid impurity region having a second conductivity type impurity having a second impurity concentration lower than the first impurity concentration. The solar cell evaluation substrate is provided on the first surface of the semiconductor substrate, has a size greater than or equal to the interval between the grid impurity regions, and has a second conductivity type impurity at a first impurity concentration. 1 impurity concentration evaluation region.

  The solar cell evaluation substrate according to the present invention has an effect that the sheet resistance of the impurity diffusion layer can be accurately measured even when the impurity diffusion layer is thinned.

The top view which looked at the photovoltaic cell concerning Embodiment 1 of this invention from the light-receiving surface side The top view which looked at the photovoltaic cell concerning Embodiment 1 of this invention from the back surface side facing a light-receiving surface. It is principal part sectional drawing which shows the structure of the photovoltaic cell concerning Embodiment 1 of this invention, and sectional drawing along the AA in FIG. The flowchart for demonstrating an example of the manufacturing method of the photovoltaic cell concerning Embodiment 1 of this invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the first embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the first embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the first embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the first embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the first embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the first embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the first embodiment of the present invention. The figure which shows an example of the application pattern of the n-type dopant containing paste in this Embodiment 1. The characteristic figure which shows the change of the sheet resistance of the light-receiving surface of the p-type silicon substrate after formation of the n-type impurity diffusion layer by the flow rate of the phosphorus oxychloride gas in the diffusion process Schematic diagram showing the measurement position on a p-type single crystal silicon substrate in a horizontally long thermal diffusion furnace Schematic diagram showing the principle of a 4-probe measuring instrument The schematic diagram which shows an example of the coating pattern of n-type dopant containing paste for confirming the sheet resistance of the 1st n-type impurity diffusion layer concerning Embodiment 1 of this invention The schematic diagram which shows an example of the coating pattern of n-type dopant containing paste for confirming the sheet resistance of the 1st n-type impurity diffusion layer concerning Embodiment 1 of this invention In the first embodiment of the present invention, two sets of processing substrates from the left in the thermal diffusion furnace are viewed from above in the case where the solar cell manufacturing and the production of the monitor wafer are simultaneously performed using the thermal diffusion furnace. Pattern diagram Schematic of the pattern of the impurity diffusion layer of the monitor wafer concerning Embodiment 1 of this invention Sectional drawing of the principal part around the 1st n-type impurity diffusion layer measurement area | region in the monitor wafer concerning Embodiment 1 of this invention Sectional drawing of the principal part of the periphery of the second n-type impurity diffusion layer measurement region in the monitor wafer according to the first embodiment of the present invention. 19 is an enlarged view of the main part of FIG. The figure which shows an example of the shape in the surface of the p-type single crystal silicon substrate of the 1n type impurity diffused layer measurement area | region and 2nd n type impurity diffused layer measurement area | region concerning Embodiment 1 of this invention The figure which shows the other example of the shape in the surface of the p-type single-crystal silicon substrate of the 1n type impurity diffusion layer measurement area | region and 2nd n type impurity diffusion layer measurement area | region concerning Embodiment 1 of this invention The figure which shows the other example of the shape in the surface of the p-type single-crystal silicon substrate of the 1n type impurity diffusion layer measurement area | region and 2nd n type impurity diffusion layer measurement area | region concerning Embodiment 1 of this invention The figure which shows the other example of the shape in the surface of the p-type single-crystal silicon substrate of the 1n type impurity diffusion layer measurement area | region and 2nd n type impurity diffusion layer measurement area | region concerning Embodiment 1 of this invention The figure which shows the other example of the shape in the surface of the p-type single-crystal silicon substrate of the 1n type impurity diffusion layer measurement area | region and 2nd n type impurity diffusion layer measurement area | region concerning Embodiment 1 of this invention The top view which looked at the photovoltaic cell concerning Embodiment 2 of this invention from the light-receiving surface side The top view which looked at the photovoltaic cell concerning Embodiment 2 of this invention from the back surface side facing a light-receiving surface. It is principal part sectional drawing which shows the structure of the photovoltaic cell concerning Embodiment 2 of this invention, and sectional drawing along the BB line in FIG. The flowchart for demonstrating an example of the manufacturing method of the photovoltaic cell concerning Embodiment 2 of this invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Cross-sectional view of relevant parts for explaining an example of the manufacturing process of the solar battery cell according to the second embodiment of the present invention. Sectional drawing which shows the structure of the photovoltaic cell concerning Embodiment 3 of this invention. The flowchart for demonstrating an example of the evaluation method of the photovoltaic cell concerning Embodiment 4 of this invention.

  Hereinafter, a solar cell evaluation substrate and a solar cell evaluation method according to embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. In the drawings shown below, the scale of each member may be different from the actual scale for easy understanding. The same applies between the drawings.

Embodiment 1 FIG.
First, a solar cell to which the solar cell evaluation substrate and the solar cell evaluation method according to the first embodiment is applied will be described. FIG. 1 is a plan view of a solar battery cell 1 according to a first embodiment of the present invention as viewed from the light receiving surface side. FIG. 2 is a plan view of the solar battery cell 1 according to the first exemplary embodiment of the present invention viewed from the back side facing the light receiving surface. FIG. 3 is a main part sectional view showing the configuration of the solar battery cell 1 according to the first embodiment of the present invention, and is a sectional view taken along line AA in FIG.

  Solar cell 1 is a crystalline solar cell whose outer shape in the plane direction has a square shape. In solar cell 1, n-type impurity diffusion is performed by diffusion of phosphorus, which is an n-type impurity element, on the light-receiving surface side of semiconductor substrate 2 made of p-type single crystal silicon having a square shape of 156 mm × 156 mm, that is, 156 mm square. The layer 3 is formed, and the semiconductor substrate 11 having a pn junction is formed. Hereinafter, the semiconductor substrate 2 may be referred to as a p-type single crystal silicon substrate 2. The semiconductor substrate 2 may be a p-type polycrystalline silicon substrate.

  A passivation film 6 on the n-type impurity diffusion layer made of a silicon nitride film as an insulating film is formed on the n-type impurity diffusion layer 3. Hereinafter, the passivation film 6 on the n-type impurity diffusion layer is referred to as the passivation film 6 on the n-type layer. By providing the n-type overlayer passivation film 6 on the n-type impurity diffusion layer 3, defects on the surface of the p-type single crystal silicon substrate 2 can be inactivated. The n-type upper passivation film 6 also functions as an antireflection film. The n-type upper passivation film 6 is not limited to a silicon nitride film, and an insulating film such as a silicon oxide film may be used.

  Here, in order to measure the sheet resistance of only the n-type impurity diffusion layer, the sheet resistance value when the n-type impurity diffusion layer is formed on the p-type silicon substrate by thermal diffusion may be measured. If an n-type impurity diffusion layer is formed on a p-type silicon substrate, no current flows between the p-type silicon substrate and the n-type impurity diffusion layer due to a pn junction. Therefore, if the sheet resistance of the n-type impurity diffusion layer is measured from the surface of the n-type impurity diffusion layer by the four-terminal method, the sheet resistance of only the n-type impurity diffusion layer can be measured. Hereinafter, an n-type impurity element is simply referred to as an n-type impurity.

  On the light-receiving surface side of the p-type single crystal silicon substrate 2, minute unevenness (not shown) constituting a texture structure for confining light is formed.

The n-type upper passivation film 6 is an insulating film having translucency. As the n-type upper passivation film 6, an aluminum oxide (Al ₂ O ₃ ) film having a thickness of 5 nm and a silicon nitride (SiN) film having a refractive index of 2.1 and a thickness of 80 nm are n-type impurity diffusion. The layers 3 are sequentially formed. The n-type upper passivation film 6 is not limited to an aluminum oxide (Al ₂ O ₃ ) film and a silicon nitride (SiN) film, but is an insulating material such as a silicon oxide (SiO ₂ ) film or a titanium oxide (TiO ₂ ) film. It may be formed by a film. In this solar cell 1, light L is incident from the n-type upper passivation film 6.

  In addition, a plurality of long and narrow n-type impurity diffusion layer upper grid electrodes 8 are arranged side by side on the light receiving surface side of the semiconductor substrate 11, and the n-type impurity diffusion layer upper bus that is electrically connected to the n-type impurity diffusion layer upper grid electrode 8. An electrode 9 is provided orthogonal to the grid electrode 8 on the n-type impurity diffusion layer. Hereinafter, the n-type impurity diffusion layer upper grid electrode 8 is referred to as an n-type layer upper grid electrode 8. The bus electrode 9 on the n-type impurity diffusion layer is referred to as the bus electrode 9 on the n-type layer. The n-type layer upper grid electrode 8 and the n-type layer upper bus electrode 9 are electrically connected to the n-type impurity diffusion layer 3 at the bottom portion.

  The n-type upper-layer grid electrode 8 has a width of about 50 μm or more and 150 μm or less, and is arranged in a number of 100 or more and 200 or less in parallel at predetermined intervals, and collects electricity generated inside the semiconductor substrate 11. Electricity. The n-type layer-top bus electrode 9 has a width of about 0.5 mm or more and 1.0 mm or less, and three or more and five or less pieces are arranged per solar cell, and the n-type layer-top grid The electricity collected by the electrode 8 is taken out to the outside. The n-type layer upper grid electrode 8 and the n-type layer upper bus electrode 9 constitute an n-type impurity diffusion layer upper electrode 7 as a light-receiving surface side electrode having a comb shape. Hereinafter, the n-type impurity diffusion layer upper electrode 7 is referred to as an n-type layer upper electrode 7. In the first embodiment, the number of n-type layer-top grid electrodes 8 is 100, the number of n-type layer-top bus electrodes 9 is four, the electrode width of the n-type layer-top grid electrode 8 is 50 μm, n The electrode width of the mold layer upper bus electrode 9 is 1.0 mm. In FIG. 1, the number of the n-type upper-layer grid electrodes 8 is reduced for the sake of illustration.

  And in the photovoltaic cell 1 concerning this Embodiment 1, two types of layers are formed as the n-type impurity diffusion layer 3, and the selective emitter structure is formed. That is, in the surface layer portion of the p-type single crystal silicon substrate 2 on the light-receiving surface side, the n-type impurity diffusion layer 3 is provided in the lower region of the n-type layer upper electrode 7 that is the light-receiving surface side electrode and in the region adjacent to the lower region. In FIG. 1, a high concentration impurity diffusion layer in which n-type impurities are uniformly diffused at a relatively high concentration, that is, a first n-type impurity diffusion layer 4 which is a low resistance diffusion layer is formed. Further, in the surface layer portion on the light receiving surface side of the p-type single crystal silicon substrate 2, the n-type impurity is relatively low in the n-type impurity diffusion layer 3 in the region where the first n-type impurity diffusion layer 4 is not formed. A second n-type impurity diffusion layer 5 is formed which is a low-concentration impurity diffusion layer uniformly diffused in concentration, that is, a high-resistance diffusion layer.

  Therefore, if the impurity diffusion concentration of the first n-type impurity diffusion layer 4 is the first diffusion concentration and the impurity diffusion concentration of the second n-type impurity diffusion layer 5 is the second diffusion concentration, the second diffusion concentration is the first diffusion concentration. It becomes smaller than the diffusion concentration. If the sheet resistance value of the first n-type impurity diffusion layer 4 is the first sheet resistance value and the sheet resistance value of the second n-type impurity diffusion layer 5 is the second sheet resistance value, the second sheet resistance value is It becomes larger than the sheet resistance value.

  In addition, on the back surface of the semiconductor substrate 11, a p-type impurity diffusion layer upper electrode 10 as a back surface side electrode is formed over the entire surface. Hereinafter, the p-type impurity diffusion layer upper electrode 10 is referred to as a p-type layer upper electrode 10.

  Below, the manufacturing method of the photovoltaic cell 1 concerning this Embodiment 1 is demonstrated. FIG. 4 is a flowchart for explaining an example of a method for manufacturing the solar battery cell 1 according to the first embodiment of the present invention. FIGS. 5-11 is principal part sectional drawing for demonstrating an example of the manufacturing process of the photovoltaic cell 1 concerning Embodiment 1 of this invention. 5 to 11 are cross-sectional views of relevant parts corresponding to FIG.

(Silicon substrate preparation process)
In step 1, a p-type single crystal silicon substrate 2 is prepared as a semiconductor substrate. The p-type single crystal silicon substrate 2 is manufactured by cutting and slicing a single crystal silicon ingot formed by a method such as a CZ (Czochralski) method to a desired external dimension and thickness using a cutting machine such as a band saw and a multi-wire saw. The In the first embodiment, a square p-type single crystal silicon substrate 2 having a thickness of about 180 μm and an outer dimension of 156 mm or more and 158 mm or less × 156 mm or more and 158 mm or less and having rounded chamfers at square corners is prepared. Is done. The outer shape of the p-type single crystal silicon substrate 2 is a square that is cut out by round chamfering of round corners R100 or more and R105 or less of a circle of 156 mm or more, 158 mm or less × 156 mm or more and 158 mm or less cut out from a cylindrical ingot. Is. The length of the diagonal line of the 156 mm square is about 220 mm. Therefore, the outer shape of the p-type single crystal silicon substrate 2 exhibiting a square of 156 mm square has a square shape with four corners of the square cut off by about 10 mm.

  The obtained p-type single crystal silicon substrate 2 is subjected to a specification evaluation as to whether various conditions such as thickness and outer dimensions satisfy predetermined specifications, and the substrate satisfying the specifications is used for manufacturing the solar battery cell 1. It is done.

(Surface cleaning, texture structure formation process)
In step 2, pyramidal fine irregularities are formed as a texture structure on the light receiving surface side surface of the p-type single crystal silicon substrate 2. For the formation of the texture structure, a chemical solution in which about 10 wt% or more and 15 wt% or less of isopropyl alcohol is mixed with an aqueous solution of sodium hydroxide (NaOH) of about 5 wt% or more and 10 wt% or less is used. The surface of the p-type single crystal silicon substrate 2 is anisotropically etched by immersing the p-type single crystal silicon substrate 2 in a chemical heated to about 80 ° C. or more and about 90 ° C. or less for about 15 to 20 minutes. Micro unevenness is formed on the entire surface of the single crystal silicon substrate 2.

  Here, a chemical solution in which isopropyl alcohol is mixed in an aqueous sodium hydroxide solution is used as an etching solution for forming a texture structure. However, it is commercially available for etching in an alkaline aqueous solution such as an aqueous sodium hydroxide solution or an aqueous potassium hydroxide (KOH) solution. You may use the chemical | medical solution with which this additive was added as an etching liquid. In this step, the p-type single crystal silicon substrate 2 is etched from about 5 μm to 10 μm from the substrate surface, so that the damage layer formed on the substrate surface at the time of slicing can be removed at the same time. 2 substrate cleaning is performed simultaneously. Note that the p-type single crystal silicon substrate 2 may be cleaned separately in advance.

(N-type dopant-containing paste application process)
In Step 3, an n-type dopant-containing paste 21 as a diffusion source-containing coating agent is shown in FIG. 5 in order to form the first n-type impurity diffusion layer 4 which is a high-concentration impurity diffusion layer in the n-type impurity diffusion layer 3. As described above, the p-type single crystal silicon substrate 2 is coated and formed on the first surface as the light receiving surface. The n-type dopant-containing paste 21 is printed in a comb shape corresponding to the shape of the n-type layer upper electrode 7 using a screen printing method. FIG. 12 is a diagram showing an example of an application pattern of the n-type dopant-containing paste 21 in the first embodiment. As shown in FIG. 12, the n-type dopant-containing paste 21 is printed with a grid pattern 23 corresponding to the n-type layer upper grid electrode 8 and a bus pattern 24 corresponding to the n-type layer upper bus electrode 9. The n-type dopant-containing paste 21 is not sublimated or burned out even at the thermal diffusion temperature in the first diffusion step of step 4 described later, that is, the heat treatment temperature, and is not acidic but is a neutral resin paste.

The main constituent material of the n-type dopant-containing paste 21 includes at least one kind of glass powder containing n-type impurities diffused with respect to the p-type single crystal silicon substrate 2 and at least one kind of solvent. The n-type dopant-containing paste 21 may contain other additives in consideration of applicability. The n-type impurity contained in the glass powder for diffusing the n-type impurity with respect to the p-type single crystal silicon substrate 2 is at least one element selected from P (phosphorus) and Sb (antimony). The glass powder containing at least one element selected from P (phosphorus) and Sb (antimony) as an n-type impurity includes at least one selected from P ₂ O ₃ , P ₂ O ₅ and Sb ₂ O ₃ N-type impurity-containing material, SiO ₂ , K ₂ O, Na ₂ O, Li ₂ O, BaO, SrO, CaO, MgO, BeO, ZnO, PbO, CdO, V ₂ O ₅ , SnO, ZrO ₂ , TiO ₂ and at least one glass component material selected from MoO ₃ . The n-type dopant-containing paste 21 is made into a paste by dissolving the glass powder in a solvent.

  On the first n-type impurity diffusion layer 4, an n-type upper layer electrode 7 is formed in a later step, and the first n-type impurity diffusion layer 4 and the n-type upper layer electrode 7 are brought into electrical contact. An arrangement error occurs when the n-type upper electrode 7 is formed. For this reason, the first n-type impurity diffusion layer 4 spreads outside the outer shape of the n-type layer upper electrode 7 at a position where the n-type layer upper electrode 7 is formed in the plane of the p-type single crystal silicon substrate 2. It has an outer shape and is formed in a larger shape than the n-type layer upper electrode 7.

  Specifically, the screen printing of the n-type dopant-containing paste 21 is performed using a screen printing plate in which the width of the opening is wider than that of the n-type layer upper electrode 7. When the formation width of the n-type layer upper electrode 7 is set to 50 μm, the width of the n-type dopant-containing paste 21 is set to 100 μm in consideration of misalignment when the n-type layer upper electrode 7 is formed.

  The n-type dopant-containing paste 21 has a width of 50 μm or more and 150 μm or less in a region where the n-type upper-layer grid electrode 8 is formed on one surface of the p-type single crystal silicon substrate 2, and the number of 100 or more and 200 or less. Is printed over the entire width of the substrate at intervals of 0.75 mm to 1.5 mm. Further, the n-type dopant-containing paste 21 has three widths of 0.5 mm or more and 1.5 mm or less in the region where the n-type upper-layer bus electrode 9 is formed on one surface of the p-type single crystal silicon substrate 2. The number of 5 or less is printed. In the first embodiment, 100 n-type dopant-containing pastes 21 having a width of 100 μm are printed in order to form a grid electrode formation region in which the n-type upper layer grid electrode 8 having a width of 50 μm is formed. Further, four n-type dopant-containing pastes 21 having a width of 1.2 mm are printed in order to form a bus electrode formation region in which the 1.0 mm-wide n-type upper bus electrode 9 is formed.

  After printing the n-type dopant-containing paste 21, a drying step for drying the n-type dopant-containing paste 21 is performed. If the drying speed of the n-type dopant-containing paste 21 is low after printing the n-type dopant-containing paste 21, the printed n-type dopant-containing paste 21 may bleed and a desired print pattern may not be obtained. For this reason, drying of the n-type dopant-containing paste 21 is preferably performed quickly, and it is preferable to dry the n-type dopant-containing paste 21 at a high temperature using a drying device such as an infrared heater.

  When terpineol is contained as a solvent in the n-type dopant-containing paste 21, it is preferable to dry the n-type dopant-containing paste 21 at a temperature of 200 ° C. or higher. Moreover, when ethyl cellulose is contained as a resin component in the n-type dopant-containing paste 21, it is preferable to dry the n-type dopant-containing paste 21 at a temperature of 400 ° C. or higher in order to burn the ethyl cellulose. Even when the n-type dopant-containing paste 21 is dried at a temperature lower than 400 ° C., there is no problem because ethyl cellulose can be combusted in the subsequent diffusion step.

(First diffusion process)
In step 4, after drying the n-type dopant-containing paste 21, the boat on which the p-type single crystal silicon substrate 2 is placed is put into a thermal diffusion furnace, and the heat of phosphorus, which is an n-type impurity, by the n-type dopant-containing paste 21. A first heat treatment is performed as a first diffusion step which is a diffusion step. This first diffusion process is the first stage of the two stages of continuous diffusion processes.

In the first diffusion step, an atmosphere in which an atmosphere gas such as nitrogen gas (N ₂ ), oxygen gas (O ₂ ), a mixed gas of nitrogen and oxygen (N ₂ / O ₂ ), and the atmosphere is circulated in the thermal diffusion furnace. Done in state. The flow rate of the atmospheric gas is not particularly limited. Further, the flow rate ratio of each atmosphere in the case of a mixed atmosphere is not particularly limited, and any flow rate may be used. As an example, the flow rate of the mixed gas of nitrogen and oxygen (N ₂ / O ₂ ) is N ₂ : 5.7 SLM, O ₂ : 0.6 SLM. That is, in the first diffusion step, phosphorus oxychloride (POCl ₃ ) is not used, and there is no diffusion source of phosphorus as an n-type impurity other than the n-type dopant-containing paste 21. Therefore, in the first diffusion step, phosphorus is diffused from the n-type dopant-containing paste 21 into the p-type single crystal silicon substrate 2 in an atmosphere that does not contain phosphorus, which is a dopant element. A 1n type impurity diffusion layer 4 is formed.

  The first diffusion step is performed at a temperature of 870 ° C. or higher and 940 ° C. or lower and held for about 5 minutes or longer and 10 minutes or shorter. Therefore, thermal diffusion of phosphorus, which is an n-type impurity, is performed only in the lower part of the region where the n-type dopant-containing paste 21 is printed in the p-type single crystal silicon substrate 2. Thereby, diffusion of phosphorus, which is an n-type impurity, is performed only in a region extending outside the outer shape of the formation region of the n-type upper electrode 7 in the plane of the p-type single crystal silicon substrate 2.

  By this first diffusion step, phosphorus, which is an n-type impurity, has a relatively high concentration from the n-type dopant-containing paste 21 to the lower region of the printing region of the n-type dopant-containing paste 21 on the surface of the p-type single crystal silicon substrate 2. Then, the first n-type impurity diffusion layer 4 is formed as shown in FIG. The first n-type impurity diffusion layer 4 is formed in a region extending outside the outer shape of the formation region of the n-type layer upper electrode 7 in the plane of the p-type single crystal silicon substrate 2. It becomes a lower region of the upper electrode 7 and a region adjacent to the lower region.

  The first n-type impurity diffusion layer 4 is formed in a comb shape with the same width as the printing width of the n-type dopant-containing paste 21. In the first embodiment, 100 first n-type impurity diffusion layers 4 with a width of 100 μm, which are grid electrode formation regions, are formed in a region where the n-type upper layer grid electrode 8 is formed. Further, four first n-type impurity diffusion layers 4 having a width of 1.2 mm, which are bus electrode forming regions, are formed in a region where the n-type upper bus electrode 9 is formed.

  In the first embodiment, by forming the first n-type impurity diffusion layer 4 using the n-type dopant-containing paste 21, the n-type impurities are diffused to the p-type single crystal silicon substrate 2 at a high concentration, and the sheet resistance is reduced. 20Ω / sq. Or more, 80Ω / sq. The first n-type impurity diffusion layer 4 is formed in the following range. That is, when an electrode material suitable for a high sheet resistance is used in a single emitter layer, the first n-type impurity diffusion layer 4 is 80 Ω / sq. Can be set. On the other hand, by adjusting various conditions such as the conditions of the n-type dopant-containing paste 21 and heat treatment conditions, 20 Ω / sq. The first n-type impurity diffusion layer 4 having a sheet resistance of a certain degree can be realized.

Further, when thermal diffusion is performed in the first diffusion step under the condition containing oxygen gas (O ₂ ), the n-type dopant-containing paste 21 on the surface of the p-type single crystal silicon substrate 2 is not printed. A thin oxide film (not shown) is formed on the surface due to the influence of thermal diffusion.

(Second diffusion process)
In step 5, after completion of the first diffusion step, a second heat treatment is subsequently performed as a second diffusion step, which is a thermal diffusion step of phosphorus, which is an n-type impurity by phosphorus oxychloride (POCl ₃ ). That is, the p-type single crystal silicon substrate 2 is not taken out of the thermal diffusion furnace, and the second diffusion process is continuously performed in the same thermal diffusion furnace after the first diffusion process. This second diffusion process is the second stage of the two-stage continuous diffusion process.

The second diffusion step is performed in the presence of phosphorus oxychloride (POCl ₃ ) gas in a thermal diffusion furnace. That is, in the first diffusion step, thermal diffusion was performed under an atmospheric condition that does not contain phosphorus oxychloride (POCl ₃ ), but in the second diffusion step, phosphorus oxychloride (as a diffusion source of phosphorus that is an n-type impurity) Thermal diffusion is performed under atmospheric conditions including POCl ₃ ). The flow rate of the atmospheric gas is not particularly limited, and may be set as appropriate according to various conditions such as diffusion concentration, diffusion temperature, and diffusion time. Further, the second diffusion step is performed by lowering the temperature from 870 ° C. or higher and 940 ° C. or lower of the first diffusion step to 800 ° C. or higher and 840 ° C. or lower and maintaining the temperature for about 10 minutes or longer and 20 minutes or shorter. .

  By this second diffusion step, the second concentration which is relatively lower than that of the first n-type impurity diffusion layer 4 in the region other than the printing region of the n-type dopant-containing paste 21 on the surface of the p-type single crystal silicon substrate 2. As shown in FIG. 7, the second n-type impurity diffusion layer 5 is formed by thermally diffusing phosphorus, which is an n-type impurity, at the diffusion concentration. The second n-type impurity diffusion layer 5 serves as a light receiving surface on which light enters in the solar battery cell 1. In addition, a phosphosilicate glass (PSG) layer, which is a glassy layer 22 deposited on the surface during the diffusion process, is formed on the surface of the p-type single crystal silicon substrate 2 immediately after the second diffusion step. Yes.

  Further, in the first diffusion step, phosphorus, which is an n-type impurity, is contained in the glass powder of the n-type dopant-containing paste 21, so that phosphorus is not easily volatilized even during the first heat treatment. For this reason, generation | occurrence | production of volatilization gas suppresses that phosphorus is spread | diffused in the area | region where the n-type dopant containing paste 21 is not apply | coated in the surface of the p-type single crystal silicon substrate 2. FIG. Thus, since the second n-type impurity diffusion layer 5 is formed only by vapor phase diffusion in the second diffusion step, the phosphorus concentration in the second n-type impurity diffusion layer 5 is kept low, and the second n-type impurity diffusion layer 5 sheet resistance of 100 Ω / sq. It becomes possible to make the degree.

(Pn separation step)
In step 6, pn separation is performed to electrically insulate the n-type upper layer electrode 7 and the p-type upper layer electrode 10 which are electrodes formed in a later step. Since n-type impurity diffusion layer 3 is uniformly formed on the surface of p-type single crystal silicon substrate 2, the surface and the back surface of p-type single crystal silicon substrate 2 are in an electrically connected state. For this reason, when the n-type layer upper electrode 7 and the p-type layer upper electrode 10 are formed as they are, the n-type layer upper electrode 7 and the p-type layer upper electrode 10 are electrically connected. In order to cut off this electrical connection, the second n-type impurity diffusion layer 5 formed in the end face region of the p-type single crystal silicon substrate 2 is removed by dry etching to perform pn separation. As another method for removing the influence of the second n-type impurity diffusion layer 5, there is also a method of performing end face separation with a laser.

(Glassy layer removal process)
In step 7, as shown in FIG. 8, the impurity-containing layer containing impurities formed on p-type single crystal silicon substrate 2 is removed. Specifically, the p-type single crystal silicon substrate 2 is dipped in a 10% hydrofluoric acid solution for about 360 seconds, and then washed with water. Thereby, the n-type dopant containing paste 21 and the vitreous layer 22 formed on the surface of the p-type single crystal silicon substrate 2 are removed. As a result of the above process, a selective impurity diffusion layer structure composed of the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5 on the surface side of the p-type single crystal silicon substrate 2 is obtained as the n-type impurity diffusion layer 3. It is done. The semiconductor substrate 2 made of p-type silicon as the first conductivity type layer and the n-type impurity diffusion layer 3 as the second conductivity type layer formed on the light receiving surface side of the semiconductor substrate 2 constitute a pn junction. The obtained semiconductor substrate 11 is obtained.

(N-type layer passivation film forming step)
In step 8, on the surface of the semiconductor substrate 11 where the n-type impurity diffusion layer 3 is formed, as shown in FIG. 9, an n-type upper passivation film 6 that is an n-type impurity diffusion layer side passivation film is formed. The n-type upper passivation film 6 is a silicon nitride (SiN) film having a refractive index of 2.1 and a film thickness of 80 nm using a plasma CVD method and using a mixed gas of silane gas and ammonia (NH ₃ ) gas as a raw material. A film is formed. Further, the passivation film 6 on the n-type layer may be formed by other methods such as a vapor deposition method or a thermal CVD method.

(Electrode formation process)
In step 9, as shown in FIG. 10, the electrode is printed and dried by screen printing to form a dry electrode. First, an Ag-containing paste 7a, which is an electrode material paste containing Ag powder and glass frit, is applied onto the passivation film 6 on the n-type layer on the surface side of the semiconductor substrate 11 by screen printing. Thereafter, the Ag-containing paste 7a is dried, whereby the n-type upper layer electrode 7 in a dry state to be the n-type impurity diffusion layer upper electrode is formed. The Ag-containing paste 7a is dried at 250 ° C. for 5 minutes.

  Here, the n-type layer upper electrode 7 is formed at a position enclosed in the region of the first n-type impurity diffusion layer 4 having a width of 100 μm and a width of 1.2 mm formed in the first diffusion step of the step 4. For this reason, the n-type upper electrode 7 needs to be formed in alignment with the first n-type impurity diffusion layer 4. In the first embodiment, the passivation film on the n-type layer is formed after the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5 are formed by the first diffusion process and the second diffusion process which are two-stage continuous diffusion processes. The surface side of the semiconductor substrate 11 on which the 6 is formed is photographed with a dedicated camera that can visualize the first n-type impurity diffusion layer 4. Thereby, the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5 are identified. In this way, by recognizing the position of the region of the first n-type impurity diffusion layer 4 and determining the printing position of the Ag-containing paste 7a, the Ag-containing paste 7a is printed on the first n-type impurity diffusion layer 4 with high accuracy. It becomes possible.

  Next, an Al-containing paste 10a, which is an electrode material paste containing Al powder and glass frit, is applied to the entire back surface of the semiconductor substrate 11 by screen printing. Thereafter, the Al-containing paste 10a is dried, whereby the p-type layer upper electrode 10 in a dry state to be the p-type impurity diffusion layer upper electrode is formed. The Al-containing paste 10a is dried at 250 ° C. for 5 minutes.

(Electrode firing process)
In step 10, the electrode material paste printed and dried on the light-receiving surface side and the back surface side of the semiconductor substrate 11 is fired simultaneously. Specifically, the semiconductor substrate 11 is introduced into a firing furnace, and a short-time heat treatment is performed in an air atmosphere at a peak temperature of about 600 ° C. to 900 ° C., for example, 800 ° C. for 3 seconds. Thereby, the resin component in the electrode material paste disappears. On the light receiving surface side of the semiconductor substrate 11, the silver material is n-type while the glass material contained in the Ag paste 7 a of the n-type layer upper electrode 7 is melted and penetrates the passivation film 6 on the n-type layer. It contacts with the silicon of the impurity diffusion layer 3 and resolidifies. As a result, as shown in FIG. 11, an n-type upper-layer grid electrode 8 and an n-type upper-layer bus electrode 9 as the n-type upper-layer electrode 7 are obtained. Is ensured.

  On the back side of the semiconductor substrate 11, the glass material contained in the Al-containing paste 10a of the p-type upper electrode 10 melts and reacts with silicon to resolidify. As a result, the p-type layer upper electrode 10 is obtained as shown in FIG. 11, and electrical conduction between the p-type layer upper electrode 10 and the silicon of the semiconductor substrate 11 is ensured.

  By performing the steps as described above, the solar battery cell 1 according to the first embodiment shown in FIGS. 1 to 3 can be manufactured. In addition, the order of arrangement of the paste, which is an electrode material, on the semiconductor substrate 11 may be switched between the light receiving surface side and the back surface side.

In the manufacturing method of the solar cell 1 according to the first embodiment described above, the n-type dopant-containing paste 21 is applied to the p-type single crystal silicon substrate 2, and in addition to the n-type dopant-containing paste 21, phosphorus, which is a dopant, is applied. The first n-type impurity diffusion layer 4 is formed by performing the first diffusion step without the diffusion source. Then, after the first diffusion step, the p-type single crystal silicon substrate 2 is not taken out of the thermal diffusion furnace in which the first diffusion step is performed, and the second is performed using phosphorus oxychloride (POCl ₃ ) as a phosphorus diffusion source. The second n-type impurity diffusion layer 5 is formed by performing the diffusion process in the same thermal diffusion furnace. That is, the two-stage continuous diffusion process of the first diffusion process using the n-type dopant-containing paste 21 and the second diffusion process using phosphorus oxychloride (POCl ₃ ) is the thermal diffusion of the p-type single crystal silicon substrate 2. Performed without removal from the furnace.

  Thereby, the diffusion process of phosphorus can be efficiently performed, and the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5 can be easily formed separately to form the selective impurity diffusion layer structure. Thereby, an n-type impurity diffusion layer having a selective impurity diffusion layer structure can be formed easily and at low cost without performing a plurality of complicated steps.

That is, in the method for manufacturing a solar cell described above, as a method for forming a selective impurity diffusion layer structure having different impurity concentrations in the lower region of the electrode and other regions, an n-type impurity containing an n-type impurity is used. Thermal diffusion using the dopant-containing paste 21 is performed. In this case, the n-type dopant-containing paste 21 is printed on the lower region of the electrode in the p-type single crystal silicon substrate 2 and a thermal diffusion process is performed, followed by a thermal diffusion process using phosphorus oxychloride (POCl ₃ ). Thus, a high-concentration n-type impurity diffusion layer can be formed in the lower region of the electrode, and an n-type impurity diffusion layer having a lower concentration than the lower region of the electrode can be formed in the other region.

  As described above, by using the n-type dopant-containing paste 21, the n-type impurity diffusion layer 3 having a selective impurity diffusion layer structure can be easily formed at low cost. Here, matters to be noted in the diffusion process will be described.

In the second diffusion step, when adjusting the diffusion conditions for obtaining a desired light-receiving surface sheet resistance value on the light-receiving surface side of the p-type single crystal silicon substrate 2, it is necessary to pay attention to the following matters. That is, when phosphorus is diffused by phosphorus oxychloride (POCl ₃ ) on the p-type single crystal silicon substrate 2 on which the n-type dopant-containing paste 21 is printed, the diffusion conditions such as temperature, pressure, and flow rate are set to n When the n-type impurity diffusion layer 3 is formed on the p-type single crystal silicon substrate 2 only by diffusion using phosphorus oxychloride (POCl ₃ ) in which the type dopant containing paste 21 is not used, the second n-type impurity diffusion layer 5 The n-type impurity concentration is lowered, and the sheet resistance of the light receiving surface after the formation of the n-type impurity diffusion layer 3 is increased.

The reason is that phosphorus oxychloride (POCl ₃ ) is consumed by the n-type dopant-containing paste 21 printed on the p-type single crystal silicon substrate 2 during the second diffusion step. Therefore, in the second diffusion step, an amount of phosphorus oxychloride (POCl ₃ ) proportional to the number of p-type single crystal silicon substrates 2 put in the thermal diffusion furnace is consumed, so that the diffusion conditions of the second diffusion step are This point needs to be noted when making adjustments.

As a method for preventing the sheet resistance of the light receiving surface after the formation of the n-type impurity diffusion layer 3 from increasing as described above, the following method can be cited. Ie, n-type dopant-containing paste 21 is not printed on the silicon substrate, as compared with the time of diffusion only by phosphorus oxychloride (POCl _3), phosphorus oxychloride per same processing quantity (POCl ₃₎ to increase the flow rate of the gas .

FIG. 13 is a characteristic diagram showing a change in sheet resistance of the light-receiving surface of the p-type single crystal silicon substrate 2 after the formation of the n-type impurity diffusion layer 3 due to the flow rate of phosphorus oxychloride (POCl ₃ ) gas during the diffusion process. . In FIG. 13, the horizontal axis indicates the arrangement position of the p-type single crystal silicon substrate 2 in the heat diffusion furnace 31 provided horizontally, and the vertical axis indicates the sheet of the light receiving surface of the p-type single crystal silicon substrate 2 after the diffusion process. Resistance [Ω / sq. ] Is shown. FIG. 14 is a schematic diagram showing a measurement position on the p-type single crystal silicon substrate 2 in the heat diffusion furnace 31 provided in a horizontally long shape. The numbers on the p-type single crystal silicon substrate 2 in FIG. 14 correspond to the numbers on the horizontal axis in FIG. 13, that is, the measurement positions.

The mark ◇ in FIG. 13 indicates data of Sample 1 in which phosphorus is diffused only with phosphorus oxychloride (POCl ₃ ) on the p-type single crystal silicon substrate 2 on which the n-type dopant-containing paste 21 is not printed. ing. In FIG. 13, Δ marks indicate that phosphorus is formed on the p-type single crystal silicon substrate 2 on which the n-type dopant-containing paste 21 is printed by the two-stage continuous diffusion process by the first diffusion process and the second diffusion process. Data of sample 2 subjected to diffusion is shown. The flow rate of phosphorus oxychloride (POCl ₃ ) in the second diffusion step of sample 2 is the same as that of sample 1. The circles in FIG. 13 indicate the sample 3 in which phosphorus was diffused in the first diffusion step and the second diffusion step on the p-type single crystal silicon substrate 2 on which the n-type dopant-containing paste 21 was printed. Data are shown. The flow rate of phosphorus oxychloride (POCl ₃ ) in the second diffusion step of sample 3 is larger than that in sample 1.

In this thermal diffusion furnace 31, phosphorus oxychloride (POCl ₃ ) gas, which is a diffusion gas for diffusing phosphorus into the p-type single crystal silicon substrate 2, is introduced from the left end side in FIG. The diffusion gas flows and is exhausted from the right end side. The p-type single crystal silicon substrate 2 has a plate surface parallel to the central axis of the quartz tube and the flow direction of the diffusion gas, and a set of several tens of substrates arranged in a horizontal direction with a predetermined interval. Are arranged vertically. A plurality of sets are arranged at predetermined intervals in the extending direction of the thermal diffusion furnace 31. Here, hundreds of p-type single crystal silicon substrates 2 are put into the thermal diffusion furnace 31 for continuous diffusion. However, for the purpose of illustration, in FIGS. 13 and 14, seven sets of p-type single crystal silicon substrates 2 from the left end in the thermal diffusion furnace 31 are shown.

  By arranging the p-type single crystal silicon substrate 2 in parallel with the flow direction of the diffusion gas, the diffusion gas is generated between adjacent p-type single crystal silicon substrates 2 in the direction perpendicular to the plate surface of the p-type single crystal silicon substrate 2. There is an effect that it becomes easy to flow. As a result, the efficiency is higher than when a plurality of p-type single crystal silicon substrates 2 are arranged in a state in which the plate surface of the p-type single crystal silicon substrate 2 is perpendicular to the flow direction of the diffusion gas and at a predetermined interval. The diffusion gas can be brought into contact with the p-type single crystal silicon substrate 2 in a good and uniform manner, and variations in the diffusion amount of phosphorus for each p-type single crystal silicon substrate 2 can be suppressed.

As can be seen from FIG. 13, the flow rate of phosphorus oxychloride (POCl ₃ ) in the second diffusion step is the same as that in the case of sample 1, and the two-stage continuous diffusion step by the first diffusion step and the second diffusion step is performed. In the case of the sample 2 performed, the sheet resistance of the light-receiving surface of the p-type single crystal silicon substrate 2 after the formation of the n-type impurity diffusion layer 3 increases as the flow direction of phosphorus oxychloride (POCl ₃ ) increases. . This is because phosphorus oxychloride (POCl ₃ ) is consumed by the n-type dopant-containing paste 21 printed on the p-type single crystal silicon substrate 2 during the second diffusion step.

On the other hand, Sample _{3 in which} the flow rate of phosphorus oxychloride (POCl ₃ ) in the second diffusion step was increased from that in Sample 1 and the two-stage continuous diffusion step by the first diffusion step and the second diffusion step was performed. In this case, the sheet resistance of the light receiving surface hardly changes in all the p-type single crystal silicon substrates 2, and a uniform sheet resistance value is obtained. Therefore, by increasing the flow rate of the phosphorus oxychloride (POCl ₃ ) gas in the second diffusion process in the two-stage continuous diffusion process, the sheet resistance on the light receiving surface after the formation of the n-type impurity diffusion layer 3 can be stabilized. A highly uniform value can be obtained.

Examples of such increase of the flow rate of phosphorus oxychloride (POCl ₃₎ gas in the second diffusion step, phosphorus oxychloride to the p-type single crystal silicon substrate 2 n-type dopant-containing paste 21 is not applied (POCl ₃ ) Only when the flow rate condition is N ₂ : 5.8 SLM, O ₂ : 0.9 SLM, POCl ₃ : 1.5 SLM, the p-type single layer coated with the n-type dopant-containing paste 21 is used. The flow rate conditions that are the diffusion conditions in the second diffusion step for the crystalline silicon substrate 2 may be N ₂ : 5.8 SLM, O ₂ : 0.9 SLM, POCl ₃ : 2.0 SLM. Here, the flow rate of phosphorus oxychloride (POCl ₃ ) gas in the case where 100 p-type single crystal silicon substrates 2 are collectively processed is shown.

Next, a printing pattern of the n-type dopant-containing paste 21 used in the first embodiment will be described. When performing diffusion of phosphorus, which is an n-type impurity, in the p-type single crystal silicon substrate 2 by the solar cell manufacturing method described above, in order to confirm whether the n-type impurity diffusion layer is formed at a desired concentration, The sheet resistance of the n-type impurity diffusion layer is measured. In general, in thermal diffusion using phosphorus oxychloride (POCl ₃ ), processing is performed using a quartz tube with 300 or more substrates inserted into one tube. At this time, it is desirable that the sheet resistance of the substrate does not depend on the position of the tube and the position of the substrate in the tube, but in reality, variation in sheet resistance occurs between the substrates and within the substrate. The variation in sheet resistance also depends on the target value, but as an example, the target value 60Ω / sq. On the other hand, about ± 10% is assumed between the substrates and within the substrates.

  In the case of a structure having a single impurity diffusion layer that does not make a difference in impurity concentration between the lower region of the electrode and other regions in the production of solar cells so far, the impurity diffusion layer on the light receiving surface In order to manage the diffusion conditions, the sheet resistance of the light receiving surface of an arbitrary substrate that actually becomes a solar battery cell should be evaluated. That is, in the case of an n-type impurity diffusion layer having a single impurity concentration that does not make a difference in impurity concentration between the lower region of the electrode and other regions, the substrate that will eventually become a solar cell In any part of the substrate, it is possible to confirm whether or not a desired design value is obtained, and it is a management target.

  On the other hand, when forming a selective impurity diffusion layer structure in which the impurity concentration is different between the lower region of the electrode and the other region, both the lower region of the electrode and the other region have a desired sheet resistance. It is structurally difficult to confirm whether or not the evaluation is performed on a substrate that finally becomes a solar battery cell. In the current solar battery cell, when the grid electrode width is 50 μm, the target width of the impurity diffusion layer in the lower region of the electrode is less than 100 μm.

  In general, the sheet resistance is measured by a sheet resistance measuring instrument using a four-probe method. As an example, the sheet resistance of the light-receiving surface of the substrate can be evaluated by the 4-probe method by using VR-70 manufactured by Kokusai Electric Eltech Co., Ltd., which is a 4-probe measuring instrument. The four-probe configuration of the four-probe measuring instrument requires that at least a 4 mm square or more impurity diffusion layer with the same specifications is required because four probes are linearly arranged at 1 mm intervals. However, the pattern of the impurity diffusion layer in the lower region of the electrode in the current solar cell has a width of about 100 μm, while the width of the impurity diffusion layer in which the impurity concentration in other regions other than the lower portion of the electrode is changed is less than 2 mm. It has become. That is, the impurity diffusion layer formed between the patterns of the impurity diffusion layer in the lower region of the electrode adjacent in the width direction is also less than 2 mm.

  Therefore, in such a selective impurity diffusion layer structure, when the diffusion condition is derived for each of the lower region of the electrode and other regions, the impurity diffusion has a structure that does not eventually become a solar cell. It is necessary to form and evaluate a dedicated substrate for deriving the layer diffusion conditions. Hereinafter, a dedicated substrate for deriving the diffusion conditions of the impurity diffusion layer is referred to as a monitor wafer.

  Since the monitor wafer is used for deriving the diffusion conditions of the impurity diffusion layer, the structure of the solar cell can be simulated, and the monitor wafer is inserted into the thermal diffusion furnace, so that the monitor wafer is finally applied to the substrate that becomes the solar cell. It is preferable that the influence in the thermal diffusion treatment can be kept as small as possible. On the other hand, since it is necessary to dare to produce a structure that does not eventually become a solar battery cell, it is not preferable that the structure of the monitor wafer and the production process become complicated.

As described above, when forming a structure having a lower region of an electrode having a relatively high impurity concentration and another region having a relatively low impurity concentration, apart from a substrate that eventually becomes a solar cell, It is necessary to prepare a monitor wafer. Note that shown here, if the relatively impurity concentration using an n-type dopant-containing paste for forming the lower region of the high electrode considers the influence of the n-type dopant-containing paste, during diffusion N ₂ Alternatively, an O ₂ condition is set.

  FIG. 15 is a schematic diagram showing the principle of the four-probe measuring instrument. The four-probe measuring instrument has four probes arranged linearly at 1 mm intervals. In the measurement of sheet resistance using a four-probe measuring instrument, the probe is brought into contact with the n-type impurity diffusion layer 42 provided on the surface layer of the p-type silicon substrate 41. With the probe in contact with the n-type impurity diffusion layer 42, current is supplied from the applied current source 45 to the two current probes 43 at both ends of the four probes, and the center of the four probes is centered. The sheet resistance is measured by measuring the voltage of the two voltage probes 44 with a voltmeter 46. Since no current flows in the reverse direction at the pn junction, the current flows only through the n-type impurity diffusion layer 42, so that the sheet resistance of only the n-type impurity diffusion layer 42 can be measured. An example of the size of the p-type silicon substrate 41 is 156 mm square. An example of the thickness of the p-type silicon substrate 41 is 0.2 mm. An example of the thickness of the n-type impurity diffusion layer 42 is 0.3 μm.

  As described above, the four probes of the four-probe measuring instrument have four probes arranged in a straight line at 1 mm intervals. Accordingly, there is an interval of 3 mm from the probe at one end to the probe at the other end of the four probes. For this reason, even when the probes arranged in a straight line are displaced in the rotational direction in the surface direction, an area of at least a 4 mm square is required in order to realize appropriate measurement.

  However, in a solar cell having an outer dimension of 156 mm square and provided with 100 grid electrodes, the interval between the patterns of the impurity diffusion layers in the lower region of the grid electrode adjacent in the width direction is 1.5 mm. It will be about. The width of the impurity diffusion layer in the lower region of the grid electrode is about 100 μm.

  In general, a head equipped with four probes in a four-probe measuring instrument has external dimensions along the plate surface of a substrate to be measured of both a width and a depth of about several centimeters. Normally, in the four-probe measuring instrument, the head automatically moves to several points in the plane of the substrate to be measured, and the sheet resistance is measured. However, a head having an external dimension of about several centimeters is not suitable for measuring any desired part having a width of about 1.5 mm. Moreover, when aligning a measurement object part and a head visually, it is difficult to drop the head to an arbitrary desired part having a width of about 1.5 mm. Therefore, in the four-probe measuring instrument, it is difficult to place the probe on any desired portion having a width of about 1.5 mm.

  In other words, it is theoretically possible to perform measurement by placing the probe mounted on the head on a portion having a width of about 1.5 mm, but in reality, there is a problem of positioning accuracy and measurement is difficult. . Further, since the width of the impurity diffusion layer in the lower region of the grid electrode is about 100 μm, it cannot be measured. For this reason, when using a four-terminal measuring instrument, a substrate to be a solar cell is used for the impurity diffusion layer between the impurity diffusion layer in the lower region of the grid electrode and the pattern of the impurity diffusion layer in the lower region of the grid electrode. In the evaluation of the sheet resistance in use, an appropriate evaluation cannot be made. In other words, the size of the pattern of the n-type impurity diffusion layer to be a measurement target necessary for the measurement is 1 mm × 4 mm based on the principle of a four-terminal measuring instrument that performs measurement by the four-probe method.

  For this reason, when a selective high-concentration impurity layer is formed, the width of the region of the grid electrode portion in the first n-type impurity diffusion layer 4, that is, the width of the region where the n-type upper grid electrode 8 is formed is 100 μm. It is difficult to evaluate with the substrate which finally becomes the solar battery cell 1 due to the mechanism of the device for measuring the sheet resistance.

  When examining the sheet resistance of the first n-type impurity diffusion layer 4, it is necessary to form some structure for confirming the sheet resistance of the first n-type impurity diffusion layer 4. Conceptually, if only the sheet resistance of the first n-type impurity diffusion layer 4 is to be grasped, as shown in FIG. 16 as an example, the entire light receiving surface of the p-type single crystal silicon substrate 2 is n-type. A simple application pattern of the n-type dopant-containing paste 21 that is the application region 51 of the n-type dopant-containing paste to which the dopant-containing paste 21 is applied can be considered. In this case, the first n-type impurity diffusion layer 4 is formed on the entire light receiving surface of the p-type single crystal silicon substrate 2. FIG. 16 is a schematic diagram showing an example of a coating pattern of the n-type dopant-containing paste 21 for confirming the sheet resistance of the first n-type impurity diffusion layer 4 according to the first embodiment of the present invention.

  Furthermore, when the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5 are to be evaluated simultaneously on the same p-type single crystal silicon substrate 2, an n-type dopant-containing paste is shown as an example in FIG. The n-type coated region 51 and the non-coated region 52 of the n-type dopant-containing paste to which the n-type dopant-containing paste 21 is not applied are arranged at the same frequency in the plane of the p-type single crystal silicon substrate 2. A pattern in which the application region 51 of the dopant-containing paste and the non-application region 52 of the n-type dopant-containing paste have a staggered pattern is conceivable. In this case, the region of the first n-type impurity diffusion layer 4 formed by applying the n-type dopant-containing paste 21 and the second n-type impurity diffusion layer 5 formed without applying the n-type dopant-containing paste 21 are used. The area is a staggered pattern. FIG. 17 is a schematic diagram illustrating an example of a coating pattern of the n-type dopant-containing paste 21 for confirming the sheet resistance of the first n-type impurity diffusion layer 4 according to the first embodiment of the present invention.

However, as described above, phosphorus oxychloride (POCl ₃ ) is consumed by the n-type dopant-containing paste 21 printed on the p-type single crystal silicon substrate 2 during the second diffusion step. The amount of phosphorus oxychloride (POCl ₃ ) consumed varies depending on the amount of n-type dopant-containing paste 21 applied, so that the state of reproduction of the amount of phosphorus oxychloride (POCl ₃ ) consumed under the manufacturing conditions for solar cells is reproduced. Therefore, it is necessary to diffuse phosphorus to the monitor wafer .

That is, in the diffusion process at the time of manufacturing the solar cell, phosphorus oxychloride (POCl ₃ ) flows between the p-type single crystal silicon substrates 2 while being consumed by the n-type dopant-containing paste 21. For this reason, the concentration of phosphorus oxychloride (POCl ₃ ) in the diffusion gas in the vicinity of the surface of the p-type single crystal silicon substrate 2 for solar cells is included in the original diffusion gas when the solar cells are manufactured. It becomes lower than the concentration of phosphorus oxychloride (POCl ₃ ). Then, phosphorus, which is an impurity, is diffused between the patterns of the impurity diffusion layer in the lower region of the grid electrode with the diffusion gas in which the concentration of the phosphorus oxychloride (POCl ₃ ) is reduced.

Therefore, in the case of the monitor wafer for evaluation, as in the case of the p-type single crystal silicon substrate 2 for solar cells, when phosphorus is diffused in a state where the diffusion gas in which the concentration of phosphorus oxychloride (POCl ₃ ) is reduced is reproduced. It is necessary to evaluate the impurity concentration. Relative consumption of phosphorus oxychloride to be consumed in the production conditions of the solar cell (POCl _3), the consumption of phosphorus oxychloride even when many consumption (POCl _3), also phosphorus oxychloride (POCl ₃₎ Even if the amount is reduced, there is a difference between the phosphorus diffusion concentration in the impurity diffusion layer of the solar battery cell and the phosphorus diffusion concentration in the impurity diffusion layer of the monitor wafer.

  In this case, as a matter required for the coating pattern of the n-type dopant-containing paste 21, the coating amount of the n-type dopant-containing paste 21 is set to be equal to the coating amount at the time of manufacturing the solar battery cell as much as possible. The sheet resistance of the region 4 and the region of the second n-type impurity diffusion layer 5 can be measured in the same substrate, and can be measured by a general sheet resistance measuring device. For this purpose, it is necessary to use a monitor wafer 61 having a structure similar to that of the solar battery cell.

  And the monitor wafer 61 is produced on the conditions close | similar to manufacture of a normal photovoltaic cell, Preferably on the same conditions. FIG. 18 shows two sets of processing from the left in the thermal diffusion furnace 31 in the case where the solar cell manufacturing and the production of the monitor wafer are simultaneously performed using the thermal diffusion furnace 31 in the first embodiment of the present invention. It is the schematic diagram which looked at the board | substrate from the top. In each set, 41 processing substrates are arranged at an interval of 3 mm in the horizontal direction. In the production of the monitor wafer, the p-type single crystal silicon substrate 2 under the same conditions as the p-type single crystal silicon substrate 2 for manufacturing solar cells is used. In FIG. 18, the p-type single crystal silicon substrate 2 for producing the monitor wafer is also referred to as the monitor wafer 61, so that the p-type single crystal silicon substrate 2 for producing the solar cell and the monitor wafer are produced. It is distinguished from the p-type single crystal silicon substrate 2.

  At the time of manufacturing a normal solar cell in which the diffusion concentration of phosphorus in the impurity diffusion layer is not evaluated, the p-type single crystal silicon substrate 2 for the solar cell is disposed at all positions in the thermal diffusion furnace 31. In the solar cell evaluation method according to the first embodiment, in order to evaluate the diffusion concentration of phosphorus in the impurity diffusion layer, in each set, in the arrangement direction in which the treatment substrates are arranged, that is, the plate surface of the treatment substrate The monitor wafers 61 are arranged every ten sheets from both ends, the center, and both ends in the direction perpendicular to. That is, in each set, the monitor wafers 61 are arranged at the first, eleventh, twenty-first, thirty-first and forty-first positions from one end side in the arrangement direction. The p-type single crystal silicon substrate 2 for solar cells is disposed at other locations. The numbers shown on the left side in FIG. 18 indicate the order of each set of processing substrates from one end side in the arrangement direction.

  Depending on the diffusion conditions, there may be a difference in the phosphorus diffusion concentration in the impurity diffusion layer between the processing substrate at both ends in the arrangement direction and the processing substrate at the center in each set. As an example, since the diffusion gas hardly flows in the central portion in the arrangement direction, the phosphorus diffusion concentration in the impurity diffusion layer of the processing substrate in the central portion is determined so that the diffusion of phosphorus in the impurity diffusion layer of the processing substrate in other locations in the arrangement direction. It may decrease compared to the concentration. Further, when comparing the upstream set and the downstream set in the flow direction of the diffusion gas, the diffusion concentration of phosphorus in the impurity diffusion layer of the processing substrate in the downstream set indicates that the impurity diffusion in the processing substrate in the upstream set It may be lower than the diffusion concentration of phosphorus in the layer. It is required to reduce the dispersion of the phosphorus diffusion concentration in the impurity diffusion layer and to manufacture the phosphorus diffusion concentration in the impurity diffusion layer with a uniform and appropriate diffusion concentration. For this purpose, it is preferable to evaluate by placing monitor wafers at both ends, the center, and the middle in each set.

On the other hand, the portion where the monitor wafer 61 is not disposed in the arrangement direction by arranging the p-type single crystal silicon substrate 2 of solar cell, in together when reproducing conditions close to normal solar cell manufacturing, The manufacture of the solar battery cell and the creation of the monitor wafer 61 can be performed simultaneously.

  The inventors have found the structure shown in FIGS. 19 to 21 as the structure of a monitor wafer that is a substrate for evaluation of a solar battery cell that satisfies the above specifications. FIG. 19 is a schematic diagram of the pattern of the impurity diffusion layer of the monitor wafer according to the first embodiment of the present invention. FIG. 20 is a main-portion cross-sectional view of the periphery of the first n-type impurity diffusion layer measurement region 62 in the monitor wafer according to the first embodiment of the present invention. FIG. 21 is a cross-sectional view of a principal part around the second n-type impurity diffusion layer measurement region 63 in the monitor wafer according to the first embodiment of the present invention.

The monitor wafer 61 according to the first embodiment has a structure simulating the n-type impurity diffusion layer 3 of the solar battery cell 1 and, like the solar battery cell 1 to be evaluated, the p-type single crystal silicon substrate 2. N-type impurity diffusion layer 3 is provided on one surface. In addition, the same code | symbol as the photovoltaic cell 1 is attached | subjected also about the n-type impurity diffusion layer which simulated the photovoltaic cell 1 used as evaluation object. That is, the monitor wafer 61 has the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5. The monitor wafer 61 includes a first n-type impurity diffusion layer measurement region 62, which is a first impurity concentration measurement region formed by printing the n-type dopant-containing paste 21 in the same manner as the first n-type impurity diffusion layer 4, and Similarly to the 2n-type impurity diffusion layer 5, the second n-type impurity diffusion layer measurement region 63, which is a second impurity concentration measurement region formed by diffusion using only phosphorus oxychloride (POCl ₃ ), is used as the p-type single crystal silicon substrate 2 On one side.

  The first n-type impurity diffusion layer measurement region 62 is an impurity diffusion layer for measuring sheet resistance with a four-probe measurement instrument. The first n-type impurity diffusion layer measurement region 62 is a grid which is an elongated first n-type impurity diffusion layer 4 corresponding to the lower part of the grid electrode 8 on the n-type layer of the solar battery cell 1 in the first n-type impurity diffusion layer 4. The impurity region has a size equal to or larger than the interval adjacent to another grid impurity region. As a result, a large measurement region can be secured, and measurement with a four-probe measuring instrument is facilitated even when the grid impurity region is thinned.

  The first n-type impurity diffusion layer measurement region 62 is formed under the same conditions using the same n-type dopant-containing paste 21 in the same process as the first n-type impurity diffusion layer 4 of the solar battery cell 1 to be evaluated. Therefore, it has the same depth and n-type impurity concentration as the first n-type impurity diffusion layer 4, and has n-type impurities at the first impurity concentration. Therefore, the sheet resistance of the first n-type impurity diffusion layer 4 of the solar battery cell 1 can be confirmed by measuring the sheet resistance of the first n-type impurity diffusion layer measurement region 62. Then, by confirming the sheet resistance of the first n-type impurity diffusion layer 4, the n-type impurity concentration of the first n-type impurity diffusion layer 4 of the solar battery cell 1 can be estimated.

  Similar to the first n-type impurity diffusion layer 4, the first n-type impurity diffusion layer measurement region 62 formed by printing the n-type dopant-containing paste 21 has a sheet resistance of 20Ω / sq. Therefore, the sheet resistance of a general n-type layer used for the current n-type upper electrode 7 is 70 Ω / sq. Since there is a large difference compared to the degree, the in-plane distribution state of the n-type impurity concentration of the first n-type impurity diffusion layer 4 in the p-type single crystal silicon substrate 2 can be grasped with a minimum number. Are arranged at four points. The first n-type impurity diffusion layer measurement regions 62 need only be arranged at four or more points, and the p-type single diffusion region 4 can be grasped in the in-plane distribution state of the n-type impurity concentration of the first n-type impurity diffusion layer 4. It is preferable that the crystal silicon substrate 2 be disposed at a target position with respect to a center line that equally divides the plane of the crystal silicon substrate 2 in the left-right direction.

  As described above, the sheet resistance of the first n-type impurity diffusion layer 4 is 20Ω / sq. Which is a low value as the n-type impurity diffusion layer of the solar battery cell. The sheet resistance of the first n-type impurity diffusion layer measurement region 62 is also 20 Ω / sq. It will be about. In this case, even when the dependence on the position in the plane of the p-type single crystal silicon substrate 2 in the quartz tube of the diffusion equipment and the uniformity of the sheet resistance in the plane of the p-type single crystal silicon substrate 2 are taken into account. If the number of sheet resistance measurement points of the first n-type impurity diffusion layer measurement region 62 in the plane of the p-type single crystal silicon substrate 2 is about four, it is sufficient for confirming the sheet resistance of the first n-type impurity diffusion layer 4. is there.

  The sheet resistance of the first n-type impurity diffusion layer measurement region 62 is 20 Ω / sq. Therefore, even when the sheet resistance of the first n-type impurity diffusion layer measurement region 62 varies in the plane of the p-type single crystal silicon substrate 2, the sheet resistance is 70Ω / sq. The variation in sheet resistance is small compared to the case of the degree. Therefore, even when the variation in sheet resistance of the first n-type impurity diffusion layer measurement region 62 in the plane of the p-type single crystal silicon substrate 2 is taken into consideration, the first n-type impurity in the plane of the p-type single crystal silicon substrate 2 is taken into account. If the number of measurement points of the sheet resistance in the diffusion layer measurement region 62 is about four, it is sufficient for confirming the sheet resistance of the first n-type impurity diffusion layer 4.

  Further, by adding one central point in the plane of the p-type single crystal silicon substrate 2 to the sheet resistance measurement portion of the first n-type impurity diffusion layer measurement region 62, the first n-type impurity diffusion of the solar battery cell 1 is performed. The structure of the monitor wafer 61 more suitable for checking the sheet resistance of the layer 4 can be realized.

  The second n-type impurity diffusion layer measurement region 63 is an impurity diffusion layer for measuring sheet resistance with a four-probe measurement instrument. The second n-type impurity diffusion layer measurement region 63 is a grid which is an elongated first n-type impurity diffusion layer 4 corresponding to the lower part of the grid electrode 8 on the n-type layer of the solar cell 1 in the first n-type impurity diffusion layer 4. The impurity region has a size equal to or larger than the interval adjacent to another grid impurity region. As a result, a large measurement region can be secured, and measurement with a four-probe measuring instrument is facilitated even when the grid impurity region is thinned.

  Since the second n-type impurity diffusion layer measurement region 63 is formed under the same conditions in the same process as the second n-type impurity diffusion layer 5 of the solar battery cell 1 to be evaluated, it is equivalent to the second n-type impurity diffusion layer 5. It has depth and n-type impurity concentration, and has an n-type impurity layer at the second impurity concentration. Therefore, the sheet resistance of the second n-type impurity diffusion layer 5 of the solar battery cell 1 can be confirmed by measuring the sheet resistance of the second n-type impurity diffusion layer measurement region 63. Then, by confirming the sheet resistance of the second n-type impurity diffusion layer 5, the n-type impurity concentration of the second n-type impurity diffusion layer 5 of the solar battery cell 1 can be estimated.

On the other hand, the second n-type impurity diffusion layer measurement region 63 formed by diffusion only with phosphorus oxychloride (POCl ₃ ) as in the second n-type impurity diffusion layer 5 is generally similar to the second n-type impurity diffusion layer 5. Sheet resistance of a single concentration n-type impurity diffusion layer of 70Ω / sq. 90 Ω / sq. Higher than The sheet resistance is more than about. Therefore, the distribution in the plane of the p-type single crystal silicon substrate 2 in the second n-type impurity diffusion layer measurement region 63 is 70 Ω / sq. Which is the sheet resistance of a general single-concentration n-type impurity diffusion layer. Since the uniformity is lower than in the case of FIG. 5, the n-type impurity concentration layer of the second n-type impurity diffusion layer 5 in the p-type single crystal silicon substrate 2 is arranged at 25 points so that it can be grasped in the plane. . The second n-type impurity diffusion layer measurement region 63 may basically be disposed at the five points of the central one point in the plane of the p-type single crystal silicon substrate 2 and at least four points on the outer peripheral side. It is arranged at 25 points so that a more detailed situation can be grasped. The second n-type impurity diffusion layer measurement region 63 is preferably two pairs of points on the outer peripheral side that are symmetrical with respect to the central point. That is, the four points on the outer peripheral side of the second n-type impurity diffusion layer measurement region 63 may be arranged at target positions with respect to the center line that equally divides the plane of the p-type single crystal silicon substrate 2 on the left and right. preferable.

  In the first embodiment, the dimensions of the first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 in the plane of the p-type single crystal silicon substrate 2 are the same as those of a general sheet resistance measurement device. In the measurement with the four-probe measuring instrument, the 8 mm × 8 mm square is set so that the measurement can be easily performed by placing the probe in the center of the measurement part. 13 and 14 described above are derived using the first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 having the pattern shown in FIG.

The dimension of the first n-type impurity diffusion layer measurement region 62 is not required to be larger than 8 mm square from the viewpoint that the sheet resistance measurement operation can be easily performed. When the dimension of the first n-type impurity diffusion layer measurement region 62 is larger than 8 mm square, the coating amount of the n-type dopant-containing paste 21 is originally applied to the p-type single crystal silicon substrate 2 for solar cells as the grid pattern 23. Compared with the case where it was done, it increases significantly. As the application amount of the n-type dopant-containing paste 21 increases, the amount of phosphorus oxychloride (POCl ₃ ) consumed by the n-type dopant-containing paste 21 increases in the second diffusion step in forming the monitor wafer 61. The effect of the increase in the amount of phosphorus oxychloride (POCl ₃ ) consumption on the diffusion state of phosphorus in the second n-type impurity diffusion layer measurement region 63 around the pattern region of the first n-type impurity diffusion layer measurement region 62; In other words, the effect of reducing the amount of phosphorus diffusion increases. For this reason, the dimension of the first n-type impurity diffusion layer measurement region 62 is not preferably larger than necessary.

  The dimension of the second n-type impurity diffusion layer measurement region 63 is not required to be larger than 8 mm square from the viewpoint that the sheet resistance measurement operation can be easily performed. When the size of the second n-type impurity diffusion layer measurement region 63 is larger than 8 mm square, the amount of the n-type dopant-containing paste 21 is originally applied to the p-type single crystal silicon substrate for solar cells for forming the grid pattern 23. 2 compared with the case where it was applied.

By reducing the coating amount of the n-type dopant-containing paste 21 for forming the grid pattern 23, the consumption amount of phosphorus oxychloride (POCl ₃ ) by the n-type dopant-containing paste 21 in the second diffusion step in forming the monitor wafer 61. Less. The effect of the decrease in the amount of phosphorus oxychloride (POCl ₃ ) consumption on the phosphorus diffusion state of the second n-type impurity diffusion layer measurement region 63 around the pattern region of the first n-type impurity diffusion layer measurement region 62; That is, the effect of reducing the amount of phosphorus diffusion is reduced. For this reason, the dimension of the first n-type impurity diffusion layer measurement region 62 is not preferably larger than necessary.

  In the case where the second n-type impurity diffusion layer measurement regions 63 are arranged at 25 points in an arrangement of 5 columns × 5 rows as shown in FIG. 19 in the plane of the 156 mm square p-type single crystal silicon substrate 2, the second n-type impurity When the diffusion layer measurement regions 63 are evenly arranged, the arrangement interval between two second n-type impurity diffusion layer measurement regions 63 adjacent in the column direction or the row direction is 31.2 mm. Here, in actual manufacturing, in order to facilitate the management of the arrangement of the second n-type impurity diffusion layer measurement region 63, the arrangement interval between the two second n-type impurity diffusion layer measurement regions 63 adjacent in the column direction or the row direction. Is preferably in units of 1 mm. Here, the arrangement interval is a distance between the centers of the second n-type impurity diffusion layer measurement regions 63 in the column direction or the row direction.

  Therefore, in the plane of the 156 mm square p-type single crystal silicon substrate 2, the arrangement interval of the second n-type impurity diffusion layer measurement regions 63 in the column direction or the row direction is preferably 32 mm. The distance between the end of the second n-type impurity diffusion layer measurement region 63 in the column direction and the side of the p-type single crystal silicon substrate 2 adjacent to the second n-type impurity diffusion layer measurement region 63 in the column direction is 14 mm. It is preferable that Similarly, the distance between the second n-type impurity diffusion layer measurement region 63 at the end in the row direction and the side of the p-type single crystal silicon substrate 2 adjacent to the second n-type impurity diffusion layer measurement region 63 in the row direction is: It is preferable to be 14 mm.

  FIG. 22 is an enlarged view of a main part of FIG. In FIG. 22, when viewed in the horizontal direction, that is, when viewed in the row direction, the band α, the standard band β, the band γ, the standard band β, and the band α are arranged in this order. Here, the band α is a region where the second n-type impurity diffusion layer measurement region 63 is arranged in the row direction. The standard band β is a region where neither the first n-type impurity diffusion layer measurement region 62 nor the second n-type impurity diffusion layer measurement region 63 is arranged in the row direction. The band γ is a region where the first n-type impurity diffusion layer measurement region 62 is arranged in the row direction. Since the width of the band α is 8 mm, the width of the band γ is 8 mm, and the interval between two adjacent bands α is 32 mm, the width of the standard band β is 8 mm. The interval between two adjacent bands α is the distance between the centers of the second n-type impurity diffusion layer measurement regions 63 in the row direction. Although FIG. 22 shows the case when viewed in the horizontal direction, the same applies when viewed in the vertical direction in FIG. 22, that is, when viewed in the column direction.

  In the case where 25 second n-type impurity diffusion layer measurement regions 63 of 8 mm square with respect to the in-plane of the 156 mm square p-type single crystal silicon substrate 2 are arranged uniformly in an arrangement of 5 columns × 5 rows, In the direction or the row direction, a standard band β having the same width as both can be provided between the second n-type impurity diffusion layer measurement region 63 and the first n-type impurity diffusion layer measurement region 62. Further, the second n-type impurity diffusion layer measurement region 63 and the first n-type impurity diffusion layer measurement region 62 are mutually measured by the presence of the standard band β when phosphorus is diffused in each region. Do not affect each other, and phosphorus is diffused independently of each other.

That is, in the first diffusion step in forming the monitor wafer 61, phosphorus is not diffused from the n-type dopant-containing paste 21 into the second n-type impurity diffusion layer measurement region 63, and phosphorus is not directly diffused into the region immediately below the n-type dopant-containing paste 21. Is diffused to form the first n-type impurity diffusion layer measurement region 62. In addition, in the second diffusion step in forming the monitor wafer 61, since the standard band β exists, printing is performed on the first n-type impurity diffusion layer measurement region 62 adjacent to the second n-type impurity diffusion layer measurement region 63. The consumption of phosphorus oxychloride (POCl ₃ ) by the n-type dopant containing paste 21 does not affect the diffusion of phosphorus into the second n-type impurity diffusion layer measurement region 63. For this reason, in the monitor wafer 61, the second n-type impurity diffusion layer measurement region 63 and the first n n are reproduced in a state in which conditions close to the consumption of phosphorus oxychloride (POCl ₃ ) consumed under normal solar cell manufacturing conditions are reproduced. A type impurity diffusion layer measurement region 62 is formed.

  Then, by measuring the sheet resistance between the second n-type impurity diffusion layer measurement region 63 and the first n-type impurity diffusion layer measurement region 62, the first n-type impurity below the n-type layer upper grid electrode 8 in the solar battery cell 1 is measured. The same sheet resistance as that of the diffusion layer 4 and the same sheet resistance as that of the second n-type impurity diffusion layer 5 under the n-type layer upper grid electrode 8 can be measured with higher accuracy. Thereby, the sheet resistance of the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5 can be appropriately evaluated.

Regarding the dimensions of the measurement regions of the second n-type impurity diffusion layer measurement region 63 and the first n-type impurity diffusion layer measurement region 62, when the measurement region size is larger than 8 mm square, the width of the standard band β is narrowed. In this case, in the above-described second diffusion step, phosphorus oxychloride (n-type dopant-containing paste 21 printed on the first n-type impurity diffusion layer measurement region 62 adjacent to the second n-type impurity diffusion layer measurement region 63 ( The consumption of POCl ₃ ) affects the diffusion of phosphorus into the second n-type impurity diffusion layer measurement region 63. For this reason, it is not appropriate to make the dimension of the measurement region larger than 8 mm square. By setting the dimensions of the measurement regions of the second n-type impurity diffusion layer measurement region 63 and the first n-type impurity diffusion layer measurement region 62 to be 8 mm square, it is possible to secure a standard band β having the same size as both. The measurement area is suitably 8 mm square.

  In the configuration of the four-probe measuring instrument, when the probe has a mechanism that can contact the probe at an arbitrary position in units of less than 1 mm, the size of the measurement location is 1 mm × 4 mm square or more. If there is.

  That is, the monitor wafer 61 according to the first embodiment is provided on the first conductive type semiconductor substrate and the region corresponding to the shape of the grid electrode of the solar battery cell on the first surface of the semiconductor substrate. A plurality of elongated grid impurity regions having a second conductivity type impurity layer at an impurity concentration of 1 and a region between grid impurity regions provided on the first surface of the semiconductor substrate and adjacent to each other in the width direction; An inter-grid impurity region having a second conductivity type impurity layer having a second impurity concentration lower than the first impurity concentration and a first surface of the semiconductor substrate, and having a size larger than the interval between the grid impurity regions. A first impurity concentration measurement region having a second conductivity type impurity layer at a first impurity concentration and a first surface of the semiconductor substrate, and having a size equal to or larger than a distance between the grid impurity regions; 2 Comprising a second impurity concentration measurement region having an impurity layer of the second conductivity type impurity concentration, the.

  Here, in the first embodiment, the semiconductor substrate of the first conductivity type is the p-type single crystal silicon substrate 2. The first surface is one surface of the p-type single crystal silicon substrate 2 on the light receiving surface side. The grid impurity region is an elongated first n-type impurity diffusion layer 4 corresponding to a lower part of the grid electrode 8 on the n-type impurity diffusion layer of the solar battery cell 1 in the first n-type impurity diffusion layer 4. The inter-grid impurity region is the second n-type impurity diffusion layer 5. The first impurity concentration measurement region is the first n-type impurity diffusion layer measurement region 62. The second impurity concentration measurement region is the second n-type impurity diffusion layer measurement region 63.

  FIG. 23 is a diagram showing an example of the shape of the first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 in the plane of the p-type single crystal silicon substrate 2 according to the first embodiment of the present invention. It is. The first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 shown in FIG. 23 are provided in order to secure a wide region that can include all of the regions 64 in contact with the probe of the four-probe measurement instrument. The rectangular shape is 1 mm × 4 mm square.

  FIG. 24 shows another example of the shape of the first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 in the plane of the p-type single crystal silicon substrate 2 according to the first embodiment of the present invention. FIG. The first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 shown in FIG. 24 ensure a wide region that can include all of the regions 64 in contact with the probe of the four-probe measurement instrument, and Considering the printing accuracy of the n-type dopant-containing paste 21, it is a rectangular shape of 2 mm × 5 mm square.

FIG. 25 shows another example of the shape of the first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 in the plane of the p-type single crystal silicon substrate 2 according to the first embodiment of the present invention. FIG. The first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 shown in FIG. 25 ensure a wide region that can contain all of the region 64 that the probe of the four-probe measurement instrument contacts, and The first n-type impurity diffusion layer 4 having an elongated shape below the grid electrode 8 on the n-type layer is a region that is at least twice the interval adjacent in the width direction, and the first n-type below the bus electrode 9 on the n-type layer. A square shape of 8 mm × 8 mm square is formed so as to be a region larger than the width of the impurity diffusion layer 4. The interval between the elongated first n-type impurity diffusion layers 4 below the n-type layer upper grid electrode 8 is about 1.5 mm, and considering the printing accuracy, it is set to about 8 mm × 8 mm square, so that four probes are provided. The sheet resistance can be easily measured without having to increase the accuracy of the contact position.

  FIG. 26 shows another example of the shape of the first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 in the plane of the p-type single crystal silicon substrate 2 according to the first embodiment of the present invention. FIG. The first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 shown in FIG. 26 may have an elliptical shape with a minor axis of 2 mm × major axis of 5 mm.

  FIG. 27 shows another example of the shape of the first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 in the plane of the p-type single crystal silicon substrate 2 according to the first embodiment of the present invention. FIG. The first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 shown in FIG. 27 may be circular with a diameter of 8 mm.

  Even in a substrate in which a p-type impurity diffusion layer having a selective impurity diffusion layer structure is formed on the surface of an n-type silicon substrate, the first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63 described above are included. By forming the corresponding first p-type impurity diffusion layer measurement region and second p-type impurity diffusion layer measurement region, the sheet resistance of the p-type impurity diffusion layer having the selective impurity diffusion layer structure can be confirmed.

  As described above, the sheet resistance corresponding to the impurity diffusion layer having the selective impurity diffusion layer structure is measured using the solar cell evaluation substrate according to the first embodiment. As a result, even when the impurity diffusion layer having the selective impurity diffusion layer structure is thinned, the same sheet resistance as that of the first n-type impurity diffusion layer 4 below the n-type upper grid electrode 8 in the solar battery cell 1 and n The same sheet resistance as that of the lower second n-type impurity diffusion layer 5 between the grid electrodes 8 on the mold layer can be accurately measured by a four-probe measuring instrument that is a sheet resistance measuring instrument using a four-probe method. Thereby, the sheet resistance between the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5 can be accurately evaluated. Moreover, the board | substrate for evaluation of the photovoltaic cell concerning this Embodiment 1 can be formed in low cost by the same simple process as the manufacturing process of the photovoltaic cell 1 of a product.

  In improving the photoelectric conversion efficiency of the solar battery cell 1, it is important to optimize the first impurity concentration of the first n-type impurity diffusion layer 4 and the second impurity concentration of the second n-type impurity diffusion layer 5. . Since the sheet resistance of the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5 can be accurately evaluated by using the solar cell evaluation substrate according to the first embodiment, It is possible to accurately estimate the first impurity concentration and the second impurity concentration in the solar battery cell 1. Further, by using the solar cell evaluation substrate according to the first embodiment, the impurity concentration can be accurately estimated with a structure close to the structure of the solar battery cell 1. This facilitates the derivation of diffusion conditions that can optimize the first impurity concentration and the second impurity concentration, and can effectively improve the photoelectric conversion efficiency of the solar battery cell 1.

Moreover, in the board | substrate for evaluation of the photovoltaic cell concerning this Embodiment 1, the application quantity of the n-type dopant containing paste 21 is made equal to the application quantity at the time of photovoltaic cell manufacture as much as possible, and it is p-type at the time of a 2nd diffusion process. The amount of phosphorus oxychloride (POCl ₃ ) consumed by the n-type dopant-containing paste 21 printed on the single crystal silicon substrate 2 can be made equal to the coating amount at the time of manufacturing the solar cell as much as possible.

  Therefore, by using the solar cell evaluation substrate according to the first embodiment, even when the impurity diffusion layer is thinned, the sheet resistance of the impurity diffusion layer can be accurately measured, and the impurity diffusion The impurity concentration of the layer can be estimated with high accuracy.

Embodiment 2. FIG.
FIG. 28: is the top view which looked at the photovoltaic cell 101 concerning Embodiment 2 of this invention from the light-receiving surface side. FIG. 29: is the top view which looked at the photovoltaic cell 101 concerning Embodiment 2 of this invention from the back surface side facing a light-receiving surface. 30 is a main-portion cross-sectional view showing the configuration of the solar battery cell 101 according to the second embodiment of the present invention, and is a cross-sectional view along the line BB in FIG.

  The solar battery cell 101 is a crystalline solar battery cell whose outer shape in the plane direction has a square shape. In solar cell 101, p-type impurity diffusion layer 103 is formed by diffusion of boron, which is a p-type impurity element, on the light-receiving surface side of semiconductor substrate 102 made of square n-type single crystal silicon having an outer dimension of 156 mm × 156 mm. Thus, a semiconductor substrate 117 having a pn junction is formed. Hereinafter, the semiconductor substrate 102 may be referred to as an n-type single crystal silicon substrate 102. A p-type impurity diffusion layer passivation film 104 made of an insulating film is formed on the p-type impurity diffusion layer 103. Hereinafter, the passivation film 104 on the p-type impurity diffusion layer is referred to as a passivation film 104 on the p-type layer. Note that an n-type polycrystalline silicon substrate may be used as the semiconductor substrate 102. In the second embodiment, the first conductivity type is n-type and the second conductivity type is p-type.

  On the light-receiving surface side of the n-type single crystal silicon substrate 102, minute unevenness (not shown) that forms a texture structure for confining light is formed.

The p-type upper passivation film 104 is a light-transmitting insulating film. As the p-type upper passivation film 104, an aluminum oxide (Al ₂ O ₃ ) film 105 having a thickness of 5 nm and a silicon nitride (SiN) film 106 having a refractive index of 2.1 and a thickness of 80 nm are p-type. They are sequentially formed on the impurity diffusion layer 103. The p-type upper passivation film 104 is not limited to an aluminum oxide (Al ₂ O ₃ ) film and a silicon nitride (SiN) film, but is an insulating material such as a silicon oxide (SiO ₂ ) film or a titanium oxide (TiO ₂ ) film. It may be formed by a film. In the solar battery cell 101, light L enters from the p-type upper passivation film 104.

  In addition, a plurality of long and narrow p-type impurity diffusion layer upper grid electrodes 108 are arranged side by side on the light receiving surface side of the semiconductor substrate 117, and on the p-type impurity diffusion layer electrically connected to the p-type impurity diffusion layer upper grid electrode 108. A bus electrode 109 is provided orthogonal to the p-type impurity diffusion layer upper grid electrode 108. Hereinafter, the p-type impurity diffusion layer upper grid electrode 108 is referred to as a p-type layer upper grid electrode 108. The p-type impurity diffusion layer upper bus electrode 109 is referred to as a p-type layer upper bus electrode 109. The p-type layer upper grid electrode 108 and the p-type layer upper bus electrode 109 are electrically connected to the p-type impurity diffusion layer 103 at the bottom portion.

  The p-type upper layer grid electrode 108 has a width of about 50 μm or more and 150 μm or less, and is arranged in a number of 100 or more and 200 or less in parallel at predetermined intervals, and collects electricity generated inside the semiconductor substrate 117. Electricity. The p-type layer-top bus electrode 109 has a width of about 0.5 mm or more and 1.0 mm or less, and three or more and five or less pieces are arranged per solar cell, and the p-type layer-top grid The electricity collected by the electrode 108 is taken out. The p-type layer upper grid electrode 108 and the p-type layer upper bus electrode 109 constitute a p-type impurity diffusion layer upper electrode 107 as a light-receiving surface side electrode having a comb shape. Hereinafter, the p-type impurity diffusion layer upper electrode 107 is referred to as a p-type layer upper electrode 107. In the second embodiment, the number of p-type layer-top grid electrodes 108 is 100, the number of p-type layer-top bus electrodes 109 is four, the electrode width of the p-type layer-top grid electrode 108 is 50 μm, p The electrode width of the mold layer upper bus electrode 109 is 1.0 mm. In FIG. 28, the number of p-type upper-layer grid electrodes 108 is reduced for the sake of illustration.

  And in the photovoltaic cell 101 concerning this Embodiment 2, two types of layers are formed as the n-type impurity diffusion layer 110, and the selective impurity diffusion layer structure is formed. That is, in the surface layer portion on the back surface side of the n-type single crystal silicon substrate 102, the n-type impurity diffusion layer 110 is provided in a lower region of the n-type impurity diffusion layer upper electrode 114 that is a back surface side electrode and a region adjacent to the lower region. A high concentration impurity diffusion layer in which n-type impurities are uniformly diffused at a relatively high concentration, that is, a first n-type impurity diffusion layer 111 which is a low resistance diffusion layer is formed. Further, in the surface layer portion on the back surface side of the n-type single crystal silicon substrate 102, the n-type impurity in the n-type impurity diffusion layer 110 has a relatively low concentration in the region where the first n-type impurity diffusion layer 111 is not formed. A second n-type impurity diffusion layer 112 that is a low-concentration impurity diffusion layer that is uniformly diffused, that is, a high-resistance diffusion layer is formed.

  Therefore, if the impurity diffusion concentration of the first n-type impurity diffusion layer 111 is the first diffusion concentration and the impurity diffusion concentration of the second n-type impurity diffusion layer 112 is the second diffusion concentration, the second diffusion concentration is the first diffusion concentration. It becomes smaller than the diffusion concentration. When the sheet resistance value of the first n-type impurity diffusion layer 111 is the first sheet resistance value and the sheet resistance value of the second n-type impurity diffusion layer 112 is the second sheet resistance value, the second sheet resistance value is It becomes larger than the sheet resistance value.

  The second n-type impurity diffusion layer 112 that is a low-concentration impurity diffusion layer suppresses recombination on the back surface of the semiconductor substrate 117 as a BSF layer, and contributes to realizing a favorable open-circuit voltage of the solar battery cell 101. The first n-type impurity diffusion layer 111 that is a high-concentration impurity diffusion layer reduces the contact resistance with the n-type impurity diffusion layer upper electrode 114 that is the back surface side electrode, and realizes a favorable fill factor of the solar battery cell 101. Contribute to.

  The solar battery cell 101 according to the second embodiment configured as described above has a first n-type having a relatively low sheet resistance at the lower part of the n-type impurity diffusion layer upper electrode 114 that is the back-side electrode on the back side. Impurity diffusion layer 111 is formed to reduce the contact resistance between n-type single crystal silicon substrate 102 and n-type impurity diffusion layer upper electrode 114. In addition, a second n-type impurity diffusion layer 112 having a relatively low n-type impurity concentration is formed in a region other than the first n-type impurity diffusion layer 111 on the back surface side of the solar battery cell 101, and holes are generated and disappeared. Reduce the binding speed. Therefore, the solar battery cell 101 according to the first embodiment has a selective impurity diffusion layer structure composed of the first n-type impurity diffusion layer 111 and the second n-type impurity diffusion layer 112.

  A silicon nitride film is provided on the back surface of the semiconductor substrate 117 as the passivation film 113 on the n-type impurity diffusion layer, which is an insulating film throughout. Hereinafter, the passivation film 113 on the n-type impurity diffusion layer is referred to as the passivation film 113 on the n-type layer.

  In addition, a plurality of elongated elongated n-type impurity diffusion layer upper grid electrodes 115 are arranged on the back surface of the semiconductor substrate 117, and the n-type impurity diffusion layer upper bus electrode is electrically connected to the n-type impurity diffusion layer upper grid electrode 115. 116 is provided orthogonal to the grid electrode 115 on the n-type impurity diffusion layer. The n-type impurity diffusion layer upper grid electrode 115 and the n-type impurity diffusion layer upper bus electrode 116 are electrically connected to a first n-type impurity diffusion layer 111 described later at the bottom surface part. Hereinafter, the n-type impurity diffusion layer upper grid electrode 115 is referred to as an n-type layer upper grid electrode 115. The n-type impurity diffusion layer upper bus electrode 116 is referred to as an n-type layer upper bus electrode 116.

  The n-type upper layer grid electrode 115 has a width of about 50 μm or more and about 150 μm and is arranged in parallel at a predetermined interval of 100 or more and 200 or less to collect electricity generated inside the semiconductor substrate 117. To do. In addition, the n-type layer-top bus electrode 116 has a width of about 0.5 mm or more and 1.0 mm or less, and 3 or more and 5 or less pieces are arranged per one solar cell. The electricity collected by the grid electrode 115 is taken out to the outside. Then, the n-type impurity diffusion layer upper electrode 114 is constituted by the n-type layer upper grid electrode 115 and the n-type layer upper bus electrode 116 as a back-side electrode having a comb shape. Hereinafter, the n-type impurity diffusion layer upper electrode 114 is referred to as an n-type layer upper electrode 114. In the second embodiment, the number of grid electrodes 115 on the n-type layer is 100, the number of bus electrodes 116 on the n-type layer is 4, and the electrode width of the grid electrode 115 on the n-type layer is 60 μm, n The electrode width of the mold layer upper bus electrode 116 is 1.0 mm. In FIG. 29, the number of the n-type upper-layer grid electrodes 115 is reduced for the sake of illustration.

  Below, the manufacturing method of the photovoltaic cell 101 concerning this Embodiment 2 is demonstrated. FIG. 31 is a flowchart for explaining an example of the manufacturing method of the solar battery cell 101 according to the second embodiment of the present invention. 32 to 42 are cross-sectional views of relevant parts for explaining an example of the manufacturing process of the solar battery cell 101 according to the second embodiment of the present invention. 32 to 42 are cross-sectional views of relevant parts corresponding to FIG.

(Silicon substrate preparation process)
In step 21, an n-type single crystal silicon substrate 102 is prepared as a semiconductor substrate. The n-type single crystal silicon substrate 102 is also manufactured in the same manner as the p-type single crystal silicon substrate 2 according to the first embodiment. Thereafter, the process similar to the process 2 in the first embodiment is performed until the texture structure forming process in the process 22. Is done.

(Boron-containing oxide film, protective oxide film forming process)
In step 23, the boron-containing oxide film 121 and the protective oxide film 122 receive light on the n-type single crystal silicon substrate 102 as shown in FIG. 32, due to the diffusion of p-type impurities into the n-type single crystal silicon substrate 102. It is formed on one surface to be a surface. Specifically, an n-type single crystal silicon substrate 102 heated to about 500 ° C. is supplied from an atmospheric pressure silane (SiH ₄ ) gas, oxygen (O ₂ ) gas, and diborane (B ₂ H ₆ ) supplied into the processing chamber. The boron-containing oxide film 121 having a thickness of 30 nm is first formed by being exposed to a mixed gas atmosphere with gas.

Then, after the boron-containing oxide film 121 is formed, the supply of diborane to the processing chamber is stopped, and the n-type single crystal silicon substrate 102 is exposed to a mixed gas atmosphere of silane and oxygen to have a thickness of 120 nm. A protective oxide film 122 is formed on the boron-containing oxide film 121. Here, a protective oxide film 122 of 120 nm is deposited on the boron-containing oxide film 121 as a capping film so that boron is not volatilized in the atmosphere in a later heat treatment step.

(P-type impurity diffusion layer forming step)
In step 24, the n-type single crystal silicon substrate 102 on which the boron-containing oxide film 121 and the protective oxide film 122 are formed is heat-treated, whereby the p-type impurity diffusion layer 103 is formed as shown in FIG. Specifically, a boat on which the n-type single crystal silicon substrate 102 is placed is inserted into a horizontal furnace, and heat treatment is performed at a temperature of about 1050 ° C. for about 30 minutes. By this heat treatment, boron is diffused from the boron-containing oxide film 121 to the surface layer of the n-type single crystal silicon substrate 102, and a p-type impurity diffusion layer 103 is formed on the surface layer on one surface side of the n-type single crystal silicon substrate 102. By performing such boron diffusion, the sheet resistance is 90 Ω / sq. About a p-type impurity diffusion layer 103 can be formed. Note that boron, which is a p-type impurity, has a lower diffusion coefficient into silicon than an n-type impurity typified by phosphorus. For this reason, in order to diffuse boron into the n-type single crystal silicon substrate 102, a heat treatment at a higher temperature than the n-type impurity diffusion step described later is required. That is, in the p-type impurity diffusion layer forming step, heat treatment is performed at a higher temperature than in the first diffusion step and the second diffusion step described later.

(N-type dopant-containing paste application process)
In step 25, in order to form the first n-type impurity diffusion layer 111 which is a high-concentration impurity diffusion layer in the n-type impurity diffusion layer 110, an n-type dopant-containing paste 123 as a diffusion source-containing coating agent is shown in FIG. As described above, the n-type single crystal silicon substrate 102 is applied and formed on the other surface as the back surface. The n-type dopant-containing paste 123 is printed in a comb shape corresponding to the shape of the n-type layer upper electrode 114 using a screen printing method. For n-type dopant-containing paste 123, the same material as n-type dopant-containing paste 21 in Embodiment 1 is used.

  The steps after step 26 basically form solar cells through the same steps as those after step 4 described in the first embodiment. However, although the selective emitter structure is formed as the selective impurity diffusion layer structure in the first embodiment, the selective BSF layer is formed as the selective impurity diffusion layer structure in the second embodiment.

  In the case of the second embodiment, the silicon substrate is n-type, and the boron-containing oxide film 121 and protective oxide film 122 formed up to step 24 in FIG. 31 are formed on the surface opposite to the surface on which the n-type dopant-containing paste is applied. And p-type impurity diffusion layer 103, which is a p-type emitter, is different from the first embodiment. Steps 26 to 30 in FIG. 31 correspond to steps 4 to 8 in FIG. 4, respectively. Further, Step 32 and Step 33 in FIG. 31 correspond to Step 9 and Step 10 in FIG. 4, respectively. Since the subsequent steps are substantially the same as those in the first embodiment, only the outline will be described.

(First diffusion process)
In step 26, the first diffusion step proceeds in the same manner as in step 4 of FIG. 4, and the first n-type impurity diffusion layer 111 is formed using the n-type dopant-containing paste 123, whereby the first n-type impurity diffusion layer 111 is formed. The n-type impurity can be diffused into the n-type single crystal silicon substrate 102 at a high concentration. As a result, the sheet resistance is 20 Ω / sq. Or more, 80Ω / sq. The first n-type impurity diffusion layer 111 is formed in the following range. Here, the sheet resistance value is assumed to be a case where n-type impurities are diffused into the p-type silicon substrate. When n-type impurities are diffused in an n-type silicon substrate, the sheet resistance value is measured to be lower than when n-type impurities are diffused in the same manner as when n-type impurities are diffused into a p-type silicon substrate. Also, the value is assumed to be when n-type impurities are diffused into the silicon substrate.

(Second diffusion process)
In step 27, processing and reaction proceed as in step 5 of FIG. By this second diffusion step, a second concentration that is relatively lower than that of the first n-type impurity diffusion layer 111 in the region other than the printing region of the n-type dopant-containing paste 123 on the surface of the n-type single crystal silicon substrate 102. As shown in FIG. 36, the second n-type impurity diffusion layer 112 is formed as shown in FIG. 36, and the first n-type impurity diffusion layer 111 and the second n-type impurity diffusion layer are formed as BSF layers. An n-type impurity diffusion layer 110 made of 112 is formed. As the BSF layer, the sheet resistance of the second n-type impurity diffusion layer 112 is 150 Ω / sq. By making it larger, it is possible to increase the photoelectric conversion efficiency. In addition, a phosphosilicate glass (PSG) layer, which is a vitreous layer 124 deposited on the surface during the diffusion process, is formed on the surface of the n-type single crystal silicon substrate 102 immediately after the second diffusion step.

(Pn separation step)
In step 28, processing is performed in the same manner as in step 6 of FIG.

(Glassy layer removal process)
In step 29, processing is performed in the same manner as in step 7 of FIG. However, in step 29, the boron-containing oxide film 121, the protective oxide film 122, the n-type dopant-containing paste 123, and the vitreous layer 124 formed on the surface of the n-type single crystal silicon substrate 102 are removed. Then, as shown in FIG. 37, the semiconductor substrate 102 made of n-type silicon as the first conductivity type layer and the p-type impurity diffusion layer 103 as the second conductivity type layer formed on the light receiving surface side of the semiconductor substrate 102. Thus, a semiconductor substrate 117 having a pn junction is obtained. Further, as the n-type impurity diffusion layer 110, a selective impurity diffusion layer structure including a first n-type impurity diffusion layer 111 and a second n-type impurity diffusion layer 112 on the back side of the n-type single crystal silicon substrate 102 is obtained.

(N-type layer passivation film forming step)
In step 30, as in step 8 of FIG. 4, an n-type impurity diffusion layer side passivation film is formed on the back surface of the semiconductor substrate 117 where the n-type impurity diffusion layer 110 is formed, as shown in FIG. A passivation film 113 on the mold layer is formed. The n-type upper passivation film 113 is a silicon nitride (SiN) film having a refractive index of 2.1 and a film thickness of 80 nm using a plasma CVD method and using a mixed gas of silane gas and ammonia (NH ₃ ) gas as a raw material. A film is formed. The n-type upper passivation film 113 may be formed by other methods such as a vapor deposition method or a thermal CVD method.

(P-type layer passivation film forming step)
In step 31, a p-type upper passivation film 104, which is a p-type impurity diffusion layer-side passivation film, is formed on the light receiving surface of the semiconductor substrate 117 where the p-type impurity diffusion layer 103 is formed. First, in order to obtain good passivation performance for the p-type impurity diffusion layer 103, an aluminum oxide film 105 having a negative fixed charge is formed with a film thickness of 5 nm as shown in FIG. Next, using the plasma CVD method, as shown in FIG. 40, a silicon nitride film 106 having a refractive index of 2.1 and a film thickness of 80 nm is formed. Further, the p-type upper passivation film 104 also functions as an antireflection film.

(Electrode formation process)
In step 32, the electrode is printed and dried by screen printing to form a dry electrode. First, as shown in FIG. 41, an Ag-containing paste 114a, which is an electrode material paste containing Ag and glass frit, is formed on the n-type upper grid electrode 115 on the n-type upper passivation film 113 on the back side of the semiconductor substrate 117. And it apply | coats to the shape of the bus electrode 116 on an n-type layer by screen printing. Thereafter, the Ag-containing paste 114a is dried, whereby a dry n-type layer upper electrode 114 to be an n-type impurity diffusion layer upper electrode is formed. The Ag-containing paste 114a is dried at 250 ° C. for 5 minutes.

  The step 32 of the second embodiment is different from the step 9 of the first embodiment in the electrode formation step on the p-type impurity diffusion layer 103 side. Next, as shown in FIG. 41, an AgAl-containing paste 107a, which is an electrode material paste containing Ag, Al, and glass frit, is formed on the p-type passivation film 104 on the light-receiving surface side of the semiconductor substrate 117. The shape of the upper grid electrode 108 and the p-type upper bus electrode 109 is applied by screen printing. Thereafter, the AgAl-containing paste 107a is dried, whereby the p-type layer upper electrode 107 in a dry state to be the p-type impurity diffusion layer upper electrode is formed. Here, in order to maintain good electrical continuity between the p-type upper electrode 107 and the p-type impurity diffusion layer 103, an AgAl paste containing about 3 wt% Al is used. The AgAl-containing paste 107a is dried at 250 ° C. for 5 minutes.

(Electrode firing process)
In step 33, the electrode material paste printed and dried on the light receiving surface side and the back surface side of the semiconductor substrate 117 is simultaneously fired. Specifically, the semiconductor substrate 117 is introduced into a firing furnace, and a short-time heat treatment is performed at 800 ° C. for 3 seconds at a peak temperature of about 600 ° C. to 900 ° C. in an air atmosphere. Thereby, the resin component in the electrode material paste disappears. On the light-receiving surface side of the semiconductor substrate 117, the glass material contained in the AgAl-containing paste 107a of the p-type upper electrode 107 melts and penetrates through the silicon nitride film 106 and the aluminum oxide film 105. Comes into contact with the silicon of the p-type impurity diffusion layer 103 and resolidifies. As a result, as shown in FIG. 42, the p-type layer upper grid electrode 108 and the p-type layer upper bus electrode 109 are obtained as the p-type layer upper electrode 107, and the p-type layer upper electrode 107 and the silicon of the semiconductor substrate 117 Is ensured. On the back surface side of the semiconductor substrate 117, the silver material is a first n-type impurity while the glass material contained in the Ag-containing paste 114 a of the n-type layer upper electrode 114 is melted and penetrates the passivation film 113 on the n-type layer. It contacts with the silicon of the diffusion layer 111 and resolidifies. As a result, an n-type layer upper grid electrode 115 and an n-type layer upper bus electrode 116 are obtained as the n-type layer upper electrode 114, and electrical conduction between the n-type layer upper electrode 114 and the silicon of the semiconductor substrate 117 is ensured. The

  By performing the steps as described above, the solar battery cell 101 according to the second embodiment shown in FIGS. 28 to 30 can be manufactured. Note that the order of arrangement of the paste, which is an electrode material, on the semiconductor substrate 117 may be switched between the light receiving surface side and the back surface side.

  Similar to the case of the first embodiment, the n-type impurity diffusion layer simulating the selective impurity diffusion layer structure on the back surface side of the solar battery cell 101 according to the second embodiment and the first n-type impurity diffusion layer measurement The sheet resistance corresponding to the impurity diffusion layer having the selective impurity diffusion layer structure is measured by using the solar cell evaluation substrate according to the second embodiment having the region 62 and the second n-type impurity diffusion layer measurement region 63. . Thereby, even when the impurity diffusion layer having the selective impurity diffusion layer structure is thinned, the same sheet resistance as that of the first n-type impurity diffusion layer 111 and the same sheet resistance as that of the second n-type impurity diffusion layer 112 in the solar battery cell 101 are obtained. Can be measured with high accuracy by a four-probe measuring instrument which is a sheet resistance measuring instrument using the four-probe method. Thereby, the sheet resistance between the first n-type impurity diffusion layer 111 and the second n-type impurity diffusion layer 112 can be accurately evaluated.

  Since the sheet resistance between the first n-type impurity diffusion layer 111 and the second n-type impurity diffusion layer 112 can be accurately evaluated by using the solar cell evaluation substrate according to the second embodiment, The first impurity concentration and the second impurity concentration in the solar battery cell 101 can be accurately estimated. This facilitates the derivation of the diffusion conditions that can optimize the first impurity concentration and the second impurity concentration in the solar battery cell 101, and can effectively improve the photoelectric conversion efficiency of the solar battery cell. It becomes.

Embodiment 3 FIG.
FIG. 43 is a cross-sectional view of a main part showing the configuration of the solar battery cell 131 according to the third embodiment of the present invention. 43 is a cross-sectional view corresponding to FIG. In addition, in FIG. 43, the same code | symbol is attached | subjected about the same member as the photovoltaic cell 101 concerning Embodiment 2. FIG. The solar cell 131 according to the third embodiment has a configuration in which the solar cell 101 according to the second embodiment is inverted. That is, in the solar cell 101 according to the second embodiment, a pn junction including the n-type single crystal silicon substrate 102 and the p-type impurity diffusion layer 103 is formed on the light receiving surface side of the solar cell 101, and the n-type single crystal. An n-type impurity diffusion layer 110 is formed as a BSF layer on the back side of the silicon substrate 102.

  On the other hand, in the solar cell 131 according to the third embodiment, a pn junction composed of the n-type single crystal silicon substrate 102 and the p-type impurity diffusion layer 103 is formed on the back side of the solar cell 131, and the n-type single crystal silicon is formed. An n-type impurity diffusion layer 110 is formed as an FSF (Front Surface Field) layer on the light receiving surface side of the substrate 102. The FSF layer has the same effect as the BSF layer. In the solar cell 131, the light L is incident from the n-type upper passivation film 113. That is, in the solar cell 131, the n-type upper passivation film 113 side is the light-receiving surface side, and the p-type upper passivation film 104 side is the back side. The solar battery cell 131 is formed by the same manufacturing method as that of the solar battery cell 101 according to the second embodiment.

  Then, as in the case of the second embodiment, the sheet resistance corresponding to the impurity diffusion layer having the selective impurity diffusion layer structure is measured using the evaluation substrate for the solar battery cell according to the second embodiment. As a result, even when the impurity diffusion layer having the selective impurity diffusion layer structure is thinned, the same sheet resistance as that of the first n-type impurity diffusion layer 111 and the same sheet resistance as that of the second n-type impurity diffusion layer 112 in the solar battery cell 131 are obtained. Can be measured with high accuracy by a four-probe measuring instrument which is a sheet resistance measuring instrument using the four-probe method. Thereby, the sheet resistance between the first n-type impurity diffusion layer 111 and the second n-type impurity diffusion layer 112 can be accurately evaluated.

  Therefore, as in the case of the second embodiment, the sheet resistance between the first n-type impurity diffusion layer 111 and the second n-type impurity diffusion layer 112 can be accurately evaluated. The impurity concentration and the second impurity concentration can be accurately estimated. This facilitates the derivation of the diffusion conditions that can optimize the first impurity concentration and the second impurity concentration in the solar cell 131, and can effectively improve the photoelectric conversion efficiency of the solar cell. It becomes.

Embodiment 4 FIG.
In the fourth embodiment, a solar cell evaluation method using the monitor wafer 61 which is the above-described solar cell evaluation substrate will be described. The formation of selective emitters is important for increasing the photoelectric conversion efficiency of solar cells. In particular, the selective emitter can be formed easily and inexpensively by using the manufacturing method of forming the selective emitter using the dopant paste as described above.

  On the other hand, as the structure of the selective emitter, the grid electrode is required to be thinned from 50 μm to 150 μm from the viewpoint of high photoelectric conversion efficiency. When the grid electrode is thinned, it is necessary to thin the high-concentration impurity diffusion layer below the grid electrode. However, with the structure of the solar cell, the impurity diffusion layer is required due to the structure of the sheet resistance measuring device. The sheet resistance of the impurity diffusion layer could not be evaluated in order to confirm the impurity concentration.

  In the solar cell evaluation method of the fourth embodiment, by using the monitor wafer described above, it is possible to provide a diffusion region that can be measured with a sheet resistance measuring instrument while simulating the impurity diffusion region of the selective emitter structure, A solar cell evaluation method for evaluating the impurity concentration of the solar cell will be described.

  FIG. 44 is a flowchart for explaining an example of the solar battery evaluation method according to the fourth embodiment of the present invention. Here, the solar cell 1 evaluation method according to the first embodiment will be described as an example. Since the monitor wafer 61 is created in the same process as the solar cell 1, the method for manufacturing the monitor wafer 61 is basically the same as the method for manufacturing the solar cell 1.

  First, step 1 and step 2 described in the flowchart of FIG. 4 are performed.

(N-type dopant-containing paste application process)
In step 41, n-type dopant-containing paste 21 is applied and formed on one surface to be a light-receiving surface in p-type single crystal silicon substrate 2. Here, the n-type dopant-containing paste 21 has the same pattern as that shown in FIG. 19, and the n-type impurity of the solar cell 1 simulating the impurity diffusion region of the selective emitter structure, as in the production of the solar cell 1. The comb-shaped region corresponding to the diffusion layer 3 and the region corresponding to the first n-type impurity diffusion layer measurement region 62 are printed using the screen printing method. However, the n-type dopant-containing paste 21 is not formed in the region corresponding to the second n-type impurity diffusion layer measurement region 63 in the region corresponding to the n-type impurity diffusion layer 3.

  That is, the n-type dopant-containing paste 21 includes a region corresponding to the n-type impurity diffusion layer 3 and a region corresponding to the first n-type impurity diffusion layer measurement region 62 and corresponds to the second n-type impurity diffusion layer measurement region 63. Printed in the area excluding the area. The n-type dopant-containing paste 21 is composed of a glass powder containing a diffusing element and an organic solvent for obtaining a viscosity suitable for printing. The organic solvent is a glass powder containing a diffusing element that evaporates in a drying step after printing. It becomes solidified on the substrate surface.

(First diffusion process)
Next, in step 42, the same processing as in step 4 described in the flowchart of FIG. 4 is performed. By this first diffusion step, phosphorus, which is an n-type impurity, has a relatively high concentration from the n-type dopant-containing paste 21 to the lower region of the printing region of the n-type dopant-containing paste 21 on the surface of the p-type single crystal silicon substrate 2. The first n-type impurity diffusion layer 4 and the first n-type impurity diffusion layer measurement region 62 are formed with the pattern shown in FIG.

  That is, the p-type single crystal silicon substrate 2 is aligned at equal intervals in the direction orthogonal to the central axis with the plate surface parallel to the central axis of the quartz tube, as in the manufacturing of the solar battery cell 1. Place them vertically at regular intervals. The interval between the p-type single crystal silicon substrates 2 is about 2 mm to 5 mm. When this interval is reduced, the flow of the source gas and carrier gas between the p-type single crystal silicon substrates 2 becomes non-uniform, and the uniformity of impurity diffusion concentration decreases. Further, when this interval is increased, the number of p-type single crystal silicon substrates 2 that can be processed at one time is reduced, and productivity is lowered.

  Then, by raising the substrate temperature without flowing the source gas having the saturated vapor of the liquid diffusion source in the thermal diffusion furnace 31, the region corresponding to the n-type impurity diffusion layer 3 and the first n-type impurity diffusion layer measurement region 62 are formed. A first diffusion step is performed in which n-type impurities are diffused into the p-type single crystal silicon substrate 2 from the n-type dopant-containing paste 21 applied to the corresponding region.

(Second diffusion process)
Next, in step 43, the same processing as step 5 described in the flowchart of FIG. 4 is performed. By this second diffusion step, the second concentration which is relatively lower than that of the first n-type impurity diffusion layer 4 in the region other than the printing region of the n-type dopant-containing paste 21 on the surface of the p-type single crystal silicon substrate 2. The phosphorus, which is an n-type impurity, is thermally diffused to the diffusion concentration of n, and the second n-type impurity diffusion layer 5 and the second n-type impurity diffusion layer measurement region 63 are formed in the pattern shown in FIG.

  That is, after the first diffusion step, the impurity diffusion layer is formed on the entire surface of the substrate by flowing the source gas and the carrier gas in the thermal diffusion furnace 31 without taking out the substrate from the thermal diffusion furnace 31 and continuously with the first diffusion step. A second diffusion step is performed to form In the second diffusion step, a diffusion source is supplied between the p-type single crystal silicon substrates 2 by the source gas. For this reason, on the surface of the p-type single crystal silicon substrate 2 on which the n-type dopant-containing paste 21 is applied, the n-type dopant-containing paste 21 is not applied, and the impurity diffusion layer in the lower region of the grid electrode adjacent in the width direction An impurity diffusion layer can be formed in an inter-grid region that is an elongated region corresponding to the region. Thereby, the monitor wafer 61 is formed.

  However, the impurity diffusion source contained in the source gas is consumed not only by the dopant glass, that is, phosphorus glass, but also by the reaction with the adjacent n-type dopant-containing paste 21 on the substrate surface in the inter-grid region. That is, the impurity diffusion concentration in the inter-grid region varies depending on the configuration of the application region of the adjacent n-type dopant-containing paste 21. Therefore, in order to appropriately evaluate the impurity diffusion concentration in the inter-grid region, it is necessary to use a substrate on which the second diffusion process has been performed with a structure similar to the structure of the solar battery cell. Therefore, on the monitor wafer, an impurity diffusion layer simulating the selective emitter structure or the impurity diffusion region of the selective BSF layer is formed.

(Sheet resistance measurement process)
Next, in step 44, the first n-type impurity diffusion layer measurement region 62, which is the first impurity concentration measurement region, and the second impurity concentration measurement region in the p-type single crystal silicon substrate 2 taken out from the thermal diffusion furnace 31. The sheet resistance with respect to the second n-type impurity diffusion layer measurement region 63 is measured by a four-probe measuring instrument, and the first impurity concentration and the second impurity concentration in the solar battery cell 1 are evaluated based on the measurement result. .

  As described above, the first n-type impurity diffusion layer measurement region 62 has the same depth and n-type impurity concentration as the first n-type impurity diffusion layer 4, and the second n-type impurity diffusion layer measurement region 63 includes the second n-type impurity diffusion layer measurement region 63. It has the same depth and n-type impurity concentration as the type impurity diffusion layer 5. Therefore, according to the sheet resistance measurement results of the first n-type impurity diffusion layer measurement region 62 and the second n-type impurity diffusion layer measurement region 63, the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5 of the solar cell 1 are measured. Sheet resistance can be confirmed. Then, due to the sheet resistance of the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5, the first impurity concentration of the first n-type impurity diffusion layer 4 and the second n-type impurity diffusion layer 5 of the solar cell 1 are determined. 2 can be accurately evaluated.

  Note that the solar cell evaluation method is not limited to the selective emitter structure, or the impurity concentration of the selective impurity diffusion layer structure such as the selective BSF layer structure and the selective FSF layer structure can be evaluated in the same manner as described above. Is possible.

  The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

  DESCRIPTION OF SYMBOLS 1 Solar cell, 2 Semiconductor substrate, 3 n-type impurity diffusion layer, 4 1st n-type impurity diffusion layer, 5 2nd n-type impurity diffusion layer, 6 Passivation film on n-type impurity diffusion layer, 7 N-type impurity diffusion layer upper electrode 7a Ag-containing paste, 8 n-type impurity diffusion layer upper grid electrode, 9 n-type impurity diffusion layer upper bus electrode, 10 p-type impurity diffusion layer upper electrode, 10a Al-containing paste, 11 semiconductor substrate, 21 n-type dopant-containing paste , 22 Vitreous layer, 23 Grid pattern, 24 Bath pattern, 31 Thermal diffusion furnace, 41 p-type silicon substrate, 42 n-type impurity diffusion layer, 43 Current probe, 44 Voltage probe, 45 Applied current source, 46 Voltmeter 51 Application region 52 Non-application region 61 Monitor wafer 62 First n-type impurity diffusion layer measurement region 63 Second n-type impurity diffusion layer measurement Constant region, 64 contact region, 101 solar cell, 102 semiconductor substrate, 103 p-type impurity diffusion layer, 104 p-type impurity diffusion layer passivation film, 107 p-type impurity diffusion layer electrode, 108 p-type impurity Grid electrode on diffusion layer, bus electrode on 109 p-type impurity diffusion layer, 110 n-type impurity diffusion layer, 111 first n-type impurity diffusion layer, 112 second n-type impurity diffusion layer, 113 passivation film on n-type impurity diffusion layer, 114 n-type impurity diffusion layer upper electrode, 115 n-type impurity diffusion layer upper electrode, 116 n-type impurity diffusion layer upper bus electrode, 117 semiconductor substrate, 121 boron-containing oxide film, 122 protective oxide film, 123 n-type dopant-containing paste .

Claims (8)

A first conductivity type semiconductor substrate;
A plurality of elongated grids that are provided on the first surface of the semiconductor substrate and have impurities of the second conductivity type at a first impurity concentration in a region corresponding to the shape of the grid electrode of the solar battery cell to be evaluated An impurity region;
A second conductivity type impurity having a second impurity concentration lower than the first impurity concentration is provided in a region between the grid impurity regions adjacent to each other in the width direction and provided on the first surface of the semiconductor substrate. An inter-grid impurity region having,
A first impurity concentration evaluation region provided on the first surface of the semiconductor substrate, having a size greater than or equal to the interval between the grid impurity regions, and having a second conductivity type impurity at the first impurity concentration;
The board | substrate for evaluation of the photovoltaic cell characterized by providing. A first conductivity type semiconductor substrate;
A plurality of elongated grids that are provided on the first surface of the semiconductor substrate and have impurities of the second conductivity type at a first impurity concentration in a region corresponding to the shape of the grid electrode of the solar battery cell to be evaluated An impurity region;
A second conductivity type impurity having a second impurity concentration lower than the first impurity concentration is provided in a region between the grid impurity regions adjacent to each other in the width direction and provided on the first surface of the semiconductor substrate. An inter-grid impurity region having,
A second impurity concentration evaluation region provided on the first surface of the semiconductor substrate, having a size equal to or larger than the interval between the grid impurity regions and having a second conductivity type impurity layer at the second impurity concentration; ,
With
The second impurity concentration evaluation region has a size of 8 mm × 8 mm square or less in the plane of the semiconductor substrate;
Evaluation substrate of a solar cell according to claim.   A region in which the second impurity concentration evaluation region is not disposed, and is arranged side by side with the second impurity concentration evaluation region, and includes a standard band that is a region having the same width as the second impurity concentration evaluation region;
  The evaluation substrate for a solar battery cell according to claim 2, wherein:   A first impurity concentration evaluation region provided on the first surface of the semiconductor substrate and having an impurity of a second conductivity type at the first impurity concentration;
  The second impurity concentration evaluation region, the standard band, and the first impurity concentration evaluation region are sequentially arranged;
  The substrate for evaluation of a solar battery cell according to claim 3. A second impurity concentration evaluation region provided on the first surface of the semiconductor substrate, the second impurity concentration evaluation region having a size equal to or larger than a distance between the grid impurity regions and having a second conductivity type impurity layer at the second impurity concentration; Preparing,
The evaluation substrate for a solar battery cell according to claim 1. The first impurity concentration evaluation region and the second impurity concentration evaluation region have dimensions of 1 mm × 4 mm square or more and 8 mm × 8 mm square or less in the plane of the semiconductor substrate;
The solar cell evaluation substrate according to claim 5 . The first impurity concentration evaluation region is disposed in four or more positions in a plane of the semiconductor substrate with respect to a center line that equally divides the plane of the semiconductor substrate on the left and right.
In the plane of the semiconductor substrate, the second impurity concentration evaluation region is targeted with respect to a central point in the plane of the semiconductor substrate and a center line that equally divides the plane of the semiconductor substrate in the left-right direction. Being arranged at four or more positions,
The evaluation substrate for a solar battery cell according to claim 5 or 6 . A solar cell evaluation method for evaluating a solar cell using the solar cell evaluation substrate according to any one of claims 5 to 7 ,
Second conductivity containing impurities of a second conductivity type in a region including the grid impurity region and the first impurity concentration evaluation region on the first surface of the semiconductor substrate and excluding the second impurity concentration evaluation region. A second conductivity type dopant paste application step of applying a type dopant containing paste;
A first diffusion step of raising the temperature of the semiconductor substrate without flowing a source gas in a state where the semiconductor substrate is inserted into a thermal diffusion furnace together with the solar battery cell;
Along with the solar cells, in the thermal diffusion furnace, the semiconductor substrate is heated while flowing the source gas in succession to the first diffusion step without taking out the semiconductor substrate from the thermal diffusion furnace. A second diffusion step of forming a battery cell evaluation substrate;
A measurement step of measuring the sheet resistance of the first impurity concentration evaluation region and the second impurity concentration evaluation region of the semiconductor substrate taken out from the thermal diffusion furnace;
The evaluation method of the photovoltaic cell characterized by including.

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