JP6607608B2 - Radar equipment - Google Patents

Description

  The present invention relates to an interference reduction apparatus.

In recent years, depletion of frequency resources has become a problem due to the spread of various wireless communication systems. Therefore, it is required to reduce unnecessary waves (spurious) emitted outside the frequency band assigned to each communication system as much as possible so that communication failure does not occur due to interference or interference between different communication systems. Yes. Internationally, various wireless communication systems are required to achieve a strict attenuation level (such as ITU-R recommendation SM.1541).
Similar to the radio communication system, the radar apparatus is required to achieve a more severe attenuation level in order to prevent interference or interference caused by unnecessary waves.

  A technique for preventing interference between adjacent radar devices has already been studied (for example, Patent Document 1). However, it has not been a technique for achieving a severe attenuation level as described above. In order to meet these requirements, the development and popularization of radar devices that use solid state (solid elements), which can easily suppress spurious, from magnetrons, which are easy to obtain high-power oscillation signals but are difficult to suppress spurious. Progressing.

  However, for example, when using a magnetron in a ship radar, a transmission power of several tens of kilometers [W] is obtained, whereas when using a solid state, only a few hundred [W] can be obtained. In general, the radar apparatus has a short search distance when the peak value of the transmission power is low. Therefore, the radar apparatus using the solid state has a short search distance.

  Therefore, the decrease in search performance caused by the decrease in transmission power that occurs when the magnetron is changed to the solid state is compensated by combining the signal transmission time and the pulse compression processing. This achieves a strict attenuation level against spurious and maintains search performance.

  However, in other communication systems that use a frequency band adjacent to a frequency band allocated for use of a radar device (hereinafter referred to as a radar band), even though the attenuation level against spurious is satisfied, A signal transmitted from the device may cause interference due to interference or interference.

  In general, a receiving apparatus used in a communication system performs demodulation and decoding by down-converting a received signal in a frequency band assigned to the communication system to an intermediate frequency or a baseband frequency. At this time, when the relationship between the radar band, the frequency band of the communication system, and the local oscillation frequency used for down-conversion by the receiving apparatus of the communication system is as follows, the above-described communication failure may occur.

  FIG. 10 is a diagram illustrating an example of frequency band allocation and local oscillation frequency in the reception device when a communication failure occurs. As shown in FIG. 10 (a), the frequency band from the frequency F1 to the frequency F2 is allocated to the radar band, and the frequency band from the frequency F3 to the frequency F4 is allocated to another communication system. The case where the local oscillation frequency FLo in is set between the frequency F2 and the frequency F3 will be described.

  FIG. 10B is a diagram illustrating a frequency band of a signal obtained by down-conversion by the receiving apparatus when the frequency allocation as illustrated in FIG. 10A is performed. A desired signal in the frequency band from frequency F3 to frequency F4 allocated to the communication system is down-converted and converted to a signal in the frequency band from frequency (F3-FLo) to frequency (F4-FLo). Further, a signal in the radar band from the frequency F1 to the frequency F2 including the image frequency that is lower than the local oscillation frequency FLo is also converted into a signal in the frequency band from the frequency (FLo-F1) to the frequency (FLo-F2). .

  As described above, the pulse signal transmitted from the radar device appears as an image signal anywhere from the frequency (FLo-F1) to the frequency (FLo-F2), and from the frequency (F3-FLo) to the frequency (F4-FLo). It overlaps with the frequency band up to. At this time, the pulse signal transmitted from the radar apparatus may cause interference due to interference or interference in communication in the communication system.

  That is, depending on the setting of the local oscillation frequency used in the receiving device of another communication system, the signal in the radar band becomes an image signal that overlaps the signal in the communication system. Will be caused. On the other hand, a receiving apparatus used in a communication system usually has a function of suppressing an image frequency signal so as to suppress interference caused by an image frequency signal.

JP 2005-195450 A

  However, when the reception device and the radar device are close to each other, the reception device cannot sufficiently suppress the image frequency signal when the reception power of the signal transmitted from the radar device is significantly higher than the reception power of the desired signal. The desired signal may not be demodulated and decoded.

  In addition, when switching from magnetron to solid state in a radar device, the transmission time is extended to compensate for the decrease in search capability due to a decrease in transmission power, so that interference generated in the receiver of the communication system may appear more prominently. There is.

  The present invention has been made in view of the above situation, and an object thereof is a case where a frequency band allocated to a radar apparatus corresponds to an image frequency in a receiving apparatus used in another communication system. Another object of the present invention is to provide an interference reduction device that can reduce interference or interference.

In order to solve the above problem, the present invention is such that a transmission wave transmitted as a sequence of n (≧ 2) pulses of different frequencies f ₁ ,..., F _n is reflected by a target within a pulse repetition period. the different frequencies _f 1 and the reflected waves arriving by, ..., component _C f1 of _{f n, ...,} separating means for separating the _{C fn,} the different frequencies _f 1, ..., a plurality P Street proportional to the distance _{f n} phase shift amount of _{(φ 11, ..., φ 1n} ), ..., (φ P1, ..., φ Pn) said phase shift process according to component _C f1, _..., applied respectively to the _{C fn,} and phase shift amount (phi ₁₁ ,..., Φ _1n ),..., (Φ _P1 ,..., Φ _Pn ), and phase combining means for obtaining the sum of the plurality of P types by combining the phases. And a processing object setting means for setting a radar signal processing target to the sum.

The present invention also provides a reflected wave that arrives when a transmission wave transmitted as a sequence of n (≧ 2) pulses of different frequencies f ₁ ,..., F _n within a pulse repetition period is reflected by a target. the different frequencies _f 1, ..., component _C f1 of _{f n, ...,} separating means for separating the _{C fn,} the component _C f1, _..., a frequency analysis of the _{C fn} individually obtain the frequency spectrum of the n different a frequency analysis means, for each frequency spectrum of the plurality n as constituted by a processing target setting means as a target of the radar signal processing by combining component power is at a maximum.

The present invention also provides a reflected wave that arrives when a transmission wave transmitted as a sequence of n (≧ 2) pulses of different frequencies f ₁ ,..., F _n within a pulse repetition period is reflected by a target. Separating means for separating the components C _f1 ,..., C _fn of the different frequencies f ₁ ,..., F _n , individually separated by the separating means over a plurality of N cycles of the pulse repetition period, and column of the plurality n of times corresponding to the components in the period of _{(C f11, ..., C f1N} ), ..., (C fn1, ..., C fnN) to each of said different frequencies _{f 1,} ..., a distance _{f n} proportional phase shift _{(φ 11, ..., φ 1N} ), ..., (φ n1, ..., φ nN) subjected to phase shift processing by, and the phase shift amount _{(φ 11, ..., φ 1N} ), ..., _{(φ n1, ..., φ nN} ) the sum of the N ways by phase-combining each A phase combining means, wherein among the sum of a plurality N Street, constructed and a processing target setting means for the sum power is maximized subject to the radar signal processing.

  According to this invention, even if the pulse signal transmitted from the radar apparatus corresponds to the image frequency in the receiving apparatus used in another communication system, it is possible to reduce interference or interference.

It is a schematic block diagram which shows the structure of the radar apparatus 1 in 1st Embodiment. 3 is a diagram illustrating an example of a sequence of pulse signals transmitted by a transmission unit 11. FIG. It is a figure which shows the image of the frequency characteristic of a pulse signal transmitted by the transmission part 11, and an amplitude characteristic. It is a schematic block diagram which shows the structure of the signal synthetic | combination part 171a between PRI in 1st Embodiment. It is a schematic block diagram which shows the structure of the different frequency signal synthetic | combination part 175 in 1st Embodiment. It is a schematic diagram which shows the process of the different frequency signal synthetic | combination part 175 in 1st Embodiment. It is a schematic diagram which shows the outline | summary of the process in the radar apparatus 1 of 1st Embodiment. It is a schematic block diagram which shows the structure of the signal synthetic | combination part 271a between PRI comprised with the radar apparatus in 2nd Embodiment. It is a figure which shows an example of the setting of the carrier wave frequency f1, f2, and f3 in 1st and 2nd embodiment. It is a figure which shows an example of allocation of the frequency band in case a communication failure generate | occur | produces, and the local oscillation frequency in a receiver. It is a schematic block diagram which shows one structure of the radar apparatus 3 in 3rd Embodiment. It is a schematic block diagram which shows the structure of the different frequency signal synthetic | combination part 371a in 3rd Embodiment. It is a schematic diagram which shows the process of the different frequency signal synthetic | combination part 371a in 3rd Embodiment. It is a schematic block diagram which shows the structure of the signal synthetic | combination part 376 between PRI in 3rd Embodiment. It is a schematic diagram which shows the outline | summary of the process in the radar apparatus 3 of 3rd Embodiment. It is a schematic block diagram which shows the structure of the different frequency signal synthetic | combination part 471a with which the radar apparatus in 4th Embodiment is equipped.

  Hereinafter, a radar apparatus according to an embodiment of the present invention will be described based on four embodiments with reference to the drawings.

  All of the radar devices according to the four embodiments described below have a transmission unit that transmits pulse signals in order of different carrier frequencies f1, f2, and f3 in a predetermined cycle, and a pulse signal transmitted from the transmission unit is a detection target. And a receiving unit that receives a reflected signal reflected by the target. In each embodiment, the way of dividing and synthesizing the reflected signal received by the receiving unit is different.

(First embodiment)
FIG. 1 is a schematic block diagram illustrating a configuration of a radar apparatus 1 according to the first embodiment. As shown in the figure, the radar apparatus 1 includes a transmission unit 11, an antenna 12, a reception unit 13, an A / D (Analog / Digital) conversion unit 14, a frequency division unit 15, a signal storage unit 16, and a signal. A synthesis unit 17 and an output processing unit 18 are provided.

  The transmission unit 11 transmits pulse signals via the antenna 12 in the order of different carrier frequencies f1, f2, and f3 determined in advance. That is, the transmission unit 11 transmits a pulse signal by performing frequency hopping to change the carrier frequency. Here, the carrier wave frequencies f1, f2, and f3 are set using the fact that the amount of frequency phase shift due to reflection from the object to be detected (target target) is proportional to the frequency interval. Specifically, it is set so that f2 = f1 + Δf and f3 = f1 + 2 × Δf. Further, the pulse signal transmitted from the transmitter 11 may be a chirp pulse in which the frequency is linearly drawn.

  The pulse signal transmitted by the transmission unit 11 will be described with reference to FIGS. FIG. 2 is a diagram illustrating an example of a series of pulse signals transmitted by the transmission unit 11. In the figure, the horizontal axis indicates time, and the vertical axis indicates transmission power. As shown in FIG. 2, the transmission unit 11 according to the present embodiment transmits a pulse signal that is predetermined by three different carrier frequencies f1, f2, and f3 in each pulse signal transmission period (PUL). Transmit continuously for time Trx. The transmission time of each of the carrier frequencies f1, f2, and f3 is, for example, time (Trx / 3). Here, the transmission time Trx is a transmission time of a pulse signal required to satisfy search performance required for detecting an object.

  FIG. 3 is a diagram illustrating an image of frequency characteristics and amplitude characteristics of a pulse signal transmitted by the transmission unit 11. FIG. 3A shows the frequency characteristics of the pulse signal. The horizontal axis indicates time, and the vertical axis indicates frequency. As shown in FIG. 3A, in each PRI, pulse signals are transmitted by switching carrier frequencies in the order of carrier frequencies f1, f2, and f3. FIG. 3B shows the amplitude characteristics of the pulse signal. The horizontal axis indicates time, and the vertical axis indicates the maximum value of the amplitude (peak value, peak value). As shown in FIG. 3B, transmission is performed so that the maximum value of the amplitude of the pulse signal transmitted at each carrier frequency is the same.

  Returning to FIG. 1, the receiving unit 13 receives, via the antenna 12, a reflected signal in which the pulse signal transmitted from the antenna 12 is reflected by the target to be detected. The A / D converter 14 performs analog-digital conversion on the reflected signal received by the receiver 13 and outputs the reflected signal to the frequency divider 15. The frequency dividing unit 15 divides the reflected signal digitized by the bandpass filter having the carrier frequencies f1, f2, and f3 as center frequencies into signals of three frequency bands.

  The signal storage unit 16 stores the signal divided into three by the frequency dividing unit 15 for each corresponding carrier frequency. Specifically, the signal storage unit 16 includes a first signal storage unit 161a, a second signal storage unit 161b, and a third signal storage unit 161c. The first signal storage unit 161a stores a signal in a frequency band corresponding to the carrier frequency f1. Similarly to the first signal storage unit 161a, the second signal storage unit 161b and the third signal storage unit 161c store signals in frequency bands corresponding to the carrier frequency f2 and the carrier frequency f3. The first signal storage unit 161a, the second signal storage unit 161b, and the third signal storage unit 161c are arranged in chronological order so that reflected signals in the PRI are processed in parallel by the signal synthesis unit 17. Store the signal.

  The signal synthesizing unit 17 synthesizes a time-series signal composed of signals stored in the signal storage unit 16 over a predetermined number of PRIs and outputs the synthesized signal to the output processing unit 18. The signal synthesizer 17 further synthesizes a phase synthesizer 171 that performs phase synthesis for each of the carrier frequencies f1, f2, and f3, and a signal that is further synthesized by the phase synthesizer 171 for each of the carrier frequencies f1, f2, and f3. And an inter-frequency signal synthesizing unit 175 that outputs the signals as one signal.

  The phase synthesizer 171 includes inter-PRI signal synthesizers 171a, 171b, and 171c corresponding to the carrier frequencies f1, f2, and f3, respectively. The inter-PRI signal synthesizer 171a outputs a signal corresponding to the carrier frequency f1 by coherent synthesis (phase addition) over 4 PRI. Similarly to the inter-PRI signal synthesizer 171a, the inter-PRI signal synthesizers 171b and 171c add and output signals corresponding to the carrier frequencies f2 and f3 over 4 PRIs. In other words, the phase synthesizer 171 performs Doppler filter bank processing on the signal corresponding to each carrier frequency for each carrier frequency f1, f2, and f3.

  The inter-frequency signal synthesizer 175 synthesizes the signals calculated by phase addition over 4 PRI for each of the carrier frequencies f1, f2, and f3 by the inter-PRI signal synthesizers 171a to 171c. The output processing unit 18 performs further processing on the signal synthesized by the inter-frequency signal synthesizing unit 175 and outputs the processed signal. For example, processing such as conversion into a video signal for display on an externally connected display device is performed.

  An example of a specific configuration of the inter-PRI signal synthesis units 171a to 171c will be described. FIG. 4 is a schematic block diagram showing the configuration of the inter-PRI signal synthesis unit 171a in the present embodiment. Since the inter-PRI signal synthesizers 171b and 171c have the same configuration as the inter-PRI signal synthesizer 171a, description thereof is omitted.

  The inter-PRI signal synthesis unit 171a includes a quadrature detector 172 and accumulators 173a and 173b. The quadrature detector 172 sequentially reads out signals corresponding to the carrier frequencies f1 for four consecutive PRIs stored in the first signal storage unit 161a, sequentially performs quadrature detection on the read signals, and converts them into I and Q signals. To separate. The amplitudes of the I signal and the Q signal are the same, and the phases are different from each other by 90 degrees. In the subsequent processing, the I signal is treated as the real part of the complex number, and the Q signal is treated as the imaginary part of the complex number. The quadrature detection can be realized by, for example, a method of mixing signals of the same frequency whose phases are different from each other by 90 degrees with a signal to be detected, a method using a Hilbert filter, or the like.

  The accumulator 173a adds the I signal output from the quadrature detector 172 by 4PRI and outputs the result. The accumulator 173b adds the Q signal output from the quadrature detector 172 by 4PRI and outputs the result. The inter-PRI signal synthesizer 171a reads the signals stored in the first signal storage unit 161a over 4 PRIs as described above, in the order of PRI1 to PRI4, PRI2 to PRI5,. Phase addition is performed in which the I signal and the Q signal based on the read signal are added independently, and the signals are sequentially output.

  Next, an example of a specific configuration of the inter-frequency signal synthesizing unit 175 will be described. FIG. 5 is a schematic block diagram showing the configuration of the inter-frequency signal synthesizing unit 175 in the present embodiment. As shown in the figure, the inter-frequency signal synthesizer 175 has phase shifters 176 and 177, adders 178a and 178b, and a maximum value determiner 179.

  The phase shifters 176 and 177 shift the phase of the signals output from the inter-PRI signal synthesis units 171b and 171c according to a combination of a plurality of predetermined phase shift amounts, and output the signals. The adder 178a adds the I signal output from the inter-PRI signal synthesis unit 171a, the I signal output from the phase shifter 176, and the I signal output from the phase shifter 177. The adder 178b adds the Q signal output from the inter-PRI signal synthesis unit 171a, the Q signal output from the phase shifter 176, and the Q signal output from the phase shifter 177.

  That is, the adders 178a and 178b add the phases of the carrier frequency f1 output from the inter-PRI signal synthesis unit 171a and the carrier frequencies f2 and f3 phase-shifted by the phase shifters 176 and 177. Maximum value determiner 179 calculates the square sum square root of the phase-added signal for each phase shift amount combination, and selects and outputs the signal having the largest square sum square root among the plurality of phase shift amount combinations.

  Here, a case will be described in which a predetermined combination of a plurality of phase shift amounts is set as follows with reference to a signal corresponding to the carrier frequency f1. Set to 4 combinations of (0, 0, 0), (0, π / 2, 2π / 2), (0, 2π / 2, 4π / 2), (0, 3π / 2, 6π / 2) It is assumed that Here, (a, b, c) represents a combination of phase shift amounts, where a is the phase shift amount for the signal corresponding to the carrier frequency f1, and b is the phase shift amount for the signal corresponding to the carrier frequency f2. C is the amount of phase shift for the signal corresponding to the carrier frequency f3.

  The phase shifter 176 performs phase shift amounts of 0, π / 2, 2π / 2, and 3π / 2 with respect to the I signal and the Q signal corresponding to the carrier frequency f2 synthesized by the inter-PRI signal synthesizer 171b. The phase-shifted signals are output in order. The phase shifter 177 performs phase shift amounts of 0, 2π / 2, 4π / 2, and 6π / 2 with respect to the I signal and the Q signal corresponding to the carrier frequency f3 synthesized by the inter-PRI signal synthesis unit 171c. The phase-shifted signals are output in order.

  For each combination of the above phase shift amounts, the adder 178a outputs the I signal output from the inter-PRI signal synthesizer 171a, the I signal output from the phase shifter 176, and the I signal output from the phase shifter 177. Add the signal. For each combination of the above phase shift amounts, the adder 178a outputs a Q signal output from the inter-PRI signal synthesis unit 171a, a Q signal output from the phase shifter 176, and a Q signal output from the phase shifter 177. Add the signal. That is, the adders 178a and 178b perform phase addition for independently adding the phase-shifted I signal and Q signal for each combination of the above-described phase shift amounts.

  The maximum value determiner 179 calculates the square sum square (amplitude) of the I signal and the Q signal added by the adders 178a and 178b for each combination of the four phase shift amounts, and calculates the four phase shift amounts. The I signal and Q signal having the largest sum of squares in the combination are selected and output.

FIG. 6 is a schematic diagram showing processing of the inter-frequency signal synthesizing unit 175 in the present embodiment.
As shown in the figure, the signals corresponding to the carrier frequencies f1, f2, and f3 and output from the inter-PRI signal synthesizers 171a to 171c are subjected to phase addition in four ways. Then, the result having the largest square sum square (amplitude) is selected and output from the four phase addition results. Thereby, SNR (Signal-Noise Ratio; signal-to-noise ratio) can be improved by 2.6 times. In this embodiment, there are four combinations of phase shift amounts. However, if the number of phase shift amount combinations (phase pattern) is increased infinitely, the SNR can be improved to three times. Thus, the inter-frequency signal synthesizer 175 rotates the phase of the signals corresponding to the carrier frequencies f1, f2, and f3 to be synthesized in proportion to the difference in the carrier frequencies by combining the phase shift amounts. Then, phase addition (coherent synthesis) is performed so that the amplitude is maximized.

  FIG. 7 is a schematic diagram showing an outline of processing in the radar apparatus 1 of the present embodiment. In the radar apparatus 1, as shown in the figure, the transmission unit 11 periodically transmits pulse signals in the order of the carrier frequencies f1, f2, and f3 in each PRI, and receives the reflected signal reflected by the object. To do. The received reflected signal is divided into signals corresponding to the carrier frequencies f1, f2, and f3 by the frequency dividing unit 15, and the first signal storage unit 161a and the second signal storage unit 161b provided in the signal storage unit 16 are provided. And stored in the third signal storage unit 161c.

  The signals corresponding to the carrier frequencies f1 to f3 stored in the first signal storage unit 161a, the second signal storage unit 161b, and the third signal storage unit 161c are subjected to 4 PRIs by the inter-PRI signal synthesis units 171a to 171c. The phases are added, and further, the signals are combined into one signal by the inter-frequency signal combining unit 175 and output. In this way, the pulse signals transmitted at the carrier frequencies f1, f2, and f3 can be combined to improve the SNR, and the transmission time at each of the three carrier frequencies is a pulse required to satisfy the search performance. Even if the transmission time is shorter than the signal transmission time Trx, the search performance can be maintained.

(Second Embodiment)
Since the radar apparatus according to the second embodiment is different from the radar apparatus 1 according to the first embodiment and the inter-PRI signal synthesis units 171a to 171c included in the radar apparatus 1, different configurations will be described, and other configurations will be described. Is omitted.

  FIG. 8 is a schematic block diagram illustrating a configuration of the inter-PRI signal synthesis unit 271a provided in the radar apparatus according to the present embodiment. The inter-PRI signal synthesizer 271a is provided in place of the inter-PRI signal synthesizer 171a in the first embodiment. Also, the inter-PRI signal synthesis units 271b and 271c are provided in place of the inter-PRI signal synthesis units 171b and 171c in the first embodiment, similarly to the inter-PRI signal synthesis unit 271a. Further, since the inter-PRI signal synthesis units 271b and 271c have the same configuration as the inter-PRI signal synthesis unit 271a, description thereof is omitted.

  As shown in FIG. 8, the inter-PRI signal synthesizer 271a includes an FFT calculator 272 and a maximum value selector 273. The FFT computing unit 272 reads a signal corresponding to the carrier frequency f1 for four consecutive PRIs stored in the first signal storage unit 161a, and converts it into a frequency domain signal by fast Fourier transform on the read four PRI signals. . The maximum value selector 273 selects a signal having the highest power frequency among the signals in the frequency domain converted by the FFT calculator 272, and the I signal (real part) and Q signal (imaginary part) of the selected signal. Is output to the inter-frequency signal synthesizer 175.

  As described above, the inter-PRI signal synthesizers 271a to 271c of the present embodiment convert the frequency domain signals by the FFT calculator 272 and synthesize them, so that the distance between the antenna 12 and the object changes. In this case, since the synthesis is performed for each frequency shifted according to the speed, the SNR can be improved over the phase addition. Further, the moving speed of the object may be detected based on the frequency shift of each of the carrier frequencies f1, f2, and f3.

  Although the configuration in which the FFT calculator 272 performs the fast Fourier transform on the signal for 4 PRI has been described, a signal having an amplitude of zero is added to the signal for 4 PRI and the number of FFT points is increased to more than 4 to perform fast Fourier transform. You may make it do. Thereby, the precision of the synthesis between PRI signals can be improved.

  The radar apparatus in each of the above embodiments coherently synthesizes a time-series reflected signal stored in the signal storage unit 16 for each carrier frequency over a predetermined period (PRI). Then, coherent synthesis is performed between carrier frequencies to improve the SNR of the reflected signal. Thereby, even if each of the transmission times at a plurality of carrier frequencies is shorter than the transmission time Trx of the pulse signal required to satisfy the search performance, the search performance can be maintained.

  Further, in each of the above-described embodiments, the configuration in which phase addition is performed by the adders 178a and 178b for each combination of phase shift amounts in the inter-frequency signal synthesizer 175 has been described, but the phase shift is performed without performing phase addition. The sum of the amplitudes (square sum of squares) of each signal may be calculated (amplitude synthesis). In this case, the maximum value determiner 179 may select and output the sum total of the largest amplitudes among the combinations of phase shift amounts.

  Further, in the inter-frequency signal synthesizing unit 175 of each of the above-described embodiments, four combinations of a plurality of predetermined phase shift amounts are used. For example, the following may be used. When there are N combinations of phase shift amounts (N is an integer of 4 or more), the phase shift amounts are (0, j × (2π / N), 2 × j × (2π / N)), (j May be set to an integer satisfying 0 ≦ j <N).

  For example, when the number of phase shift amount combinations is 8 (N = 8), the phase shift amount combinations are {(0, 0, 0), (0, π / 4, 2π / 4), (0, 2π / 4, 4π / 4), (0, 3π / 4, 6π / 4), (0, 4π / 4, 8π / 4), (0, 5π / 4, 10π / 4), (0, 6π / 4,12π / 4), (0,7π / 4,14π / 4)}. At this time, the maximum value determiner 179 selects and outputs the result having the largest square root sum of squares among the eight phase addition results. Thereby, the SNR of the signal obtained by the synthesis can be further improved.

  Further, in the signal synthesizer 17 of each of the embodiments described above, the case where the signal input to the signal synthesizer 17 is input to the inter-frequency signal synthesizer via the phase synthesizer 171 has been described. Not. This is because the configuration of the signal synthesizer 17 is determined by how the received signal is divided after being output from the A / D converter 14.

For example, when the received signal is time-divided for each PRI without providing the frequency divider 15, the signal storage unit 16 stores the signal separately for each PRI over a predetermined number of PRIs.
Since each PRI includes a different carrier frequency, it is preferable that each PRI is input to the signal synthesizing unit 17 through the inter-frequency signal synthesizing unit for each PRI, and then the signal is synthesized for each PRI and then input to the inter-PRI signal synthesizing unit. .

  Thus, the signal division method for the received signal received is not limited to frequency division. Therefore, since the specific configuration of the signal synthesizer 17 should be determined in accordance with the method of dividing the received signal, the configuration of various embodiments can be made. Hereinafter, a specific implementation method when the received signal is time-divided for each PRI without providing the frequency division unit 15 will be described.

(Embodiment 3)
The radar apparatus 3 in the third embodiment is configured as shown in the schematic block diagram of FIG.
The radar apparatus 3 includes a transmission unit 31, an antenna 32, a reception unit 33, an A / D conversion unit 34, a time division unit 35, a signal storage unit 36, a signal synthesis unit 37, and an output processing unit 38.

  The operations of the transmission unit 31, the antenna 32, the reception unit 33, and the A / D conversion unit 34 are the same as those of the transmission unit 11, the antenna 12, the reception unit 13, and the A / D conversion of the radar apparatus 1 according to the first and second embodiments. Since it is the same as each operation | movement of the part 14, description is abbreviate | omitted here. The A / D conversion unit 34 outputs the digitized reflected signal to the time division unit 35.

  The time division unit 35 divides the received signal between a predetermined number of PRIs. In the present embodiment, a case in which a received signal is divided between four PRIs (PRI1, PRI2, PRI3, PRI4) will be described. The time division unit 35 to which the received signal is input time-divides the received signal for each PRI and outputs the signal to the signal storage unit 36. The received signals divided for each PRI include different carrier frequencies f1, f2, and f3.

The signal storage unit 36 stores the data separately for each PRI. The signal storage unit 36 includes a first signal storage unit 361a, a second signal storage unit 361b, a third signal storage unit 361c, and a fourth signal storage unit 361d. The first signal storage unit 361a stores a signal corresponding to PRI1.
Similar to the first signal storage unit 361a, the second signal storage unit 361b, the third signal storage unit 361c, and the fourth signal storage unit 361d send signals corresponding to PRI2, PRI3, and PRI4 to the first signal storage unit 361a. Memorize by the same configuration.

  The signal combining unit 37 combines the signals stored in the signal storage unit 36 over a predetermined number of PRIs and outputs the combined signal to the output processing unit 38. The signal synthesis unit 37 includes inter-frequency signal synthesis units 371a, 371b, 371c, and 371d that synthesize signals having a plurality of carrier frequencies for each transmission period PRI1, PRI2, PRI3, and PRI4, and transmission periods PRI1, PRI2, PRI3, and PRI4. An inter-PRI signal synthesizer 376 that further adds the amplitudes of the synthesized signals and synthesizes them into one signal and outputs the resultant signal is provided.

  Inter-frequency signal synthesizers 371a, 371b, 371c, and 371d synthesize signals corresponding to the transmission periods PRI1, PRI2, PRI3, and PRI4, respectively. The inter-different-frequency signal synthesizer 371a performs phase addition (coherent synthesis) between three carrier frequencies by combining a plurality of phase shift amounts of signals corresponding to PRI1 over three frequencies. To select and output the maximum value. Similarly to the inter-frequency signal synthesizer 371a, the inter-frequency signal synthesizers 371b, 371c, and 371d perform PRI2, PRI3, and PRI4 over three carrier frequencies by combining a plurality of predetermined phase shift amounts. Select the maximum value for the signal corresponding to, and output it.

  The inter-PRI signal synthesizer 376 includes a combination of a plurality of phase shift amounts determined in advance between the carrier frequencies f1, f2, and f3 for each of the PRI1, PRI2, PRI3, and PRI4 by the inter-frequency signal synthesizers 371a to 371d. The signal added over the three carrier frequencies is output to the output processing unit 38.

  Similar to the output processing unit 18 of the radar apparatus 1 in the first and second embodiments, the output processing unit 38 performs further processing on the signal synthesized by the inter-PRI signal synthesis unit 376 and outputs the signal. For example, processing such as conversion into a video signal for display on an externally connected display device is performed.

An example of a specific configuration of the inter-frequency signal synthesizing units 371a to 371d will be described. FIG. 13 is a schematic diagram illustrating processing of the inter-frequency signal synthesizing unit 371a in the present embodiment.
FIG. 12 is a schematic block diagram showing the configuration of the inter-frequency signal synthesizer 371a in the present embodiment. Since the inter-frequency signal synthesizers 371b, 371c, 371d have the same configuration as the inter-frequency signal synthesizer 371a, description thereof is omitted.

  The inter-frequency signal synthesizer 371a includes a quadrature detector 372, a phase shifter 373a, a phase shifter 373b, an adder 374a, an adder 374b, and a maximum value determiner 375. The quadrature detector 372 sequentially reads signals corresponding to the carrier frequencies f1, f2, and f3 for 1PRI stored in the first signal frequency storage unit 361a, sequentially performs quadrature detection on the read signals, and outputs the I signal and Separated into Q signals. The amplitudes of the I signal and the Q signal are the same, and the phases are different from each other by 90 degrees. In the subsequent processing, the I signal is treated as the real part of the complex number, and the Q signal is treated as the imaginary part of the complex number. The quadrature detection can be realized by, for example, a method of mixing signals of the same frequency whose phases are different from each other by 90 degrees with a signal to be detected, a method using a Hilbert filter, or the like.

  The phase shifters 373a and 373b shift the phase of the signal output from the first signal storage unit 361a according to a predetermined combination of a plurality of phase shift amounts and output the phase shift signal. The adder 374a adds the f1 I signal output from the first signal storage unit 361a, the f2 I signal output from the phase shifter 373a, and the f3 I signal output from the phase shifter 373b. To do. The adder 374b adds the f1 Q signal output from the first signal storage unit 361a, the f2 Q signal output from the phase shifter 373a, and the f3 Q signal output from the phase shifter 373b. To do. The inter-frequency signal synthesizer 371a reads the signal stored in the first signal storage unit 361a over three frequencies as described above, and independently generates the I signal and the Q signal based on the read signal. The phase is added and output by a combination of a plurality of predetermined phase shift amounts.

  That is, the adders 374a and 374b add the phases of f1 output from the first signal storage unit 361a and f2 and f3 phase-shifted by the phase shifters 373a and 373b. Maximum value determiner 375 calculates the square sum square root of the phase-added signal for each phase shift amount combination, and selects and outputs the signal having the largest square sum square root among the plurality of phase shift amount combinations.

  Here, a case will be described in which a predetermined combination of a plurality of phase shift amounts is set as follows on the basis of a signal corresponding to PRI1. Set to 4 combinations of (0, 0, 0), (0, π / 2, 2π / 2), (0, 2π / 2, 4π / 2), (0, 3π / 2, 6π / 2) It is assumed that Here, (a, b, c) represents a combination of phase shift amounts, where a is the phase shift amount for the signal corresponding to f1, b is the phase shift amount for the signal corresponding to f2, and c is This is the amount of phase shift for the signal corresponding to f3.

  The phase shifter 373a outputs a signal phase-shifted by 0, π / 2, 2π / 2, 3π / 2 with respect to the I signal and Q signal corresponding to f2 output from the quadrature detector 372. Output in order. The phase shifter 373b outputs a signal phase-shifted by 0, 2π / 2, 4π / 2, 6π / 2 with respect to the I signal and Q signal corresponding to f3 output from the quadrature detector 372. Output in order.

  The adder 374a outputs the I signal of f1 output from the quadrature detector 372, the I signal of f2 output from the phase shifter 373a, and the phase shifter 373b for each combination of the above phase shift amounts. And the I signal of f3. The adder 374b outputs the Q signal of f1 output from the quadrature detector 372, the Q signal of f2 output from the phase shifter 373a, and the phase shifter 373b for each combination of the above phase shift amounts. And the Q signal of f3. That is, the adders 374a and 374b perform phase addition for independently adding the phase-shifted I signal and Q signal for each combination of the above-described phase shift amounts.

  The maximum value determiner 375 calculates the square sum square (amplitude) of the I signal and the Q signal added by the adders 374a and 374b for each combination of the four phase shift amounts, and calculates the four phase shift amounts. The I signal and Q signal having the largest square sum square root in the combination are selected and output to the inter-PRI signal synthesis unit 376.

  FIG. 13 is a schematic diagram illustrating processing of the inter-frequency signal synthesizing unit 371 in the present embodiment. As shown in the figure, the signals corresponding to f1, f2, and f3, which are output from the quadrature detector 372, are phase-shifted in four ways and subjected to phase addition, and four phase additions are performed. The result having the largest square root (amplitude) is selected and output. Thereby, SNR can be improved to 2.9 dB or more. In this embodiment, there are four combinations of phase shift amounts, but the SNR can be improved to 4.8 dB when the combination of phase shift amounts (phase pattern) is increased infinitely.

  Next, an example of a specific configuration of the inter-PRI signal synthesis unit 376 will be described. FIG. 14 is a schematic block diagram showing the configuration of the inter-PRI signal synthesis unit 376 in the present embodiment. As shown in the figure, the inter-PRI signal synthesis unit 376 has an adder 378.

  The adder 378 adds the amplitudes of signals output from the inter-frequency signal synthesizer 371a, the inter-frequency signal synthesizer 371b, the inter-frequency signal synthesizer 371c, and the inter-frequency signal synthesizer 371d.

  FIG. 15 is a schematic diagram showing an outline of processing in the radar apparatus 3 of the present embodiment. In the radar apparatus 3, as shown in the figure, the transmission unit 11 periodically transmits pulse signals in the order of carrier frequencies f1, f2, and f3 in each PRI, and receives a reflected signal reflected by an object. To do. The received reflected signal is divided by the time division unit 35 for each transmission period of PRI1, PRI2, PRI3, and PRI4, and further the first signal storage unit 361a and the second signal provided in the signal storage unit 16 for each PRI. The data is stored in the storage unit 361b, the third signal storage unit 361c, and the fourth signal storage unit 361d, respectively.

  The signals received by PRI1 to PRI4 stored in the first signal storage unit 361a, the second signal storage unit 361b, the third signal storage unit 361c, and the fourth signal storage unit 361d are respectively inter-frequency signal synthesis units 371a. Are added to one signal by an inter-PRI signal synthesis unit 376 and output. In this way, the pulse signals transmitted at the carrier frequencies f1, f2, and f3 can be combined to improve the SNR, and the transmission time at each of the three carrier frequencies is a pulse required to satisfy the search performance. Even if the transmission time is shorter than the signal transmission time Trx, the search performance can be maintained.

  In addition, although the structure which performs a phase addition for every combination of phase shift amount in the different frequency signal synthetic | combination part 371a-d was demonstrated, the amplitude (square sum square root) of each signal shifted without phase addition was demonstrated. The sum may be calculated (amplitude synthesis). In this case, among the combinations of phase shift amounts, the sum of the largest amplitudes may be selected by the maximum value determiner and output.

(Fourth embodiment)
The radar device according to the fourth embodiment is different from the radar device 3 according to the third embodiment in the different frequency signal synthesis units 371a to 371d provided in the radar device 3, and thus different configurations will be described. Description is omitted.

  FIG. 16 is a schematic block diagram showing a configuration of the inter-frequency signal synthesizing unit 471a provided in the radar apparatus according to the present embodiment. The inter-frequency signal synthesizer 471a is provided in place of the inter-frequency signal synthesizer 371a in the third embodiment. Similarly to the inter-frequency signal synthesizing unit 471a, the inter-frequency signal synthesizing units 471b, 471c, and 471d are provided instead of the inter-frequency signal synthesizing units 371b, 371c, and 371d in the third embodiment. Moreover, since the inter-frequency signal synthesizing units 471b, 471c, and 471d have the same configuration as the inter-frequency signal synthesizing unit 471a, description thereof is omitted.

  As shown in FIG. 16, the inter-frequency signal synthesizer 471 a includes a quadrature detector 472 and an FFT calculator 473. The FFT calculator 473 reads out signals corresponding to the three carrier frequencies f1, f2, and f3 in the first PRI stored in the first signal storage unit 361a, and the three carrier frequencies in the read one PRI. The signal is converted to a frequency domain signal by fast Fourier transform. The maximum value selector 474 selects a signal having the highest power among the frequency domain signals converted by the FFT calculator 473, and outputs the selected signal to the inter-PRI signal synthesizer 376.

  Note that the configuration in which the FFT calculator 472 performs fast Fourier transform on a signal corresponding to three carrier frequencies has been described, but a signal having zero amplitude is added to the signal corresponding to three carrier frequencies, and the number of FFT points is calculated from four. You may make it enlarge and perform a fast Fourier transform.

  As described above, the radar apparatus 3 in the third and fourth embodiments performs coherent synthesis over a plurality of carrier frequencies with respect to the reflected signal for each carrier frequency stored in the signal storage unit 36 for each PRI. Further, the SNR of the reflected signal is improved by performing synthesis over a predetermined PRI. Thereby, even if each of the transmission times at a plurality of carrier frequencies is shorter than the transmission time Trx of the pulse signal required to satisfy the search performance, the search performance can be maintained.

  In the third and fourth embodiments, the signal storage unit 36 includes the first signal storage unit 361a, the second signal storage unit 361b, the third signal storage unit 361c, and the fourth signal storage unit 361d based on FIG. The parallel processing stored in the four storage units and further combined in parallel by the four different frequency signal combining units has been described. However, for example, serial processing using a ring buffer is also possible. For example, the time division unit 35 divides sequentially input signals and outputs them to the signal storage unit 36. After the signal is temporarily stored in the signal storage unit 36, the signal output from the time division unit 35 is newly stored in the storage unit in which the signal output to the signal synthesis unit 37 is stored. The same signal processing result can be obtained with a relatively simple configuration.

  As described above, the radar apparatus according to each of the above-described embodiments uses a plurality of carrier frequencies in a time-division manner in the pulse signal transmission time Trx required for satisfying the search performance required for detecting the target. Are sent periodically. When the pulse signal transmitted from the radar apparatus 1 corresponds to an image frequency in a receiving apparatus used in another communication system, it appears as a signal dispersed at the image frequency. Thereby, since the interference which a pulse signal gives in an image frequency can be disperse | distributed to several frequencies, the influence which it has on other communication systems can be reduced.

  Further, in each of the above-described embodiments, as shown in FIG. 9, the frequency band assigned to the radar apparatus is an image frequency band at the baseband frequency stage or the intermediate frequency stage in the receiving apparatus of another communication system. The carrier frequencies f1, f2, and f3 may be set as follows.

  FIG. 9 is a diagram illustrating an example of setting the carrier frequencies f1, f2, and f3 in the above-described embodiments. In another communication system, when communication is performed by dividing the frequency band assigned to the communication system into n sub-frequency bands (channels), each of the carrier frequencies f1, f2, and f3 is down-converted. In order to appear as image signals in different sub-frequency bands (ch.1, ch.2, ch.3).

  That is, the frequency intervals between the carrier frequencies f1, f2, and f3 may be set according to the channel allocation frequency interval in another communication system. As a result, the pulse signals transmitted from the radar device at the carrier frequencies f1, f2, and f3 appear dispersed as image signals in different channels in other communication systems, so that the interference applied can be further reduced.

  In another communication system, when a signal that has been subjected to error correction coding is used for communication, the length of the pulse signal transmitted using the carrier frequencies f1, f2, and f3 is set to the error correction coding. A shorter burst error duration may be set. That is, the pulse signal transmission time at the carrier frequencies f1, f2, and f3 may be set according to the burst error duration allowed in other communication systems.

  When the transmission time is set in this way, even if the pulse signal transmitted from the radar device interferes as an image signal in a receiving device of another communication system, an error caused by the interference is corrected by error correction decoding of the communication system. can do. Thereby, it can prevent that an error arises with the pulse signal transmitted from the radar apparatus, and the interference which the pulse signal transmitted from the radar apparatus gives can be reduced.

  Note that the above-described radar apparatus may have a computer system therein. In that case, the processes of the A / D conversion units 14 and 34, the frequency division unit 15 or the time division unit 35, the signal storage units 16 and 36, and the signal synthesis units 17 and 37 described above are computer-readable in the form of a program. The above processing is performed when the computer reads out and executes the program stored in the recording medium. Here, the computer-readable recording medium means a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Alternatively, the computer program may be distributed to the computer via a communication line, and the computer that has received the distribution may execute the program.

  In each of the embodiments described above, the case where the pulse signal is transmitted using three carrier frequencies has been described. However, the present invention is not limited to this, and the pulse signal may be transmitted using two or more carrier frequencies.

  Further, in each of the embodiments described above, the configuration for synthesizing 4 PRI signals has been described, but the number of PRIs to be synthesized may be other than four. When the radar apparatus is operated by rotating the antenna, the number of PRIs to be combined may be set based on the rotation angular velocity of the antenna, the half width of the antenna directivity gain, and the PRI. Thereby, the improvement of the sensitivity by the synthesis and the decrease in the azimuth resolution can be prevented.

  In each of the above-described embodiments, the configuration in which one radar apparatus transmits a pulse signal and receives a reflected signal has been described. However, the radar apparatus is divided into an apparatus that transmits a pulse signal and an apparatus that receives a reflected signal. Alternatively, a bistatic or multistatic radar system including two or more devices may be used.

  As described above, the present invention is not limited to the above-described embodiments, and various configurations of the embodiments are possible within the scope of the present invention, and any improvement may be applied to all or some of the components.

DESCRIPTION OF SYMBOLS 1,3 ... Radar apparatus 11,31 ... Transmission part 12,32 ... Antenna 13,33 ... Reception part 14,34 ... A / D conversion part 15 ... Frequency division part 16 ... Signal storage part 17 ... Signal synthesis part 18,38 ... Output processing unit 161a ... First signal storage unit 161b ... Second signal storage unit 161c ... Third signal storage unit 171 ... Phase synthesis unit 171a, 171b, 171c, 271a, 271b, 271c ... Inter-PRI signal synthesis unit 172 ... Orthogonal Detectors 173a, 173b ... Accumulator 175 ... Inter-frequency signal synthesizer 176, 177 ... Phase shifters 178a, 178b ... Adder 179 ... Maximum value determiner 272 ... FFT calculator 273 ... Maximum value selector 35 ... Hour Dividing unit 36 ... signal storage unit 37 ... signal synthesis unit 361a ... first signal storage unit 361b ... second signal storage unit 361c ... third signal storage unit 361d ... 4 signal storage units 371a, 371b, 371c, 371d, 471a, 471b, 471c, 471d ... inter-frequency signal synthesis units 372 ... quadrature detectors 373a, 373b ... phase shifters 374a, 374b ... adders 375 ... maximum value determiners 376 ... PRI signal combiner 378 ... Adder 472 ... Orthogonal detector 473 ... FFT operator 474 ... Maximum value selector

Claims (3)

In the pulse repetition period, a reflected wave that arrives when a transmission wave transmitted as a train of n (≧ 2) pulses of different frequencies f ₁ ,..., F _n is reflected by the target is changed to the different frequencies f ₁ ,. .., F _n components C _f1 ,..., C _fn separating means,
The different frequencies f _1, ..., the amount of phase shift of a plurality P as proportional to the distance _{f n (φ 11, ...,} φ 1n), ..., (φ P1, ..., φ Pn) the components of phase shift processing by C _f1 ,..., C _fn , and phase synthesis for each phase shift amount (φ ₁₁ ,..., Φ _1n ),..., (Φ _P1 ,..., Φ _Pn ) The desired phase synthesis means;
An interference reduction apparatus comprising: a processing target setting unit that targets a sum of the plurality of P sums having the highest power as a radar signal processing target of a ship radar. In the pulse repetition period, a reflected wave that arrives when a transmission wave transmitted as a train of n (≧ 2) pulses of different frequencies f ₁ ,..., F _n is reflected by the target is changed to the different frequencies f ₁ ,. .., F _n components C _f1 ,..., C _fn separating means,
Frequency analysis means for individually analyzing the frequency of the components C _f1 ,..., C _fn to obtain the n frequency spectra;
Said plurality n frequency as spectrum for each Le, interference reduction apparatus characterized by comprising a processing target setting unit power is the target of the radar signal processing of the ship radar by combining the components is maximum. In the pulse repetition period, a reflected wave that arrives when a transmission wave transmitted as a train of n (≧ 2) pulses of different frequencies f ₁ ,..., F _n is reflected by the target is changed to the different frequencies f ₁ ,. .., F _n components C _f1 ,..., C _fn separating means,
The pulse repetition are individually separated by said separating means over a period of several N times the period, and the column of the plurality N of times corresponding to the components in the period of _{(C f11, ..., C f1N} ), ..., (C _{fn1, ...,} each of the _{C FNN),} the different frequencies _{f 1,} ..., the phase shift amount (phi ₁₁ in proportion to the distance of _{f n, ..., φ 1N)} , ..., (φ n1, ..., φ nN) And a phase synthesis means for obtaining the N sums by _performing phase synthesis for each of the phase shift amounts (φ ₁₁ ,..., Φ _1N ),..., (Φ _n1 ,..., Φ _nN ). When,
An interference reduction apparatus comprising: a processing target setting unit that targets a sum of the plurality of N sums having a maximum power as a radar signal processing target of a ship radar.