JP6604794B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- JP6604794B2 JP6604794B2 JP2015184482A JP2015184482A JP6604794B2 JP 6604794 B2 JP6604794 B2 JP 6604794B2 JP 2015184482 A JP2015184482 A JP 2015184482A JP 2015184482 A JP2015184482 A JP 2015184482A JP 6604794 B2 JP6604794 B2 JP 6604794B2
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本発明は半導体の製造方法に関し、特に半導体基板上の配線の上に形成する層間絶縁膜の形成方法に関するものである。 The present invention relates to a semiconductor manufacturing method, and more particularly to a method for forming an interlayer insulating film formed on a wiring on a semiconductor substrate.
半導体装置の高集積化に伴い、基板表面の平坦化技術の重要性が増している。従来、シラン系ＣＶＤ膜およびＴＥＯＳ系プラズマＣＶＤ膜が層間絶縁膜として用いられていたが、微細化に伴いオーバーハング形状やボイドが発生するようになったため、フロー形状に優れたＴＥＯＳ−Ｏ３系常圧ＣＶＤ膜（以下Ｏ３−ＴＥＯＳ膜と略記）が用いられるようになった。 With the high integration of semiconductor devices, the importance of planarizing the substrate surface is increasing. Conventionally, a silane-based CVD film and a TEOS-based plasma CVD film have been used as an interlayer insulating film. However, since the overhang shape and voids are generated with the miniaturization, the TEOS-O3 system that is excellent in flow shape is used. A pressure CVD film (hereinafter abbreviated as O3-TEOS film) has come to be used.
通常のＯ３−ＴＥＯＳ膜の成膜方法では、まずＡｌ配線層上にプラズマＣＶＤによるＳｉＯ2膜を成膜する。このＳｉＯ2膜には、Ｏ３−ＴＥＯＳ膜中に含まれる水分が多いことによる水分ストッパー層としての役割、そしてＯ３−ＴＥＯＳ膜の引っ張り応力の緩和ためのストレス緩和層としての役割がある。また、Ｏ３−ＴＥＯＳ膜は必要以上に厚くするとクラックが入りやすくなるため、下地のプラズマＣＶＤによるＳｉＯ2膜においても埋め込み状態に応じた膜厚が必要となる。シラン系プラズマＣＶＤによるＳｉＯ2膜と、ＴＥＯＳ系プラズマＣＶＤによるＳｉＯ2膜ではＴＥＯＳ系プラズマＣＶＤによるＳｉＯ2膜の方の埋め込み性が良いため、平坦化の点ではＴＥＯＳ系の方が望ましく、ＴＥＯＳ系プラズマＣＶＤによるＳｉＯ2膜の方が下地膜として採用されることが多い。 In a normal O3-TEOS film forming method, first, an SiO 2 film is formed by plasma CVD on an Al wiring layer. This SiO 2 film has a role as a moisture stopper layer due to a large amount of moisture contained in the O3-TEOS film and a role as a stress relaxation layer for alleviating the tensile stress of the O3-TEOS film. Further, if the O3-TEOS film is made thicker than necessary, cracks are likely to occur. Therefore, the SiO 2 film formed by the underlying plasma CVD needs to have a thickness corresponding to the embedded state. And the SiO 2 film by a silane-based plasma CVD, because good filling properties towards SiO 2 film by TEOS based plasma CVD in the SiO 2 film by TEOS based plasma CVD, desirably towards the TEOS system in terms of planarization, TEOS-based In many cases, a SiO 2 film formed by plasma CVD is used as a base film.
一方、Ｏ３−ＴＥＯＳ膜は下地依存性が強いため、下地の種類や表面状態によって成膜速度が遅くなったり、表面モフォロジーが悪化したりするため、良好な埋め込み形状が得られないといった問題がある。 On the other hand, since the O3-TEOS film has a strong base dependency, the film forming speed is slowed down or the surface morphology is deteriorated depending on the type and surface state of the base, so that there is a problem that a good embedded shape cannot be obtained. .
この問題に対して、下地依存性を排除するための表面改質処理として、例えば、特許文献１では、基板を加熱した状態で高周波プラズマ処理を行い、表面改質をする方法が開示されている。また、特許文献２では、低周波、及び高周波の２周波のＮ2プラズマ照射を行う方法が開示されている。 To solve this problem, for example, Patent Document 1 discloses a method of performing surface modification by performing high-frequency plasma treatment while a substrate is heated as surface modification processing for eliminating base dependency. . Patent Document 2 discloses a method of performing N 2 plasma irradiation of low frequency and high frequency two frequencies.
しかしながら、上記特許文献に開示した方法を行った場合でも、完全に下地依存性が消えるわけではなく、実際のウェハ上で場所によって成膜速度が遅くなる場合が見られ、特にウェハ外周部のＡｌ配線上で成膜速度が低下して、Ｏ３−ＴＥＯＳ膜の膜厚の面内均一性が悪化する場合がある。 However, even when the method disclosed in the above-mentioned patent document is performed, the base dependency does not completely disappear, and there are cases where the film formation rate becomes slow depending on the location on the actual wafer. In some cases, the film formation rate is lowered on the wiring, and the in-plane uniformity of the film thickness of the O3-TEOS film is deteriorated.
そこで、本発明は配線構造を有する半導体基板の上にＯ３−ＴＥＯＳ膜による膜厚均一性の良好な層間絶縁膜を形成することが可能な半導体装置の製造方法を提供することを課題とする。 Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming an interlayer insulating film with good film thickness uniformity using an O3-TEOS film on a semiconductor substrate having a wiring structure.
上記課題を解決するために以下の手段を用いた。
まず、配線が形成された半導体基板上に層間絶縁膜を形成する半導体装置の製造方法において、前記配線が形成された半導体基板上に第１の層間絶縁膜を成膜する工程と、前記第１の層間絶縁膜の表面にプラズマ照射する工程と、次いで、前記第１の層間絶縁膜上に前記第１の層間絶縁膜よりも膜厚の薄い第２の層間絶縁膜を成膜する工程と、前記第２の層間絶縁膜の上に第３の層間絶縁膜を成膜する工程と、からなることを特徴とする半導体装置の製造方法を用いた。
In order to solve the above problems, the following means were used.
First, in a manufacturing method of a semiconductor device in which an interlayer insulating film is formed on a semiconductor substrate on which wiring is formed, a step of forming a first interlayer insulating film on the semiconductor substrate on which the wiring is formed; Irradiating the surface of the interlayer insulating film with plasma, and then forming a second interlayer insulating film having a thickness smaller than that of the first interlayer insulating film on the first interlayer insulating film; A method of manufacturing a semiconductor device, comprising: forming a third interlayer insulating film on the second interlayer insulating film.
また、前記第１の層間絶縁膜がＴＥＯＳ系プラズマＣＶＤによるＳｉＯ2膜であり、前記第２の層間絶縁膜がシラン系プラズマＣＶＤによるＳｉＯ2膜であり、前記第３の層間絶縁膜がＴＥＯＳ−Ｏ３系常圧ＣＶＤ膜であることを特徴とする半導体装置の製造方法を用いた。 Further, the first interlayer insulating film is a SiO 2 film by TEOS plasma CVD, the second interlayer insulating film is a SiO 2 film by silane plasma CVD, and the third interlayer insulating film is TEOS- A method for manufacturing a semiconductor device, which is an O3-based atmospheric pressure CVD film, was used.
また、前記第２の層間絶縁膜であるシラン系プラズマＣＶＤによるＳｉＯ2膜の成膜において、３００Å以下の膜厚で形成することを特徴とする半導体装置の製造方法を用いた。 In addition, a method of manufacturing a semiconductor device is used, in which the SiO 2 film is formed by silane plasma CVD, which is the second interlayer insulating film, with a film thickness of 300 mm or less.
また、前記プラズマ照射する工程において、アンモニアガスを含むガス系でプラズマ照射することを特徴とする半導体装置の製造方法を用いた。
また、前記プラズマ照射する工程において、笑気ガスを含むガス系でプラズマ照射することを特徴とする半導体装置の製造方法を用いた。
Further, in the plasma irradiation step, a semiconductor device manufacturing method is used, in which plasma irradiation is performed with a gas system containing ammonia gas.
In the plasma irradiation step, the semiconductor device manufacturing method is characterized in that plasma irradiation is performed with a gas system containing a laughing gas.
上記手段を用いることで、配線構造を有する半導体基板上に膜厚均一性の良好な層間絶縁膜を形成できる。 By using the above means, an interlayer insulating film with good film thickness uniformity can be formed on a semiconductor substrate having a wiring structure.
以下、本発明の実施例を説明する。
図１は本発明の実施例を説明する各工程の断面図である。図１（ａ）は半導体基板１上に絶縁膜を介してＡｌ積層配線２を形成した断面図である。絶縁膜は図示されていない。ここで、本実施例では、Ａｌ配線は、上層にＴｉＮの反射防止膜、及び、下層にＴｉＮ／Ｔｉのバリアメタル層を有したＡｌ合金膜の積層配線を使用し、膜厚は６５００Å程度で形成されている。ただし、本発明においては、Ａｌ配線は、Ａｌ合金の単層でも、積層でもよく、半導体プロセスで通常用いられるものを使用することが可能であり特に制限されない。
Examples of the present invention will be described below.
FIG. 1 is a sectional view of each step for explaining an embodiment of the present invention. FIG. 1A is a cross-sectional view in which an Al laminated wiring 2 is formed on a semiconductor substrate 1 via an insulating film. The insulating film is not shown. Here, in this embodiment, the Al wiring uses a laminated wiring of an Al alloy film having a TiN antireflection film in the upper layer and a TiN / Ti barrier metal layer in the lower layer, and the film thickness is about 6500 mm. Is formed. However, in the present invention, the Al wiring may be a single layer or a laminated layer of an Al alloy, and those normally used in a semiconductor process can be used and are not particularly limited.
次に、図１（ｂ）に示すように、Ａｌ積層配線上に、ＴＥＯＳ系プラズマＣＶＤによるＳｉＯ2膜（Ｐ−ＴＥＯＳ膜）３からなる第１の層間絶縁膜３を形成する。実施例では、４０００Å程度で成膜した。 Next, as shown in FIG. 1B, a first interlayer insulating film 3 made of a SiO 2 film (P-TEOS film) 3 is formed on the Al laminated wiring by TEOS plasma CVD. In the example, the film was formed at about 4000 mm.
次に、図１（ｃ）に示すように、Ｐ−ＴＥＯＳ膜３からなる第１の層間絶縁膜３の表面の改質工程として半導体基板上面にプラズマ照射する。プラズマ照射条件の一例としては、高周波電力：４００Ｗ、圧力：６．０Ｔｏｒｒ、Ｎ２：８４０ｓｃｃｍ、ＮＨ3：４０ｓｃｃｍ、基板温度：４００℃、照射時間：２０秒で行う。上記例では、アンモニアを含むガス系のプラズマ照射を行ったが、この条件に限定されることなく、笑気ガス（Ｎ2Ｏ、亜酸化窒素）系のプラズマ照射でも良い。窒素（Ｎ）を含むガス系のプラズマ照射により、Ｐ−ＴＥＯＳ膜３の表面は、僅かであるが窒化され、疎水性が高まる。これは、シリコン原子の未結合手が窒素と結合して終端されるためと考えられる。一般に下地が疎水性であるとその上に形成されるＣＶＤによる絶縁膜は、下地の表面状態の影響を受けにくくなり膜厚の均一性が高まるとされている。 Next, as shown in FIG. 1C, the upper surface of the semiconductor substrate is irradiated with plasma as a modification process of the surface of the first interlayer insulating film 3 made of the P-TEOS film 3. As an example of plasma irradiation conditions, high-frequency power: 400 W, pressure: 6.0 Torr, N2: 840 sccm, NH 3 : 40 sccm, substrate temperature: 400 ° C., irradiation time: 20 seconds. In the above example, the plasma irradiation of gas containing ammonia is performed. However, the plasma irradiation of laughing gas (N 2 O, nitrous oxide) may be used without being limited to this condition. The surface of the P-TEOS film 3 is slightly nitrided by irradiation with a gas-based plasma containing nitrogen (N), and the hydrophobicity is increased. This is presumably because the dangling bonds of silicon atoms are terminated by bonding with nitrogen. In general, when the underlying layer is hydrophobic, an insulating film formed by CVD on the underlying layer is less affected by the surface state of the underlying layer, and the uniformity of the film thickness is increased.
次に、図２（ａ）に示すように、シラン系プラズマＣＶＤによるＳｉＯ2膜（シラン系Ｐ−ＳｉＯ２膜）の第２の層間絶縁膜４を形成する。ここで注意する点は、第２の層間絶縁膜４を形成しているシラン系Ｐ−ＳｉＯ2膜はＰ−ＴＥＯＳ膜と比べて段差被覆性が悪いので、Ｐ−ＴＥＯＳ膜からなる第１の層間絶縁膜３よりも薄い膜厚で形成する。また、この後に成膜するＯ３−ＴＥＯＳ膜の下地依存性が解消できる膜厚だけ成膜すれば良い。したがって、膜厚の範囲としては１００から８００Åであり、下地となっているＰ−ＴＥＯＳ膜の２から２０％程度でよい。本実施例では、高周波電力：４００Ｗ、圧力：１．８Ｔｏｒｒ、Ｎ２：２５００ｓｃｃｍ、ＳｉＨ4：６０ｓｃｃｍ、Ｎ2０：６０００ｓｃｃｍ、成膜温度：４００℃の条件で、３００Å程度で成膜する。 Next, as shown in FIG. 2A, a second interlayer insulating film 4 of an SiO 2 film (silane P-SiO 2 film) is formed by silane plasma CVD. The point to be noted here is that the silane-based P—SiO 2 film forming the second interlayer insulating film 4 has poor step coverage as compared with the P-TEOS film. It is formed with a film thickness thinner than the interlayer insulating film 3. Further, it is only necessary to form the O3-TEOS film to be formed later by a thickness that can eliminate the base dependency. Accordingly, the film thickness ranges from 100 to 800 mm, and may be about 2 to 20% of the underlying P-TEOS film. In this embodiment, the film is formed at about 300 ° C. under the conditions of high frequency power: 400 W, pressure: 1.8 Torr, N2: 2500 sccm, SiH 4 : 60 sccm, N 2 0: 6000 sccm, and film formation temperature: 400 ° C.
次に、図２（ｂ）に示すように、ＴＥＯＳ−Ｏ３系常圧ＣＶＤ膜（Ｏ３−ＴＥＯＳ膜）からなる第３の層間絶縁膜５を形成する。実施例では、ＴＥＯＳ流量：６７３ｓｃｃｍ、Ｏ2／Ｏ3流量：６４００ｓｃｃｍ、Ｏ3濃度：１５０ｇ／ｍ３、成膜温度：４００℃で行った。 Next, as shown in FIG. 2B, a third interlayer insulating film 5 made of a TEOS-O3-based atmospheric pressure CVD film (O3-TEOS film) is formed. In the examples, the TEOS flow rate was 673 sccm, the O 2 / O 3 flow rate was 6400 sccm, the O 3 concentration was 150 g / m 3, and the film formation temperature was 400 ° C.
図３に、異なる下地条件（Ａ乃至Ｄ）において形成されたＯ３−ＴＥＯＳ膜の膜厚測定結果を示す。縦軸は実サンプル上に成膜されたＯ３−ＴＥＯＳ膜厚を、ベアＳｉウェハに成膜した場合の膜厚との比で示している。各下地条件において、ウェハ中心部とウェハ外周部において測定した結果を示している。各下地条件は次の通りである。 FIG. 3 shows the film thickness measurement results of the O3-TEOS film formed under different base conditions (A to D). The vertical axis indicates the O3-TEOS film thickness formed on the actual sample as a ratio with the film thickness when the film is formed on the bare Si wafer. The results of measurement at the wafer center and the wafer outer periphery under each base condition are shown. Each ground condition is as follows.
Ａ．下地条件Ａ：プラズマ処理を行わないＰ−ＴＥＯＳのみの場合
Ｂ．下地条件Ｂ：Ｐ−ＴＥＯＳにプラズマ処理無しにシラン系Ｐ−ＳｉＯ2膜を形成した場合
Ｃ．下地条件Ｃ：Ｐ−ＴＥＯＳにプラズマ処理だけを施した場合
Ｄ．下地条件Ｄ：Ｐ−ＴＥＯＳにプラズマ処理を施し、シラン系Ｐ−ＳｉＯ２膜を形成した場合（本実施例）
下地条件Ａのように下地依存性が強く出てしまう場合には、ベアＳｉウェハ上に比べて、成膜レートが低下してしまうため、比率は低くなる。下地依存性が解消されるに従い、本実施例の下地条件Ｄのように１００％に近づく。
A. Base condition A: In the case of only P-TEOS without plasma treatment. Base condition B: When a silane P-SiO 2 film is formed on P-TEOS without plasma treatment. Base condition C: When only plasma treatment is applied to P-TEOS. Base condition D: P-TEOS is subjected to plasma treatment to form a silane-based P-SiO2 film (Example)
In the case where the substrate dependency becomes strong as in the substrate condition A, the film formation rate is lower than that on the bare Si wafer, so the ratio is low. As the background dependency is eliminated, it approaches 100% as in the background condition D of the present embodiment.
従来のＳｉＨ4−Ｎ2Ｏ系Ｐ−ＳｉＯ2膜を形成せずプラズマ処理したＰ−ＴＥＯＳ単層の下地の場合、実ウェハのＡｌ積層配線上に成膜されるＯ３−ＴＥＯＳの膜厚は、ベアＳｉウェハに成膜した場合のＯ３−ＴＥＯＳ膜厚との比で、外周部では７５％程度であったものが、本実施例の下地条件ＤのようにＰ−ＴＥＯＳ成膜後にプラズマ照射を行い、シラン系Ｐ−ＳｉＯ2膜を成膜した後にＯ３−ＴＥＯＳ膜を成膜すると、ウェハ中心部で１００％、ウェハ外周部で９５％程度まで向上させることができた。なお、下地条件Ａのようにプラズマ処理を行わないＰ−ＴＥＯＳのみの下地ではウェハ中心部で７６％、ウェハ外周部で６９％程度であり、Ｐ−ＴＥＯＳにプラズマ処理無しにシラン系Ｐ−ＳｉＯ2膜を形成した場合（下地条件Ｂ）はウェハ外周部で７５％であった。また、Ｐ−ＴＥＯＳにプラズマ処理だけを施した場合（下地条件Ｃ）は、ウェハ中心部で改善は認められるが、ウェハ外周部で７５％であり改善の必要がある。本実施例では、プラズマ処理とシラン系Ｐ−ＳｉＯ２膜形成の両方を施すことで、ウェハ中心部および外周部にて９５％以上の膜厚が得られている。 In the case of a base of a P-TEOS single layer that is plasma-treated without forming a conventional SiH 4 —N 2 O-based P—SiO 2 film, the film thickness of O 3 -TEOS formed on the Al laminated wiring of the actual wafer is The ratio of the thickness of the O3-TEOS film formed on the bare Si wafer was about 75% at the outer peripheral portion, but the plasma irradiation was performed after the P-TEOS film formation as in the base condition D of this example. When the O3-TEOS film was formed after the silane-based P—SiO 2 film was formed, it was possible to improve the wafer center to 100% and the wafer outer periphery to about 95%. In addition, in the base of only P-TEOS that is not subjected to plasma treatment as in the base condition A, it is about 76% at the wafer central portion and about 69% at the outer peripheral portion of the wafer. When two films were formed (underlying condition B), it was 75% at the wafer outer periphery. Further, when only P-TEOS is subjected to plasma treatment (underlying condition C), an improvement is recognized at the wafer central portion, but 75% at the wafer outer peripheral portion, which needs to be improved. In this embodiment, by performing both the plasma treatment and the silane-based P—SiO 2 film formation, a film thickness of 95% or more is obtained at the wafer central portion and the outer peripheral portion.
また、上記ベアＳｉ上膜厚との比の面内均一性は、従来のＳｉＨ4−Ｎ2０系Ｐ−ＳｉＯ2膜を形成せずプラズマ処理したＰ−ＴＥＯＳ単層下地での場合１４％以上あったものが、本実施例の方法においては、２．６％程度に大幅に減少した。 Further, the in-plane uniformity of the ratio to the film thickness on the bare Si is 14% in the case of a P-TEOS single layer underlayer that is plasma-treated without forming a conventional SiH 4 —N 2 0-based P—SiO 2 film. What has been described above is greatly reduced to about 2.6% in the method of this example.
本願の発明を実施した半導体装置の態様は以下のようになる。
１．半導体装置について
半導体基板上に設けられた金属からなる配線と、
前記配線を覆う、前記半導体基板全面に設けられたＴＥＯＳ系プラズマＣＶＤＳｉＯ2膜からなる第１の層間絶縁膜と、
前記第１の層間絶縁膜の上に設けられたシラン系プラズマＣＶＤＳｉＯ2膜からなる第２の層間絶縁膜と、
前記第２の層間絶縁膜の上に設けられたＴＥＯＳ−Ｏ３系常圧ＣＶＤ膜からなる第３の層間絶縁膜と、
を有し、
前記第１の層間絶縁膜は窒化された表面を有していることを特徴とする半導体装置となる。
The aspect of the semiconductor device in which the invention of the present application is implemented is as follows.
1. About a semiconductor device A wiring made of a metal provided on a semiconductor substrate,
A first interlayer insulating film made of a TEOS-based plasma CVDSiO 2 film provided on the entire surface of the semiconductor substrate, covering the wiring;
A second interlayer insulating film made of a silane-based plasma CVDSiO 2 film provided on the first interlayer insulating film;
A third interlayer insulating film made of a TEOS-O3-based atmospheric pressure CVD film provided on the second interlayer insulating film;
Have
The first interlayer insulating film has a nitrided surface to provide a semiconductor device.
２．前記半導体装置を引用する態様として以下の通り。
前記第２の層間絶縁膜は、膜厚が１００から８００Åであることを特徴とする半導体装置となる。
2. Examples of the semiconductor device cited as follows.
The second interlayer insulating film is a semiconductor device having a thickness of 100 to 800 mm.
本発明は半導体製造方法に関するものであり、特に半導体基板上の配線間に形成する層間絶縁膜の形成方法に利用されるものである。 The present invention relates to a semiconductor manufacturing method, and particularly to a method for forming an interlayer insulating film formed between wirings on a semiconductor substrate.
１ 半導体基板
２ Ａｌ積層配線
３ Ｐ−ＴＥＯＳ膜
４ ＳｉＨ4系Ｐ−ＳｉＯ2膜
５ Ｏ３−ＴＥＯＳ膜
Ａ，Ｂ，Ｃ，Ｄ 下地条件
1 semiconductor substrate 2 Al laminated wiring 3 P-TEOS film 4 SiH 4 based P-SiO 2 film 5 O3-TEOS film A, B, C, D underlying conditions
Claims (4)
配線が形成された半導体基板全面にＴＥＯＳ系プラズマＣＶＤによるＳｉＯ2膜からなる第１の層間絶縁膜を成膜する工程と、
前記第１の層間絶縁膜の表面にプラズマ照射する工程と、
次いで、前記第１の層間絶縁膜上に前記第１の層間絶縁膜よりも膜厚の薄いシラン系プラズマＣＶＤによるＳｉＯ2膜からなる第２の層間絶縁膜を成膜する工程と、
前記第２の層間絶縁膜の上にＴＥＯＳ−Ｏ３系常圧ＣＶＤ膜からなる第３の層間絶縁膜を成膜する工程と、からなることを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device, comprising:
Forming a first interlayer insulating film made of a SiO 2 film by TEOS plasma CVD on the entire surface of the semiconductor substrate on which the wiring is formed;
Irradiating the surface of the first interlayer insulating film with plasma;
Next, a step of forming a second interlayer insulating film made of a SiO 2 film by silane-based plasma CVD having a thickness smaller than that of the first interlayer insulating film on the first interlayer insulating film;
Forming a third interlayer insulating film made of a TEOS-O3-based atmospheric pressure CVD film on the second interlayer insulating film.
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