TW548794B - Method of forming barrier layer between low k material layer and interconnect - Google Patents

Method of forming barrier layer between low k material layer and interconnect Download PDF

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TW548794B
TW548794B TW91117746A TW91117746A TW548794B TW 548794 B TW548794 B TW 548794B TW 91117746 A TW91117746 A TW 91117746A TW 91117746 A TW91117746 A TW 91117746A TW 548794 B TW548794 B TW 548794B
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layer
low
material layer
dielectric material
copper
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TW91117746A
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Chinese (zh)
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Shyh-Dar Lee
Chen-Chiu Hsue
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Silicon Integrated Sys Corp
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Abstract

This invention discloses a method of forming barrier layer between low k material layer and interconnect. Firstly, a substrate is provided, which is covered with an insulation layer and has a metal interconnect formed therein. Then, a sealing layer is formed on the metal interconnect and on top of the dielectric layer. Subsequently, a reaction gas is used to perform a plasma treatment on the sealing layer, in which the reaction gas used includes at least one of CO2, NH3, NO2, silane, 3MS and 4MS. Finally, a low k material is formed on the sealing layer.

Description

103年02月14日更正替換頁 九、發明說明: ---- 發明領域: 特別是有關於一種在 本發明係有關於—種半導體元件製造方法, 低介電材料層細連線間形成轉層之方法。 相關技術說明: 隨著積體魏職料㈣發展,具有低餘常數和高電子遷移 阻抗的銅金屬’已逐織應絲作為金屬内連線的㈣,取代以往 _金屬製程技術。由於銅的電阻率比紹低,在一固定的線寬下會 有較高的信號傳輸速度。 雖然銅的物理性質對於應用在元件上具有很大的優勢,但是鋼有 -些紹所沒有的缺點必需克服。例如,麵在製造過程巾非常容易 受到氧化。此外,銅很容易擴散到相鄰的材料(包括介電質),所以 當使用銅作為金屬内連線時,都需以阻障材料將銅導線封住。 傳統上,一般都會在沉積銅金屬之後,沉積一金屬阻障材料,一 般稱為封蓋層(Sealing layer)、覆蓋層(Cap layer)、或包覆層 (encapsulationlayer)。雖然其他材質亦可使用,但通常是以氮化石夕來 作為此封蓋層。 第1圖係繪示出一習知雙鑲嵌式導線剖面圖。標號100表示為一 半導體基底,其覆蓋有一絕緣層102,且具有複數溝槽。鋼金屬層 104沉積於絕緣層102上並填入於溝槽中。多餘的銅金屬層104通 548794 103年02月14日更ϋ替稹頁 常藉由化學機械研磨法(Chemical mechanical polishing)研磨到絕緣 層102表面以將之去除。之後,一封蓋層1〇6沉積於銅金屬層ι〇4 及絕緣層102上。一具有雙鑲欲(dual damascene)結構之低介電常數 (lowk)材料層1〇8接著形成於此封蓋層1〇6上。 同樣地’一銅金屬層110沉積於低介電常數材料層108並填入雙 鑲嵌構造中。此處’雙鑲嵌構造中的銅金屬層11〇經由去除部分的 ®封蓋層106以電性連接於銅内連線1〇4,如第1圖所示。多餘的銅 金屬層110同樣藉由化學機械研磨法(chemicai mechanicai 研磨至低介電常數材料層108以將之去除。 此封蓋層106通常為氮化矽(SiN),以作為一金屬阻障層而防止 銅金屬層104及110中的銅原子擴散至絕緣層1〇2及低介電常數材 料層108。另外,此封蓋層106亦可作為雙鑲嵌製程中的姓刻終止 • 層。 然而,位於低介電常數漏層及_連線之間賴蓋層具有可靠 度的問題,例如銅導線間的電子遷移(他_^峰如〇11,_及依 dependent dielectric breakdown,TDDB) 〇 而吕,在封蓋層沉積於鋼表面之後,接著介電層會沉積於封蓋層上 方。此沉積介電層的製程會產生應力而損害到封蓋層。再者在雙 鑲嵌製程後_化學機械研雜程中,低介電常數材料層及封蓋層 6 103年02月14日更正替換頁 之間不佳的附著力將造成介電層的剝離,導致水氣的進入及銅原子 的擴散。 發明概述: 有鑑於此,本發明之目的在於提供一種在低介電材料層與與内連 線間形成阻障層之方法,其藉由對封蓋層實施一電漿處理以增加低 W電常數材料層與封蓋層之間的附著力。 本發明之另一目的在於提供一種在低介電材料層與内連線間形_ 成阻障層之方法,其藉由在低介電常數材料層與封蓋層之間形成一 附著層以防止在形成低介電材料層期間對封蓋層造成損害,以及避 免在後續的化學機械研磨製程中造成低介電材料層的剝離。 根據上述之目的,本發明提供一種在低介電材料層與内連線間形 成阻障層之方法。首先,提供—基底,其覆蓋有-絕緣層且絕緣層 具有一金屬内連線。接著,在金屬内連線及絕緣層上方形成一封蓋 廣。然後’藉由一反應氣體對封蓋層實施一電漿處理,其中所使用籲 的反應氣體包括二氧化碳、氨氣、二氧化氮、矽烷、三甲基矽烷(3MS) 及四甲基矽烷(4MS)之至少一種。最後,在封蓋層上形成一低介電 材料層。再者’此封蓋層係由氮化石夕、碳化矽、碳氫化石夕、碳氧化 矽、及碳氮化矽之一種所構成。 又根據上述之另一目的’本發明提供一種在低介電材料層與内連 線間形成阻障層之方法。首先,提供一基底,其覆蓋有一絕緣層且Correction and replacement on February 14, 103 Page IX. Description of the invention: ---- Field of the invention: In particular, it relates to a method for manufacturing a semiconductor device in the present invention, forming a transition between thin wires of a layer of low dielectric material. Layer method. Relevant technical description: With the development of integrated materials, copper metal with low residual constant and high electron migration resistance has been woven into wire as a metal interconnect, replacing traditional metal processing technology. Since the resistivity of copper is lower than that of Shaw, it will have a higher signal transmission speed under a fixed line width. Although the physical properties of copper have great advantages for application to components, steel has some disadvantages that must not be overcome. For example, noodles are very susceptible to oxidation during the manufacturing process. In addition, copper can easily diffuse into adjacent materials (including dielectrics), so when copper is used as the metal interconnect, it is necessary to seal the copper wire with a barrier material. Traditionally, a metal barrier material is generally deposited after the copper metal is deposited, which is generally referred to as a sealing layer, a cap layer, or an encapsulation layer. Although other materials can also be used, it is usually covered with nitride. FIG. 1 is a cross-sectional view of a conventional dual-mosaic wire. Reference numeral 100 denotes a semiconductor substrate, which is covered with an insulating layer 102 and has a plurality of trenches. The steel metal layer 104 is deposited on the insulating layer 102 and filled in the trench. The excess copper metal layer 104 is usually replaced by 548794 on February 14, 103. The surface of the insulating layer 102 is usually removed by chemical mechanical polishing. After that, a cap layer 106 is deposited on the copper metal layer ι04 and the insulating layer 102. A low-k material layer 108 having a dual damascene structure is then formed on the capping layer 106. Similarly, a copper metal layer 110 is deposited on the low dielectric constant material layer 108 and filled into the dual damascene structure. Here, the copper metal layer 110 in the 'dual damascene structure is electrically connected to the copper interconnect 104 via the ® capping layer 106 which is removed, as shown in FIG. 1. The excess copper metal layer 110 is also removed by chemical mechanical polishing (chemicai mechanicai) to a low dielectric constant material layer 108. The capping layer 106 is usually silicon nitride (SiN) as a metal barrier This layer prevents the copper atoms in the copper metal layers 104 and 110 from diffusing into the insulating layer 102 and the low-dielectric constant material layer 108. In addition, the capping layer 106 can also be used as a final termination layer in a dual damascene process. However, there is a problem with the reliability of the capping layer between the low dielectric constant drain layer and the connection, such as the electron migration between copper wires (other peaks such as 〇11, _ and dependent dielectric breakdown, TDDB). And Lu, after the capping layer is deposited on the steel surface, then the dielectric layer will be deposited on the capping layer. This process of depositing the dielectric layer will cause stress to damage the capping layer. After the dual damascene process_ In the chemical mechanical research process, the low dielectric constant material layer and the capping layer 6 February 14, 103 Correction of poor adhesion between replacement pages will cause the dielectric layer to peel off, leading to the entry of water vapor and copper atoms Summary of the Invention: In light of this, this The purpose of the invention is to provide a method for forming a barrier layer between a low-dielectric material layer and an interconnect, by applying a plasma treatment to the capping layer to increase the distance between the low-W electric constant material layer and the capping layer. Another object of the present invention is to provide a method for forming a barrier layer between a low-dielectric material layer and an interconnect, by forming a barrier layer between the low-dielectric constant material layer and the capping layer. An adhesion layer is used to prevent the capping layer from being damaged during the formation of the low-dielectric material layer, and to prevent the low-dielectric material layer from being peeled off in the subsequent chemical mechanical polishing process. According to the above object, the present invention provides an A method for forming a barrier layer between a dielectric material layer and an interconnect. First, a substrate is provided, which is covered with an insulating layer and the insulating layer has a metal interconnect. Then, a metal interconnect and an insulating layer are formed over the substrate. One cover is wide. Then, the cover layer is subjected to a plasma treatment with a reaction gas, which includes carbon dioxide, ammonia, nitrogen dioxide, silane, trimethylsilane (3MS) and Methyl silicon At least one kind of alkane (4MS). Finally, a low-dielectric material layer is formed on the capping layer. Furthermore, the capping layer is composed of nitride nitride, silicon carbide, hydrocarbon, silicon oxycarbide, and carbon. According to another object of the present invention, the present invention provides a method for forming a barrier layer between a low dielectric material layer and an interconnect. First, a substrate is provided, which is covered with an insulating layer and

Claims (1)

548794 . -----— ·' 103年02月14日更正替換頁 可由碳化矽(SiC)、碳氫化矽(SICH)、碳氧化矽(SiCO)、及碳氮化矽 (SiCN)之一種所構成。之後,請參照第2C圖,對封蓋層206實施一 電漿處理。其中,所使用的反應氣體為二氧化碳(C0 2 )、氨氣_ 3 )、 二氧化氮(NO 2 )、石夕烧(SiH 4 )、三曱基>5夕炫(trimethylSilane,3MS) 及四甲基石夕烧(tetramethylsilane,4MS)之至少一種,以形成具有表面 活化的封蓋層206a。本實施例所通入的反應氣體中,二氧化碳、氨 氣、二氧化氮、矽烷、三甲基矽烷(3MS)及四甲基矽烷(4MS)的流速鲁 分別在500到1500SCCm的範圍、1500到3500SCCm的範圍、500 到 1500SCCm 的範圍、500 到 1500SCCm 的範圍、500 到 2500SCCm 的範圍、及500到2500SCCm的範圍。 接下來’請參照第2d圖,一低介電(l〇wk)材料層208,例如SILK、 FLARE、及ΡΑΠ,形成於封蓋層2〇6a上。其中,此低介電材料層 208具有一雙鑲嵌構造。隨後,銅金屬層21〇係沉積於低介電材料 層208上並填入雙鑲嵌構造中。此處,雙鑲嵌構造中的銅金屬層21〇 經由去除部分的封蓋層206a以電性連接於銅内連線204 ^ 接下來,請參照第2e圖,多餘的銅金屬層21〇係藉由化學機械 研磨法研磨至低介電材料層2〇8表面以在低介電材料層2()8中形成 銅内連線210。 9 103年02月14日更正替換*頁 如之前所述’封蓋層206&係作為一金屬阻障層而防止銅金屬屬 204及210中的銅原子擴散至絕緣層2()2及低介電常數材料層朋, 且可作為雙鑲絲程中的飯刻終止層。由於具有表面活化的封蓋層 206a與低介電材料層208作用而改善低介電常數材料層2〇8與封蓋 層206aM_著力。因此,根據本發明之方法,可防止介電常數 材料層208在後續的化學機械_製程中繼。亦即,可排除因封 蓋層與低介電材料層之間;Ϊ;佳的附著性造成可靠度降低的問題。 以下配合第3a到3d圖說明本發明第二實施例之在低介電材料層 與内連線間形成阻障層之方法。首先,請參照第3a圖,提供一基底 200。接著,一絕緣層202 ,例如氧化石夕層或有機矽玻璃 (〇rgananosilicate,OSG),沉積於此基底2〇〇上。此絕緣層2〇2中, 形成有製作内連線之溝槽。然後,一金屬層2〇4,例如銅金屬,係 /儿積於絕緣層202上並填入溝槽中。多餘的銅金屬層2〇4係藉由化 學機械研磨法研磨至絕緣層202表面以在絕緣層202中形成銅内連 線 204。 接下來,請參照第3b圖,一封蓋層206接著形成於銅内連線2〇4 及絕緣層202上。在本實施例中,此封蓋層206係氮化石夕層,其亦 可由碳化矽(SiC)、碳氫化石夕(SiCH)、碳氧化矽(sic〇)、及碳氮化矽 (SlCN)之一種所構成。之後,一附著層.207係形成於封蓋層206上。 548794 . < — 103年02月14日更正替換頁 在本實施例中’有兩種形成此附著層207的方法。一種是藉有使用 化學氣相沉積法(chemical vapor deposition)以形成附著層207,其中 所使用的反應氣體為二氧化碳、氨氣、二氧化氮、矽烷、三甲基矽 烧(3MS)及四甲基矽烷(4MS)之至少一種;另一種則是在封蓋層206 上塗覆一矽酸鹽溶液(作為附著促進劑)以形成附著層207。其中, 藉由藉有使用化學氣相沉積法形成的附著層207,厚度在1〇〇到2〇〇 埃的範圍。另外,藉由塗覆矽酸鹽溶液形成的附著層207,厚度在_ 1000到2000埃的範圍。 接下來,凊參照第3C圖,一低介電(lowk)材料層208,例如SILK、 FLARE、及PAI1 ’形成於附著層207上。其中,此低介電材料層2〇8 具有一雙鑲嵌構造。隨後,銅金屬層21〇係沉積於低介電材料層 上並填入雙鑲嵌構造中。此處’雙鑲嵌構造中的銅金屬層210經由 去除部分的附著層207及其下方的封蓋層206以電性連接於銅内連 線 204。 · 接下來,請參照第3d圖,多餘的銅金屬層210係藉由化學機械 研磨法研磨至低介電材料層2〇8表面以在低介電材料層2⑽中形成 銅内連線210。 在本實施例中,附著層2〇7及其下方的封蓋層2()6係構成一複合 式阻障層’且可增加其與低介電材料層2〇8之間的附著力。亦即,548794. ------ · 'February 14, 2013 Correction Replacement page can be one of Silicon Carbide (SiC), Silicon Carbide (SICH), Silicon Carbide (SiCO), and Silicon Carbide (SiCN) Made up. After that, referring to FIG. 2C, a plasma treatment is performed on the capping layer 206. Among them, the reaction gases used are carbon dioxide (C0 2), ammonia _ 3), nitrogen dioxide (NO 2), Shi Xiyan (SiH 4), trimethyl group (trimethylSilane (3MS)) and At least one kind of tetramethylsilane (4MS) to form a capping layer 206a having a surface activation. In the reaction gas passed in this embodiment, the flow rates of carbon dioxide, ammonia, nitrogen dioxide, silane, trimethylsilane (3MS) and tetramethylsilane (4MS) are in the range of 500 to 1500 SCCm, and 1500 to 3500SCCm range, 500 to 1500SCCm range, 500 to 1500SCCm range, 500 to 2500SCCm range, and 500 to 2500SCCm range. Next, please refer to FIG. 2d. A low-dielectric (10wk) material layer 208, such as SILK, FLARE, and PAII, is formed on the capping layer 206a. The low-dielectric material layer 208 has a double damascene structure. Subsequently, the copper metal layer 21 is deposited on the low-dielectric material layer 208 and filled into the dual damascene structure. Here, the copper metal layer 21 in the dual damascene structure is electrically connected to the copper interconnect 204 through the capping layer 206a of the removed portion. ^ Next, referring to FIG. 2e, the extra copper metal layer 21 is borrowed. The surface of the low-dielectric material layer 208 is ground by a chemical mechanical polishing method to form a copper interconnect 210 in the low-dielectric material layer 2 () 8. 9 February 14, 103 Correction Replacement * page as mentioned earlier 'Capping layer 206 & acts as a metal barrier layer to prevent copper atoms in copper metals 204 and 210 from diffusing into insulating layer 2 () 2 and lower The dielectric constant material layer can be used as a meal-engraving stop layer in the double-wire setting process. Due to the action of the cap layer 206a having a surface activation and the low dielectric material layer 208, the low dielectric constant material layer 208 and the cap layer 206a are improved. Therefore, according to the method of the present invention, the dielectric constant material layer 208 can be prevented from being relayed in the subsequent chemical mechanical process. That is, the problem of lowered reliability due to the good adhesion between the capping layer and the low dielectric material layer can be eliminated. The method of forming a barrier layer between the low-dielectric material layer and the interconnects according to the second embodiment of the present invention will be described with reference to FIGS. 3a to 3d. First, referring to FIG. 3a, a substrate 200 is provided. Next, an insulating layer 202, such as a stone oxide layer or an organosilicate glass (OSG), is deposited on the substrate 200. In this insulating layer 202, a trench for forming interconnects is formed. Then, a metal layer 204, such as copper metal, is deposited on the insulating layer 202 and filled into the trench. The extra copper metal layer 204 is ground to the surface of the insulating layer 202 by a chemical mechanical polishing method to form a copper interconnect 204 in the insulating layer 202. Next, referring to FIG. 3b, a capping layer 206 is then formed on the copper interconnects 204 and the insulating layer 202. In this embodiment, the capping layer 206 is a nitrided silicon nitride layer, which may also be composed of silicon carbide (SiC), silicon carbide (SiCH), silicon oxycarbide (sic0), and silicon carbonitride (SlCN). One kind of composition. Thereafter, an adhesion layer .207 is formed on the capping layer 206. 548794. < February 14, 103, Replacement page correction In this embodiment, there are two methods of forming this adhesion layer 207. One is to use chemical vapor deposition to form an adhesion layer 207. The reaction gases used are carbon dioxide, ammonia, nitrogen dioxide, silane, trimethylsilicon (3MS), and tetramethyl At least one kind of silane (4MS); the other is to apply a silicate solution (as an adhesion promoter) on the capping layer 206 to form an adhesion layer 207. Among them, the thickness of the adhesion layer 207 formed by using a chemical vapor deposition method is in a range of 100 to 2000 angstroms. In addition, the thickness of the adhesion layer 207 formed by applying a silicate solution is in the range of 1000 to 2000 angstroms. Next, referring to FIG. 3C, a low-k material layer 208 such as SILK, FLARE, and PAI1 'is formed on the adhesion layer 207. The low-dielectric material layer 208 has a double damascene structure. Subsequently, the copper metal layer 21 is deposited on the low-dielectric material layer and filled into the dual damascene structure. Here, the copper metal layer 210 in the 'dual damascene structure is electrically connected to the copper interconnect 204 via the removed adhesive layer 207 and the capping layer 206 thereunder. · Next, referring to Fig. 3d, the excess copper metal layer 210 is ground to the surface of the low-dielectric material layer 208 by chemical mechanical polishing to form a copper interconnect 210 in the low-dielectric material layer 2⑽. In this embodiment, the adhesion layer 2007 and the capping layer 2 () 6 below it constitute a composite barrier layer 'and can increase the adhesion between the adhesion layer 2 and the low-dielectric material layer 208. that is,
TW91117746A 2002-08-07 2002-08-07 Method of forming barrier layer between low k material layer and interconnect TW548794B (en)

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