JP6602910B2 - Semiconductor structure, integrated circuit structure, and manufacturing method thereof - Google Patents

Description

  Embodiments of the present invention relate to the field of semiconductor devices and processing, and in particular, to self-aligned gate edges and local interconnect structures, and methods for fabricating self-aligned gate edges and local interconnect structures.

  During the past decades, scaling of structures in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to increasingly fine structures allows for increased density of functional units over a limited area of a semiconductor chip. For example, by reducing transistor dimensions, an increased number of memory or logic devices can be built on the chip, resulting in the manufacture of products with increased capacity. However, aiming for more capacity is not without problems. The need to optimize the performance of each device is becoming increasingly important.

  In the manufacture of integrated circuit devices, multi-gate transistors such as tri-gate transistors have become more widely used as device dimensions continue to shrink. In conventional processes, tri-gate transistors are generally fabricated on either a bulk silicon substrate or a silicon-on-insulator substrate. In some examples, a bulk silicon substrate is preferred because of its lower cost and because it allows an uncomplicated tri-gate manufacturing process.

  However, scaling of a multi-gate transistor has not been possible without thinking about it. Lithographic processes used to pattern these building blocks as the dimensions of these building blocks of microelectronic circuits are reduced and the number of basic building blocks produced in a given area increases. The restrictions on are now out of control. In particular, there may be a trade-off between the minimum dimensions (critical dimensions) of structures that are patterned into the semiconductor stack and the spacing between such structures.

FIG. 3 shows a plan view of a layout including a plurality of fin-based semiconductor devices including end-to-end spacing.

Sectional drawing of the important process process in the manufacturing method of the conventional finFET or a tri-gate process is shown. Sectional drawing of the important process process in the manufacturing method of the conventional finFET or a tri-gate process is shown. Sectional drawing of the important process process in the manufacturing method of the conventional finFET or a tri-gate process is shown. Sectional drawing of the important process process in the manufacturing method of the conventional finFET or a tri-gate process is shown.

FIG. 4 shows a cross-sectional view of important process steps in a self-aligned gate edge process fabrication approach for a finFET or tri-gate device, according to one embodiment of the present invention. FIG. 4 shows a cross-sectional view of important process steps in a self-aligned gate edge process fabrication approach for a finFET or tri-gate device, according to one embodiment of the present invention. FIG. 4 shows a cross-sectional view of important process steps in a self-aligned gate edge process fabrication approach for a finFET or tri-gate device, according to one embodiment of the present invention. FIG. 4 shows a cross-sectional view of important process steps in a self-aligned gate edge process fabrication approach for a finFET or tri-gate device, according to one embodiment of the present invention.

FIG. 4 shows a cross-sectional view and corresponding top view of processing steps in another self-aligned gate edge process fabrication approach for a finFET or tri-gate device, according to another embodiment of the present invention. FIG. 4 shows a cross-sectional view and corresponding top view of processing steps in another self-aligned gate edge process fabrication approach for a finFET or tri-gate device, in accordance with another embodiment of the present invention. FIG. 4 shows a cross-sectional view and corresponding top view of processing steps in another self-aligned gate edge process fabrication approach for a finFET or tri-gate device, in accordance with another embodiment of the present invention. FIG. 4 shows a cross-sectional view and corresponding top view of processing steps in another self-aligned gate edge process fabrication approach for a finFET or tri-gate device, in accordance with another embodiment of the present invention. FIG. 4 shows a cross-sectional view and corresponding top view of processing steps in another self-aligned gate edge process fabrication approach for a finFET or tri-gate device, in accordance with another embodiment of the present invention. FIG. 4 shows a cross-sectional view and corresponding top view of processing steps in another self-aligned gate edge process fabrication approach for a finFET or tri-gate device, according to another embodiment of the present invention. FIG. 4 shows a cross-sectional view and corresponding top view of processing steps in another self-aligned gate edge process fabrication approach for a finFET or tri-gate device, in accordance with another embodiment of the present invention.

FIG. 4 illustrates a cross-sectional view of a portion of a semiconductor device having a self-aligned gate / trench contact end cap (SAGE) with a local interconnect (LI) patterned with pitch division according to one embodiment of the present invention.

FIG. 4 illustrates a cross-sectional view of a portion of a semiconductor device having a self-aligned gate / trench contact end cap (SAGE) with a self-aligned local interconnect (SAGELI), in accordance with another embodiment of the present invention.

FIG. 3 shows a three-dimensional cross-sectional view from various angles of various steps in the manufacture of a self-aligned gate end cap, according to one embodiment of the present invention. FIG. 3 shows a three-dimensional cross-sectional view from various angles of various steps in the manufacture of a self-aligned gate end cap, according to one embodiment of the present invention. FIG. 3 shows a three-dimensional cross-sectional view from various angles of various steps in the manufacture of a self-aligned gate end cap, according to one embodiment of the present invention. FIG. 3 shows a three-dimensional cross-sectional view from various angles of various steps in the manufacture of a self-aligned gate end cap, according to one embodiment of the present invention. FIG. 3 shows a three-dimensional cross-sectional view from various angles of various steps in the manufacture of a self-aligned gate end cap, according to one embodiment of the present invention. FIG. 3 shows a three-dimensional cross-sectional view from various angles of various steps in the manufacture of a self-aligned gate end cap, according to one embodiment of the present invention. FIG. 3 shows a three-dimensional cross-sectional view from various angles of various steps in the manufacture of a self-aligned gate end cap, according to one embodiment of the present invention. FIG. 3 shows a three-dimensional cross-sectional view from various angles of various steps in the manufacture of a self-aligned gate end cap, according to one embodiment of the present invention.

FIG. 2 shows a three-dimensional cross-sectional view from the perspective of various structural options for providing a basis for manufacturing a local interconnect, according to one embodiment of the present invention. FIG. 2 shows a three-dimensional cross-sectional view from the perspective of various structural options for providing a basis for manufacturing a local interconnect, according to one embodiment of the present invention. FIG. 2 shows a three-dimensional cross-sectional view from the perspective of various structural options for providing a basis for manufacturing a local interconnect, according to one embodiment of the present invention. FIG. 2 shows a three-dimensional cross-sectional view from the perspective of various structural options for providing a basis for manufacturing a local interconnect, according to one embodiment of the present invention.

FIG. 4 illustrates a cross-sectional view of a non-planar semiconductor device having self-aligned gate edge isolation according to an embodiment of the present invention.

FIG. 8B shows a top view made along the aa ′ axis of the semiconductor device of FIG. 8A, in accordance with one embodiment of the present invention.

1 illustrates a computing device according to one implementation of the invention.

  A self-aligned gate edge and local interconnect structure and a method of manufacturing the self-aligned gate edge and local interconnect structure are described. In the following description, numerous specific details are set forth, such as specific integrations and material forms, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to those skilled in the art that multiple embodiments of the invention may be practiced without these specific details. In other instances, well-known features such as integrated circuit design layout have not been described in detail so as not to unnecessarily obscure embodiments of the present invention. In addition, it should be understood that the various embodiments shown in the drawings are illustrative and are not necessarily drawn to scale.

  One or more embodiments of the present invention relate to a plurality of semiconductor structures or devices having one or more gate edge structures (eg, as a plurality of gate isolation regions) among a plurality of gate electrodes of the plurality of semiconductor structures or devices. . One or more embodiments relate to the fabrication of local interconnects for such gate electrode structures. In addition, methods for fabricating gate edge isolation structures in a self-aligned manner and / or methods for fabricating local interconnects are also described. In one or more embodiments, self-aligned gate edge structures and / or local interconnects are fabricated for logic transistors based on complementary metal oxide semiconductor (CMOS) devices.

  To explain the situation, scaling of the gate endcap region and trench contact (TCN) endcap region is an important contributor to improving transistor layout area and density. The gate end cap region and the TCN end cap region refer to the gate and TCN protruding from the diffusion region / fin of the semiconductor device. As an example, FIG. 1 shows a top view of a layout 100 that includes fin-based semiconductor devices that include end-to-end spacing. Referring to FIG. 1, the first semiconductor device 102 and the second semiconductor device 104 are based on semiconductor fins 106 and 108, respectively. Each device 102 and 104 has a gate electrode 110 or 112, respectively. In addition, each device 102 and 104 has a trench contact (TCN) 114 and 116, respectively, in the source and drain regions of the fins 106 and 108, respectively. The gate electrodes 110 and 112 and the TCNs 114 and 116 each have an end cap region, and the end cap regions are disposed away from the corresponding fins 106 and 108, respectively.

  Referring again to FIG. 1, the gate end cap and TCN end cap dimensions typically need to include a margin for mask alignment errors to ensure robust transistor operation even in the worst case mask misalignment. As a result, an end-to-end interval 118 remains. Therefore, another important design rule that is essential for improving transistor layout density is the spacing between two adjacent end caps facing each other. However, the parameter “end cap × 2 + end-to-end spacing” is becoming increasingly difficult to scale using lithographic patterning to meet the scaling requirements for new technologies. Specifically, the additional end cap length required to account for mask alignment errors is due to the longer overlap between the TCN and the gate electrode. Capacitance values are also increased, thereby increasing the dynamic energy consumption of the product and degrading performance. Prior solutions have focused on improving alignment margins and increasing patterning or resolution to allow for a reduction in both end cap dimensions and end cap spacing.

  In accordance with one embodiment of the present invention, an approach provided for self-aligned gate endcaps and TCNs that protrude from the semiconductor fins without the need to consider any mask alignment is described. In one such embodiment, a disposable spacer is fabricated on the edge of the semiconductor fin, which determines the protruding dimensions of the gate end cap and contacts. The end cap process defined by the spacer allows the gate end cap region and the TCN end cap region to be self-aligned with respect to the semiconductor fins, and thus an extra end cap length that addresses mask misalignment. Do not need. Furthermore, the approach described herein does not require lithographic patterning at the previously required stage, since the gate endcap and TCN endcap / overhang dimensions remain fixed, and between electrical parameters of the device. This results in improved (ie reduced) variation.

  To provide a control comparison, FIGS. 2A-2D show cross-sectional views of multiple processing steps that are important in a conventional finFET or tri-gate process fabrication approach. In contrast, FIGS. 3A-3D illustrate cross-sectional views of a number of processing steps that are important in a self-aligned gate edge process manufacturing approach for a finFET or tri-gate device, according to one embodiment of the present invention.

  Referring to FIGS. 2A and 3A, a bulk semiconductor substrate 200 or 300, such as a bulk single crystal silicon substrate, is provided having a plurality of fins 202 or 302 etched therein, respectively. In one embodiment, the plurality of fins are formed directly in the bulk substrate 200 or 300 and thus are integrally formed with the bulk substrate 200 or 300. It should be understood that a plurality of shallow trench isolation structures can be formed between a plurality of fins in the substrate 200 or 300. Referring to FIG. 3A, a hard mask layer 304, such as a silicon nitride hard mask layer, and a pad oxide layer 306, such as a silicon dioxide layer, are patterned on the plurality of fins 302 after patterning to form the plurality of fins 302. To remain. On the other hand, referring to FIG. 2A, such a hard mask layer and a pad oxide layer are removed.

  Referring to FIG. 2B, a dummy or permanent gate insulator layer 210 is formed on a plurality of exposed surfaces of a plurality of semiconductor fins 202, and a dummy gate layer 212 is formed on the resulting structure. Meanwhile, referring to FIG. 3B, a dummy or permanent gate insulator layer 310 is formed on a plurality of exposed surfaces of a plurality of semiconductor fins 302, and a plurality of dummy spacers 312 are formed adjacent to the resulting structure. Has been.

  Referring to FIG. 2C, patterning is performed to cut the gate end cap and a plurality of isolation regions 214 are formed at the resulting patterned dummy gate end 216. In the conventional process approach, larger gate end caps must be manufactured to account for misalignment of the gate mask, as illustrated by arrowed area 218. On the other hand, referring to FIG. 3C, by providing an isolation layer over the structure of FIG. 3B, a plurality of self-aligned isolation regions 314 are formed, for example, by deposition and planarization. In one such embodiment, the self-aligned gate endcap process does not require extra space for mask alignment, as compared in FIGS. 2C and 3C.

  Referring to FIG. 2D, the dummy gate electrode 212 of FIG. 2C is replaced with a plurality of permanent gate electrodes. If a dummy gate insulator layer is used, such a dummy gate insulator layer can also be replaced by a permanent gate insulator layer in this process. In the illustrated example, a dual metal gate replacement process is provided to provide an N-type gate electrode 220 on the first semiconductor fin 202A and a P-type gate electrode 222 on the second semiconductor fin 202B. Executed. The N-type gate electrode 220 and the P-type gate electrode 222 are formed between the plurality of gate edge isolation structures 214, but form a P / N junction 224 where both gate electrodes are in contact. The exact position of the P / N junction 224 can vary depending on misalignment, as illustrated by the region 226 with arrows.

  Meanwhile, referring to FIG. 3D, the hard mask layer 304 and the pad oxide layer 306 are removed, and the plurality of dummy spacers 314 in FIG. 3C are replaced with a plurality of permanent gate electrodes. If a dummy gate insulator layer is used, such a dummy gate insulator layer can also be replaced by a permanent gate insulator layer in this process. In the illustrated example, a dual metal gate replacement process is provided to provide an N-type gate electrode 320 on the first semiconductor fin 302A and a P-type gate electrode 322 on the second semiconductor fin 302B. Executed. The N-type gate electrode 320 and the P-type gate electrode 322 are formed between the plurality of gate edge isolation structures 314 and are also separated by them.

  Referring again to FIG. 2D, the local interconnect 240 may be fabricated to contact the N-type gate electrode 220 and the P-type gate electrode 222 to provide a conductive path around the P / N junction 224. Similarly, referring to FIG. 3D, a local interconnect 340 is fabricated to bring the N-type gate electrode 320 and the P-type gate electrode 322 into contact and provide a conductive path over the isolation structure 314 interposed therebetween. obtain. With reference to both FIG. 2D and FIG. 3D, a hard mask 242 or 342 may be formed on the local interconnect 240 or 340, respectively.

  In another aspect, the hard mask and pad oxide layers may not be retained on the patterned fins throughout the manufacturing process of the dummy spacer and the plurality of self-aligned gate edge isolation structures. Therefore, the height of the plurality of semiconductor fins may need to be differentiated by another method with respect to the height of the plurality of dummy spacers. As an example, FIGS. 4A-4G are cross-sectional views and corresponding views of multiple processing steps in another self-aligned gate edge process manufacturing technique for a finFET or tri-gate device, according to another embodiment of the present invention. FIG.

  Referring to FIG. 4A, a bulk semiconductor substrate 400, such as a bulk single crystal silicon substrate, is provided having a plurality of fins 402 etched therein. In one embodiment, the plurality of fins 402 are formed directly in the bulk substrate 400 and thus are integrally formed with the bulk substrate 400. It should be understood that a plurality of shallow trench isolation structures can be formed between a plurality of fins within the substrate 400. In one embodiment, as illustrated in FIG. 4A, multiple artifacts due to patterning of multiple fins 402, such as hard mask layers and pad oxide layers, have been removed.

  Referring to FIG. 4B, a plurality of dummy spacers 404 are formed along a plurality of side walls of the plurality of fins 402. In one embodiment, the plurality of dummy spacers 404 is formed by a deposition and etching process that ultimately exposes the surfaces of the plurality of fins 402. It should be understood that the plurality of fins 402 may be protected prior to forming the plurality of dummy spacers 404, for example, by deposition or growth of a dummy gate insulator layer. In one embodiment, the plurality of fins 402 are a plurality of silicon fins protected with a silicon dioxide layer, and the plurality of dummy spacers are made of silicon nitride or similar material. However, in another embodiment, the plurality of fins 402 are not protected at this stage.

  Referring to FIG. 4C, a plurality of isolation structures 406 are formed in the plurality of open regions of the structure of FIG. 4B. In one embodiment, a plurality of isolation regions 406 are formed by depositing an insulator film over the structure of FIG. 4B and then planarizing it (eg, by chemical mechanical polishing). In certain embodiments, the plurality of isolation structures are comprised of a material such as, but not limited to, silicon oxide, silicon nitride, silicon carbide, or combinations thereof.

  Referring to FIG. 4D, the plurality of fins 402 are recessed with respect to the height of the plurality of separation structures 406 and the height of the plurality of dummy spacers 404. In one embodiment, the recess is performed by using a selective etch process. In one such embodiment, the overcoat layer initially formed on the plurality of fins 402 is removed before or while the plurality of fins 402 are recessed.

  Referring to FIG. 4E, a plurality of dummy spacers 404 are removed from the structure of FIG. 4D. In one embodiment, the removal is performed by using a selective etching process. In one such embodiment, the plurality of isolation structures 406 are composed of silicon oxide, the plurality of fins 402 are composed of silicon, and the plurality of selectively removed dummy spacers are composed of silicon nitride.

  Referring to FIG. 4F, a gate electrode stack 408 is formed at the position where the plurality of dummy spacers 404 are removed and along the surface of the plurality of recessed fins 402. In one embodiment, the gate electrode stack 408 includes a conformal gate insulator layer 410, such as a high dielectric constant gate insulator layer, and a metal gate electrode 412. The cross-sectional view of FIG. 4F is made along the aa ′ axis of the top view of FIG. 4F. However, it should be understood that the top view is made somewhat deep into the structure to show the entire plurality of fins 402. In practice, the metal gate material 412 will cover the plurality of fins 402 in a top view.

  Referring to FIG. 4G, a plurality of trench contacts 414 are formed along the surface of the recessed plurality of fins 402 adjacent to the plurality of gate electrode stacks 408. In one embodiment, the plurality of trench contacts 414 are in contact with the source and drain regions in the plurality of fins 402 and are separated from the plurality of gate electrode stacks 408 by a plurality of insulator spacers 416. The cross-sectional view of FIG. 4G is made along the bb ′ axis of the top view of FIG. 4G. However, it should be understood that the top view is made somewhat deep into the structure to show the entire plurality of fins 402. Actually, in the top view, the trench contact 414 covers the plurality of fins 402.

  In another aspect, referring again to FIG. 3D, in one embodiment, one or more of the above approaches may be performed above a gate and trench contact (TCN) to connect adjacent gate and TCN electrodes. Requires an additional local interconnect layer (LI). In one such embodiment, such a local interconnect needs to overlap the gate and TCN without causing a contact-to-gate (CTG) short circuit. As such, local interconnect manufacturing may require a sufficient CTG short margin, patterning multiple lines at half the gate pitch, and maintaining robust LI-TCN contacts. Thus, alignment between LI and gate or TCN is another difficult patterning problem. Thus, according to one embodiment of the present invention, a method for manufacturing a plurality of local interconnect lines that self-align to the gate and TCN is provided to address the above concerns without having to consider any mask alignment. This approach involves the manufacture of spacers along the higher stack, including dummy gates and hard masks, extending above the self-aligned gate end cap. In one such embodiment, the plurality of spacers function as a continuous plurality of self-aligning walls that separate the gates and contacts. Two additional insulator materials with contrasting etch characteristics are used as hard masks that allow the selective opening of the gate-LI (LIG) and TCN-LI (LIT) regions. obtain.

  As an example, FIG. 5A illustrates a cross-sectional view of a portion of a semiconductor device having a self-aligned gate / trench contact endcap (SAGE) with a pitch-patterned local interconnect (LI) according to one embodiment of the invention. Show. FIG. 5B, on the other hand, illustrates a cross-sectional view of a portion of a semiconductor device having a self-aligned gate / trench contact endcap (SAGE) with a self-aligned local interconnect (SAGELI), according to another embodiment of the present invention.

  Referring to FIG. 5A, the semiconductor device 500 A includes semiconductor fins 502. A plurality of low self-aligned isolation structures 504 isolate regions of alternating gates 506 and trench contacts 508. A plurality of upper isolation structures 510 separate the alternating trench contact local interconnect 512 and gate local interconnect 514. As shown in FIG. 5A, trench contact local interconnect 512 and gate local interconnect 514 are formed by pitch division patterning to accommodate misalignment. It should also be understood that multiple insulator caps may be formed on the trench contact local interconnect 512 and the gate local interconnect 514, as illustrated in FIG. 5A.

  Referring to FIG. 5B, the semiconductor device 500B includes semiconductor fins 552. A plurality of high self-aligned isolation structures 554 separate alternating gate 556 and trench contact 558 regions. A plurality of identical isolation structures 554 also isolate alternating trench contact local interconnects 562 and gate local interconnects 564. The trench contact local interconnect 562 and the gate local interconnect 564 are formed without using additional lithography operations as required in the case of FIG. 5A. It should be understood that a plurality of insulator caps can be formed on the trench contact local interconnect 562 and the gate local interconnect 564, as illustrated in FIG. 5B. In one embodiment, the trench contact local interconnect 512 and the gate local interconnect 514 are manufactured at different stages, and the process of forming each replaces the actual permanent material of the trench contact local interconnect 512 and the gate local interconnect 514. It should also be understood that the use of the plug / hard mask layer as a placeholder has been exploited before. Further, although all locations are shown in FIG. 5B as having gate local interconnects or trench contact local interconnects, not all locations need be selected for local interconnects. At locations that are not selected, the insulator plug or hard mask may remain (ie, not selected for removal at specific locations).

  In accordance with an embodiment of the present invention, as an exemplary approach, FIGS. 6A-6H show three-dimensional cross-sectional views from different perspectives of various processes in the manufacture of multiple self-aligned gate endcaps. In accordance with one embodiment of the present invention, FIGS. 7A-7D show oblique three-dimensional cross-sectional views of various structural options for providing a basis for local interconnect manufacturing.

  Referring to FIG. 6A, a plurality of semiconductor fins 602 are formed by patterning a substrate 600, such as a single crystal silicon substrate, and the patterning includes pitch 2-division patterning or pitch 4-division patterning. Further, while the fin 602 is patterned, the protective film layer 604, the dummy gate layer 606 (polycrystalline silicon layer, etc.), and the hard mask layer 608 are patterned.

  Referring to FIG. 6B, a shallow trench isolation (STI) layer 610 is formed on the structure of FIG. 6A. In one embodiment, the STI layer 610 includes a silicon dioxide layer and is formed by chemical vapor deposition (CVD) and then chemical mechanical planarization (CMP). In one embodiment, the STI structure includes a liner insulator layer 612, as shown in FIG. 6B.

  Referring to FIG. 6C, the STI layer 610 of FIG. 6B is recessed to form an STI structure 614 (which may include a liner insulator layer), and a dummy gate insulator layer 616 is formed on the resulting structure. In one such embodiment, the dummy gate insulator layer 616 is formed by deposition and further deposited on the STI structure 614 as shown. Further, although also illustrated, the hard mask layer 608 can be removed.

  Referring to FIG. 6D, a plurality of spacers 618 are formed along the plurality of sidewalls of the plurality of protrusions of the structure of FIG. 6C. In one embodiment, the plurality of spacers 618 are formed by a deposition process and then an anisotropic etch process. In one such embodiment, the plurality of spacers is comprised of deposited polycrystalline silicon. Depending on the spacing between a particular plurality of fins 602, the spacer 618 may be separate from all other spacers or may be integral with another spacer. As an example, portion 620A has separate spacers 618A, whereas portion 620B includes a pair of continuous spacers 618B. Accordingly, referring collectively to FIGS. 6A-6D, the finFET “hat” and dummy gate poly are patterned using a standard pitch division fin patterning process, and the spacers Formed on both sides of the fin-polypillar.

  Referring to FIG. 6E, a plurality of gaps between the plurality of spacers 618 in FIG. 6D are filled with an insulator material layer 622 to form a plurality of transistor isolations. In one embodiment, the insulator material is comprised of a silicon nitride material.

  Referring to FIG. 6F, the insulator material layer 622 is planarized (eg, by CMP) to expose the dummy gate layer 606 and the corresponding plurality of spacers 618. In one embodiment, the dummy gate layer 606 and the corresponding plurality of spacers 618 are both composed of polycrystalline silicon. This process forms a self-aligned end cap separation wall 624.

  Referring to FIG. 6G, on the structure of FIG. 6H, a second dummy layer and hard mask stack, or only a high hard mask, is deposited and patterned using pitch division gate patterning (both in both cases). 6G, shown as member 626). In one embodiment, if a dummy layer and hardmask stack is used, the dummy layer is comprised of polycrystalline silicon.

  Referring to FIG. 6H, selective anisotropic etching is performed on hard mask layer 626, isolation wall 624, and finFET “hat” 616 (eg, remaining from the dummy gate insulator layer). Thus, a straightened shape is provided between the patterned lines and the resulting end cap isolation cage 628. Although not shown, a conductive layer is provided to provide multiple trench contacts after gate spacer formation, N-type or P-type source / drain formation, and gate electrode replacement (eg, with a high dielectric constant / metal gate). A material is formed in the plurality of end cap isolation cages 628. If the plurality of separation walls are sufficiently high, a plurality of self-aligned local interconnect lines can be produced. Several examples are described below in connection with FIGS. 7C and 7D.

  To provide an initial comparison, FIG. 7A shows a three-dimensional cross-sectional view of the base structure 700A without self-aligned gate edge separation as seen from an angle. Referring to FIG. 7A, the plurality of fins 702A have a dummy gate layer 704A and a corresponding hard mask 706A patterned thereon. In the next production of multiple local interconnects, a pitch division patterning scheme will need to be used.

  FIG. 7B shows a three-dimensional cross-sectional view of the basic structure 700B having self-aligned gate edge separation as seen from an angle. Referring to FIG. 7B, the plurality of fins 702B have a dummy gate layer 704B and a corresponding hard mask 706B patterned thereon. A plurality of self-aligned gate edge isolation structures 708B are formed between various groups of the plurality of fins 702B. However, hard mask 706B is relatively low compared to multiple self-aligned gate edge isolation structures 708B. Therefore, a pitch division patterning scheme will need to be used in the next manufacturing of multiple local interconnects.

  FIG. 7C shows a three-dimensional cross-sectional view of the base structure 700C with self-aligned gate edge separation as seen from an angle. Referring to FIG. 7C, the plurality of fins 702C include a dummy gate layer 704C, a corresponding second dummy layer 705C, and a corresponding hard mask 706C patterned thereon. A plurality of self-aligned gate edge isolation structures 708C are formed between various groups of the plurality of fins 702C. The height of the hard mask 706C combined with the second dummy layer 705C is relatively high compared to the self-aligned gate edge isolation structure 708C. Therefore, a self-aligned local interconnect technique can be used in the next local interconnect manufacturing.

  FIG. 7D shows a three-dimensional cross-sectional view of the base structure 700D with self-aligned gate edge separation as seen from an angle. Referring to FIG. 7D, the plurality of fins 702D have a dummy gate layer 704D and a corresponding high hard mask 706D patterned thereon. A plurality of self-aligned gate edge isolation structures 708D are formed between various groups of the plurality of fins 702D. The height of the high hard mask 706D is relatively high compared to the plurality of self-aligned gate edge isolation structures 708D. Therefore, a self-aligned local interconnect technique can be used in the next local interconnect manufacturing.

  More generally, one or more embodiments described herein may include various important front-end masks such as area scaling, capacitance reduction, and / or gate cut masks. Provides a means for deletion. In one such embodiment, the minimum transistor width can be reduced by up to 30% by implementing one or more of the approaches described herein. Smaller transistor dimensions reduce the capacitance between the gate and the TCN and other parasitic capacitances. Since no extra mask steps are required to form multiple end caps, contacts, and local interconnect lines, many masks required for such multiple structures in a standard process are omitted.

  More specifically, the plurality of main features of the one or more embodiments described above may include one or more of the following three items. (1) The gate end cap is the distance from the fin edge to the separation edge. This distance is defined by the spacer width and is the same size for all transistors. Since no lithographic patterning is required to define the end cap, there is no need to consider mask alignment in the end cap. (2) The protrusion of TCN from the fin is determined by the spacer width and is not affected by the alignment of the mask. (3) The multiple local interconnect lines are self-aligned with respect to the gate and TCN by utilizing multiple gate patterning lines above the isolation walls of the transistor and can be selectively opened at one time. Forming a hard mask. Embodiments are applicable to the 7 nm node generation, for example, improving transistor layout density and gate capacitance (improving dynamic energy and performance) and reducing the total number of masks.

  It will be appreciated that the structures resulting from the above exemplary processing techniques can be used in the same or similar form in subsequent processing operations to complete device manufacturing, such as PMOS and NMOS device manufacturing. Should. As an example of a completed device, FIGS. 8A and 8B show a non-planar type with self-aligned gate edge isolation as manufactured according to one embodiment of the invention and on the structure described in connection with FIG. 3D. FIG. 2 shows a cross-sectional view and a plan view (made along the aa ′ axis of the cross-sectional view), respectively, of the semiconductor device.

  Referring to FIG. 8A, a semiconductor structure or device 800 is formed of a substrate 802 and a non-planar active region formed in an isolation region 806 (eg, a fin structure including protruding fin portions 804 and sub-fin regions 805). including. A plurality of gate structures 808 are disposed on the plurality of protrusions 804 in the non-planar active region and on a portion of the isolation region 806. As shown, the plurality of gate structures 808 includes a gate electrode 850 and a gate insulator layer 852. In one embodiment, although not shown, the plurality of gate structures 808 may also include an insulator cap layer. The plurality of gate structures 808 are separated by a self-aligned gate edge isolation structure 820. A local interconnect 854 connects a plurality of adjacent gate structures 808. The gate contact 814 and the overlying gate contact via 816 are also seen from this perspective along with the overlying metal interconnect 860, all of which are located in the interlayer insulator stack or layer 870. As can also be seen from the perspective view of FIG. 8A, in one embodiment, the gate contact 814 is disposed over a plurality of non-planar active regions. As also illustrated in FIG. 8A, there is a boundary 880 between the doping profile of the plurality of protruding fin portions 804 and the plurality of sub-fin regions 805, although other embodiments may include these regions. The doping profile between does not include such a boundary.

  Referring to FIG. 8B, a plurality of gate structures 808 are shown disposed over the plurality of protruding fin portions 804 and separated by a plurality of self-aligned gate edge isolation structures 820. Although source and drain regions 804A and 804B of a plurality of protruding fin portions 804 are shown in this perspective, it should be understood that these regions overlap with a plurality of trench contact structures. In one embodiment, the source and drain regions 804A and 804B are doped portions of the original material of the plurality of protruding fin portions 804. In another embodiment, the material of the plurality of protruding fin portions 804 is removed and replaced with another semiconductor material, for example, by epitaxial growth. In any case, the source and drain regions 804A and 804B may extend below the height of the insulator layer 806, ie, into the subfin region 805.

  In one embodiment, the semiconductor structure or device 800 is a non-planar device such as, but not limited to, a finFET or a tri-gate device. In one such embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional object. In one such embodiment, a plurality of gate structures 808 surround at least the top and sidewall pairs of the three-dimensional object.

  The substrate 802 can be made of a semiconductor material that can withstand the manufacturing process and transfer charges. In one embodiment, the substrate 802 is a crystalline silicon, silicon / germanium, or germanium layer doped with a charge carrier such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof to form the active region 804. A configured bulk substrate. In one embodiment, the silicon atom concentration in the bulk substrate 802 is greater than 97%. In another embodiment, the bulk substrate 802 is comprised of an epitaxial layer grown on a separate crystal substrate. For example, a silicon epitaxial layer grown on a boron-doped bulk silicon single crystal substrate. Bulk substrate 802 may instead be composed of a III-V material. In one embodiment, the bulk substrate 802 is a III-V such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimony, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. Composed of family materials. In one embodiment, the bulk substrate 802 is composed of a III-V material and the charge carrier dopant impurity atoms include, but are not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

  The isolation region 806 ultimately electrically isolates or contributes to the isolation of portions of the permanent gate structure from the underlying bulk substrate or isolates the active regions of the fins. Or may be composed of a suitable material that separates the active areas formed in the underlying bulk substrate. For example, in one embodiment, the isolation region 806 is comprised of an insulator material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon doped silicon nitride.

  The plurality of self-aligned gate edge isolation structures 820 may ultimately be constructed of suitable materials that electrically isolate or contribute to the isolation of portions of the plurality of gate structures from each other. For example, in one embodiment, the isolation region 806 is comprised of an insulator material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon doped silicon nitride.

  The plurality of gate structures 808 can be comprised of a gate electrode stack that includes a gate insulator layer 852 and a gate electrode layer 850. In one embodiment, the gate electrode of the gate electrode stack is comprised of a metal gate and the gate insulator layer is comprised of a high dielectric constant material. For example, in one embodiment, the gate insulator layer is not limited to hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate. , Strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, lead zinc niobate, or combinations thereof. Further, a portion of the gate insulator layer may include a native oxide layer formed from some top layer of the substrate 802. In one embodiment, the gate insulator layer is comprised of an upper high dielectric constant portion and a lower portion comprised of an oxide of semiconductor material. In one embodiment, the gate insulator layer is composed of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride.

  In one embodiment, the gate electrode is not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or It is composed of a metal layer such as a conductive metal oxide. In certain embodiments, the gate electrode is comprised of a filler material that does not set the work function formed above the layer that sets the work function of the metal.

  The plurality of spacers associated with the plurality of gate electrode stacks ultimately isolate or permanently isolate the permanent gate structure from a plurality of adjacent conductive contacts, such as a plurality of self-aligned contacts. It can be composed of suitable contributing materials. For example, in one embodiment, the plurality of spacers is comprised of an insulator material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

  The gate interconnect via 816 overlying the local interconnect 854, the gate contact 814, may be composed of a conductive material. In one embodiment, one or more of the plurality of contacts or the plurality of vias is made of a metal species. The metal species may be a pure metal such as tungsten, nickel, cobalt, or may be an alloy such as an intermetallic alloy or a metal semiconductor alloy (eg, a silicide material). It should be understood that the hard mask layer may be disposed on the local interconnect 854 at a location where the gate contact 814 is not disposed thereon. Further, the local interconnect 854 can be manufactured by lithographic patterning, or in other embodiments, can be manufactured as a self-aligned interconnect structure along the higher-level structure of the self-aligned gate edge isolation structure 820.

  In one embodiment (not shown), providing structure 800 includes forming a contact pattern that is substantially perfectly aligned with an existing gate pattern, but with very tight alignment margins. Delete the use of the process. In one such embodiment, this approach allows for the use of an inherently highly selective wet etch (eg, over conventional dry or plasma etches) to provide multiple contact openings. Is generated. In one embodiment, the contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, this approach allows for the elimination of the need for another critical lithographic operation to generate the contact pattern, as used in conventional approaches. In one embodiment, the trench contact grid is not patterned separately, but rather is formed between a plurality of poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before the gate grid cut.

Further, the plurality of gate structures 808 can be manufactured by a replacement gate process. In such an approach, a dummy gate material such as polysilicon or silicon nitride pillar material can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate insulator layer is also formed in this process, unlike surviving from initial processing. In one embodiment, the plurality of dummy gates are removed by a dry etch process or a wet etch process. In one embodiment, the dummy gate is composed of polycrystalline silicon or amorphous silicon and is removed using a dry etching process including the use of SF ₆ . In another embodiment, the plurality of dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed using a wet etch process that includes the use of hydrous NH ₄ OH or tetramethylammonium hydroxide. In one embodiment, the plurality of dummy gates are composed of silicon nitride and are removed using a wet etch containing hydrous phosphoric acid.

  In one embodiment, one or more approaches described herein are substantially intended for a dummy / replacement gate process in combination with a dummy / replacement contact process to arrive at structure 800. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature annealing of at least a portion of the permanent gate stack. For example, in one such specific embodiment, annealing of at least some of the permanent plurality of gate structures is performed at a temperature greater than about 600 ° C., for example, after the gate insulator layer is formed. Annealing is performed before the formation of permanent contacts.

  Referring again to FIG. 8A, in one embodiment, the semiconductor device has a plurality of contact structures that contact portions of the gate electrode formed over the active region. In general, one or more of the present invention before forming (eg, in addition to) forming a gate contact structure (such as a via) over the active portion of the gate and in the same layer as the trench contact via This embodiment initially involves using a gate aligned trench contact process. Such a process can be implemented to form a plurality of trench contact structures for the manufacture of semiconductor structures, eg, integrated circuits. In one embodiment, the trench contact pattern is formed to match an existing gate pattern. On the other hand, conventional approaches typically involve an additional lithographic process with strict alignment of the lithographic contact pattern to the existing gate pattern in combination with selective contact etching. For example, conventional processes can include patterning of poly (gate) grids along with patterning of separate contact structures.

  FIG. 9 illustrates a computing device 900 according to one implementation of the invention. Computing device 900 houses board 902. The board 902 can include a plurality of components including, but not limited to, a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some embodiments, at least one communication chip 906 is also physically and electrically coupled to the board 902. In further embodiments, communication chip 906 is part of processor 904.

  Depending on its multiple applications, computing device 900 may include multiple other components that may or may not be physically and electrically coupled to board 902. These other components include, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, graphic processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch Screen display, touch screen controller, battery, audio codec, video codec, output amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (hard disk drive, compact Disc (CD), digital versatile disc (DVD), etc.).

  The communication chip 906 enables wireless communication for transferring data to and from the computing device 900. The term “wireless” and its derivatives refer to multiple circuits, devices, systems, methods, technologies, communication channels that can communicate data by using modulated electromagnetic radiation over a non-solid medium. And so on. This term does not imply that the associated devices do not include any wires, but in some embodiments it may not. The communication chip 906 includes, but is not limited to, Wi-Fi (IEEE802.11 family), WiMAX (IEEE802.16 family), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, Multiple, including GSM (R), GPRS, CDMA, TDMA, DECT, Bluetooth (R), their derivatives, and 3G, 4G, 5G and any other wireless protocols specified below Either a wireless standard or a wireless protocol may be implemented. The computing device 900 may include a plurality of communication chips 906. For example, the first communication chip 906 may be dedicated to a plurality of short-range wireless communication such as Wi-Fi (registered trademark) and Bluetooth (registered trademark), and the second communication chip 906 may include GPS, EDGE. , GPRS, CDMA, WiMAX (registered trademark), LTE, Ev-DO and others may be dedicated to multiple long-range wireless communications.

  The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some embodiments of the present invention, a processor integrated circuit die includes one or more devices, such as a plurality of MOS-FET transistors, constructed in accordance with embodiments of the present invention. The term “processor” refers to any device or device that processes electronic data from multiple registers and / or memories and converts the electronic data into other electronic data that can be stored in the multiple registers and / or memories. Can refer to a portion of the device.

  Communication chip 906 also includes an integrated circuit die packaged within communication chip 906. According to another embodiment of the present invention, an integrated circuit die of a communication chip includes one or more devices, such as a plurality of MOS-FET transistors, constructed according to embodiments of the present invention.

  In further embodiments, another component housed within computing device 900 is an integrated circuit that includes one or more devices, such as a plurality of MOS-FET transistors, constructed in accordance with embodiments of the present invention. A die may be included.

  In various embodiments, the computing device 900 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner. , Monitors, set-top boxes, entertainment control units, digital cameras, portable music players, or digital video recorders. In further embodiments, computing device 900 may be any other electronic device that processes data.

  Accordingly, embodiments of the present invention include self-aligned gate edge and local interconnect structures and methods for fabricating self-aligned gate edge and local interconnect structures.

  In one embodiment, the semiconductor structure includes a semiconductor fin disposed over the substrate and having a length in a first direction. The gate structure is disposed on the semiconductor fin and has a first end facing the second end in a second direction orthogonal to the first direction. The pair of gate edge isolation structures is centered on the semiconductor fin. The first gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and the second gate edge isolation structure of the pair of gate edge isolation structures is: Located directly adjacent to the second end of the gate structure.

  In one embodiment, the semiconductor structure further includes source and drain regions disposed in the semiconductor fins on both sides of the gate structure. The first trench contact is disposed on the source region, and the second trench contact is disposed on the drain region. Each of the first trench contact and the second trench contact has a first end facing the second end in a second direction. The first gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the first trench contact and the first end of the second trench contact. The second gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the first trench contact and the second end of the second trench contact.

  In one embodiment, the semiconductor structure further includes a second semiconductor fin disposed above the substrate and having a length in a first direction, the second semiconductor fin being spaced apart from the first semiconductor fin. ing. The second gate structure is disposed on the second semiconductor fin, and the second gate structure has a first end facing the second end in a second direction. The second gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the second gate structure. The third gate edge isolation structure is disposed directly adjacent to the second end of the second gate structure. Of the pair of the third gate edge isolation structure and the gate edge isolation structure, the second gate edge isolation structure has the second semiconductor fin at the center.

  In one embodiment, the semiconductor structure further includes a local interconnect disposed above and electrically connecting the first and second gate structures.

  In one embodiment, the local interconnect is self-aligned with a pair of gate edge isolation structures and a third gate edge isolation structure.

  In one embodiment, the gate structure is an N-type gate structure and the second gate structure is a P-type gate structure.

  In one embodiment, the gate structure includes a high dielectric constant gate insulator layer and a metal gate electrode.

  In one embodiment, the pair of gate edge isolation structures is comprised of a material such as, but not limited to, silicon oxide, silicon nitride, silicon carbide, or combinations thereof.

  In one embodiment, the semiconductor structure includes a semiconductor fin disposed over the substrate and having a length. Alternating source / drain regions and channel regions are disposed within the length of the semiconductor fin, each source / drain region having an associated trench contact disposed over the semiconductor fin, and each channel region Has an associated gate structure disposed over the semiconductor fin. The semiconductor structure also includes a plurality of gate edge isolation structures. Adjacent trench contacts and gate structures are separated by one gate edge isolation structure among a plurality of gate edge isolation structures. The gate local interconnect is disposed above one of the plurality of gate structures and between a pair of gate edge isolation structures.

  In one embodiment, the semiconductor structure further includes an insulator cap disposed on the gate local interconnect, the insulator cap being disposed between the plurality of pairs of gate edge isolation structures.

  In one embodiment, the semiconductor structure further includes a trench contact local interconnect disposed over one of the plurality of trench contacts and between the second pair of gate edge isolation structures.

  In one embodiment, the semiconductor structure further includes an insulator cap disposed on the trench contact local interconnect, the insulator cap being disposed between the second pair of gate edge isolation structures.

  In one embodiment, each gate structure includes a high dielectric constant gate insulator layer and a metal gate electrode.

  In one embodiment, each of the plurality of gate edge isolation structures is comprised of a material such as, but not limited to, silicon oxide, silicon nitride, silicon carbide, or combinations thereof.

  In one embodiment, the semiconductor structure includes a semiconductor fin disposed over the substrate and having a length. Alternating source / drain regions and channel regions are disposed within the length of the semiconductor fin, each source / drain region having an associated trench contact disposed over the semiconductor fin, and each channel region Has an associated gate structure disposed over the semiconductor fin. The semiconductor structure also includes a plurality of gate edge isolation structures. Adjacent trench contacts and gate structures are separated by one gate edge isolation structure among a plurality of gate edge isolation structures. The trench contact local interconnect is disposed over one of the plurality of trench contacts and between a pair of gate edge isolation structures.

  In one embodiment, the semiconductor structure further includes an insulator cap disposed on the trench contact local interconnect, the insulator cap being disposed between the plurality of pairs of gate edge isolation structures.

  In one embodiment, each gate structure includes a high dielectric constant gate insulator layer and a metal gate electrode.

  In one embodiment, each of the plurality of gate edge isolation structures is comprised of a material such as, but not limited to, silicon oxide, silicon nitride, silicon carbide, or combinations thereof.

  In one embodiment, a method of manufacturing a semiconductor structure includes forming first and second parallel semiconductor fins over a substrate. The method also includes forming a plurality of dummy spacers adjacent to the respective sidewalls of the first and second semiconductor fins. The plurality of dummy spacers of the first semiconductor fin are not integrated with the plurality of dummy spacers of the second semiconductor fin. The method also includes forming an isolation structure between the plurality of dummy spacers of the first and second semiconductor fins. The method also includes removing the plurality of dummy spacers. The method also includes forming a first replacement gate structure on the first semiconductor fin and a second replacement gate structure on the second semiconductor fin, the first and second gate structures comprising: , Directly adjacent to the separation structure and separated from each other by the separation structure.

  In one embodiment, the method also includes forming a first pair of trench contacts on the first semiconductor fin and a second pair of trench contacts on the second semiconductor fin. The first and second pairs of trench contacts are directly adjacent to and separated from each other by the isolation structure.

  In one embodiment, the method also includes the step of recessing the first and second semiconductor fins after forming the isolation structure and before removing the plurality of dummy spacers.

  In one embodiment, forming the plurality of dummy spacers includes forming and etching a polycrystalline silicon layer.

  In one embodiment, forming the isolation structure includes depositing and planarizing a material such as, but not limited to, silicon oxide, silicon nitride, silicon carbide, or combinations thereof.

  In one embodiment, forming one or both of the first and second replacement gate structures includes forming a high dielectric constant gate insulator layer and a metal gate electrode.

  In one embodiment, the method also includes forming a local interconnect that electrically connects the first and second replacement gate structures above the first and second replacement gate structures.

Claims (27)

A first fin having a longest dimension along a first direction;
A second fin having a longest dimension along the first direction;
A first gate structure on the first fin having a longest dimension along a second direction orthogonal to the first direction;
An edge having a longest dimension along the second direction, discontinuous with the first gate structure along the second direction, and facing an edge of the first gate structure along the second direction A second gate structure on the second fin,
Along the second direction, between the edge of the first gate structure and the edge of the second gate structure, and in contact with the edge of the first gate structure and the edge of the second gate structure A gate edge isolation structure having a length along the first direction that is longer than a length of the first gate structure and the second gate structure along the first direction;
An insulator material laterally adjacent to and in contact with the gate edge isolation structure and having a composition different from the composition of the gate edge isolation structure;
Bei to give a,
The first gate structure comprises a first gate insulator layer and a first gate electrode;
The second gate structure comprises a second gate insulator layer and a second gate electrode;
The integrated circuit structure , wherein the gate edge isolation structure is in contact with a gate insulator layer of the first gate structure and a gate insulator layer of the second gate structure. The integrated circuit structure according to claim 1 , wherein the gate edge isolation structure is in contact with a metal gate electrode layer of the first gate structure and a metal gate electrode layer of the second gate structure. The gate insulator layer of the first gate structure comprises a high dielectric constant insulator material;
The integrated circuit structure of claim 1 or 2, wherein the gate insulator layer of the second gate structure comprises a high dielectric constant insulator material. A first fin having a longest dimension along a first direction;
A second fin having a longest dimension along the first direction;
A first gate structure on the first fin having a longest dimension along a second direction orthogonal to the first direction;
An edge having a longest dimension along the second direction, discontinuous with the first gate structure along the second direction, and facing an edge of the first gate structure along the second direction A second gate structure on the second fin,
Along the second direction, between the edge of the first gate structure and the edge of the second gate structure, and in contact with the edge of the first gate structure and the edge of the second gate structure A gate edge isolation structure having a length along the first direction that is longer than a length of the first gate structure and the second gate structure along the first direction;
An insulator material laterally adjacent to and in contact with the gate edge isolation structure and having a composition different from the composition of the gate edge isolation structure;
With
The gate edge isolation structure, said has a height greater than the height of the height and the second gate structure of the first gate structure, Integrated Circuit structure. The apparatus further comprises a local interconnect over a portion of the first gate structure, over a portion of the gate edge isolation structure, and over a portion of the second gate structure. 5. The integrated circuit structure according to 4 . The integrated circuit structure of claim 5 , wherein the local interconnect electrically couples the first gate structure to the second gate structure. 7. The method of claim 6 , further comprising a gate contact that contacts a portion of the local interconnect on the first gate structure, but does not contact a portion of the local interconnect on the second gate structure. An integrated circuit structure as described. A first fin having a longest dimension along a first direction;
A second fin having a longest dimension along the first direction;
A first gate structure on the first fin having a longest dimension along a second direction orthogonal to the first direction;
An edge having a longest dimension along the second direction, discontinuous with the first gate structure along the second direction, and facing an edge of the first gate structure along the second direction A second gate structure on the second fin,
Along the second direction, between the edge of the first gate structure and the edge of the second gate structure, and in contact with the edge of the first gate structure and the edge of the second gate structure A gate edge isolation structure having a length along the first direction that is longer than a length of the first gate structure and the second gate structure along the first direction;
An insulator material laterally adjacent to and in contact with the gate edge isolation structure and having a composition different from the composition of the gate edge isolation structure;
With
The gate edge isolation structure comprises silicon and nitrogen, Integrated Circuit structure. Forming a first fin having a longest dimension along a first direction;
Forming a second fin having a longest dimension along the first direction;
Forming a first gate structure on the first fin having a longest dimension along a second direction orthogonal to the first direction;
An edge having a longest dimension along the second direction, discontinuous with the first gate structure along the second direction, and facing an edge of the first gate structure along the second direction Forming a second gate structure on the second fin with
Along the second direction, between the edge of the first gate structure and the edge of the second gate structure, and in contact with the edge of the first gate structure and the edge of the second gate structure Forming a gate edge isolation structure having a length along the first direction that is longer than a length of the first gate structure and the second gate structure along the first direction;
Forming an insulator material having a composition different from the composition of the gate edge isolation structure laterally adjacent to and in contact with the gate edge isolation structure;
Bei to give a,
The first gate structure comprises a first gate insulator layer and a first gate electrode;
The second gate structure comprises a second gate insulator layer and a second gate electrode;
A method of manufacturing an integrated circuit structure, wherein the gate edge isolation structure contacts a gate insulator layer of the first gate structure and a gate insulator layer of the second gate structure . The method of claim 9 , wherein the gate edge isolation structure is in contact with a metal gate electrode layer of the first gate structure and a metal gate electrode layer of the second gate structure. The gate insulator layer of the first gate structure comprises a high dielectric constant insulator material;
11. The method of claim 9 or 10 , wherein the gate insulator layer of the second gate structure comprises a high dielectric constant insulator material. Forming a first fin having a longest dimension along a first direction;
Forming a second fin having a longest dimension along the first direction;
Forming a first gate structure on the first fin having a longest dimension along a second direction orthogonal to the first direction;
An edge having a longest dimension along the second direction, discontinuous with the first gate structure along the second direction, and facing an edge of the first gate structure along the second direction Forming a second gate structure on the second fin with
Along the second direction, between the edge of the first gate structure and the edge of the second gate structure, and in contact with the edge of the first gate structure and the edge of the second gate structure Forming a gate edge isolation structure having a length along the first direction that is longer than a length of the first gate structure and the second gate structure along the first direction;
Forming an insulator material having a composition different from the composition of the gate edge isolation structure laterally adjacent to and in contact with the gate edge isolation structure;
With
The method of manufacturing an integrated circuit structure, wherein the gate edge isolation structure has a height higher than a height of the first gate structure and a height of the second gate structure. Forming a local interconnect over the portion of the first gate structure, over the portion of the gate edge isolation structure, and over the portion of the second gate structure; 13. The method of claim 12 , comprising. The method of claim 13 , wherein the local interconnect electrically couples the first gate structure to the second gate structure. Forming a gate contact overlying a portion of the local interconnect over the first gate structure but not over a portion of the local interconnect over the second gate structure; The method according to claim 14 . Forming a first fin having a longest dimension along a first direction;
Forming a second fin having a longest dimension along the first direction;
Forming a first gate structure on the first fin having a longest dimension along a second direction orthogonal to the first direction;
An edge having a longest dimension along the second direction, discontinuous with the first gate structure along the second direction, and facing an edge of the first gate structure along the second direction Forming a second gate structure on the second fin with
Along the second direction, between the edge of the first gate structure and the edge of the second gate structure, and in contact with the edge of the first gate structure and the edge of the second gate structure Forming a gate edge isolation structure having a length along the first direction that is longer than a length of the first gate structure and the second gate structure along the first direction;
Forming an insulator material having a composition different from that of the gate edge isolation structure laterally adjacent to and in contact with the gate edge isolation structure;
With
The gate edge isolation structure comprises silicon and nitrogen, methods better to manufacture the integrated circuit structure. A semiconductor fin disposed above the substrate and having a length in a first direction;
A gate structure disposed on the semiconductor fin, having a first end facing the second end in a second direction orthogonal to the first direction, and having a top surface;
A pair of gate edge isolation structures centered on the semiconductor fin, and
A first gate edge isolation structure of the pair of gate edge isolation structures is disposed immediately adjacent to the first end of the gate structure;
A second gate edge isolation structure of the pair of gate edge isolation structures is disposed immediately adjacent to the second end of the gate structure;
The semiconductor structure, wherein the pair of gate edge isolation structures has a top surface that is above the top surface of the gate structure. A semiconductor fin disposed above the substrate and having a length in a first direction;
A gate structure disposed on the semiconductor fin, having a first end facing the second end in a second direction orthogonal to the first direction, and having a top surface;
A pair of gate edge isolation structures centered on the semiconductor fin;
A source region and a drain region disposed in the semiconductor fin on both sides of the gate structure;
A first trench contact disposed over the source region and a second trench contact disposed over the drain region;
Bei to give a,
A first gate edge isolation structure of the pair of gate edge isolation structures is disposed immediately adjacent to the first end of the gate structure;
A second gate edge isolation structure of the pair of gate edge isolation structures is disposed immediately adjacent to the second end of the gate structure;
The pair of gate edge isolation structures has a top surface that is coplanar with or above the top surface of the gate structure;
Each of the first trench contact and the second trench contact has a first end facing the second end in the second direction;
The first gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the first trench contact and the first end of the second trench contact;
The second gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the first trench contact and the second end of the second trench contact. , semi-conductor structure. A semiconductor fin disposed above the substrate and having a length in a first direction;
A gate structure disposed on the semiconductor fin, having a first end facing the second end in a second direction orthogonal to the first direction, and having a top surface;
A pair of gate edge isolation structures centered on the semiconductor fin;
A second semiconductor fin disposed above the substrate and having a length in the first direction and spaced from the semiconductor fin;
A second gate structure having a first end disposed on the second semiconductor fin and facing the second end in the second direction;
A third gate edge isolation structure disposed directly adjacent to the second end of the second gate structure;
A local interconnect disposed above the gate structure and the second gate structure and electrically coupling the gate structure and the second gate structure;
With
A first gate edge isolation structure of the pair of gate edge isolation structures is disposed immediately adjacent to the first end of the gate structure;
A second gate edge isolation structure of the pair of gate edge isolation structures is disposed immediately adjacent to the second end of the gate structure;
The pair of gate edge isolation structures has a top surface that is coplanar with or above the top surface of the gate structure;
The second gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the second gate structure;
The second gate edge isolation structure of the third gate edge isolation structure and the pair of gate edge isolation structures is centered on the second semiconductor fin,
It said local interconnect, wherein the pair of gate edge isolation structure and said third gate edge isolation structure and self-aligned, semi-conductor structure. The semiconductor structure according to claim 19 , wherein the gate structure is an N-type gate structure, and the second gate structure is a P-type gate structure. 21. The semiconductor structure according to any one of claims 17 to 20, wherein the gate structure comprises a high dielectric constant gate insulator layer and a metal gate electrode. The semiconductor structure according to any one of claims 17 to 21, wherein the pair of gate edge isolation structures comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, and combinations thereof. A semiconductor fin disposed above the substrate and having a length in a first direction;
A gate structure disposed on the semiconductor fin, having a first end facing the second end in a second direction orthogonal to the first direction, and comprising a high dielectric constant gate insulator layer and a metal gate electrode; ,
A pair of gate edge isolation structure and
A source region and a drain region disposed in the semiconductor fin on both sides of the gate structure;
A first trench contact disposed over the source region and a second trench contact disposed over the drain region ;
The first gate edge isolation structure of the pair of gate edge isolation structures is the same as the second gate edge isolation structure of the pair of gate edge isolation structures being separated from the second side surface of the semiconductor fin. Spaced from the first side of the semiconductor fin;
The first gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and the second gate of the pair of gate edge isolation structures An edge isolation structure is disposed directly adjacent to the second end of the gate structure ;
Each of the first trench contact and the second trench contact has a first end facing the second end in the second direction;
The first gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the first trench contact and the first end of the second trench contact;
The second gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the first trench contact and the second end of the second trench contact. , Semiconductor structure. A semiconductor fin disposed above the substrate and having a length in a first direction;
A gate structure disposed on the semiconductor fin, having a first end facing the second end in a second direction orthogonal to the first direction, and comprising a high dielectric constant gate insulator layer and a metal gate electrode; ,
A pair of gate edge isolation structures;
A second semiconductor fin disposed above the substrate and having a length in the first direction and spaced from the semiconductor fin;
A second gate structure having a first end disposed on the second semiconductor fin and facing the second end in the second direction;
A third gate edge isolation structure disposed directly adjacent to the second end of the second gate structure;
A local interconnect disposed above the gate structure and the second gate structure and electrically coupling the gate structure and the second gate structure;
With
The first gate edge isolation structure of the pair of gate edge isolation structures is the same as the second gate edge isolation structure of the pair of gate edge isolation structures being separated from the second side surface of the semiconductor fin. Spaced from the first side of the semiconductor fin;
The first gate edge isolation structure of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and the second gate of the pair of gate edge isolation structures An edge isolation structure is disposed directly adjacent to the second end of the gate structure;
The second gate edge isolation structure of the pair of gate edge isolation structures is provided directly adjacent to the first end of the second gate structure;
The second gate edge isolation structure of the third gate edge isolation structure and the pair of gate edge isolation structures is centered on the second semiconductor fin,
It said local interconnect, wherein the pair of gate edge isolation structure and said third gate edge isolation structure and self-aligned, semi-conductor structure. 25. The semiconductor structure of claim 24 , wherein the gate structure is an N-type gate structure and the second gate structure is a P-type gate structure. 26. The semiconductor structure according to any one of claims 23 to 25, wherein the gate structure comprises a high dielectric constant gate insulator layer and a metal gate electrode. 27. The semiconductor structure according to any one of claims 23 to 26, wherein the pair of gate edge isolation structures comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, and combinations thereof.

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