JP6600172B2 - Power module semiconductor device, manufacturing method thereof, and inverter device - Google Patents

Description

  The present embodiment relates to a power module semiconductor device, a manufacturing method thereof, and an inverter device.

  Currently, many research institutions are conducting research and development of silicon carbide (SiC) devices. As a feature of the SiC power device, the on-resistance is lower than that of the conventional Si power device, and high-speed switching and high-temperature operation can be exemplified.

  In a conventional Si power device such as an insulated gate bipolar transistor (IGBT), the operable temperature range is up to about 150 ° C.

  However, the SiC power device can theoretically operate up to about 600 ° C.

  In the conventional Si power module, it is necessary to increase the device area in order to reduce the on-resistance of the Si power device, and there is a limit to downsizing the power module.

  In the SiC power module, since the on-resistance of the SiC device is low, even a device with a small area can conduct a large current, and the SiC power module can be downsized.

  The package of these SiC power devices adopts a case type, a semiconductor device formed by transfer molding as in Patent Document 1, or a socket integrally molded as in Patent Document 2, and a terminal is press-fitted. Some have disclosed transfer molds that form press-fit vertical terminals.

JP 2005-183463 A JP 2010-129795 A

  However, as described in Patent Document 1, a transfer-molded semiconductor device is generally not suitable for miniaturization because the terminal rows are generally arranged in the horizontal direction with respect to the outer peripheral surface of the package portion. There was a problem that there was.

  On the other hand, the power semiconductor module described in Patent Document 2 enables the size reduction of the transfer mold module by arranging the terminals in a direction perpendicular to the surface of the mold resin.

  However, in this power semiconductor module, the external terminals are press-fitted into the metal cylinder after resin molding so that the external terminals are arranged in a direction perpendicular to the surface of the mold resin. There is a concern that the external terminal may fall out of the metal tube due to being used or vibration during use.

  The present embodiment provides a power module semiconductor device that can be reduced in size and can improve breakage due to load stress and terminal loss, a method for manufacturing the power module semiconductor device, and an inverter device having the power module semiconductor device.

According to one aspect of the present embodiment, an insulating substrate, a first pattern of a copper plate layer disposed on the insulating substrate, a semiconductor device disposed on the first pattern, and the semiconductor device and the electrical A power system terminal connected electrically, a signal system terminal electrically connected to the semiconductor device and arranged extending in a direction perpendicular to a main surface of the insulating substrate, and the signal system terminal a first locking member for locking, the portion of the first engagement member so as to expose the said and a resin layer covering the semiconductor device and the insulating substrate, wherein the first locking The member has a feed hole and a feed hole for filling the inside thereof with a resin, and the power module semiconductor device is provided in which the feed hole is larger than the feed hole .

  According to another aspect of the present embodiment, the power module includes a plurality of power module semiconductor devices, and the resin layer has a rectangular shape in plan view having a longitudinal direction and a short direction, and each power module An inverter device is provided in which a semiconductor device is arranged close to the short direction.

According to another aspect of the present embodiment, the semiconductor device disposed on the first pattern of the copper plate layer disposed on the insulating substrate, and the power system terminal electrically connected to the semiconductor device And a signal system terminal electrically connected to the semiconductor device and extending in a direction perpendicular to the main surface of the insulating substrate, and a first latch for latching the signal system terminal A first step of holding both surfaces facing each other in the vertical direction of the insulating substrate with a first mold and a second mold, and the first mold and the second mold. in in the mold is filled with resin, so as to expose a portion of said first locking member, have a second step of forming a resin layer covering the semiconductor device and the insulating substrate said first locking member, it is filled with the resin therein And a dispensing holes and because the feed Nyuana, the method for manufacturing power module semiconductor device the feed Nyuana formed larger than the dispensing holes is provided.

  According to the present embodiment, it is possible to provide a power module semiconductor device that can be miniaturized and that can improve breakage due to load stress and terminal disconnection, a manufacturing method thereof, and an inverter device having this power module semiconductor device. .

The bird's-eye view of the power module semiconductor device of the straight wiring structure which concerns on embodiment. The plane block diagram of the power module semiconductor device of the straight wiring structure which concerns on embodiment. 1A is a side view in the direction of the arrow III in FIG. 1, FIG. 1B is another side view in the direction of the arrow III in FIG. 1, and FIG. The side view with respect to the illustration arrow IV direction of FIG. The circuit representation figure of the power module semiconductor device which concerns on embodiment. The detailed circuit representation figure of the power module semiconductor device which concerns on embodiment. The plane pattern block diagram of the power module semiconductor device which concerns on embodiment. FIG. 8 is a schematic sectional view taken along line VIII-VIII in FIG. 7. FIG. 8 is a schematic cross-sectional structure diagram taken along line IX-IX in FIG. 7. FIG. 8 is a schematic cross-sectional structure diagram taken along line XX in FIG. 7. FIG. 8 is a schematic sectional view taken along line XI-XI in FIG. 7. It is a four-view figure of 1 terminal holder applied to the power module semiconductor device which concerns on embodiment, (a) Top view which looked at 1 terminal holder from right above, (b) 1 terminal holder from the direction of arrow B shown in figure The side view which looked, (c) The side view which looked at the 1 terminal holder from the illustration arrow C direction, (d) The side view which looked at the 1 terminal holder from the illustration arrow D direction. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a five-side view of a two-terminal holder applied to a power module semiconductor device according to an embodiment; (a) a top view of the two-terminal holder viewed from directly above; (C) a side view of the two-terminal holder viewed from the direction of the arrow C, (d) a side view of the two-terminal holder viewed from the direction of the arrow D, and (e) a side view of the two-terminal holder illustrated by the arrow E. The side view seen from the direction. The plane block diagram which arranged the six power module semiconductor devices which concern on embodiment, and comprised the 3-phase alternating current inverter. The connection diagram between each terminal which has arrange | positioned six power module semiconductor devices which concern on embodiment, and comprised the 3-phase alternating current inverter. The plane block diagram which also includes the connection wiring (bus-bar) electrode (GNDL * POWL) between each power terminal which has arrange | positioned six power module semiconductor devices which concern on embodiment, and comprised the three-phase alternating current inverter. FIG. 17A is a schematic cross-sectional structure diagram taken along line XVIIa-XVIIa in FIG. 16, and FIG. 16B is a schematic cross-sectional structure diagram along line XVIIb-XVIIb in FIG. (A) Another schematic cross-sectional structure diagram along line XVIIa-XVIIa in FIG. 16, (b) Another schematic cross-sectional structure diagram along line XVIIb-XVIIb in FIG. (A) Still another schematic cross-sectional structure diagram along line XVIIa-XVIIa in FIG. 16, (b) Still another schematic cross-sectional structure diagram along line XVIIb-XVIIb in FIG. The figure which shows the example which has arrange | positioned the signal system terminal (SS * G * DS) non-linearly in the plane block diagram shown in FIG. The figure which shows the example which has arrange | positioned the control board and the power supply board | substrate to the upper part in the plane block diagram shown in FIG. FIG. 22 is a schematic cross-sectional structure diagram taken along line XXII-XXII in FIG. 21. The bird's-eye view which has arrange | positioned the control board and the power supply board | substrate on the three-phase alternating current inverter comprised by arranging six power module semiconductor devices which concern on embodiment. The circuit block diagram of the full bridge inverter comprised by arrange | positioning four power module semiconductor devices which concern on embodiment. The plane block diagram which also includes the connection electrode (GNDL * POWL) between each power terminal which has arrange | positioned four power module semiconductor devices which concern on embodiment, and comprised the full bridge inverter. It is an example of the semiconductor device applied to the power module semiconductor device which concerns on embodiment, Comprising: The typical cross-section figure of SiC MOSFET. FIG. 4 is a schematic cross-sectional structure diagram of a SiC MOSFET that is an example of a semiconductor device applied to the power module semiconductor device according to the embodiment and includes a source pad electrode SP and a gate pad electrode GP. The circuit structural example which connected the snubber capacitor between the power terminal PL and the ground terminal NL in the schematic circuit structure of the three-phase alternating current inverter comprised using the power module semiconductor device which concerns on embodiment. The circuit block diagram of the three-phase alternating current inverter comprised using the power module semiconductor device which concerns on embodiment. (A) The plane block diagram of the carbon jig used for manufacture of the power module semiconductor device which concerns on embodiment, (b) The plane block diagram which shows a mode that the power module semiconductor device was mounted in the carbon jig. FIG. 31 is a schematic cross-sectional structure diagram along XXXI-XXXI in FIG. 30B, in which a carbon jig on which a power module semiconductor device is mounted is mounted on a hot plate and cut in the longitudinal direction of the carbon jig. In the manufacturing method of the power module semiconductor device which concerns on embodiment, the typical cross-section figure explaining a transfer mold molding process. In the manufacturing method of the power module semiconductor device which concerns on embodiment, the typical cross-section figure explaining the process following FIG. 32 of transfer mold shaping | molding. FIG. 34 is a schematic cross-sectional structure diagram illustrating a process following transfer FIG. 33 in transfer mold molding in the method for manufacturing the power module semiconductor device according to the embodiment. The typical cross-section figure of the power module semiconductor device which concerns on other form of implementation. The plane block diagram which also includes the connection wiring (bus-bar) electrode (GNDL * POWL) between each power terminal which has arrange | positioned six power module semiconductor devices which concern on other embodiment, and comprised the three-phase alternating current inverter. The plane block diagram which also includes the connection electrode (GNDL * POWL) between each power terminal which has arrange | positioned four power module semiconductor devices which concern on other embodiment, and comprised the full bridge inverter.

  Next, embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the cross-sectional view is schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and in this embodiment, the material, shape, structure, arrangement, etc. of the component parts are described below. It is not something specific. This embodiment can be modified in various ways within the scope of the claims.

[Configuration of power module semiconductor device]
A power module semiconductor device 2 having a straight wiring structure according to the present embodiment, and a bird's-eye view configuration of a 1 in 1 module is represented as shown in FIG. In the power module semiconductor device 2 having a straight wiring structure according to the present embodiment, the signal system terminals SS · G · DS are arranged so as to protrude from the resin layer 12 in the vertical direction as shown in FIG. .

  Although 1 in 1 can be regarded as one large transistor, there may be a plurality of built-in transistor devices. There are 2 in 1, 4 in 1, 6 in 1, etc., but this is a module with 2 in 1 and 2 in 1 connected to 2 vertical transistors in FIG. 28 (inverter circuit). Modules with built-in wiring are called 4 in 1, and those with all wiring are called 6 in 1.

  The signal system terminal DS is held in a state of being locked by a one-terminal holder 101 as a first locking member embedded in the main surface portion of the resin layer 12 at the same height as the mold surface. G · SS is held in a state of being locked by a two-terminal holder 102 as a first locking member embedded in the main surface portion of the resin layer 12 at the same height as the mold surface.

  Further, the planar configuration of the power module semiconductor device 2 having a straight wiring structure according to the present embodiment is expressed as shown in FIG. 1 is represented as shown in FIG. 3 (a), and the side structure of another power module semiconductor device 2B in the direction of arrow III in FIG. 1 is shown in FIG. 3 (b). A side surface structure of yet another power module semiconductor device 2C in the direction of arrow III in FIG. 1 is represented as shown in FIG. Further, the side structure in the direction of arrow IV in FIG. 1 is expressed as shown in FIG.

  In the power module semiconductor device 2 according to the present embodiment, a circuit representation of the one-in-one module is expressed as shown in FIG. Further, in the power module semiconductor device 2 according to the present embodiment, a detailed circuit representation of the one-in-one module is expressed as shown in FIG.

  The power module semiconductor device 2 according to the present embodiment has a one-in-one module configuration. That is, one MOSFET (semiconductor device) Q is built in one module. As an example, five chips (MOS transistors × 5) can be mounted as shown in FIG. 7, and up to five MOSFETs Q are connected in parallel. A part of the five chips can be mounted for the diode DI.

  FIG. 5 shows a diode DI connected in reverse parallel between the source and drain of the MOSFET Q. The main electrode of MOSFET Q is represented by a drain terminal DT and a source terminal ST as power system terminals. The diode DI is composed of a body Di or a body Di of an individual chip.

  In FIG. 6, SS is a source sense terminal, DS is a drain sense terminal, and G is a gate signal terminal, both of which constitute a signal system terminal.

  A planar pattern configuration of the power module semiconductor device 2 having a straight wiring structure according to the present embodiment is expressed as shown in FIG. A schematic cross-sectional structure along the line VIII-VIII in FIG. 7 is represented as shown in FIG. 8, and a schematic cross-sectional structure along the line IX-IX in FIG. 7 is represented as shown in FIG. A schematic cross-sectional structure taken along line XX of FIG. 7 is represented as shown in FIG. 10, and a schematic cross-sectional structure taken along line XI-XI of FIG. 7 is represented as shown in FIG.

  As shown in FIGS. 7 and 8, the power module semiconductor device 2 having a straight wiring structure according to the present embodiment includes an insulating substrate 10 and a first pattern 10a (a copper plate layer 10a disposed on the insulating substrate 10). D), a semiconductor device Q arranged on the first pattern 10a (D), a power system terminal ST · DT and a signal system terminal DS · G · SS electrically connected to the semiconductor device Q, and a signal system 1 terminal holder 101 that locks the terminal DS, 2 terminal holder 102 that locks the signal system terminals G and SS, and the upper surface of the 1 terminal holder 101 and the 2 terminal holder 102 are exposed from the mold surface. And a resin layer 12 covering the device Q and the insulating substrate 10.

  Here, the signal system terminals DS, G, and SS are arranged extending in a direction perpendicular to the main surface of the insulating substrate 10, and the power system terminals ST and DT are arranged in parallel with the main surface of the resin layer 12. Along the longitudinal direction of the layer 12, the resin layers 12 are arranged extending in opposite directions from opposite side surfaces, and have a straight wiring structure.

  In power module semiconductor device 2 having a straight wiring structure according to the present embodiment, power system terminals ST and DT are arranged in parallel to the main surface from the side surface of resin layer 12 as shown in FIGS. ing.

  Further, the power system terminals ST and DT are arranged along the longitudinal direction of the resin layer 12 so as to extend in opposite directions from the opposite side surfaces of the resin layer 12.

  The power system terminals ST · DT are arranged with predetermined steps VD1, VD2, and VD3 in the thickness direction of the resin layer 12, as shown in FIGS. 3 (a) to 3 (c).

  Further, the direction perpendicular to the main surface of the insulating substrate 10 is equal to the direction perpendicular to the main surface of the resin layer 12.

  On the other hand, the signal system terminals DS, G, and SS may be arranged linearly on the main surface of the resin layer 12 as shown in FIGS.

  The signal system terminal may include a gate signal terminal G and a sensor terminal. Further, the sensor terminal may include a source sense terminal SS and a drain sense terminal DS.

  Here, in addition to the source sense terminal SS and the drain sense terminal DS, the illustration is omitted, but the thermistor connection terminal for temperature sensing is perpendicular to the main surface of the insulating substrate 10 like the signal system terminal. You may arrange in.

  The power module semiconductor device 2 having a straight wiring structure according to the present embodiment includes an electrode pattern GSP / SSP arranged adjacent to the semiconductor device Q on the insulating substrate 10, as shown in FIG. The signal system terminals G · SS are connected to the electrode patterns GSP · SSP by soldering. The signal system terminal DS is connected to the first pattern 10a (D) by soldering.

  As shown in FIGS. 7 and 9, the drain sense terminal DS is connected to the first pattern 10 a (D) by soldering via the solder layer 3 c and is perpendicular to the main surface of the insulating substrate 10. It is arranged extending in the direction.

  Further, the drain sense terminal DS is locked by the one-terminal holder 101, so that the solder layer 3c at the connection portion with the first pattern 10a (D) is protected. That is, the drain sense terminal DS is already soldered to the first pattern 10a (D) via the solder layer 3c before the molding process for forming the resin layer 12, and the state protruding in the vertical direction is 1 It is held by the terminal holder 101. Therefore, when the drain sense terminal DS is press-fitted into a metal tube such as a socket after resin molding, a load stress at the time of press-fitting is applied to the connection portion by the drain sense terminal DS or the solder layer 3c, or the drain sense terminal DS is caused by vibration during use. It is possible to prevent so-called terminal disconnection in which the sense terminal DS falls off from the metal tube.

  As shown in FIGS. 7 and 10, the gate signal terminal G is connected to the gate signal electrode pattern GSP by soldering via the solder layer 3c, and the gate signal electrode pattern GSP and the source sense electrode pattern SSP are connected. Between the first and second electrodes, bent upward and extending perpendicularly to the main surface of the insulating substrate 10. Further, the gate signal terminal G is locked by the two-terminal holder 102, so that the solder layer 3c at the connection portion with the gate signal electrode pattern GSP is protected.

  As shown in FIGS. 7 and 11, the source sense terminal SS is connected to the source sense electrode pattern SSP by soldering via the solder layer 3c, and the gate signal electrode pattern GSP and the source sense electrode pattern SSP are connected. Between the first and second electrodes, bent upward and extending perpendicularly to the main surface of the insulating substrate 10. Further, the source sense terminal SS is locked by the two-terminal holder 102, so that the solder layer 3c at the connection portion with the source sense electrode pattern SSP is protected.

  That is, the gate signal terminal G and the source sense terminal SS are already solder-connected to the gate signal electrode pattern GSP and the source sense electrode pattern SSP through the solder layer 3c before the molding process for forming the resin layer 12. The state protruding in the vertical direction is held by the two-terminal holder 102. Therefore, by applying the gate signal terminal G and the source sense terminal SS to a metal tube such as a socket after resin molding, load stress at the time of press fitting is applied to the connection portion by the gate signal terminal G, the source sense terminal SS and the solder layer 3c. So that the gate signal terminal G and the source sense terminal SS fall out of the metal tube due to vibration during use or the like.

  Note that the gate signal terminal G and the source sense terminal SS may be individually locked by the one-terminal holder 101, similarly to the drain sense terminal DS.

On the other hand, the insulating substrate 10 may be formed of a ceramic substrate. Here, the ceramic substrate can be formed of, for example, Al ₂ O ₃ , AlN, SiN, AlSiC, or at least a surface of insulating SiC.

  Furthermore, the power module semiconductor device 2 according to the present embodiment is arranged on the second pattern 10a (S) of the first copper plate layer 10a and the semiconductor device Q as shown in FIGS. The columnar electrode 20, the upper surface plate electrode 22 disposed on the columnar electrode 20, the drain terminal DT disposed on the first pattern 10a (D), the second pattern 10a (S), and the upper A columnar connection electrode 18n connected to the face plate electrode 22 and a source terminal ST connected to the columnar connection electrode 18n are provided.

  The power system terminals ST and DT are connected to the source terminal ST connected to the source pad electrode SP (see FIG. 27) of the semiconductor device Q and to the drain electrode pattern D (see FIGS. 26 and 27) of the semiconductor device Q. And a drain terminal DT. The source terminal ST is connected to the source pad electrode SP of the semiconductor device Q, and the drain terminal DT is connected to the drain electrode pattern D of the semiconductor device Q.

  Further, as shown in FIG. 7, the gate signal terminal G and the source sense terminal SS of the semiconductor device Q are respectively connected to the gate signal electrode pattern GSP and the source sense electrode arranged adjacent to the semiconductor device Q through bonding wires. Bonded with the pattern SSP.

  Further, the first pattern 10a (D) and the semiconductor device Q are bonded via the solder layer 3b, and the second pattern 10a (S) and the columnar connection electrode 18n are also bonded via the solder layer 3b.

  Further, the columnar electrode 20 and the upper surface plate electrode 22 are joined via the solder layer 3a, and the columnar connection electrode 18n, the upper surface plate electrode 22 and the source terminal ST are also joined via the solder layer 3a.

  The power module semiconductor device 2 according to the present embodiment may include a diode DI arranged adjacent to the semiconductor device Q on the first pattern 10a (D) in a one-in-one module configuration. The cathode K of the diode DI is connected to the first pattern 10 a (D), and the anode A is connected to the upper surface plate electrode 22 via the columnar electrode 20.

  Here, the semiconductor device Q is formed of, for example, a SiC MOSFET, and the diode DI can be formed of, for example, a SiC Schottky Barrier Diode (SBD).

  The second copper plate layer 10b disposed on the back surface of the insulating substrate 10 functions as a heat spreader.

  The resin layer 12 may be transfer molded with an epoxy resin or a silicone resin.

  The plurality of chips of the semiconductor device Q are arranged on the surface of the insulating substrate 10 at positions separated from each other in a plan view when viewed from the thickness direction of the insulating substrate 10, and are resin-molded by the resin layer 12.

  Further, the columnar connection electrode 18n may be formed of an electrode material having a relatively small value of coefficient of thermal expansion (CTE), such as CuMo or Cu.

  The portion of the upper surface plate electrode 22 may be formed of an electrode material having a relatively small CTE value, for example, CuMo, Cu, or the like.

  The portion of the columnar electrode 20 may be formed of an electrode material having a relatively small CTE value, for example, CuMo, Cu, or the like.

  When materials of the same size having the same CTE value are compared, the generated stress is larger in a material having a larger Young's modulus value. For this reason, a member with a small value of generated stress can be achieved by selecting a material having a smaller value of Young's modulus × CTE.

  CuMo has such advantages. Moreover, although CuMo is inferior to Cu, its electrical resistivity is relatively low.

  In addition to solder bonding, techniques such as metal particle bonding, solid phase diffusion bonding, and liquid phase diffusion (TLP: Transient Liquid Phase) bonding can be applied to the formation of the bonding structure of each member.

  For example, the metal particle bonding is formed by baking a paste material containing conductive particles. The firing temperature of the paste material is, for example, about 200 to 400 ° C. The conductive particles are metal fine particles, such as silver particles, gold particles, nickel or copper particles. For example, when silver particles are applied as the metal fine particles, the concentration of the silver particles is, for example, about 80% by mass to about 95% by mass. The average particle size in the case of silver nanoparticles is about 10 nm to about 100 nm.

  In the internal structure of the vertical terminal of the power module semiconductor device 2 according to the present embodiment, since the metal terminal component is directly soldered to the electrode pattern or the like, a component such as a socket is not required.

  Here, the structure of the one-terminal holder 101 is shown in a four-view diagram shown in FIG. 12 (a diagram viewed from the top in FIG. 12A and a diagram viewed from each side in FIGS. 12B to 12D). It is expressed as follows. As shown in FIG. 12A, the one-terminal holder 101 has a rectangular upper surface portion in the short direction of the power module semiconductor device 2. On the upper surface of the one-terminal holder 101, a drain sense terminal DS is inserted, and an opening 101b that holds the inserted drain sense terminal DS in a locked state is provided.

  Inside the one-terminal holder 101, as shown in FIG. 12B, a resin filling portion 101a connected to the opening 101b is formed. Further, as shown in FIG. 12C, an inlet 101c as a resin inlet hole connected to the resin filling portion 101a is opened on one side surface of the one-terminal holder 101. On the other hand, as shown in FIG. 12D, a delivery port 101d as a resin delivery hole connected to the resin filling portion 101a is opened on the other side surface of the one-terminal holder 101 facing the delivery port 101c.

  In the present embodiment, in the one-terminal holder 101, the inlet 101c is opened larger than the outlet 101d so that the resin filling portion 101a is sufficiently filled with the mold resin. That is, the one-terminal holder 101 has a resin filling portion made of mold resin by arranging the inlet 101c toward the upstream side of the injection of the mold resin and the outlet 101d toward the downstream side of the injection. It is possible to more reliably fill the interior of 101a. Thereby, sufficient insulation and strength within the one-terminal holder 101 are ensured.

  As an example, when the cross-sectional dimension of the drain sense terminal DS is 1.5 mm × 0.5 mm, the dimensions of each part of the one-terminal holder 101 are expressed as follows (unit: mm). For example, in FIGS. 12A to 12D, d1 = 2.7, d2 = 3.35, d3 = 8.2 + α, d11 = 2.1, d12 = 2.75, d13 = 1.5. D14 = 0.3, d21 = 1.8, d22 = 0.7, d23 = 2.0, d31 = 3.5, d32 = 2.1, d33 = 2.0, d41 = 2.1, d42. = 2.0, d43 = 2.0.

  The curvatures of the Ra part to the Re part are Ra = 2-R0.35 and Rb = Rc = Rd = Re = 4-R0.5, where R is the radius of curvature.

  However, in the manufacturing process before the molding process, d3 is designed so that the one-terminal holder 101 is taller by α than the molding surface (vertical main surface) of the resin layer 12 (for example, α = about 10 μm to 200 μm).

  The structure of the two-terminal holder 102 is as shown in a five-side view shown in FIG. 13 (a diagram viewed from the top in FIG. 13A and a diagram viewed from each side in FIGS. 13B to 13E). expressed. As illustrated in FIG. 13A, the two-terminal holder 102 has a rectangular upper surface portion in the longitudinal direction of the power module semiconductor device 2. A gate signal terminal G is inserted into the upper surface portion of the two-terminal holder 102, an opening 102b for holding the inserted gate signal terminal G in a locked state, and a source sense terminal SS are inserted. And an opening 102c that holds the inserted source sense terminal SS in a locked state.

  Inside the two-terminal holder 102, as shown in FIGS. 13B and 13C, a resin filling portion 102a connected to the openings 102b and 102c is formed. Further, as shown in FIG. 13D, an inlet 102d as a resin inlet hole connected to the resin filling portion 102a is opened on one side surface of the two-terminal holder 102. On the other hand, on the other side surface of the two-terminal holder 102 facing the inlet port 102d, as shown in FIG. 13 (e), an outlet port 102e serving as a resin outlet hole connected to the resin filling portion 102a is opened.

  In the present embodiment, in the two-terminal holder 102, the inlet 102d is opened larger than the outlet 102e so that the resin filling portion 102a is sufficiently filled with the mold resin. That is, the two-terminal holder 102 has a resin filling portion made of mold resin by disposing the inlet 102d toward the upstream side of injection of the mold resin and the outlet 102e toward the downstream side of injection. It is possible to more reliably fill the inside of 102a. Thereby, sufficient insulation and strength in the two-terminal holder 102 are ensured.

  As an example, when the cross-sectional dimensions of the gate signal terminal G and the source sense terminal SS are 1.5 mm × 0.5 mm, the dimensions of each part of the two-terminal holder 102 are expressed as follows (unit: mm ). For example, in FIGS. 13A to 13E, e1 = 8.4, e2 = 4.0, e3 = 8.6 + α, e11 = 7.8, e13 = 6.7, e21 = 1.8. E22 = 0.7, e23 = 0.08, e31 = 3.5, e32 = 5.0, e33 = 2.0, e41 = 3.0, e42 = 2.0, e43 = 2.0, e51 = 0.4, e52 = 0.5, e53 = 1.0.

  The curvatures of the Pa part to the Pe part are Pa = 4-R0.35 and Pb = Pc = Pd = Pe = 4-R0.5, where R is the radius of curvature.

  However, e3 is designed so that the two-terminal holder 102 is taller than the mold surface of the resin layer 12 by α in the manufacturing process before the molding process (for example, α = about 10 μm to 200 μm). .

  The one-terminal holder 101 and the two-terminal holder 102 are plastic parts having predetermined heat resistance, such as high heat resistance such as PPS (polyphenylene sulfide) resin or PEEK (polyether ether ketone) resin, LCP (liquid crystal polymer) ( It is formed of a plastic (or engineering plastic or super engineering plastic) having 150 ° C. or higher, preferably 200 ° C. or higher.

[Configuration of three-phase AC inverter]
A schematic plan configuration in which six power module semiconductor devices 2 having a straight wiring structure according to the present embodiment are arranged to constitute a three-phase AC inverter device 4 is expressed as shown in FIG.

  In the power module semiconductor device 2 having the straight wiring structure according to the present embodiment, since the signal system terminals SS, G, and DS are not arranged on the outer periphery of the resin layer 12, they are arranged in parallel as shown in FIG. Also can reduce the distance between power modules.

  Moreover, the connection relationship between each terminal which comprised the power module semiconductor device 2 of the straight wiring structure which concerns on this Embodiment, and comprised the three-phase alternating current inverter apparatus 4 is represented as shown in FIG.

  Also included are connection wiring (bus bar) electrodes (GNDL · POWL) between the power terminals, in which six power module semiconductor devices 2 having a straight wiring structure according to the present embodiment are arranged to constitute a three-phase AC inverter device 4. The planar configuration is expressed as shown in FIG.

  The transistors Q1 and Q4, Q2 and Q5, and Q3 and Q6 each constitute a half-bridge inverter.

  As shown in FIGS. 15 and 16, the drain terminals DT1, DT2, and DT3 of the transistors Q1, Q2, and Q3 are commonly connected by a power supply bus bar electrode POWL, and the source terminals ST4 and ST5 of the transistors Q4, Q5, and Q6 are connected. ST6 is commonly connected by a grounding bus bar electrode GNDL.

  As shown in FIGS. 15 and 16, the source terminals ST1, ST2, and ST3 of the transistors Q1, Q2, and Q3 are connected to the drain terminals DT4, DT5, and DT6 of the transistors Q4, Q5, and Q6, respectively. Commonly connected by VL and WL. As a result, three-phase outputs of U, V, and W are obtained from the bus bar electrodes UL, VL, and WL.

  Also, a schematic cross-sectional structure along the line XVIIa-XVIIa in FIG. 16 is expressed as shown in FIG. 17A, and a schematic cross-sectional structure along the line XVIIb-XVIIb in FIG. 16 is shown in FIG. Represented as shown.

  Further, another schematic cross-sectional structure taken along line XVIIa-XVIIa in FIG. 16 is represented as shown in FIG. 18A, and another schematic cross-sectional structure taken along line XVIIb-XVIIb in FIG. It is expressed as shown in (b).

  Further, another schematic cross-sectional structure along the line XVIIa-XVIIa in FIG. 16 is represented as shown in FIG. 19A, and yet another schematic cross-sectional structure along the line XVIIb-XVIIb in FIG. It is expressed as shown in FIG.

  Further, as shown in FIGS. 3A to 3C, the power system terminals ST / DT are arranged with predetermined steps VD1, VD2, and VD3 in the thickness direction of the resin layer 12, as shown in FIG. The example of 17 corresponds to the example having the predetermined step VD1 shown in FIG. 3A, and the example of FIG. 18 corresponds to the example having the predetermined step VD2 shown in FIG. The example of FIG. 19 corresponds to the example having the predetermined step VD3 shown in FIG.

  That is, in the example having the predetermined step VD1 shown in FIG. 3A, the bus bar electrodes UL, VL, and WL have a straight electrode structure as well as the bus bar electrodes POWL and GNDL as shown in FIG. Have.

  In the example having the predetermined step VD2 shown in FIG. 3B, the bus bar electrodes POWL and GNDL have a straight electrode structure, but as shown in FIG. 18A, the bus bar electrodes UL, VL, and WL are Since the value of the predetermined step VD2 is relatively small, the electrode structure is bent upward.

  In the example having the predetermined step VD3 shown in FIG. 3C, the bus bar electrodes POWL and GNDL have a straight electrode structure. However, as shown in FIG. 19A, the bus bar electrodes UL, VL, and WL are Since the value of the predetermined step VD3 is relatively large, the electrode structure is bent downward.

  In the three-phase AC inverter device 4 configured by arranging six power module semiconductor devices 2 having a straight wiring structure according to the present embodiment, an example in which the signal system terminals SS, G, and DS are arranged non-linearly is shown in FIG. As shown in FIG.

  That is, in the power module semiconductor device 2 according to the present embodiment, the signal system terminals DS, G, and SS may be non-linearly arranged on the main surface of the resin layer 12. Alternatively, the signal system terminals DS, G, and SS may be randomly arranged on the main surface of the resin layer 12.

  Inverter device 4 in which a plurality of power module semiconductor devices 2 according to the present embodiment are arranged in parallel has a plurality of power module semiconductor devices 2 arranged in parallel as shown in FIGS. The power system terminals ST and DT of the device 2 are connected to each other via bus bar electrodes GNDL and POWL.

  Further, in the inverter device 4 in which a plurality of power module semiconductor devices 2 according to the present embodiment are arranged in parallel, the drain terminal DT and the source terminal ST of the power module semiconductor device 2 are the source terminals of the adjacent power module semiconductor devices 2. The ST and the drain terminal DT are arranged so as to face each other.

  The inverter device 4 in which a plurality of power module semiconductor devices 2 according to the present embodiment are arranged in parallel includes a first transistor and a second transistor (Q1 and Q4) that form a half bridge in the plurality of power module semiconductor devices 2. ), (Q2, Q5), (Q3, Q6) are arranged adjacent to each other, and the source terminal / drain terminal of the first transistor and the drain terminal / source terminal of the second transistor are arranged adjacent to each other. Yes.

  That is, the source terminal / drain terminal (ST1, DT4) of the first transistor / second transistor (Q1, Q4), the drain terminal / source terminal (DT1, ST4) of the first transistor / second transistor (Q1, Q4), Source terminal / drain terminal (ST2, DT5) of the first transistor / second transistor (Q2, Q5), drain terminal / source terminal (DT2, ST5) of the first transistor / second transistor (Q2, Q5), first The source terminal / drain terminal (ST3 / DT6) of the transistor / second transistor (Q3 / Q6) and the drain terminal / source terminal (DT3 / ST6) of the first transistor / second transistor (Q3 / Q6) are adjacent to each other. Are arranged as follows.

  In the power module semiconductor device 2 according to the present embodiment, the power system terminals ST · DT of each set of the power module semiconductor devices 2 are connected to each other via the bus bar electrodes UL, VL, and WL, so that the three-phase The AC inverter device 4 can be configured compactly.

  Since the power module semiconductor device 2 according to the present embodiment has a stepped terminal structure in a straight wiring module structure, it is possible to realize a wiring with a low inductance Ls of the external wiring (bus bar wiring).

  In the power module semiconductor device 2 according to the present embodiment, in a one-in-one configuration, the drain terminal DT and the source terminal ST are arranged straight (straight) at both ends of the rectangular resin layer 12 in plan view, and the drain terminal DT. By providing a step in the height position between the source terminal ST and the source terminal ST, a three-phase AC inverter device (6 in 1) can be easily configured by arranging the modules side by side in parallel.

  In addition, by providing a step at the height position of the drain terminal DT and the source terminal ST, it is possible to easily secure the insulation distance between the bus bar electrodes POWL, GNDL, UL, VL, WL for wiring between the modules. Also, the wiring efficiency can be improved.

  In addition, in the three-phase AC inverter device 4 to which the power module semiconductor device 2 according to the present embodiment is applied, the wiring length can be reduced as compared with the configuration in which the wiring (bus bar electrode) is bent to ensure the insulation distance. In addition, the parasitic inductance Ls can be reduced by about 10% compared to the conventional case. By providing a step on the module terminal, it is not necessary to bend external wiring (the bus bar that connects modules), so the bus bar wiring length can be shortened. Here, Ls represents a series inductance component of the wiring length of the bus bar.

[Vertical stacked structure]
In the planar configuration including the connection wiring (bus bar) electrodes (GNDL · POWL) between the power terminals in which the six power module semiconductor devices 2 according to the present embodiment are arranged to constitute the three-phase AC inverter device 4, the control board An example in which the power supply board 6 and the power supply substrate 8 are arranged at the top is represented as shown in FIG. 21, and a schematic cross-sectional structure taken along line XXII-XXII in FIG. 21 is represented as shown in FIG.

  A three-phase AC inverter device 4 configured by arranging six power module semiconductor devices 2 according to the present embodiment is arranged on a plurality of power module semiconductor devices 2 arranged in parallel as shown in FIGS. And a control board 6 for controlling the power module semiconductor device 2 and a plurality of power module semiconductor devices 2 arranged in parallel to supply power to the power module semiconductor device 2 and the control board 6 8 and the length in the vertical direction in which the signal system terminals DS, G, and SS extend is a length connectable to the control board 6 and the power supply board 8.

  A bird's-eye view configuration diagram in which the control board 6 and the power supply board 8 are arranged on the three-phase AC inverter device 4 configured by arranging six power module semiconductor devices 2 according to the present embodiment is expressed as shown in FIG. The 23, the signal system terminals (DS1, G1, SS1), (DS2, G2, SS2), (DS3, G3, SS3), (DS4, G4, SS4), ( DS5, G5, SS5) and (DS6, G6, SS6) are connected in the vertical direction to the control board 6 and the power supply board 8, respectively, to constitute the three-phase AC inverter device 4. In FIG. 23, the detailed patterns of the control board 6 and the power supply board 8 are not shown for simplification. In FIG. 23, in order to clarify the details of the structure, the distance between the power module semiconductor device 2 and the control board 6 / power supply board 8 in the vertical direction is relatively long. The top is arranged close to the distance.

In the three-phase AC inverter device 4 configured by arranging six power module semiconductor devices 2 having a straight wiring structure according to the present embodiment, a control board 6, a power supply board 8, a snubber capacitor C (not shown), and the like are arranged vertically. It becomes easy to arrange in a stacked structure, and the system can be slimmed.
[Configuration of full bridge inverter]
The circuit configuration of the full bridge inverter device 5 configured by arranging four power module semiconductor devices 2 according to the present embodiment is expressed as shown in FIG.

  In addition, a plan configuration including connection wiring (bus bar) electrodes (GNDL · POWL) between the power terminals in which the four power module semiconductor devices 2 according to the present embodiment are arranged to constitute the full bridge inverter device 5 is shown in FIG. As shown in FIG.

  Also in the full bridge inverter device 5 configured by arranging four power module semiconductor devices 2 according to the present embodiment, a control board 6 (not shown), a power supply board 8 (not shown), and a snubber capacitor C (not shown). Etc. can be easily arranged in a vertically stacked structure, and the system can be slimmed.

[Configuration example of semiconductor device]
As an example of the semiconductor device 100 (Q) applied to the power module semiconductor device 2 according to the present embodiment, a schematic cross-sectional structure of an SiC MOSFET is an SiC semiconductor substrate composed of an n ⁻ high resistance layer as shown in FIG. 26, the p base region 28 formed on the surface side of the SiC semiconductor substrate 26, the source region 30 formed on the surface of the p base region 28, and the surface of the SiC semiconductor substrate 26 between the p base regions 28. Gate insulating film 32, gate electrode 38 disposed on gate insulating film 32, source electrode 34 connected to source region 30 and p base region 28, and back surface opposite to the surface of SiC semiconductor substrate 26. And an n ⁺ drain region 24 disposed on the n ⁺ drain region 24 and a drain pad electrode 36 connected to the n ⁺ drain region 24.

  In FIG. 26, the semiconductor device 100 is composed of a planar gate type n-channel vertical SiC MOSFET, but may be composed of a trench gate type n-channel vertical SiC MOSFET.

  Further, a GaN-based FET or the like can be applied to the semiconductor device 100 applied to the power module semiconductor device 2 according to the present embodiment instead of the SiC MOSFET.

  For the semiconductor device 100 applied to the power module semiconductor device 2 according to the present embodiment, any of SiC-based, GaN-based, or AlN-based power devices can be applied.

  Furthermore, for example, a MOS transistor having a band gap energy of 1.1 eV to 8 eV can be used for the semiconductor device 100 applied to the power module semiconductor device 2 according to the present embodiment.

  27 is an example of the semiconductor device 100 applied to the power module semiconductor device 2 according to the present embodiment, and a schematic cross-sectional structure of the SiC MOSFET including the source pad electrode SP and the gate pad electrode GP is represented as shown in FIG. Is done. The gate pad electrode GP is connected to the gate electrode 38 disposed on the gate insulating film 32, and the source pad electrode SP is connected to the source electrode 34 connected to the source region 30 and the p base region 28.

  Further, as shown in FIG. 27, the gate pad electrode GP and the source pad electrode SP are disposed on a passivation interlayer insulating film 44 covering the surface of the semiconductor device 100.

  In the SiC semiconductor substrate 26 below the gate pad electrode GP and the source pad electrode SP, although not shown in the configuration example of FIG. 27, a transistor structure with a fine structure is provided as in the central portion of FIG. May be formed.

  Further, as shown in FIG. 27, the source pad electrode SP may be extended and disposed on the passivation interlayer insulating film 44 also in the transistor structure in the central portion.

In the power module semiconductor device 2 according to the present embodiment, a circuit configuration in which the snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL is expressed as shown in FIG. When the power module semiconductor device 2 according to the present embodiment is connected to the storage battery E, a large surge voltage Ldi / dt is generated due to the high switching speed of the SiC device due to the inductance L of the connection line. For example, assuming that the current change di = 300 A and the time change dt = 100 nsec accompanying switching, di / dt = 3 × 10 ⁹ (A / s). Although the value of the surge voltage Ldi / dt varies depending on the value of the inductance L, the surge voltage Ldi / dt is superimposed on the storage battery E. The surge voltage Ldi / dt can be absorbed by the snubber capacitor C connected between the power supply terminal PL and the ground terminal NL.

[Application examples using power module semiconductor devices]
Next, with reference to FIG. 29, a three-phase AC inverter configured using power module semiconductor device 2 according to the present embodiment will be described.

  As shown in FIG. 29, the three-phase AC inverter includes a gate drive unit 50, a power module unit 52 connected to the gate drive unit 50, and a three-phase AC motor unit 54. The power module unit 52 is connected to U-phase, V-phase, and W-phase inverters corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 54. Here, in FIG. 29, the gate drive unit 50 is connected to the SiC MOSFETs Q1 and Q4. Although not shown, it is also connected to SiC MOSFETs Q2 and Q5 and SiC MOSFETs Q3 and Q6.

  The power module unit 52 includes inverter-structured SiC MOSFETs Q1 and Q4, Q2 and Q5 between a plus terminal (+) and a minus terminal (−) to which a converter 48 to which a storage battery (E) 46 is connected is connected. And Q3 and Q6 are connected. Furthermore, diodes D1 to D6 are connected in antiparallel between the sources and drains of the SiC MOSFETs Q1 to Q6, respectively.

  In the power module semiconductor device 2 according to the present embodiment, the structure of the single-phase inverter corresponding to the U-phase portion of FIG. 29 has been described. A three-phase power module part 52 can also be formed.

[Method for Manufacturing Power Module Semiconductor Device]
In the method for manufacturing the power module semiconductor device 2 according to the present embodiment, a schematic plan configuration of the carbon jig 400 used in the soldering process of the power system terminals ST / DT and the signal system terminals DS / G / SS is shown in FIG. It is expressed as shown in 30 (a).

  As shown in FIG. 30B, the carbon jig 400 includes a substrate insertion portion 402 at the center, and a concave drain terminal DT placement portion 401a and a source terminal ST placement portion 401b at both left and right ends.

  Further, a schematic cross section in which the power module semiconductor device 2 is mounted on the carbon jig 400, the carbon jig 400 on which the power module semiconductor device 2 is mounted is mounted on the hot plate 403, and is cut in the longitudinal direction of the carbon jig 400. The structure is represented as shown in FIG.

  Note that FIG. 31 corresponds to the schematic cross-sectional structure along XXXI-XXXI in FIG. 30B, and the soldering process of the power system terminals ST / DT and the signal system terminals DS / G / SS is performed. Is shown. However, the signal system terminals DS, G, and SS indicate the relative positions of the signal systems terminals DS, G, and SS by broken lines.

  By heating the hot plate 403, the signal system terminal DS can be soldered to the first pattern 10a (D) and the signal system terminal G · SS can be soldered to the electrode pattern GSP · SSP. In addition, the power system terminals ST · DT can be soldered to the columnar connection electrodes 18 n and the first pattern 10 a (D) of the power module semiconductor device 2. Here, when a high melting point solder is used, the hot plate 403 is heated to about 340 ° C. to 360 ° C., for example.

  As shown in FIG. 32, the 1-terminal holder 101 is engaged with the soldered signal system terminal DS, and the 2-terminal holder 102 is engaged with the soldered signal system terminal G / SS. After that, a sealing step is performed.

  In the method for manufacturing power module semiconductor device 2 according to the present embodiment, by using carbon jig 400 having the structure shown in FIGS. 30 to 31, power system terminals ST · DT and insulating substrate 10 are parallel to each other. Sex can be secured.

  Moreover, in the manufacturing method of the power module semiconductor device 2 according to the present embodiment, a schematic cross-sectional structure for explaining the transfer molding process is expressed as shown in FIGS.

  That is, in FIGS. 32 to 34, the structure in which the one-terminal holder 101 and the two-terminal holder 102 are attached to the signal system terminals DS, G, and SS through the manufacturing process is turned upside down. A state is shown in which the upper mold 220 and the lower mold 200 are removed after the resin layer 12 is formed by being sandwiched between the mold 200) and the lower mold (first mold) 200 and encapsulating the mold resin. . In FIGS. 32 to 34, 202 and 203 are main body placement portions / terminal placement portions, 204a and 204b are accommodation portions for signal system terminals DS, G, and SS, and 223 is a resin injection portion.

  In the method for manufacturing the power module semiconductor device 2 according to the present embodiment, the 1-terminal holder 101 and the 2-terminal holder 102 attached so as to be taller than the mold surface by the height da (α) When the upper and lower parts of the body are sandwiched between the upper mold 220 and the lower mold 200, they are pressed in the vertical direction by the lower mold 200. In this state, that is, in a state where the one-terminal holder 101 and the two-terminal holder 102 are securely in contact with the lower mold 200 and are in close contact with each other, the resin injection into the resin injection portion 223 is executed.

  In the method for manufacturing the power module semiconductor device 2 according to the present embodiment, the lower mold 200 is made to be connected to the one terminal holder 101 · by using the upper mold 220 and the lower mold 200 shown in FIGS. Since it is in close contact with the two-terminal holder 102, the stepped terminal structure of the power system terminals ST and DT is realized without causing resin leakage or the like.

  According to the power module semiconductor device 2 according to the present embodiment, the signal system terminals DS, G, and SS are supported by the one terminal holder 101 and the two terminal holder 102 in a state of protruding in the vertical direction. There is no need to add a process for bending and securing insulation of the system terminals DS, G, and SS, thereby reducing the number of processes and the risk of failure.

  In particular, a load stress applied when the signal system terminals DS, G, and SS are press-fitted into the socket is applied to the power module semiconductor device 2, and the signal system terminals DS, G, and SS are caused by vibration during long-term use. It is possible to prevent the device 2 from coming off.

[Other forms of implementation]
[Configuration of power module semiconductor device]
As shown in FIG. 35, in power module semiconductor device 2A according to another embodiment of the present invention, power system terminals ST and DT are further extended in the direction perpendicular to the main surface of insulating substrate 10. It is set as the composition.

  Further, in the power module semiconductor device 2A according to another embodiment of the present invention, the power system terminal DT arranged in the vertical direction is arranged in the power system arranged in the vertical direction by the one-terminal holder (second locking member) 103. The terminals ST are held by the one-terminal holder (second locking member) 104 so as to be locked. As the one-terminal holders 103 and 104, those having the same configuration as the one-terminal holder 101 can be used except for the dimensions.

  According to the configuration of the power module semiconductor device 2A according to the other embodiment of the present invention, not only the signal system terminals DS, G, and SS but also the power system terminals ST and DT can be prevented from being damaged due to load stress at the time of press-fitting. This prevents terminal disconnection due to vibration during use.

[Application examples using power module semiconductor devices]
FIG. 36 shows a planar configuration in which six power module semiconductor devices 2A according to another embodiment of the present invention are arranged in parallel to constitute a three-phase AC inverter device 4A. FIG. 37 shows a planar configuration in which four power module semiconductor devices 2A according to another embodiment of the present invention are arranged in parallel to form a full bridge inverter device 5A.

  According to the power module semiconductor device 2A according to the other embodiment of the present invention, as with the signal system terminals DS, G, and SS, the power system terminals ST and DT protrude in the vertical direction by the one terminal holders 103 and 104. Since it is supported, the size can be further reduced, and the three-phase AC inverter device 4A and the full-bridge inverter device 5A can be configured more compactly.

  That is, in the power module semiconductor device 2A according to the other embodiment of the present invention, the signal system terminals SS / G / DS and the power system terminals ST / DT are not arranged on the outer periphery of the resin layer 12, so that FIG. As shown in 37, the distance between the power modules can be further reduced even if they are arranged in parallel.

  In particular, since the terminals DS, G, SS, ST, and DT can be pulled out in the vertical direction, the wiring in the module can be shortened, which contributes to noise resistance and loss reduction. Applications are expected.

  As described above, it is possible to provide a power module semiconductor device that can be miniaturized and that can improve breakage due to load stress and terminal loss, a manufacturing method thereof, and an inverter device having the power module semiconductor device.

[Other embodiments]
Although several embodiments have been described above, the discussion and drawings that form part of the disclosure are illustrative and should not be understood as limiting the embodiments. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, each embodiment includes various forms not described here.

  The power module semiconductor device according to the present embodiment can be used for all power devices such as SiC power semiconductor modules, and particularly, in fields where miniaturization and weight reduction are required, in-vehicle / solar cells / industrial equipment / consumer equipment. It can be applied to a wide range of application fields such as inverters and converters.

2, 2A, 2B, 2C ... power module semiconductor devices 3a, 3b, 3c ... solder layers 4, 4A, 5, 5A ... inverter device 6 ... control board 8 ... power supply board 10 ... insulating board 10a, 10b ... copper plate layer 10a (D) ... 1st pattern 10a (S) ... 2nd pattern 12 ... Resin layer 18n ... Columnar connection electrode 20 ... Columnar electrode 22 ... Top plate electrode 24 ... n ⁺ drain region 26 ... SiC semiconductor substrate 28 ... p base region 30 ... Source region 32 ... Gate insulating film 34 ... Source electrode 36 ... Drain pad electrode 38 ... Gate electrode 44 ... Interlayer insulating film 46 ... Storage battery (E)
48 ... Converter 50 ... Gate drive unit 52 ... Power module unit 54 ... Three-phase AC motor unit 100, Q, Q1-Q6 ... Semiconductor device (SiC MOSFET, semiconductor chip)
101 ... 1 terminal holder (first locking member)
101a ... Resin filling part 101b ... Opening part 101c ... Inlet (inlet hole)
101d ... Outlet (outlet)
102 ... Two-terminal holder (first locking member)
102a... Resin filling portions 102b and 102c.
102e ... Sending port (sending hole)
103, 104 ... 1 terminal holder (second locking member)
200 ... Lower molds 204a and 204b ... Housing part 220 ... Upper mold 223 ... Resin injection part 400 ... Carbon jig D1-D6, DI ... Diode GP ... Gate pad electrode SP ... Source pad electrodes DT, DT1, DT2, DT3 , DT4, DT5, DT6 ... Drain terminal (power system terminal)
ST, ST1, ST2, ST3, ST4, ST5, ST6 ... Source terminal (power system terminal)
POWL, GNDL, UL, VL, WL: Busbar electrodes O, U, V, W ... Output terminals G, G1-G6 ... Gate signal terminals (signal system terminals)
SS, SS1 to SS6 ... Source sense terminal (signal system terminal)
DS, DS1 to DS6 ... Drain sense terminal (signal system terminal)
GSP: Gate signal electrode pattern SSP: Source sense electrode pattern

Claims (24)

An insulating substrate;
A first pattern of a copper plate layer disposed on the insulating substrate;
A semiconductor device disposed on the first pattern;
A power system terminal electrically connected to the semiconductor device;
A signal system terminal that is electrically connected to the semiconductor device and arranged to extend in a direction perpendicular to the main surface of the insulating substrate;
A first locking member for locking the signal system terminal;
A resin layer covering the semiconductor device and the insulating substrate so as to expose a part of the first locking member;
The power module semiconductor device, wherein the first locking member has a feed hole and a feed hole for filling a resin therein, and the feed hole is larger than the feed hole.   The power module semiconductor device according to claim 1, wherein the first locking member has predetermined heat resistance.   3. The power module semiconductor device according to claim 1, wherein the first locking member is made of PPS or PEEK plastic. 4. The resin layer has a rectangular shape in plan view having a longitudinal direction and a short direction,
The power system terminals are arranged in parallel with the main surface of the resin layer, extending in opposite directions from opposite side surfaces of the resin layer along the longitudinal direction of the resin layer, and have a straight wiring structure. The power module semiconductor device according to claim 1.   5. The power module semiconductor device according to claim 1, wherein the power system terminal is arranged with a predetermined step in a thickness direction of the resin layer.   The power module semiconductor device according to claim 1, wherein the signal system terminals are linearly arranged on a main surface of the resin layer.   The power module semiconductor device according to any one of claims 1 to 5, wherein the signal system terminals are arranged in a non-linear manner on a main surface of the resin layer.   The power module semiconductor device according to claim 1, wherein the semiconductor device is a MOSFET having a source electrode, a drain electrode, and a gate electrode. The signal system terminal includes a gate signal terminal and a sensor terminal connected to the gate electrode,
The sensor terminal has the same structure as the source sense terminal and the MOSFET connected to the source electrode, and includes a drain sense terminal connected to the source electrode of the sense MOSFET connected in common to the drain electrode and the gate electrode. The power module semiconductor device according to claim 8. The drain sense terminal is connected to the first pattern by soldering,
The power module semiconductor device according to claim 9 , wherein the gate signal terminal and the source sense terminal are connected to an electrode pattern disposed adjacent to the semiconductor device on the insulating substrate by soldering. .   The power system terminal includes a drain electrode terminal connected to a drain electrode pattern of the semiconductor device and a source electrode terminal connected to a source pad electrode of the semiconductor device. The power module semiconductor device according to claim 1.   The power module semiconductor device according to claim 1, wherein the insulating substrate is formed of a ceramic substrate. A second pattern of a copper plate layer disposed on the insulating substrate;
A columnar electrode disposed on the semiconductor device;
An upper surface plate electrode disposed on the columnar electrode;
A first power system terminal disposed on the first pattern;
A columnar connection electrode disposed on the second pattern and connected to the upper surface plate electrode;
The power module semiconductor device according to claim 1, further comprising: a second power system terminal connected to the columnar connection electrode. The semiconductor device is a MOSFET having a source electrode, a drain electrode and a gate electrode,
14. The power module semiconductor device according to claim 13, wherein the first power system terminal is connected to the source electrode, and the second power system terminal is connected to the drain electrode.   The power module semiconductor device according to claim 1, wherein the resin layer is transfer-molded with an epoxy resin or a silicone resin. The power module semiconductor device according to claim 12, wherein the ceramic substrate is Al ₂ O ₃ , AlN, SiN, AlSiC, or at least a surface of insulating SiC.   The power module semiconductor device according to any one of claims 1 to 16, wherein the semiconductor device is any one of a SiC-based power device, a GaN-based power device, and an AlN-based power device.   2. The power module semiconductor device according to claim 1, wherein the power system terminal is arranged to extend in a direction perpendicular to a main surface of the insulating substrate.   The power module semiconductor device according to claim 18, further comprising a second locking member that locks the power system terminal.   The power module semiconductor device according to claim 19, wherein the second locking member is covered with the resin layer such that a part of the second locking member is exposed.   A plurality of power module semiconductor devices according to claim 1, wherein the resin layer has a rectangular shape in plan view having a longitudinal direction and a short direction, and each power module semiconductor device is arranged in the short direction. An inverter device characterized by being arranged close to each other. A semiconductor device disposed on a first pattern of a copper plate layer disposed on an insulating substrate, a power system terminal electrically connected to the semiconductor device, and electrically connected to the semiconductor device; Including a signal system terminal arranged to extend in a direction perpendicular to the main surface of the insulating substrate, and a first locking member for locking the signal system terminal in the vertical direction of the insulating substrate. A first step of holding both opposing surface sides with a first mold and a second mold;
A resin layer covering the semiconductor device and the insulating substrate is formed by filling the first mold and the second mold with a resin and exposing a part of the first locking member. A second step of forming, and
The first locking member has a feed hole and a feed hole for filling the inside thereof with a resin, and the feed hole is formed larger than the feed hole. Device manufacturing method. The first locking member is provided such that a main surface in the vertical direction protrudes from a main surface in the vertical direction of the resin layer formed of the resin,
In the first step, when the insulating substrate is held by the first mold and the second mold, the first locking member is pressed in the vertical direction by the first mold. The method of manufacturing a power module semiconductor device according to claim 22. The power system terminal further includes a second locking member that is arranged extending in a direction perpendicular to the main surface of the insulating substrate and that locks the power system terminal,
The second locking member is provided such that the main surface in the vertical direction protrudes from the main surface in the vertical direction of the resin layer formed of the resin.
In the first step, when the insulating substrate is held by the first mold and the second mold, the second locking member is pressed in the vertical direction by the first mold. The method of manufacturing a power module semiconductor device according to claim 22.

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