JP6597837B2 - Light emitting device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a light emitting device and a method for manufacturing the light emitting device.

2. Description of the Related Art Conventionally, as a semiconductor light emitting device with high luminous efficiency, there is known a configuration in which a plurality of light emitting cells are arranged in an array of vertical and horizontal grids on a plane (see Patent Document 1). The semiconductor light emitting device is formed on the surface of the first semiconductor layer between at least one first electrode that partitions the semiconductor structure layer into a plurality of light emitting segments and a light emitting segment adjacent to the plurality of light emitting segments, At least one light reflecting groove having a light reflecting film formed on the side surface is provided.
Further, as a light emitting device, a configuration in which a first electrode is provided on the same substrate side as the first surface on which the rough surface of the second conductivity type nitride semiconductor layer is formed is disclosed (see Patent Document 2).

JP2015-156431A JP 2013-016875 A

  However, in the conventional semiconductor light emitting device, the arrangement in which the n-side electrode as the first electrode is electrically connected to the semiconductor structure layer is between the plurality of light emitting cells. Therefore, in the conventional semiconductor light emitting device, at least two light emitting cells emit light, and it is difficult to individually light them. In the semiconductor light emitting device, the semiconductor structure layer portion is continuous in the lateral direction, and the semiconductor structure layer is also present above the bottom surface of the light reflecting groove that partitions the light emitting segment, so that light propagates to the semiconductor structure layer. It will be in a state that the closeout is not good.

  Therefore, an embodiment of the present invention has an object to provide a light-emitting device that has good parting when the light-emitting cells are individually turned on, and a method for manufacturing the light-emitting device.

  A method for manufacturing a light emitting device according to an embodiment of the present invention includes a first A step of preparing a semiconductor stacked body having a first semiconductor layer and a second semiconductor layer provided on an upper surface of the first semiconductor layer, and the semiconductor Forming a plurality of light emitting cells arranged in a matrix by forming a plurality of groove portions reaching the first semiconductor layer from the upper surface side of the semiconductor stacked body in the stacked body; and the plurality of light emitting cells In each of the steps, a third A step of partially removing the first semiconductor layer from the second semiconductor layer by partially removing the second semiconductor layer from the upper surface side of the second semiconductor layer; Forming a first insulating layer having a first hole above the first semiconductor layer exposed from the second semiconductor layer in each of the light emitting cells; and continuously forming the plurality of light emitting cells and the plurality of grooves. Process A wiring electrode that is electrically connected to the first semiconductor layer and the first hole in each of the plurality of light emitting cells so as to cover the first insulating layer above a region excluding a predetermined region on the upper surface of the second semiconductor layer. A 5A step of forming a plurality of light emitting cells, a 6A step of forming a second hole in the first insulating layer above the predetermined region on the upper surface of the second semiconductor layer of each of the plurality of light emitting cells, In each light emitting cell, a seventh electrode forming a second electrode that is electrically connected to the second semiconductor layer through the second hole, and forming the first semiconductor layer in the groove from the lower surface side of the first semiconductor layer. And removing the first insulating layer by dry etching or polishing so as not to reach the first insulating layer, and after the eighth A step, from the lower surface side of the first semiconductor layer in the thickness direction of the first semiconductor layer Some A 9A step of removing the first insulating layer from the first semiconductor layer at a position of the groove and performing a rough surface processing on the surface of the first semiconductor layer removed by the 8A step; , Including.

  In addition, a method for manufacturing a light emitting device according to an embodiment of the present invention includes a first B step of preparing a semiconductor stacked body including a first semiconductor layer and a second semiconductor layer provided on an upper surface of the first semiconductor layer; Forming a plurality of grooves reaching the first semiconductor layer from the upper surface side of the semiconductor stacked body in the semiconductor stacked body, thereby forming a plurality of light emitting cells arranged in a matrix; the second B step; In each light emitting cell, a third B step of partially removing the first semiconductor layer from the second semiconductor layer by partially removing the second semiconductor layer from the upper surface side of the second semiconductor layer; A first insulating layer having a second hole is formed continuously above the plurality of light emitting cells and the plurality of grooves above a predetermined region of the upper surface of the second semiconductor layer in each of the plurality of light emitting cells. Process, A wiring electrode is formed which is electrically connected to the second semiconductor layer and the second hole in each of the light emitting cells so as to cover the first insulating layer above the region excluding the predetermined region on the upper surface of the second semiconductor layer. A 5B step, a 6B step of forming a first hole in the first insulating layer above the first semiconductor layer exposed from the second semiconductor layer of each of the plurality of light emitting cells, and the plurality of the plurality of light emitting cells. The first semiconductor layer is formed in the groove from the lower surface side of the first semiconductor layer in the seventh step of forming a first electrode that is electrically connected to the first semiconductor layer in the first hole in each light emitting cell. Further, after the step 8B of removing by dry etching or polishing so as not to reach the first insulating layer and the step of performing dry etching, the first semiconductor layer is formed from the lower surface side of the first semiconductor layer. A portion of the first insulating layer is removed by wet etching, the first insulating layer is exposed from the first semiconductor layer at the position of the groove, and the surface of the first semiconductor layer removed in the step 8B is roughened. It is good also as including the 9th B process which processes.

  Furthermore, the light emitting device according to the embodiment of the present invention includes a first semiconductor layer, a second semiconductor layer provided so that a part of the upper surface of the first semiconductor layer is exposed on the upper surface of the first semiconductor layer, and A plurality of light emitting cells arranged in a matrix, each of which has a semiconductor laminate comprising: a plurality of light emitting cells provided continuously from the plurality of light emitting cells and exposed from the second semiconductor layer in each of the plurality of light emitting cells A first insulating layer having a first hole provided above the first semiconductor layer and a second hole provided above the second semiconductor layer in each of the plurality of light emitting cells; A wiring electrode that is provided so as to cover the first insulating layer, is electrically connected to the first semiconductor layer in each of the plurality of light emitting cells, and is provided in each of the plurality of light emitting cells. In the second hole, the second A second electrode electrically connected to the semiconductor layer, the first insulating layer is exposed from the first semiconductor layer between the plurality of light emitting cells, and the lower surface of the first semiconductor layer has an uneven shape. It was set as the structure which has.

  In addition, the light emitting device according to the embodiment of the present invention is arranged in a matrix, each having a semiconductor stacked body including a first semiconductor layer and a second semiconductor layer provided on the upper surface of the first semiconductor layer. A plurality of light emitting cells, and a first hole provided continuously above the plurality of light emitting cells and provided above the first semiconductor layer exposed from the second semiconductor layer in each of the plurality of light emitting cells; A first insulating layer having a second hole provided above the second semiconductor layer in each of the plurality of light emitting cells; and provided in each of the plurality of light emitting cells, wherein the first hole has the first hole. A first electrode that is electrically connected to the semiconductor layer, has light reflectivity, is provided to cover the first insulating layer, and is electrically connected to the second semiconductor layer and the second hole in each of the plurality of light emitting cells. A wiring electrode; and The insulating layer between the plurality of light emitting cells, exposed from the first semiconductor layer, the lower surface of the first semiconductor layer may have a structure having an uneven shape.

  According to the light emitting device according to the embodiment of the present invention, it is possible to improve a parting time when a plurality of light emitting cells are individually lit. Moreover, according to the manufacturing method of the light-emitting device which concerns on embodiment of this invention, the light-emitting device with a sufficient parting-off can be manufactured.

It is a side view which shows typically an example of the light-emitting device which concerns on this embodiment. It is a top view which shows typically the part of the light emitting cell of the light-emitting device which concerns on this embodiment. It is the elements on larger scale which expand and show a part of Drawing 2A typically. It is a schematic diagram which shows the manufacturing method of the light-emitting device which concerns on this embodiment in a cross section, and is a schematic diagram which shows the state which mounted the light emitting cell group in which the bump was formed in the IC substrate electrode in which the resist was formed. It is a schematic diagram which shows the manufacturing method of the light-emitting device which concerns on this embodiment, and is a schematic diagram which shows the state which forms an underfill in the mounted light emitting cell group in a cross section. It is a schematic diagram which shows the manufacturing method of the light-emitting device which concerns on this embodiment, and is a schematic diagram which shows the state which removes the board | substrate with which the light emitting cell group was provided in a cross section. It is a schematic diagram which shows the manufacturing method of the light-emitting device which concerns on this embodiment, and is a schematic diagram which shows the state which dry-etches the semiconductor layer of a light emitting cell group in a cross section. It is a schematic diagram which shows the manufacturing method of the light-emitting device which concerns on this embodiment in a cross section, and is a schematic diagram which shows the state which wet-etches a semiconductor laminated body. It is a schematic diagram which shows the manufacturing method of the light-emitting device which concerns on this embodiment in a cross section, and is a schematic diagram which shows the state which provided the fluorescent substance layer in the light emitting cell group. It is a flowchart which shows the manufacturing method of the light-emitting device which concerns on 1st Embodiment. In the manufacturing method of the light-emitting device which concerns on 1st Embodiment, it is the elements on larger scale which expand and show typically a part of light emitting cell which formed the whole surface electrode layer on the semiconductor laminated body. FIG. 5B is a cross-sectional view taken along line VB-VB in FIG. 5A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 5B is a cross-sectional view taken along line VC-VC in FIG. 5A in the method for manufacturing the light emitting device according to the first embodiment. In the manufacturing method of the light-emitting device concerning a 1st embodiment, it is a partial expansion plan view expanding and showing typically a part of the state where a part of a semiconductor layered product was etched and a groove part was formed. FIG. 6B is a cross-sectional view taken along line VIB-VIB in FIG. 6A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 6B is a cross-sectional view taken along line VIC-VIC in FIG. 6A in the method for manufacturing the light emitting device according to the first embodiment. In the method for manufacturing a light emitting device according to the first embodiment, a part of the entire surface electrode and the first semiconductor layer is removed, and a part of the light emitting cell in which the opening exposing the first semiconductor layer from the second semiconductor layer is formed is enlarged. FIG. FIG. 7B is a cross-sectional view taken along line VIIB-VIIB in FIG. 7A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 7B is a cross-sectional view taken along line VIIC-VIIC in FIG. 7A in the method for manufacturing the light emitting device according to the first embodiment. In the manufacturing method of the light-emitting device which concerns on 1st Embodiment, it is the partial expansion plan view which expands and shows typically a part of light emitting cell which formed the 1st insulating layer continuous to a light emitting cell group and a groove part. FIG. 8B is a cross-sectional view taken along line VIIIB-VIIIB in FIG. 8A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 8B is a cross-sectional view taken along line VIIIC-VIIIC in FIG. 8A in the method for manufacturing the light emitting device according to the first embodiment. In the manufacturing method of the light-emitting device concerning a 1st embodiment, it is the elements on larger scale which expand and show typically a part of light emitting cell which formed the 1st hole in the 1st semiconductor layer. FIG. 9B is a cross-sectional view taken along line IXB-IXB in FIG. 9A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 9B is a cross-sectional view taken along line IXC-IXC in FIG. 9A in the method for manufacturing the light emitting device according to the first embodiment. In the manufacturing method of the light-emitting device concerning a 1st embodiment, it is a partial expansion plan view expanding and showing typically a part of light-emitting cell which formed a connection electrode in the 1st hole conducted to the 1st semiconductor layer. FIG. 10B is a cross-sectional view taken along line XB-XB in FIG. 10A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 10B is a cross-sectional view taken along line XC-XC in FIG. 10A in the method for manufacturing the light emitting device according to the first embodiment. In the manufacturing method of the light-emitting device which concerns on 1st Embodiment, it is the elements on larger scale which expand and show typically a part of light emitting cell which formed the wiring electrode on the 1st insulating layer. FIG. 11B is a cross-sectional view taken along line XIB-XIB in FIG. 11A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 11B is a cross-sectional view taken along line XIC-XIC in FIG. 11A in the light emitting device manufacturing method according to the first embodiment. In the manufacturing method of the light-emitting device which concerns on 1st Embodiment, it is the elements on larger scale which expand and show typically a part of light emitting cell which formed the 2nd insulating layer on the wiring electrode. FIG. 12B is a cross-sectional view taken along line XIIB-XIIB in FIG. 12A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 12B is a cross-sectional view taken along line XIIC-XIIC in FIG. 12A in the method for manufacturing the light emitting device according to the first embodiment. In the method for manufacturing a light emitting device according to the first embodiment, a partial enlarged plane schematically showing an enlarged part of a light emitting cell in which the third hole of the second insulating layer and the second hole of the first insulating layer are formed. FIG. FIG. 13B is a cross-sectional view taken along line XIIIB-XIIIB in FIG. 13A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 13B is a cross-sectional view taken along line XIIIC-XIIIC in FIG. 13A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 13B is a cross-sectional view taken along line XIIID-XIIID in FIG. 13A in the method for manufacturing the light emitting device according to the first embodiment. In the manufacturing method of the light-emitting device concerning a 1st embodiment, it is the elements on larger scale which expand and show typically a part of light emitting cell which formed the 2nd electrode on the 2nd insulating layer. FIG. 14B is a cross-sectional view taken along line XIVB-XIVB in FIG. 14A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 14B is a cross-sectional view taken along line XIVC-XIVC in FIG. 14A in the method for manufacturing the light emitting device according to the first embodiment. In the manufacturing method of the light-emitting device concerning a 1st embodiment, it is a sectional view in the XIVD-XIVD line of Drawing 14A. In the manufacturing method of the light-emitting device concerning a 1st embodiment, it is the elements on larger scale which expand and show typically a part of light emitting cell which formed the bump on the 1st electrode and the 2nd electrode. FIG. 15B is a cross-sectional view taken along line XVB-XVB in FIG. 15A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 15B is a cross-sectional view taken along line XVC-XVC in FIG. 15A in the method for manufacturing the light emitting device according to the first embodiment. FIG. 15B is a cross-sectional view taken along line XVD-XVD in FIG. 15A in the method for manufacturing the light emitting device according to the first embodiment. In the manufacturing method of the light-emitting device concerning a 1st embodiment, it is a sectional view showing typically the state of a light-emitting cell after carrying out dry etching and making a semiconductor layer thin partially expanded. In the manufacturing method of the light-emitting device concerning this embodiment, it is sectional drawing which expands partially and shows typically the state of the light emitting cell which performed wet etching and roughened the surface of the semiconductor layer. It is a flowchart which shows the manufacturing method of the light-emitting device which concerns on 2nd Embodiment. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is the elements on larger scale which expand and show typically a part of light emitting cell which formed the whole surface electrode layer on the semiconductor layered product. FIG. 19B is a cross-sectional view taken along line XIXB-XIXB in FIG. 19A in the method for manufacturing a light emitting device according to the second embodiment. FIG. 19B is a cross-sectional view taken along line XIXC-XIXC in FIG. 19A in the method for manufacturing the light emitting device according to the second embodiment. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a partial enlarged plan view expanding and showing typically a part of the state where a part of a semiconductor layered product was etched and a groove part was formed. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a sectional view in the XXB-XXB line of Drawing 20A. In the manufacturing method of the light-emitting device concerning 2nd Embodiment, it is sectional drawing in the XXC-XXC line | wire of FIG. 20A. In the method for manufacturing a light emitting device according to the second embodiment, the whole surface electrode and a part of the first semiconductor layer are removed, and a part of the light emitting cell in which the opening from which the first semiconductor layer is exposed from the second semiconductor layer is formed is enlarged. FIG. FIG. 21B is a cross-sectional view taken along line XXIB-XXB in FIG. 21A in the method for manufacturing the light emitting device according to the second embodiment. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a sectional view in the XXIC-XXIC line of Drawing 21A. In the manufacturing method of the light-emitting device which concerns on 2nd Embodiment, it is a partial enlarged plan view which expands and shows typically a part of light emitting cell which formed the 1st insulating layer continuous to a light emitting cell group and a groove part. FIG. 22B is a cross-sectional view taken along line XXIIB-XXIIB in FIG. 22A in the method for manufacturing the light emitting device according to the second embodiment. FIG. 22B is a cross-sectional view taken along line XXIIC-XXIIC in FIG. 22A in the method for manufacturing the light emitting device according to the second embodiment. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is the elements on larger scale which expand and show some light emitting cells which formed the 2nd hole in the 1st insulating layer. FIG. 23B is a cross-sectional view taken along line XXIIIB-XXIIIB in FIG. 23A in the method for manufacturing the light emitting device according to the second embodiment. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a sectional view in the XXIIIC-XXIIIC line of Drawing 23A. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is the elements on larger scale which expand and show typically a part of light emitting cell which formed the wiring electrode on the 1st insulating layer. FIG. 24B is a cross-sectional view taken along line XXIVB-XXIVB in FIG. 24A in the method for manufacturing the light emitting device according to the second embodiment. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a sectional view in the XXIVC-XXIVC line of Drawing 24A. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is the elements on larger scale which expand and show typically a part of light emitting cell which formed the 2nd insulating layer on the wiring electrode. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a sectional view in the XXVB-XXVB line of Drawing 25A. In the manufacturing method of the light-emitting device concerning 2nd Embodiment, it is sectional drawing in the XXVC-XXVC line | wire of FIG. 25A. In the method for manufacturing a light emitting device according to the second embodiment, a part schematically showing an enlarged part of the light emitting cell in which the third hole is formed in the second insulating layer and the first hole is formed in the first insulating layer. It is an enlarged plan view. FIG. 26B is a cross-sectional view taken along line XXVIB-XXVIB in FIG. 26A in the method for manufacturing the light emitting device according to the second embodiment. FIG. 26B is a cross-sectional view taken along line XXVIC-XXVIC in FIG. 26A in the method for manufacturing the light emitting device according to the second embodiment. FIG. 26B is a cross-sectional view taken along line XXVID-XXVID in FIG. 26A in the method for manufacturing the light emitting device according to the second embodiment. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a partial expansion plan view expanding and showing typically a part of light emitting cell which formed the 1st electrode and the 2nd electrode. FIG. 27B is a cross-sectional view taken along line XXVIIB-XXVIIB in FIG. 27A in the method for manufacturing the light emitting device according to the second embodiment. FIG. 27B is a cross-sectional view taken along line XXVIIC-XXVIIC in FIG. 27A in the method for manufacturing the light emitting device according to the second embodiment. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a sectional view in the XXVIID-XXVIID line of Drawing 27A. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a partial expansion plan view expanding and showing typically a part of light-emitting cell which formed a bump on the 1st electrode and the 2nd electrode. FIG. 28B is a cross-sectional view taken along line XXVIIIB-XXVIIIB in FIG. 28A in the method for manufacturing the light emitting device according to the second embodiment. FIG. 28B is a cross-sectional view taken along line XXVIIIC-XXVIIIC in FIG. 28A in the method for manufacturing the light emitting device according to the second embodiment. FIG. 28B is a cross-sectional view taken along line XXVIIID-XXVIIID in FIG. 28A in the method for manufacturing the light emitting device according to the second embodiment. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a sectional view showing typically the state after carrying out dry etching and making a semiconductor layered product thin partially partially expanded. In the manufacturing method of the light-emitting device concerning a 2nd embodiment, it is a sectional view showing typically the state of the light-emitting cell which performed wet etching and roughened the surface of the semiconductor layered product partially enlarged. . FIG. 6 is a partially enlarged plan view schematically showing a part of a light emitting device according to a second embodiment in an enlarged scale. In the method for manufacturing a light emitting device according to each embodiment, a part of a state in which one part of a light emitting cell is partitioned by a groove and formed by etching a part of a semiconductor stacked body according to a modification is schematically illustrated. FIG. In the method of manufacturing a light emitting device according to each embodiment, a part of a state in which a part of a semiconductor stacked body according to a modification is etched to form a groove in a region of one light emitting cell is schematically illustrated in an enlarged manner. It is a partial enlarged plan view. FIG. 32B is a cross-sectional view taken along line XXXIIC-XXXIIC in FIG. 32B in a modification of the method for manufacturing the light emitting device according to each embodiment.

  Hereinafter, a method for manufacturing a light emitting device and a light emitting device according to an embodiment will be described with reference to the drawings. The drawings referred to in the following description schematically show the present embodiment, and the scale, spacing, positional relationship, etc. of each member are exaggerated, or some of the members are not shown. There may be. Moreover, in the following description, the same name and code | symbol are shown in principle the same or the same member, and detailed description is abbreviate | omitted suitably.

<< Light Emitting Device 100 >>
First, an outline of the light emitting device 100 according to the present embodiment will be described with reference to FIGS. 1 to 3F.
The light emitting device 100 includes a light emitting cell group 10 that is an aggregate of a plurality of light emitting cells, and an IC substrate 20 on which the light emitting cell group 10 is provided. The light emitting device system 100S includes a light emitting device 100 having the light emitting cell group 10 and the IC substrate 20, a secondary mounting substrate 30 on which the IC substrate 20 of the light emitting device 100 is mounted, and a controller connected to the secondary mounting substrate 30. 50 and a radiator 60 provided on the secondary mounting substrate.

(First embodiment)
<Method for Manufacturing Light-Emitting Device 100>
A method of manufacturing the light emitting device 100 according to the first embodiment will be described with reference to FIGS.
The manufacturing method of the light emitting device 100 includes a first A step SA1 for preparing a semiconductor stacked body, a second A step SA2 for forming a light emitting cell group including a plurality of light emitting cells, and exposing the first semiconductor layer from the second semiconductor layer. 3A process SA3, 4A process SA4 for forming the first insulating layer, 5A process SA5 for forming the wiring electrode, 6A process SA6 for forming the second hole, and 7A for forming the second electrode It includes a process SA7, an 8A process SA8 for thinning the semiconductor layer, and a 9A process SA9 for roughening the semiconductor layer. Note that the display of the first semiconductor layer 12n, the second semiconductor layer 12p, and the light emitting layer 12a in the drawings is only FIG. 5B and FIG. 5C, and is omitted in the other drawings in FIGS. To do.

The semiconductor stacked body preparation step of preparing the semiconductor stacked body as the first A process SA1 is a process of preparing the semiconductor stacked body 12 formed on the substrate 11 as shown in FIGS. 5A to 5C. In this step, a semiconductor stack including an n-type semiconductor layer that is the first semiconductor layer 12n formed on the substrate 11, a light emitting layer 12a, and a p-type semiconductor layer that is the second semiconductor layer 12p in this order from the substrate 11 side. Prepare the body 12. The semiconductor stacked body 12 is set to a size that allows the external region 10Eb to be formed adjacent to the region 10Ea where the light emitting cell 1 is formed.
Next, a full-surface electrode forming step for forming a full-surface electrode layer 13 which is a p-side full-surface electrode on the semiconductor laminate 12 is performed. In the entire surface electrode forming step, the entire surface electrode layer 13 can be formed by, for example, a sputtering method.

  Then, the light emitting cell formation process which forms the light emitting cell 1 which is 2A process SA2 is performed. In this light emitting cell forming step, as shown in FIGS. 6A to 6C, a plurality of groove portions 14 a are formed in the semiconductor stacked body 12, and the semiconductor stacked body 12 is partitioned into regions to be a plurality of light emitting cells. 10 is a step. In the light emitting cell forming step, a plurality of groove portions 14a reaching the first semiconductor layer 12n are formed in a lattice shape from the entire surface electrode layer 13 side formed on the upper surface of the semiconductor stacked body 12, whereby a plurality of rows arranged in a matrix are formed. The light emitting cell 1 is formed. The groove portion 14a is formed by means such as etching that partially removes the semiconductor stacked body 12. Here, the groove 14a is formed by digging down to the first semiconductor layer 12n in a lattice shape so as to be a rectangular light emitting cell 1 in a top view through a mask. The number of the light emitting cells 1 formed by being partitioned by the groove portions 14a is, for example, 15 to 40 columns × 15 to 40 rows. Moreover, the depth of the groove part 14a can be made into the range of 2.0-5.0 micrometers, for example.

  Further, in the light emitting cell forming step, an external region 10Eb extending in at least one of the row direction and the column direction of the plurality of light emitting cells is disposed adjacent to the plurality of light emitting cells 1 arranged in a matrix. The groove part 14a can be formed. Here, the groove 14 a located at one end in the column direction defines an external region 10 Eb adjacent to the region 10 Ea of the semiconductor stacked body 12 forming the light emitting cell group 10. The external region 10Eb is continuously formed with a predetermined width, and is formed in a size necessary for forming the first electrode 2 for connecting to the external electrode.

  Here, one external region 10Eb extending in the column direction of the light emitting cell group 10 is formed, but two external regions 10Eb may be formed in the column direction, and may be formed not only in the column direction but also in the row direction. The external region 10Eb may be formed so as to surround the light emitting cell group 10. Furthermore, an annular outer region 10Eb may be formed so as to surround the light emitting cell group 10. By forming a plurality of external regions 10Eb and connecting an external power source to each of the external regions 10Eb, variations in current supplied to the plurality of light emitting cells 1 can be reduced. Thereby, the dispersion | variation in the current density distribution in the whole light emitting cell group 10 is reduced, and light emission nonuniformity can be reduced. In the portion of the external region 10Eb, the first electrode 2 formed by extending the wiring electrode 17 and conducting to the wiring electrode 17 is formed.

In the first semiconductor layer exposing step of exposing the first semiconductor layer 12n as the third A step SA3, as shown in FIGS. 7A to 7C, the second semiconductor layer 12p and the entire surface electrode layer 13 are removed, and the second semiconductor layer 12n is removed. In this step, a part of the first semiconductor layer 12n is exposed from the layer 12p. In this exposure step, a mask is provided at a position excluding the exposed portion, and etching or the like is performed to expose a part of the first semiconductor layer 12n from the entire surface electrode layer 13 and the second semiconductor layer 12p. The exposed region 14b is formed.
4A process SA4 is a 1st insulating layer formation process which forms the 1st insulating layer 15 in which the 1st hole 15a is formed, as shown to FIG. 9A-FIG. 9C. In the first insulating layer forming step, the first insulating layer 15 is formed so as to cover the entire surface electrode layer 13, the groove 14a, and the exposed region 14b. The first insulating layer 15 is, for example, a dielectric multilayer film in which a plurality of layers made of silicon oxide and layers made of niobium oxide are alternately stacked, and serves as a reflective layer that reflects light from the semiconductor stacked body 12. To fulfill. As an example, the first insulating layer 15 is formed with a thickness in the range of 600 nm to 1.5 μm by a sputtering method.

  Moreover, after the 1st insulating layer 15 is formed, the 1st hole formation process which forms the 1st hole 15a is performed. In the first hole forming step, the first hole 15a is formed in a region of the first insulating layer 15 that covers the exposed region 14b. The first hole 15a is formed to electrically connect a wiring electrode 17 described later to the first semiconductor layer 12n. The first hole 15a is formed by removing the first insulating layer 15 in a region corresponding to the entire exposed region 14b or a region corresponding to a part of the exposed region 14b by etching or the like. The first semiconductor layer 12n is exposed from the first insulating layer 15 in the region where the first hole 15a is provided.

  Subsequently, before performing the next process, as shown in FIGS. 10A to 10C, a connection electrode is provided in which the connection electrode 16 is provided in contact with the first semiconductor layer 12n and in conduction with the first semiconductor layer 12n in the first hole 15a. Perform the process. The connection electrode forming step is a step of forming the connection electrode 16 on the upper surface of the first hole 15a and the surrounding first insulating layer 15 by covering the periphery of the first hole 15a with a mask and performing a sputtering method or the like. . For the connection electrode 16, for example, titanium, aluminum, or an alloy containing these metals as a main component can be used. The connection electrode 16 may be a laminated body in which the single metal layer and the metal alloy layer are laminated. By forming the connection electrode 16, the electrical resistance between the connection electrode 16 and the first semiconductor layer 12 n is reduced, and compared to the case where the first semiconductor layer 12 n and the wiring electrode 17 are directly connected, The increase in the forward voltage Vf of the light emitting cell 1 can be reduced.

  As shown in FIGS. 11A to 11C, the fifth A process SA5 is a wiring electrode forming process for forming a wiring electrode 17 that is electrically connected to the first semiconductor layer 12n through the first hole 15a. In this wiring electrode formation step, the wiring electrode 17 is formed so as to cover a predetermined region on the connection electrode 16 and the first insulating layer 15 which are electrically connected to the first semiconductor layer 12n in the first hole 15a. The wiring electrode 17 is formed except for the planned region 17e where the second hole 15b (and the third hole 18a) that conducts with the second electrode 19 is to be formed. That is, the wiring electrode 17 is formed by forming a mask that covers the planned region 17e and performing a sputtering method or the like. As shown in FIG. 11A, the planned region 17e is formed by the mask so as to be a substantially circular hole. The wiring electrode 17 is made of, for example, an alloy containing aluminum as a main component. The wiring electrode 17 may be a laminate of an aluminum alloy layer and another metal layer, or may be formed by laminating a single metal layer such as titanium and a metal alloy layer. Furthermore, although two planned areas 17e are provided for one light emitting cell 1, the number is not limited.

Next, a second insulating layer forming step SA5a for forming the second insulating layer 18 in which the third hole 18a is formed is performed.
In the second insulating layer forming step, as shown in FIGS. 12A to 12C, the second insulating layer 18 is formed on the wiring electrode 17 and on the first insulating layer 15 exposed from the wiring electrode 17 in the predetermined region 17e. It is a process. The second insulating layer 18 is formed by, for example, a sputtering method. The second insulating layer 18 is, for example, an insulating layer made of SiO _2, film thickness can be such that the range of 300 nm to 700 nm.

  Next, a hole forming step SA6 is performed in which the third hole 18a is formed in the second insulating layer 18 and the second hole 15b is formed in the first insulating layer 15. In the hole forming step SA6, as shown in FIGS. 13A to 13C, the second hole 15b and the third hole 18a are formed in the second insulating layer 18 provided in the position of the predetermined region 17e in the second insulating layer 18. It is a process to do. This hole forming step SA6 includes a step that becomes the sixth step A. That is, in the hole forming step SA6, the second hole formation for forming the second hole in the first insulating layer 15 above the predetermined region (planned region 17e) on the upper surface of the second semiconductor layer 12p of each of the plurality of light emitting cells 1 is performed. A process is performed.

  In the hole forming step SA6, as shown in FIGS. 13A and 13B, the wiring electrode 17 is connected to the entire surface electrode layer 13 to be electrically connected to the second semiconductor layer 12p in a region 18e overlapping the planned region 17e in a top view. This is a step of forming the second hole 15 b and the third hole 18 a in the first insulating layer 15 and the second insulating layer 18. The second hole 15b and the third hole 18a form a mask having an opening in a part of the region 18e on the second insulating layer 18, and the first insulating layer 15 and the second insulating layer 18 are etched through the mask. It is formed by doing. The second hole 15b formed in the first insulating layer 15 and the third hole 18a formed in the second insulating layer 18 are sized and shaped as long as they are within the region 18e of the second insulating layer 18. Is not limited. The second hole 15 b and the third hole 18 a are formed so as to communicate with each other, and a part of the entire surface electrode layer 13 is exposed from the second insulating layer 18 and the first insulating layer 15.

  As shown in FIGS. 14A to 14C, the seventh A process SA7 includes a second electrode that is electrically connected to the second semiconductor layer 12p through the entire surface electrode layer 13 in the region where the second hole 15b and the third hole 18a are provided. 19 is a second electrode forming step for forming 19. The second electrode forming step includes a bump forming step of forming the second electrode 19 and forming the bump 3. In the second electrode forming step, the second electrode 19 is formed in a region where the second hole 15b and the third hole 18a communicating with the second hole 15b are provided, and the second semiconductor layer is formed via the entire surface electrode layer 13. 12p and the second electrode 19 are electrically connected. The second electrode 19 is a single piece or a laminated body of metal or alloy, and is formed by a sputtering method or the like using a mask. In the second electrode 19, the central portion 19 c, which is a region where the connection electrode 16 is provided, is formed in a concave shape in a cross-sectional view, and the portion of the connection portion 19 g connected to the entire surface electrode layer 13 is formed in a concave shape. In the single light emitting cell 1, the second electrode 19 is formed in a rectangular shape in a region surrounded by the groove 14a so as to be separated from the groove 14a. And the 2nd electrode 19 can be formed in the range of 50 to 95% by area ratio as an example with respect to the area | region enclosed by the groove part 14a in top view. The thickness of the second electrode 19 is preferably formed in the range of 300 nm to 700 nm. When forming the second electrode 19, as shown in FIG. 14D, the first electrode 2 that is separated from the second electrode 19 and is electrically connected to the wiring electrode 17 can be formed in the external region 10Eb.

  After the second electrode 19 and the first electrode 2 are formed, a bump forming step for forming a bump 3 to be connected to the IC substrate 20 described later at a predetermined position of the second electrode 19 and the first electrode 2 is performed. In the bump forming process, as shown in FIGS. 15A to 15D, four bumps 3 are formed in one region partitioned by the groove portion 14 a of the light emitting cell 1. In addition, at the position where the first electrode 2 is formed, four bumps 3 are formed around the central portion 2c. The number, diameter, and height of the bumps 3 are not particularly limited. The diameter of the bump can be, for example, about 3.0 μm to 10 μm.

  After the bump formation step, as shown in FIG. 3A, there is a light emitting cell group mounting step SA7a for flip-chip mounting the substrate 11 provided with the light emitting cell group 10 on the IC substrate electrode 22 of the IC substrate 20 via the bump 3. Done. Next, as shown in FIG. 3B, after the light emitting cell group 10 is mounted with the bumps 3, the underfill 4 is provided between the upper surface of the IC substrate 20 and the lower surface or side surface of the light emitting cell group 10. Subsequently, as shown in FIG. 3C, the substrate 11 is peeled from the light emitting cell group 10 mounted on the IC substrate 20 by a peeling means such as laser lift-off (substrate peeling step SA8). In the light emitting cell group 10 mounted on the IC substrate 20, the second electrode 19 of each light emitting cell 1 is connected to the IC substrate electrode 22 formed on the IC substrate 20 corresponding to the light emitting cell 1, respectively. It will be in the state. Thereby, each light emitting cell 1 of the light emitting cell group 10 becomes a state in which lighting control can be performed individually by controlling by the controller 50, for example.

  8A process SA8 is a semiconductor layer thinning process which thins the 1st semiconductor layer 12n of the semiconductor laminated body 12 after peeling the board | substrate 11, as shown to FIG. 3D and FIG. In this semiconductor layer thinning step, dry etching or polishing is performed so that the first semiconductor layer 12n does not reach the first insulating layer 15 formed in the groove 14a from the side of the first semiconductor layer 12n from which the substrate 11 is peeled. To remove. In the semiconductor layer thinning step, for example, reactive ion etching using a chlorine-based gas can be used as dry etching, and polishing can be performed by CMP (chemical chemical polishing) using, for example, slurry. Mechanical polishing) can be used.

  The 9A step SA9 is a semiconductor layer roughening step for roughening the surface of the first semiconductor layer 12n on the thinned side, as shown in FIGS. 3E and 17. In this semiconductor layer roughening step, a part of the first semiconductor layer 12n in the thickness direction is removed by wet etching, and the first insulating layer 15 is exposed from the first semiconductor layer 12n at the position of the groove 14a. Roughening is performed on the surface of the first semiconductor layer 12n removed in step SA. Here, when the first insulating layer 15 is exposed from the first semiconductor layer 12n at the position of the groove portion 14a, it is not divided into two steps of the 8A step SA8 and the 9A step SA9 as in this embodiment. It can also be performed in a process. For example, the first insulating layer 15 can be exposed from the first semiconductor layer 12n by performing dry etching or the like from the side of the first semiconductor layer 12n from which the substrate 11 is peeled.

  However, in this case, the wiring electrode 17, the first insulating layer 15, the second insulating layer 18 and the like provided in the groove 14a may be deteriorated or deteriorated by dry etching. As a result, a lighting failure of the light emitting cell 1 occurs due to the wiring electrode 17 being disconnected at the position of the groove 14a. Therefore, in this embodiment, after the first semiconductor layer 12n is removed by dry etching or polishing so as not to reach the first insulating layer 15 in the semiconductor layer thinning step, the first roughening step in the semiconductor layer is performed. The first semiconductor layer 12n located below the insulating layer 15 is removed by wet etching. Thereby, compared with the case where the 1st insulating layer 15 is exposed only by dry etching, alteration or deterioration of the wiring electrode 17, the 1st insulating layer 15, and the 2nd insulating layer 18 can be reduced. Furthermore, since the step of exposing the first insulating layer 15 and the step of roughening the first semiconductor layer 12n are performed simultaneously, the number of steps does not increase.

As the wet etching performed in the semiconductor layer roughening step, for example, an aqueous solution containing TMAH can be used. In such wet etching, the first insulating layer 15 made of SiO ₂ or the like is hardly etched, and the semiconductor stacked body 12 is selectively etched. The roughness of the roughened surface of the first semiconductor layer 12n is processed so that, for example, the depth of the recess is about 2.5 μm. By roughening the first semiconductor layer 12n, an uneven shape is formed on the surface of the first semiconductor layer 12n, and the light emission efficiency from the light emitting layer 12a can be improved.
In the semiconductor layer roughening step, wet etching is preferably performed so that the lower surface of the first semiconductor layer 12n is positioned closer to the second semiconductor layer 12p than the wiring electrode 17 provided in the groove 14a. Thereby, the light from the light emitting cells 1 is not easily propagated to the adjacent light emitting cells 1, and the light from the light emitting cells 1 is easily reflected by the wiring electrode 17 provided in the groove 14a. Therefore, the parting of the light emitting device 100 can be improved.

  The relationship between FIG. 3D and FIG. 16 shows the same process in different fields of view. FIG. 3D schematically shows the entire device in cross section so that the state of the entire device can be understood. The state is schematically shown in an enlarged manner. Further, the relationship between FIG. 3E and FIG. 17 also shows the same process in different fields of view, and FIG. 3E schematically shows the entire device in cross section so that the state of the entire device can be seen. FIG. One state is schematically shown in an enlarged manner.

After the semiconductor layer roughening step, the phosphor layer is formed by forming the phosphor layer 5 containing the phosphor as the wavelength conversion member on the resin serving as the base material so as to cover the roughened first semiconductor layer 12n. A forming step is performed. In the phosphor layer forming step, as an example, the phosphor layer 5 is provided by dropping means such as potting or spraying or coating means.
As shown in FIG. 1, the light emitting device 100 manufactured by the process as described above is further mounted on the secondary mounting board 30, and a controller 50 as a control mechanism is connected to the secondary mounting board 30. By providing the radiator 60 for cooling the secondary mounting substrate 30, the light emitting device system 100S is obtained. As the secondary mounting substrate 30, for example, a ceramic material such as aluminum nitride or a glass epoxy resin can be used. As the radiator 60, for example, a metal such as Al or an Al alloy can be used.

Next, the configuration of the light emitting device 100 will be described with reference to the drawings as appropriate.
The light emitting device 100 includes a light emitting cell group 10 having a plurality of light emitting cells 1, an IC substrate 20 to which the light emitting cell group 10 is connected, and a phosphor layer 5 that covers the surface of the light emitting cell group 10. . Further, an underfill 4 in which a light diffusing material is contained in a resin serving as a base material is provided between the light emitting cell group 10 of the light emitting device 100 and the IC substrate 20. The base material of the underfill 4 is preferably a material that absorbs less light from the light emitting cell 1, and for example, an epoxy resin, a silicone resin, a modified silicone resin, or the like can be used. As the light diffusing material contained in the underfill 4, titanium oxide, aluminum oxide, or the like can be used. By providing the underfill 4, the light from the light emitting cell group 10 is easily reflected by the light extraction surface side opposite to the side where the IC substrate 20 is disposed, and the light extraction efficiency is improved. Can do.

The light emitting device 100 is provided so as to cover the first insulating layer 15 having the first hole 15a and the second hole 15b in each of the light emitting cells 1, and the first semiconductor layer in each of the light emitting cells 1. The wiring electrode 17 that conducts through the first hole 15a at 12n, the second electrode 19 that is provided in each of the light emitting cells 1 and conducts through the second hole 15b and communicates with the second semiconductor layer 12p, the wiring electrode 17 and the second electrode 19 and a second insulating layer 18 having a third hole 18a provided between the first and second holes 18a. Furthermore, in the light emitting device 100, the first insulating layer 15 is exposed from the first semiconductor layer 12n between the plurality of light emitting cells 1, and the light extraction surface serving as the lower surface of the first semiconductor layer 12n has an uneven shape. ing. The light emitting device 100 has a connection electrode 16 provided in contact with the first semiconductor layer 12n in the first hole, and the wiring electrode 17 is electrically connected to the first semiconductor layer 12n through the connection electrode 16. It may be.
Hereinafter, each configuration of the light emitting device 100 will be described.

  The light emitting cell group 10 includes a first semiconductor layer 12n and a second semiconductor layer 12p provided on the upper surface of the first semiconductor layer 12n so that a part of the upper surface of the first semiconductor layer 12n is exposed. 12 have a plurality of light emitting cells 1 respectively. As shown in FIG. 2A, the plurality of light emitting cells 1 are provided in the region 10Ea so as to be aligned in the row direction and the column direction. Further, an external region 10Eb is provided adjacent to the region 10Ea along the row direction or the column direction, and the first electrode 2 is formed in the external region 10Eb. The region 10Ea and the external region 10Eb are both formed of the semiconductor stacked body 12.

As the light emitting cell 1, it is preferable to use a light emitting diode (LED). A light emitting diode having an arbitrary wavelength can be selected. For example, as blue and green light emitting diodes, those using ZnSe, nitride-based semiconductors (In _X Al _Y Ga _1-XY N, 0 ≦ X, 0 ≦ Y, X + Y ≦ 1), or GaP are used. be able to.

The IC substrate 20 includes an IC support substrate 21 and a plurality of IC substrate electrodes 22 formed on the IC support substrate 21.
As the IC support substrate 21, for example, a silicon substrate, a SiC substrate, a GaN substrate, or the like can be used. The top view shape can be formed in a rectangular shape, for example. The IC support substrate 21 is formed so that wirings are formed on the substrate surface, the substrate, etc. and can be connected to external electrodes.
The IC substrate electrode 22 is an electrode for electrically connecting the light emitting cell 1 and the first electrode 2 of the light emitting cell group 10 and is controlled by the controller 50 to individually control the lighting of the plurality of light emitting cells 1. Can do. The IC substrate electrode 22 is formed corresponding to each bump 3 so that the bump 3 formed on the upper surface of the light emitting cell 1 and the bump 3 formed on the upper surface of the first electrode 2 can be individually connected. .

  In the light emitting cell 1, the side on which the uneven shape of the first semiconductor layer 12n is formed becomes the light extraction surface. The light emitting cell 1 includes an electrode structure on the semiconductor laminate 12 on the IC support substrate 21 side, and the electrode structure and the IC substrate electrode 22 are electrically connected to each other so that individual lighting can be performed. The electrode structure of the light emitting cell 1 includes a wiring electrode 17 that electrically connects the first semiconductor layer 12n to the first electrode 2, and a second electrode 19 that is electrically connected to the second semiconductor layer 12p. Yes. Here, the light emitting cell 1 includes a connection electrode 16 that is electrically connected to the wiring electrode 17, and the first semiconductor layer 12 n is connected to the wiring electrode 17 through the connection electrode 16. In the light emitting cell 1, the entire surface electrode layer 13 is formed on the second semiconductor layer 12 p of the semiconductor stacked body 12 at a position excluding the exposed region 14 b. In the light emitting cell 1, the first insulating layer 15 is formed between the entire surface electrode layer 13 and the wiring electrode 17, and the second insulating layer 18 is formed between the wiring electrode 17 and the second electrode 19. . In the light emitting cell 1, the first electrode 2 and the second electrode 19 are arranged on the same surface side of the light emitting cell 1.

  The first electrode 2 is an electrode for supplying current to the first semiconductor layer 12n. The first electrode 2 is formed so as to cover the second insulating layer 18 in the external region 10Eb, and is connected to the wiring electrode 17 through the fourth hole 18d of the second insulating layer 18. The first electrode 2 is electrically connected to the first semiconductor layer 12 n through the wiring electrode 17 and the connection electrode 16. The first electrode 2 is formed in a rectangular shape in the external region 10Eb when viewed from above. The first electrode 2 is preferably formed using, for example, at least one selected from Ti, Al, Al alloy, Ag, and Ag alloy.

  The second electrode 19 is an electrode for supplying a current to the second semiconductor layer 12p. The second electrode 19 functions as an electrode for uniformly diffusing current in the second semiconductor layer 12p and also functions as a reflective film that reflects light from the light emitting cell 1. The second electrode 19 is formed on the upper surface of the light emitting cell 1 in a rectangular shape when viewed from above. The second electrode 19 is connected to the entire surface electrode layer 13 through the third hole 18 a of the second insulating layer 18 and the second hole 15 b of the first insulating layer 15, and is connected to the second semiconductor layer 12 p through the entire surface electrode layer 13. Is conducting. The second electrode 19 can be formed of, for example, a metal film containing at least one selected from Ti, Al, Al alloy, Ag, and Ag alloy. Here, the first electrode 2 and the second electrode 19 are formed of the same metal at the same timing by film forming means such as sputtering.

  The lower surface, which is the light extraction surface of the semiconductor stacked body 12 in the light emitting cell 1, is more than the wiring electrode 17 located in the region where the first insulating layer 15 exposed from the semiconductor stacked body 12 is provided in the cross sectional view of the light emitting cell 1. It is preferably located on the upper surface side of the semiconductor stacked body 12. Thereby, since the light propagating from the light emitting cell 1 in the lateral direction can be reflected by the wiring electrode 17, it is possible to improve the parting off when the adjacent light emitting cells 1 are turned on. Specifically, the thickness of the semiconductor stacked body 12 in the light emitting cell 1 is, for example, 1 to 10 μm, and the interval between the light emitting cells 1 is 3 to 25 μm.

  The entire surface electrode layer 13 is formed of, for example, an ITO film, and is formed so as to be connected to the second semiconductor layer 12 p and to be electrically connected to the second electrode 19. The entire surface electrode layer 13 is formed on the second semiconductor layer 12p excluding the position of the groove 14a and the exposed region 14b. The entire surface electrode layer 13 is a layer for diffusing current over the entire surface of the second semiconductor layer 12p. The full-surface electrode layer 13 is also formed on the second semiconductor layer 12p in the external region 10Eb.

The first insulating layer 15 is formed between the entire surface electrode layer 13 and the wiring electrode 17, and electrically insulates the entire surface electrode layer 13 and the wiring electrode 17. The first insulating layer 15 has a first hole 15a formed on the first semiconductor layer 12n and a second hole 15b formed in the second semiconductor layer 12p in the region of one light emitting cell 1. The entire surface electrode layer 13 is covered. Further, the first insulating layer 15 is exposed from the first semiconductor layer 12 n between the plurality of light emitting cells 1. The first insulating layer 15 also functions as protection and antistatic for the semiconductor stacked body 12. The first insulating layer 15 is formed by, for example, a single layer or a stacked layer, and can be composed of SiO ₂ , Nb ₂ O ₅ , ZrO ₂ , SiN, SiON, SiC, AlN, or the like. The first insulating layer 15 can be a dielectric multilayer film in which a plurality of dielectric layers are laminated. For example, a layer made of SiO ₂ and a layer made of Nb ₂ O ₅ are alternately laminated to form a light emitting cell. A dielectric multilayer film designed to reflect light from 1 can be used. Thereby, the light which propagates from the light emitting cell 1 in the horizontal direction can be reflected, and the parting off when the plurality of light emitting cells 1 are turned on can be improved.

  The connection electrode 16 is formed so that the wiring electrode 17 can be easily connected to the first semiconductor layer 12n. The connection electrode 16 is preferably formed of a laminated structure in which metals such as AlCu, Ti, and Ru are laminated. The connection electrode 16 is formed in a region including a circular region up to the periphery of the first hole 15 a of the first insulating layer 15.

The wiring electrode 17 has light reflectivity and is provided so as to cover the first insulating layer 15. The wiring electrode 17 is formed so as to be electrically connected to the first semiconductor layer 12n in each of the light emitting cells 1. Here, the wiring electrode 17 is connected to the first semiconductor layer 12n through the connection electrode 16 so as to be conductive. Further, the wiring electrode 17 is formed so as to open a planned region 17 e for allowing the second electrode 19 to conduct to the entire surface electrode layer 13 on both sides of the connection electrode 16. Here, the wiring electrode 17 is formed as a laminated body, and is formed, for example, by laminating AlCu, Ti, SiO ₂ or the like with respective thicknesses. When the wiring electrode 17 is formed in a region where the first insulating layer 15 is exposed from the semiconductor stacked body 12 in a top view, the light emitting cell 1 is not affected by light from the adjacent light emitting cells 1. be able to. Moreover, it is preferable that a part of the wiring electrode 17 provided between the adjacent light emitting cells is provided so as to protrude to the lower surface side from the lower surface of the first semiconductor layer 12n. Thereby, since the light propagating from the light emitting cell 1 in the lateral direction can be reflected by the wiring electrode 17, the light is not intentionally propagated to the adjacent light emitting cell 1, and the light emitting cell group 10 is closed. Can be improved.

  The second insulating layer 18 is formed between the wiring electrode 17 and the second electrode 19, and electrically insulates the wiring electrode 17 and the second electrode 19. The second insulating layer 18 is formed on the wiring electrode 17 in the region of one light emitting cell 1, and has a third hole 18a formed in the predetermined region 17e. In the second insulating layer 18, a region 18 e that is recessed by the thickness of the wiring electrode 17 is formed by the planned region 17 e in the wiring electrode 17. The third hole 18 a of the second insulating layer 18 is formed so as to communicate with the second hole 15 b of the first insulating layer 15. The second insulating layer 18 is formed continuously on the light emitting cell group 10 and also on the wiring electrode 17 on the external region 10Eb side.

The semiconductor stacked body 12 is formed in each of the light emitting cell groups 10, and is partitioned into each light emitting cell 1 by exposing the first insulating layer 15 between the plurality of light emitting cells 1. In addition, the lower surface of the first semiconductor layer 12n has an uneven shape, so that light from the semiconductor stacked body 12 can be easily extracted.
The phosphor layer 5 is formed so as to cover the light emitting cell group 10, and the lower surface of each light emitting cell 1 is covered with the phosphor layer 5. As the phosphor layer 5, for example, a material in which phosphor particles serving as a wavelength conversion member are contained in a translucent resin as a base material can be used.

The light-transmitting resin is preferably light-transmitting with respect to light emitted from the light-emitting element. For example, a silicone resin, an epoxy resin, a phenol resin, a polycarbonate resin, an acrylic resin, or a modified resin thereof is used. Can do.
As the phosphor, a phosphor used in this field can be appropriately selected, and the type and concentration of the phosphor are not particularly limited.

The layer thickness of the phosphor layer 5 is preferably 50 μm or less, for example. By setting the layer thickness of the phosphor layer 5 to 50 μm or less, the path becomes physically narrower in the in-plane direction, so that light hardly propagates. Thereby, when the light emitting cells 1 are individually turned on, the propagation of light from the lighted light emitting cells 1 to the adjacent light emitting cells 1 can be suppressed.
The light emitting device 100 configured as described above is bonded to the secondary mounting substrate 30, and the controller 50 serving as a control unit is installed on the secondary mounting substrate 30.

(Second Embodiment)
<Method for Manufacturing Light-Emitting Device 100B>
Next, a method for manufacturing a light emitting device according to the second embodiment will be described with reference to FIGS. The light emitting device manufacturing method according to the second embodiment is the same as the light emitting device manufacturing method according to the first embodiment. The electrode to which the bump 3 of each light emitting cell 1 is connected is a p-side electrode (second electrode 19). In contrast, the electrode formed on the upper surface of each light emitting cell 1 and connected to the bump 3 is different from the n-side electrode (first electrode 2). Therefore, even if it is the same name and the same code | symbol, it may be demonstrated that the place and timing formed are different.

  The manufacturing method of the light emitting device 100B includes a first B step SB1 for preparing the semiconductor stacked body 12, a second B step SB2 for forming a light emitting cell group composed of a plurality of light emitting cells, and the first semiconductor layer 12n as the second semiconductor layer 12p. A third B step SB3 exposed from the fourth step, a fourth B step SB4 for forming the first insulating layer 15, a fifth B step SB5 for forming the wiring electrode 17, and a sixth B for forming the first hole 15a in the first insulating layer 15. Process SB6, 7B process SB7 which forms the 1st electrode 2, 8B process SB8 which thins the semiconductor laminated body 12, and 9B process SB9 which roughens the semiconductor laminated body 12 are included. Note that the display of the first semiconductor layer 12n, the second semiconductor layer 12p, and the light emitting layer 12a in the drawings is only FIG. 19B and FIG. 19C, and is omitted in other drawings in FIGS. To do. In addition, the material and arrangement of each member already described are denoted by the same reference numerals, and may be omitted as appropriate.

The step of preparing the semiconductor stacked body, which is the first B step SB1, is a step of preparing the semiconductor stacked body 12 formed on the substrate 11. In this preparation step, a semiconductor including an n-type semiconductor layer that is the first semiconductor layer 12n formed on the substrate 11, a light-emitting layer 12a, and a p-type semiconductor layer that is the second semiconductor layer 12p in this order from the substrate 11 side. The laminated body 12 is prepared. The semiconductor stacked body 12 is set to a size that allows the external region 10Eb to be formed adjacent to the region 10Ea where the light emitting cell 1 is formed.
Next, a full-surface electrode forming step for forming a full-surface electrode layer 13 which is a p-side full-surface electrode on the semiconductor laminate 12 is performed. In the entire surface electrode forming step, the entire surface electrode layer 13 can be formed by, for example, a sputtering method.

  Then, the light emitting cell formation process which forms the light emitting cell 1 which is 2B process SB2 is performed. In this light emitting cell forming step, as shown in FIGS. 20A to 20C, a plurality of grooves 14 a are formed in the semiconductor stacked body 12, and the semiconductor stacked body 12 is partitioned into regions to be the plurality of light emitting cells 1. This is the process of group 10. The light emitting cell formation step is arranged in a matrix form by forming a plurality of groove portions 14a reaching the first semiconductor layer 12n in a lattice form by etching or the like from the entire surface electrode layer 13 formed on the upper surface of the semiconductor stacked body 12. A plurality of light emitting cells 1 are partitioned and formed.

  Further, in the light emitting cell forming step, an external region 10Eb extending in at least one of the row direction and the column direction of the plurality of light emitting cells is disposed adjacent to the plurality of light emitting cells 1 arranged in a matrix. The groove part 14a can be formed. In the portion of the external region 10Eb, the wiring electrode 17 is formed to extend, and the second electrode 19 that is electrically connected to the wiring electrode 17 is formed. Here, one external region 10Eb extending in the column direction of the light emitting cell group 10 is formed, but the arrangement of the external region 10Eb can be changed as in the first embodiment.

In the first semiconductor layer exposing step of exposing the first semiconductor layer 12n, which is the third B step SB3, as shown in FIGS. 21A to 21C, a part of the second semiconductor layer 12p and the entire surface electrode layer 13 are removed, In this step, a part of the second semiconductor layer 12p to the first semiconductor layer 12n is exposed by etching or the like through a mask. In this exposure step, the first semiconductor layer 12n is exposed from the entire electrode layer 13 and the second semiconductor layer 12p, and a substantially circular exposed region 14b is formed in a top view.
The fourth B step SB4 is a first insulating layer forming step for forming the first insulating layer 15 in which the first hole 15a and the second hole 15b are formed as shown in FIGS. 22A to 22C. In the first insulating layer forming step, the first insulating layer 15 is formed so as to cover the entire surface electrode layer 13, the groove 14a, and the exposed region 14b. As the first insulating layer 15, the same material as in the first embodiment described above can be used.

  In addition, after the first insulating layer 15 is formed, a second hole forming step for forming the second hole 15b is performed. The second holes 15b are formed at two locations apart on both sides of the exposed region 14b covered with the first insulating layer 15. In the second hole forming step, the second hole 15b is formed so that the wiring electrode 17 is electrically connected to the second semiconductor layer 12p through the entire surface electrode layer 13. The second holes 15b are formed in a circular shape here, but the number, shape, and size of the second holes 15b are not limited. Further, the first insulating layer 15 has a recess 15c in a region covering the exposed region 14b. The first insulating layer 15 is also provided in the groove 14a.

  The fifth B step SB5 is a wiring electrode forming step for forming the wiring electrode 17 that is electrically connected to the second semiconductor layer 12p through the second hole 15b, as shown in FIGS. 24A to 24C. In this wiring electrode formation step, the wiring electrode 17 is formed so as to cover a part of the entire surface electrode layer 13 exposed by the second hole 15b and the first insulating layer 15 excluding the recess 15c. The wiring electrode 17 is formed on the first insulating layer 15 by removing the region of the recess 15 c where the first hole 15 a conducting with the first electrode 2 is to be formed by the opening 17 a of the wiring electrode 17. That is, the wiring electrode 17 is formed by forming a mask that covers the position of the recess 15c and performing a sputtering method or the like. The wiring electrode 17 is formed on the first insulating layer 15 so as to be connected to the entire surface electrode layer 13 through the second hole 15b by the connecting portion 17g. The wiring electrode 17 is in a state where the connecting portion 17g connected to the entire surface electrode layer 13 is recessed by the thickness of the second hole 15b. The wiring electrode 17 is also formed on the first insulating layer 15 in the groove 14a.

Next, a second insulating layer forming step SB5a for forming the second insulating layer 18 in which the third hole 18a is formed is performed.
In the second insulating layer forming step SB5a, as shown in FIGS. 25A to 25C, the second insulating layer 18 is formed on the wiring electrode 17 and on the concave portion 15c of the first insulating layer 15 exposed through the opening 17a of the wiring electrode 17. Is a step of forming. The second insulating layer 18 can be formed by, for example, a sputtering method. In addition, the second insulating layer 18 is formed with a central recess 18 c of the second insulating layer 18 along with the recess of the recess 15 c of the first insulating layer 15, and with a connection 17 g of the wiring electrode 17. 18g will be formed. The second insulating layer 18 is also formed on the wiring electrode 17 in the groove 14a. The second insulating layer 18 is formed, for example, by providing a layer made of SiO _{2 with a} thickness in the range of 300 to 700 nm.

  Next, a hole forming step SB6 in which the first hole 15a is formed in the first insulating layer 15 and the third hole 18a is formed in the second insulating layer 18 is performed. In the hole forming step SB6, as shown in FIGS. 26A to 26D, the first hole 15a of the first insulating layer 15 and the third hole 18a of the second insulating layer 18 at the position of the central recess 18c of the second insulating layer 18. Is a step of forming. This hole forming step includes a step that becomes the sixth B step SB6. That is, in the hole forming step SB6, the third hole 18a of the second insulating layer 18 is formed above the predetermined region (central recess 18c) on the upper surface of the first semiconductor layer 12n of each of the plurality of light emitting cells 1, and the first The first hole forming step for forming the first hole 15a in the one insulating layer 15 is also performed.

  In the hole forming step SB6, as shown in FIGS. 26A and 26B, the first hole 15a and the first hole 15a of the first insulating layer 15 are formed in a circular concave region that is the central concave portion 18c of the second insulating layer 18 in a top view. The third hole 18a of the two insulating layer 18 is formed. The first hole 15a and the third hole 18a are formed by forming a mask that opens in the region of the central recess 18c of the second insulating layer 18, and etching through the mask. The first hole 15a formed in the first insulating layer 15 and the third hole 18a formed in the second insulating layer 18 have a size within the central recess 18c of the second insulating layer 18. The shape is not limited. The first hole 15 a and the third hole 18 a are formed so as to communicate with each other, and a part of the first semiconductor layer 12 n is exposed from the second insulating layer 18 and the first insulating layer 15.

  Further, in the hole forming step, as shown in FIG. 26D, a fourth hole 18d for conducting to the second semiconductor layer 12p is formed in the second insulating layer 18 at the position of the external region 10Eb. The fourth hole 18d is formed at the timing when the first hole 15a of the first insulating layer 15 and the third hole 18a of the second insulating layer 18 are formed. That is, a mask that opens in the region of the central recess 18c of the second insulating layer 18 and opens the position of the fourth hole 18d is formed, and etching is performed through this mask, so that the fourth hole 18d is also the first hole 18d. It is formed together with the hole 15a and the third hole 18a.

  As shown in FIGS. 27A to 27D, the seventh B step SB7 is performed in the first semiconductor layer 12n in the region where the first hole 15a of the first insulating layer 15 and the third hole 18a of the second insulating layer 18 are provided. This is a first electrode forming step for forming the first electrode 2 to be conductive. In the first electrode formation step, the first electrode 2 is formed and the second electrode 19 is formed on the second insulating layer 18 at the position of the external region 10Eb. The first electrode forming process includes a bump forming process for forming the bumps 3. In the first electrode forming step, the first electrode 2 is formed in a region where the first hole 15a and the third hole 18a are provided, and is formed to be electrically connected to the first semiconductor layer 12n. The first electrode 2 is a single or laminated body of a metal or alloy used for the electrode, and is formed by a sputtering method or the like using a mask.

  The first electrode 2 is formed with a central portion 2c formed in a concave shape in a sectional view and concave portions 2g formed separately on both sides thereof. In one light emitting cell 1, the first electrode 2 is formed in a rectangular shape, for example, spaced from the groove 14a in the center of the region surrounded by the groove 14a. And the 1st electrode 2 can be formed in 50 to 95% of range by an area ratio as an example with respect to the area | region enclosed by the groove part 14a in top view. The thickness of the first electrode 2 is preferably formed in the range of 300 to 700 nm. When forming the first electrode, as shown in FIG. 27D, the second electrode 19 that is electrically connected to the second semiconductor layer 12p can be formed in the same process.

  In the seventh B step SB7, a mask is provided in a predetermined region on the second insulating layer 18 surrounded by the groove 14a and the groove 14a, and on the second insulating layer 18 in the region 10Ea and on the second insulating layer 18 in the external region 10Eb. In addition, the first electrode 2 and the second electrode 19 are formed. The 1st electrode 2 and the 2nd electrode 19 are the simple substance or laminated body of the metal or alloy used for an electrode, and are formed by sputtering etc. using a mask. In one light emitting cell 1, the first electrode 2 is formed in the center surrounded by the groove portion 14a, for example, in a rectangular shape separated from the groove portion 14a, and as an example, in the area ratio of 50 to 95%. . The first electrode 2 and the second electrode 19 are preferably formed with a thickness in the range of 300 to 700 nm. The second electrode 19 formed in the external region 10Eb is formed away from the first electrode 2 via the groove 14a.

  After the first electrode 2 and the second electrode 19 are formed, a bump forming process is performed for forming bumps 3 for connecting to the IC substrate 20 described later at predetermined positions of the first electrode 2 and the second electrode 19. In the bump forming step, as shown in FIGS. 28A to 28D, four bumps 3 are formed in one region partitioned by the groove portion 14a of the light emitting cell 1. Further, at the position of the second electrode 19, four bumps 3 are formed around each electrode connection portion 19g. The bump 3 can be the same as that in the first embodiment.

  In addition, after the bump formation step, as shown in FIG. 3A, the substrate 11 provided with the light emitting cell group 10 is applied to the IC substrate electrode 22 of the IC substrate 20 via the bump 3 as in the first embodiment. An IC substrate mounting process for flip chip mounting is performed. As in the first embodiment, as shown in FIG. 3B, an underfill 4 is provided, and as shown in FIG. 3C, the substrate 11 is peeled off by laser lift-off, as shown in FIGS. 3E and 29. Then, as shown in FIGS. 3F and 30, the semiconductor layer roughening step, which is the ninth B step SB <b> 9, is performed.

The relationship between FIG. 3D and FIG. 29 shows the same process in different fields of view, and FIG. 3D schematically shows the entire device in cross section so that the state of the entire device can be understood. The state is schematically shown in an enlarged manner. Further, the relationship between FIG. 3E and FIG. 30 also shows the same process in different fields of view, and FIG. 3E schematically shows the whole in cross section so that the state of the entire apparatus can be seen. FIG. One state is schematically shown in an enlarged manner.
After the semiconductor layer roughening step, a phosphor layer forming step or the like may be performed as in the first embodiment.

  Next, a light emitting device 100B manufactured by the method for manufacturing a light emitting device according to the second embodiment will be described. The light emitting device 100B is formed so that the positions of the first electrode 2 and the second electrode 19 are opposite to the light emitting device 100 described above. That is, the second electrode 19 is provided in the external region 10Eb, and the first electrode 2 is provided in the region 10Ea in which the light emitting cell 1 is provided. Hereinafter, regarding the light emitting device 100B according to the second embodiment, configurations of the first electrode 2 and the second electrode 19 different from the light emitting device 100 according to the first embodiment will be mainly described.

  The light emitting device 100B includes a light emitting cell group 10 having a plurality of light emitting cells 1, an IC substrate 20 to which the light emitting cell group 10 is connected, and a phosphor layer 5 that covers the surface of the light emitting cell group 10. . The light emitting device 100B is provided so as to cover the first insulating layer 15 having the first hole 15a and the second hole 15b in each of the light emitting cells 1 and the first insulating layer 15, and the second semiconductor layer in each of the light emitting cells 1. A wiring electrode 17 that is electrically connected to 12p through the second hole 15b; a second electrode 19 that is provided in each of the light emitting cells 1 and is connected to the wiring electrode 17 that is electrically connected to the second semiconductor layer 12p through the second hole 15b; A second insulating layer 18 having a third hole 18 a provided between the electrode 17 and the second electrode 19 is provided. Further, in the light emitting device 100B, the first insulating layer 15 is exposed from the first semiconductor layer 12n between the plurality of light emitting cells 1, and the light extraction surface serving as the lower surface of the first semiconductor layer 12n has an uneven shape. ing. In the light emitting device 100B, the entire surface electrode layer 13 is provided on the second semiconductor layer 12p.

The light emitting cell group 10 includes a plurality of light emitting cells 1 arranged in the matrix direction. The light emitting cell 1 includes, as the semiconductor stacked body 12, a second semiconductor layer 12p, a light emitting layer 12a, and a first semiconductor layer 12n in order from the IC support substrate 21 side, and the first semiconductor layer 12n side serves as a light extraction surface.
As the electrode structure of the light emitting cell 1, a plurality of light emitting cells 1 are provided so as to cover the first insulating layer with the first electrode that is electrically connected to the first semiconductor layer 12 n through the first hole 15 a and having light reflectivity. A wiring electrode 17 that is electrically connected to the second semiconductor layer 12p of each through the second hole 15b is provided. Further, a second insulating layer 18 having a third hole communicating with the first hole 15 a in each of the light emitting cells 1 is provided on the wiring electrode 17.

  The first electrode 2 is an electrode for supplying current to the first semiconductor layer 12n. The first electrode 2 is formed in a rectangular shape in a top view so as to cover the second insulating layer 18. The first electrode 2 is connected to and electrically connected to the first semiconductor layer 12n through the third hole 18a of the second insulating layer 18 and the first hole 15a of the first insulating layer 15. As the first electrode 2, the same one as in the first embodiment described above can be used.

The second electrode 19 is an electrode for supplying a current to the second semiconductor layer 12p. The second electrode 19 is formed so as to cover the second insulating layer 18 in the external region 10Eb, is connected to the wiring electrode 17 through the fourth hole 18d of the second insulating layer 18, and is connected to the wiring electrode 17 through the wiring electrode 17. It is electrically connected to the second semiconductor layer 12p. The second electrode 19 is formed in a rectangular shape in the external region 10Eb when viewed from above. As the second electrode 19, the same electrode as in the first embodiment described above can be used.
A part of the wiring electrode 17 provided between the adjacent light emitting cells 1 is provided so as to protrude to the lower surface side from the lower surface of the first semiconductor layer 12n, as in the first embodiment.

The light emitting cell 1 including the first electrode 2 and the second electrode 19 as described above is mounted on the IC substrate 20 as the light emitting cell group 10 in the light emitting device 100B in a state where each of the light emitting cells 1 can be individually controlled to be lit. Is done.
Also in the manufacturing method and the light emitting device 100B of the light emitting device 100B according to the second embodiment having such a configuration, the same effects as those of the first embodiment described above can be obtained.

  In addition, the light emitting cell forming process for forming the light emitting cell 1 which is the second A process SA2 or the second B process SB2 is a light emission in a rectangular range surrounded by the groove 14a as shown in FIGS. 32A, 32B and 32C. It is also possible to remove a part of the semiconductor stacked body 12 in the region of the cell 1 and form a groove 14 w reaching the first semiconductor layer 12 n from the upper surface of the semiconductor stacked body 12. Such a groove portion 14w is not provided for partitioning the above-described semiconductor stacked body 12 into regions to be a plurality of light emitting cells 1, but the progress of light propagating from the adjacent light emitting cells 1 partitioned by the groove portion 14a. Provided to suppress. Here, when one light emitting cell 1 is lighted by individually controlling the plurality of light emitting cells 1, light propagates to the light emitting cells 1 that are not the lighting target around the light emitting cell 1, and the close-off is worsened. There is a fear. However, by forming the groove part 14w as described above in the region of the light emitting cell 1 partitioned by the groove part 14a, it is possible to suppress the progress of light propagating to the light emitting cell 1 that is not a lighting target and to improve the parting. . The groove 14w formed in the region that becomes the light emitting cell 1 can be formed in a row shape, a column shape, a lattice shape, or a concentric shape with respect to the region that becomes the light emitting cell 1, for example. The groove portion 14w can be formed after the groove portion 14a is formed, or can be formed when the groove portion 14a is formed. Moreover, the depth of the groove part 14w can be made the same as that of the said groove part 14a. An example in which such groove portions 14w are provided in a lattice pattern in the region of the light emitting cell 1 is shown in FIGS. 32B and 32C. As shown in FIG. 32B, when the light emitting cell 1 is divided into a plurality of regions by the groove 14w, a first hole 15a and a second hole 15b are provided in each of the plurality of regions (nine regions in the drawing). 15A to 15D or 28A to 28D, the respective steps are sequentially performed. At this time, the first electrode 2 or the second electrode 19 includes a plurality of regions divided by the groove portion 14w (in the drawing, nine regions as an example, other regions: a plurality of regions such as 2 × 3, 1 × 2, 2 × 2). ) Each is electrically connected to the first hole 15a or the second hole 15b. Since the subsequent steps are the same as those of the other embodiments except that the groove 14w is formed in the region to be the light emitting cell 1, the description thereof is omitted. Also, the first hole 15a and the second hole 15b described in FIG. 32B are virtually described to show that they are formed in other steps so as to be in the same state as that formed in the light emitting cell 1. However, it is appropriately formed in a later step and is not formed when the groove portion 14w is formed.

  As shown in FIG. 1, the controller 50 of the light emitting device system 100S drives the plurality of light emitting cells 1 by, for example, a passive matrix method. Wiring for driving the light emitting cell 1 by the passive matrix method is formed on the IC substrate 20 and the secondary mounting substrate side by the controller 50. In the light emitting device system 100S, each of the plurality of light emitting cells 1 can be turned on by a passive matrix method. For example, by turning on all the light emitting cells 1, as shown in FIG. It can be output as light B1. Further, in the light emitting device system 100S, the light emitting cell 1 located on the center side of the light emitting cell group 10 is turned off, and the light emitting cell 1 located on the outer peripheral portion is turned on so that the center such as the irradiation light B2 is dark. Bright light can be output around the ring. Further, by turning on only the light emitting cell 1 located at the center of the light emitting cell group 10 and turning off the light emitting cell 1 located on the outer peripheral portion, only the center such as the irradiation light B3 can output bright light. .

  Note that, when the light emitting cell 1 is turned on in the light emitting device system 100 </ b> S, heat H is generated, but the radiator 60 is installed on the secondary mounting substrate 30. Therefore, the heat H generated in the light emitting device system 100 </ b> S is radiated through the radiator 60. Therefore, the light emitting device system 100S can maintain a stable operation.

In the above-described embodiment, the connection electrode 16 is provided. However, the wiring electrode 17 may be formed without providing the connection electrode 16.
Although the second insulating layer 18 has been described as being configured, the second insulating layer 18 may not be provided, and the first electrode 2 and the second electrode 19 are arranged so as not to be electrically connected. May be.
Furthermore, in the light emitting devices 100 and 100B, the entire surface electrode layer 13 formed on the second semiconductor layer 12p may not be provided.

DESCRIPTION OF SYMBOLS 1 Light emitting cell 2 1st electrode 2a Electrode connection part 2c Center part 3 Bump 4 Underfill 5 Phosphor layer 10 Light emitting cell group 10Ea area | region 10Eb External area | region 11 Substrate 12 Semiconductor laminated body 12a Light emitting layer 12n 1st semiconductor layer 12p 2nd semiconductor Layer 13 Whole surface electrode layer 14 Light emitting element portion 14a, 14w Groove portion 14b Exposed region 15 First insulating layer 15a First hole 15b Second hole 15c Recessed portion 16 Connection electrode 17 Wiring electrode 17a Opening 17e Predetermined region 17g Connection portion 18 Second insulating layer 18a 3rd hole 18c center recessed part 18d 4th hole 18e area | region 18g recessed part 19 2nd electrode 19c center part 19g connection part 20 IC board 21 IC support board 22 IC board electrode 30 Secondary mounting board 50 Controller 60 Radiator 100 Light emitting device 100B Light emitting device 100S Light emitting device system SA1 Semiconductor stack preparation process (1A process)
SA2 Light emitting cell group forming step (2A step)
SA3 First semiconductor layer exposure step (3A step)
SA4 First insulating layer forming step (step 4A)
SA5 Wiring electrode formation process (5th A process)
SA6 hole forming step (step 6A)
SA7 Second electrode formation step (Step 7A)
SA8 Semiconductor layer thinning step (8th step)
SA9 Semiconductor layer roughening step (9th step A)
SB1 Semiconductor laminate preparation process (1B process)
SB2 Light emitting cell group formation process (2B process)
SB3 1st semiconductor layer exposure process (3B process)
SB4 first insulating layer forming step (step 4B)
SB5 Wiring electrode formation process (5th B process)
SB6 hole formation process (6th B process)
SB7 Second electrode formation step (Step 7B)
SB8 Semiconductor layer thinning process (8B process)
SB9 Semiconductor layer roughening step (9th step B)

Claims (26)

Preparing a semiconductor stacked body having a first semiconductor layer and a second semiconductor layer provided on an upper surface of the first semiconductor layer;
A second A step of forming a plurality of light emitting cells arranged in a matrix by forming a plurality of grooves reaching the first semiconductor layer from the upper surface side of the semiconductor stacked body in the semiconductor stacked body;
In each of the plurality of light emitting cells, a part of the first semiconductor layer is exposed from the second semiconductor layer by partially removing the second semiconductor layer from the upper surface side of the second semiconductor layer. Process,
A first insulating layer in which a first hole is formed above the first semiconductor layer exposed from the second semiconductor layer in each of the plurality of light emitting cells is continuously connected to the plurality of light emitting cells and the plurality of grooves. 4A process to form,
The first semiconductor layer and the first insulating layer formed in each of the plurality of light emitting cells so as to cover the first insulating layer above a region excluding a predetermined region on the upper surface of the second semiconductor layer. A 5A step of forming a wiring electrode that conducts through one hole;
A 6A step of forming a second hole in the first insulating layer above the predetermined region on the upper surface of the second semiconductor layer of each of the plurality of light emitting cells;
Forming a second electrode that is electrically connected to the second semiconductor layer in the second hole in each of the plurality of light emitting cells;
An 8A step of removing the first semiconductor layer from the lower surface side of the first semiconductor layer by dry etching or polishing so as not to reach the first insulating layer formed in the groove;
After the 8A step, a part of the first semiconductor layer in the thickness direction is removed by wet etching from the lower surface side of the first semiconductor layer, and the first insulating layer is removed from the first semiconductor at the position of the groove. A method of manufacturing a light emitting device, which includes a ninth step of exposing the layer to the surface of the first semiconductor layer removed by the eighth step A and performing a rough surface process in this order . After the step of forming the wiring electrode, a second insulating layer is formed in which a third hole communicating with the second hole is formed on the wiring electrode and the first insulating layer exposed from the wiring electrode. 2 Perform the insulating layer formation process,
In the seventh step A, the second electrode is formed above the second insulating layer, and the second semiconductor layer is formed through the second hole and the third hole formed in the second insulating layer. The method for manufacturing a light emitting device according to claim 1, wherein the light emitting device is made conductive.   3. The light emitting device according to claim 1, wherein a connection electrode forming step of providing a connection electrode in contact with the first semiconductor layer and conducting to the first semiconductor layer in the first hole is performed before the step of 5A. Device manufacturing method. In the step of forming a plurality of grooves in the semiconductor stacked body, the plurality of grooves are formed so that the plurality of light emitting cells are arranged in a matrix, and the plurality of light emitting cells arranged in a matrix Forming the groove so that an external region that is adjacent and extends in at least one of a row direction and a column direction of the plurality of light emitting cells is disposed;
4. The method of manufacturing a light emitting device according to claim 1, wherein the wiring electrode is formed to extend on the external region and is electrically connected to a first electrode provided in the external region. .   The step of forming a plurality of grooves in the semiconductor stacked body includes forming a groove reaching the first semiconductor layer from the upper surface side of the semiconductor stacked body in the semiconductor stacked body in the region of the light emitting cell. The manufacturing method of the light-emitting device as described in any one of Claims 1-4. Preparing a semiconductor stacked body having a first semiconductor layer and a second semiconductor layer provided on an upper surface of the first semiconductor layer;
A second B step of forming a plurality of light emitting cells arranged in a matrix by forming a plurality of grooves reaching the first semiconductor layer from the upper surface side of the semiconductor stacked body in the semiconductor stacked body;
In each of the plurality of light emitting cells, the second semiconductor layer is partially removed from the upper surface side of the second semiconductor layer, thereby exposing a part of the first semiconductor layer from the second semiconductor layer. Process,
A first insulating layer having a second hole is formed continuously above the plurality of light emitting cells and the plurality of grooves above a predetermined region of the upper surface of the second semiconductor layer in each of the plurality of light emitting cells. Process,
A wiring electrode that is electrically connected to the second semiconductor layer and the second hole in each of the light emitting cells is formed so as to cover the first insulating layer above the region excluding the predetermined region on the upper surface of the second semiconductor layer. 5B step to perform,
A 6B step of forming a first hole in the first insulating layer above the first semiconductor layer exposed from the second semiconductor layer of each of the plurality of light emitting cells;
A 7B step of forming, in each of the plurality of light emitting cells, a first electrode that is electrically connected to the first semiconductor layer in the first hole;
An 8B step of removing the first semiconductor layer from the lower surface side of the first semiconductor layer by dry etching or polishing so as not to reach the first insulating layer formed in the groove;
After the dry etching step, a part of the first semiconductor layer in the thickness direction is removed by wet etching from the lower surface side of the first semiconductor layer, and the first insulating layer is removed at the position of the groove. A method for manufacturing a light emitting device , comprising: a 9B step which is exposed from one semiconductor layer, and a rough surface process is performed on the surface of the first semiconductor layer removed in the 8B step in this order . After the step of forming the wiring electrode, on the first insulating layer exposed from the wiring electrode and the wiring electrode, a second insulating layer having a third hole communicating with the first hole is formed. Perform the layer formation process,
The light emission according to claim 6, wherein in the seventh step B, the first electrode is formed above the second insulating layer and is electrically connected to the first semiconductor layer through the first hole and the third hole. Device manufacturing method. In the step of forming a plurality of grooves in the semiconductor stacked body, the plurality of grooves are formed so that the plurality of light emitting cells are arranged in a matrix, and the plurality of light emitting cells arranged in a matrix Forming the groove so that an external region adjacent to and extending in at least one of a row direction and a column direction of the plurality of light emitting cells is disposed;
The method of manufacturing a light emitting device according to claim 7, wherein the wiring electrode is formed to extend on the external region and is electrically connected to a second electrode provided in the external region.   In the second B step of forming a plurality of grooves in the semiconductor stacked body, a groove reaching the first semiconductor layer from the upper surface side of the semiconductor stacked body is formed in the semiconductor stacked body in the region of the light emitting cell. The manufacturing method of the light-emitting device as described in any one of Claims 6-8.   The wet etching is performed so that a lower surface of the first semiconductor layer is positioned closer to the second semiconductor layer than the wiring electrode provided in the groove. The manufacturing method of the light-emitting device of description. Forming the semiconductor laminate on a substrate;
The method for manufacturing a light emitting device according to claim 1, wherein a substrate peeling step for peeling the substrate is performed after the step of forming the second electrode. The full-surface electrode forming step of forming a full-surface electrode layer electrically connected to the second semiconductor layer on the upper surface of the second semiconductor layer is performed before the step of forming a plurality of grooves in the semiconductor stacked body. Item 12. A method for manufacturing a light emitting device according to any one of Items 11 to 11. In a matrix, each of the semiconductor stacks includes a first semiconductor layer and a second semiconductor layer provided on the upper surface of the first semiconductor layer so that a part of the upper surface of the first semiconductor layer is exposed. A plurality of light emitting cells arranged;
A first hole provided above the front Symbol plurality of light emitting cells of the first semiconductor layer exposed from the second semiconductor layer in each, provided above said second semiconductor layer in each of the plurality of light emitting cells A first insulating layer provided continuously with the plurality of light emitting cells and exposed from the first semiconductor layer between the plurality of light emitting cells ,
A wiring electrode that has light reflectivity and is provided so as to cover the first insulating layer, and is electrically connected to the first semiconductor layer and the first hole in each of the plurality of light emitting cells;
A second electrode provided in each of the plurality of light emitting cells and electrically connected to the second semiconductor layer in the second hole;
Before Symbol lower surface of the first semiconductor layer, the light emitting device having an uneven shape. A second insulating layer provided on the wiring electrode and having a third hole communicating with the second hole in each of the light emitting cells;
The light emitting device according to claim 13, wherein the second electrode is provided above the second insulating layer and is electrically connected to the second semiconductor layer through the second hole and the third hole.   The light emitting device according to claim 13, wherein the wiring electrode has a connection electrode provided in contact with the first semiconductor layer in the first hole.   The wiring electrode is at least partially connected to a first electrode formed adjacent to the plurality of light emitting cells and extending in a row direction or a column direction with respect to the plurality of light emitting cells. The light emitting device according to claim 15. A full-surface electrode layer having light reflectivity is provided on the upper surface of the second semiconductor layer in each of the plurality of light emitting cells,
The light emitting device according to any one of claims 13 to 16, wherein the second electrode is electrically connected to the entire surface electrode layer through the second hole.   18. The light emitting device according to claim 13, wherein a part of the second electrode is provided so as to overlap with the wiring electrode in a top view of the light emitting cell. In a matrix, each of the semiconductor stacks includes a first semiconductor layer and a second semiconductor layer provided on the upper surface of the first semiconductor layer so that a part of the upper surface of the first semiconductor layer is exposed. A plurality of light emitting cells arranged;
A first hole provided above the front Symbol plurality of light emitting cells of the first semiconductor layer exposed from the second semiconductor layer in each, provided above said second semiconductor layer in each of the plurality of light emitting cells A first insulating layer that is provided continuously with the plurality of light emitting cells and is exposed from the first semiconductor layer between the plurality of light emitting cells ;
A first electrode provided in each of the plurality of light emitting cells and electrically connected to the first semiconductor layer in the first hole;
A wiring electrode that has light reflectivity and is provided so as to cover the first insulating layer and is electrically connected to the second semiconductor layer and the second hole in each of the plurality of light emitting cells;
Before Symbol lower surface of the first semiconductor layer, the light emitting device having an uneven shape. A second insulating layer provided on the wiring electrode and having a third hole communicating with the first hole in each of the light emitting cells;
The light emitting device according to claim 19, wherein the first electrode is provided on the second insulating layer and is electrically connected to the first semiconductor layer through the first hole and the third hole.   The wiring electrode is at least partially connected to a second electrode formed adjacent to the plurality of light emitting cells and extending in a row direction or a column direction with respect to the plurality of light emitting cells. Or the light-emitting device of Claim 20. A full-surface electrode layer having light reflectivity is provided on the upper surface of the second semiconductor layer in each of the plurality of light emitting cells,
The light emitting device according to claim 20 or 21, wherein the wiring electrode is electrically connected to the entire surface electrode layer through the second hole.   The light emitting device according to any one of claims 19 to 22, wherein a part of the first electrode is provided so as to overlap with the wiring electrode in a top view of the light emitting cell.   The light emitting device according to any one of claims 13 to 23, wherein a part of the wiring electrode provided between the adjacent light emitting cells is provided so as to protrude from the lower surface side of the first semiconductor layer to the lower surface side. . The first electrode is an n-electrode;
The second electrode is a p-electrode;
The first semiconductor layer is an n-side semiconductor layer;
The light emitting device according to claim 16 or 21, wherein the second semiconductor layer is a p-side semiconductor layer.   26. The light emitting device according to any one of claims 13 to 25, wherein a groove reaching the first semiconductor layer from an upper surface side of the semiconductor stacked body is provided in a region of the light emitting cell.

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