JP6590162B2 - Electric field communication transceiver - Google Patents

Description

  The present invention relates to an electric field communication transceiver that performs electric field communication by inducing an electric field in an electric field transmission medium.

  Conventionally, an electric field communication transceiver is carried, an electric field based on information to be transmitted is induced in an electric field transmission medium (for example, a living body such as a human body), and information transmission / reception is performed through the electric field transmission medium using the induced electric field. Various methods of transmitting and receiving information using an electric field communication transceiver have been proposed.

  With this type of electric field communication transceiver, it is necessary to reduce power consumption during standby, remove noise and waveform distortion due to the electric field transmission medium / environment, and transmit waveforms without distortion due to the influence of the electric field transmission medium during transmission (For example, Patent Document 1).

JP 2006-180096

  That is, in the conventional electric field communication transceiver, both the analog part and the digital part are operated at the time of reception, so that a large amount of power is consumed as a result of a long standby time even if the power is reduced.

  In electric field communication, phase modulation is often used, and demodulation is performed by a synchronous detection method. In the synchronous detection method, the received signal and the extracted carrier wave signal are digitally multiplied and demodulated, but a phase locked loop (PLL) is used to create the extracted carrier wave. However, in electric field communication with a lot of environmental noise, the phase-locked loop is not locked to an accurate carrier wave and the signal cannot be demodulated in many cases.

  Furthermore, in the amplifier circuit after signal modulation, a booster circuit using reactance is used to raise the voltage from about 3V battery voltage to about 20V used in electric field communication. It was high and distorted, causing a voltage drop due to the load, resulting in a decrease in signal recognition rate.

The object of the present invention is to reduce power consumption during standby, to remove electric field transmission media, environmental noise and waveform distortion during reception, and to efficiently amplify power during transmission and transmit a waveform without distortion. An object of the present invention is to provide a portable electric field communication transceiver using a synchronous detection method with a high rate.

In order to achieve the above object, a first feature of the electric field communication transceiver according to the present invention is that an electric field communication transceiver that demodulates a reception signal by a synchronous detection method receives a transmission side electric field communication signal via an electric field transmission medium. a reception signal detecting circuit for the carrier and modulation signals to determine other carrier and signal detect while intermittently operating the received signal, the reception signal demodulation circuit only when the received signal detection circuit detects the reception signal a power control circuit for supplying a clock, the work by the power control circuit, the reception signal demodulation circuit for demodulating the received signal, a transmission signal modulation circuit for modulating the data as a transmission signal, for amplifying said transmission signal And a voltage conversion circuit for supplying a voltage necessary for electric field communication to the transmission signal amplifier circuit.

  A second feature of the electric field communication transceiver according to the present invention is that the reception signal detection circuit in the first feature is an edge detection circuit that extracts an edge of a signal, and a signal within a certain time opened by a gate signal. A counter that counts the number of edges, an upper limit comparator, and a lower limit comparator, and when the carrier wave having the counted number of edges within the range of the upper limit comparator and the lower limit comparator is detected, the received signal It is to operate the demodulator by supplying a clock.

  Furthermore, a third feature of the electric field communication transceiver according to the present invention is that the reception signal detection circuit in the first or second feature detects a plurality of periods in which no signal wave is distorted, and an interval between the periods. And calculating and detecting the phase change point from the modulation time that is known in advance.

  Furthermore, a fourth feature of the electric field communication transceiver according to the present invention is that the received signal demodulating circuit according to any one of the first to third features comprises an analog / digital converter, an edge detection / clock extraction circuit, a phase A detection circuit and a plurality of register units, wherein the analog / digital converter converts the received signal into a digital signal, and the edge detection / clock extraction circuit converts a peak of positive and negative signals of the received signal into a digital signal Is obtained from the difference from the received signal one clock before, and a received clock synchronized with the received signal is generated, and the received clock is operated by an integer, and the phase detection circuit is free-running by the received clock multiplied by the integer. Determining a phase value based on the counter and a value sampled by the reception clock; and The phase value determined by the phase detection circuit is input to each of the reception clocks, and a point at which the phase has changed in any of the register units is obtained as a phase change point. And demodulating the digital signal for each number of symbols of the generated carrier wave.

  Further, a fifth feature of the electric field communication transceiver according to the present invention is that the transmission signal amplifier circuit in any one of the first to fourth features is configured as a class E amplifier circuit having a bridge structure. is there.

Further, a sixth feature of the electric field communication transceiver according to the present invention is that the transmission signal amplifier circuit according to the fifth feature includes upper transistors T1 and T3 and lower transistors T2 and T4 . control signal D to be inputted to the transistor T1, the control signal E input to the lower transistor T2, the upper flow in the transistors T1 and the lower transistor T2 current is driven so as not to flow, the upper The control signal F input to the transistor T3 and the control signal G input to the lower transistor T4 are driven such that no through current flows through the upper transistor T3 and the lower transistor T4. In that.

  A seventh feature of the electric field communication transceiver according to the present invention is that the transmission signal amplification circuit in the fifth feature is configured such that the output voltage of the transmission signal amplification circuit in the fifth or sixth feature It is to be amplified from 1.5 times to 2 times.

  Furthermore, an eighth feature of the electric field communication transceiver according to the present invention is that the voltage conversion circuit according to any one of the first to seventh features includes a charge pump circuit capable of changing a frequency, and changes an input frequency. The output voltage can be varied to enable driving adapted to the load.

  Furthermore, a ninth feature of the electric field communication transceiver according to the present invention is that the voltage conversion circuit in the eighth feature supplies positive or negative or two kinds of voltages to the transmission signal amplification circuit. .

  Further, a tenth feature of the electric field communication transceiver according to the present invention is that two charge pump circuits of the voltage conversion circuit in the eighth or ninth feature are formed, and the output voltage of one circuit is made positive and the other The output voltage of the circuit is made negative or the output voltages of both circuits are added.

  According to the present invention, the reception signal detection circuit can detect a signal with a few tenths of the normal reception power, thereby saving power. In particular, when the intermittent operation is not performed or the carrier signal is not detected, the reception demodulation circuit does not operate. Therefore, the standby average power can be reduced, and the battery life can be extended. Further, since the circuit does not demodulate the signal, it can be configured with a simple logic circuit.

  Furthermore, according to the present invention, even if the signal waveform is distorted due to the influence of the low power consumption received signal demodulating circuit, the received signal demodulating circuit can calculate the phase change point, so that the signal can be demodulated. It becomes.

  Furthermore, according to the present invention, a signal close to a sine wave with little distortion can be obtained by making the transmission signal transmission circuit a bridge structure and performing class E amplification operation with the electrodes.

  In addition, by configuring the voltage supply circuit with a charge pump circuit, it is possible to control the voltage value (+ V, -V) of the send signal by changing the control frequency (F) that is input. An optimum output signal can be set according to the state.

  Furthermore, by configuring the voltage supply circuit as described above, for example, the supply voltage of 3 to 5 volts and 1 to 2 volts can be increased by about plus 10 volts and / or minus 10 volts. Further, the switch loss can be reduced by using a field effect transistor (FET) as the switch of the circuit. When the circuit is divided into two circuits, it is possible to supply positive and negative voltages or two kinds of voltages. For example, the output voltage of one circuit is set to 10 volts and the output voltage of the other circuit is set to minus 10 volts. You can also.

2 shows an example of a circuit configuration of an electric field communication transceiver according to the present embodiment. This shows the state of the frequency when a signal is detected by the received signal detection circuit. It is the figure which showed an example of the circuit structure for detecting a signal in a received signal detection circuit. The state of detection of a phase change point in the reception demodulation circuit is shown. 2 shows an example of a circuit configuration of a reception demodulation circuit. It is a figure explaining the clock preparation method in the edge detection and clock extraction circuit of a reception demodulation circuit. It is a figure explaining the determination method of the phase value in a phase detection circuit. An example of a method for obtaining a phase change point based on a phase value input to a register is shown. An example of a method for obtaining a phase change point based on a phase value input to a register is shown. An example of a configuration example of a transmission signal amplifier circuit connected to a voltage conversion circuit is shown. An example of a circuit configuration example of a voltage conversion circuit is shown.

  Hereinafter, the best mode of the present invention will be described in detail for each example with reference to the drawings.

  FIG. 1 is a diagram mainly showing an example of a circuit configuration of an electric field communication transceiver according to the present invention. Among these, 1 and 1 'are electric field communication transceivers, and 2 is an electric field transmission medium which is a living body such as a human. Each electric field communication transceiver 1, 1 ′ transmits and receives each other, and a portion indicated by a chain line shows an example of a circuit configuration inside the electric field communication transceiver 1. The electric field communication transceivers 1, 1 ′ induce an electric field in the electric field communication medium 2 via the electrodes 66, 67 and transmit an electric field communication signal. One of the electrodes 66 and 67 is a transmission electrode and the other is a reception electrode. However, for example, as shown in FIG. 1, the transmission electrode and the reception electrode may be integrated into a transmission / reception electrode. The electrodes 66 and 67 may be included in the electric field communication transceiver 1 or may be externally attached.

  In FIG. 1, reference numerals 10 to 70 denote circuits of the electric field communication transceiver 1, of which 40 is a transmission / reception switching circuit, 10 is a reception signal detection circuit, 20 is a power control circuit, 30 is a reception signal demodulation circuit, and 50 is a transmission signal modulation. A circuit, 60 is a voltage conversion circuit, and 70 is a transmission signal amplification circuit.

  The transmission / reception switching circuit 40 receives a transmission-side electric field communication signal from the electric field communication transceiver 1 ′, and when the electric field communication transceiver 1 receives the signal detected by the reception electrode via the electric field transmission medium 2, the reception signal detection circuit 10. And the transmission signal received from the reception signal amplification circuit 60 is output to the transmission electrode. The transmission signal output from the transmission electrode is transmitted to the electric field communication transceiver 1 ′ via the electric field transmission medium 2, and the device (not shown) connected to the electric field communication transceiver 1 ′ is operated.

  The reception signal detection circuit 10 in the electric field communication transceiver 1 is a circuit that detects a signal received from the transmission / reception switching circuit 40, and when noise is input (noise input period A) as shown in FIG. The detection frequency is indefinite. When a normal signal is input (carrier cycle D), the frequency becomes constant (signal input period B), and a carrier (carrier wave) signal is input and detected. For signal detection, the detection rate can be set by specifying the number of edges and time.

  When the carrier signal is detected, the power control circuit 20 operates to supply a clock to the reception signal demodulation circuit 30, and the reception signal demodulation circuit 30 receives the carrier signal. The reception signal detection circuit 10 is created by a low power consumption CMOS circuit or the like, and reduces the standby average power by performing an intermittent operation. When the carrier signal is not detected, the power control circuit 20 does not operate, and the received signal demodulation circuit 30 also does not operate. As a result, power saving can be achieved, and the battery life can be extended.

  FIG. 3 shows an example of the configuration of the received signal detection circuit 10. When the reception signal is input, the edge detection circuit 11 extracts the rising edge or falling edge of the signal. The reference time gate signal 13 is composed of a low-power circuit such as an RC time constant circuit, and operates to open a time gate for a certain time (about several carrier waves).

  The counter 12 counts the edges of the carrier wave input at the reference time when the gate opens, and supplies the clock to the reception signal demodulation circuit 30 through the AND circuit 16 when the number of edges in the upper limit comparator 14 and the lower limit comparator 15 is detected. To do. Since the noise signal and unnecessary input from the environment are out of the range of the comparators 14 and 15, the received signal demodulation circuit does not operate.

  The example of FIG. 2 shows a specific example in which the upper limit of the counter for the edge K at the reference point O is set to 5 and the lower limit is set to 2, and in the carrier (carrier wave) period C, the counter for the edge K is 6, In the (carrier wave) period D, the counter of the edge K is 4. For this reason, only the carrier signal having the carrier period D that satisfies the condition of the upper and lower limit counters is detected.

  4 to 9 show a configuration example and operation of the reception signal demodulation circuit 30. FIG. The received signal demodulation circuit 30 has a function of observing a time series of signals to extract signal components in order to remove distortion included in the signals.

  Due to the influence of the electric field transmission medium 2 and the influence of the low power consumption received signal detection circuit 10, the signal waveform is distorted with respect to the ideal AMP output D (distortion period G) in the actual amplifier output E as shown in FIG. The signal change point H cannot be detected correctly due to the distortion, and an error occurs in demodulation. Therefore, a period during which the signal is stable (non-distortion period F) is detected, and the signal change point H is calculated from the interval between the period F and the next period F based on the modulation time known in advance.

  FIG. 5 shows a configuration example of the reception signal demodulation circuit 30. In the figure, reference numeral 31 denotes a reception amplifier, which amplifies the reception signal to a level at which analog / digital conversion is possible. An analog / digital converter 32 converts the digital signal into at least 2 bits. The conversion clock is operated by a clock that is an integral multiple of the carrier wave. In the example of this embodiment, 6 times as many clocks are used (see FIG. 7).

  The edge detection / clock extraction circuit 33 obtains a falling or rising portion of the digitally converted data from the difference from the data one clock before, and creates a reception clock synchronized with it. As shown in FIG. 6, the difference is taken for each clock of the data of the analog / digital converter 32, and the peak value of the signal is obtained from the resulting change in the positive / negative signal and used as the clock. In the example shown in the figure, the difference between the clock data d1 of the delay register 35a and the clock data d2 of the delay register 35b is obtained, and a positive or negative peak is detected. Since the difference is taken, the offset of the amplifier and the change in the signal bias are canceled out.

  The phase detection circuit 34 determines the phase by sampling with the clock generated by the edge detection / clock extraction circuit 33 using the counter that is self-running with the 6 times clock. In the example of FIG. 7, the counter 34a rotates clockwise with the phase value. In the case of BPSK (180 ° phase) modulation, as shown in FIG. 7, for example, 3 when the phase value is 0, 4 when the phase value is 1, and 5 when the phase value is 2. The phase change point is a counter value. In the example of FIG. 7, the phase counter value I indicates 1 at the peak of the actual amplifier output, and indicates 4 that is a value opposite to 1 after the phase change.

  The phase value is input to each delay register unit 35 for each clock, and as shown in FIGS. 8 and 9, the phase change point is an arrow where the phase value cannot be measured first, and the phase value after the change is the previous value. Are opposite numerical values (3 in the example of FIG. 8 and in the vicinity of 3 and 4 in the example of FIG. 9). In the example of FIG. 9, the phase value of R1 of the delay register unit 35 is 0, the phase value of R2 is 1, and the phase value of R3 is 0. It shows that it is coming.

Since the phase change point is generated for each number of symbols of a carrier (e.g., 8 or 16), 8 occur every clock is set to, for example 1, it occurs every 16 clock so as to set, for example 0 Demodulate.

  When the ID data is stored in the ID data response unit 4 and a signal is received from the reception signal demodulation circuit, the ID data response unit 4 sends the ID data to the transmission signal modulation circuit 50. The ID data response unit 4 may be in any form, such as a terminal such as a wearable computer or an ID card incorporating an IC chip.

  The transmission signal modulation circuit 50 modulates the signal received from the ID data response unit 4 and passes it to the transmission signal amplification circuit 60.

  The transmission signal amplifier circuit 60 is an amplifier amplifier having a bridge structure that creates a signal without distortion in electric field communication. As shown in FIG. 10, the circuit drives an electrode using a bridge circuit 61 having upper transistors T1 and T3 and lower transistors T2 and T4, and class E between the electrodes 66 and 67. In order to perform the (amplification) operation, even if the control signals D, G, E, and F are driven with a rectangular wave, a signal close to a sine wave with little distortion can be obtained.

  The control signals D, E, F, and G in FIG. 10 are driven so that no through current flows between the upper stage transistor and the lower stage transistor (for example, T1 and T2, T3 and T4). Further, for example, a PMOS element may be used for the upper transistors T1 and T3, and an NMOS element may be used for the lower transistors T2 and T4 so as to minimize the switching loss. The output voltage at both ends of the electrode has a waveform from + V to −V, and is 1.5 times (1.5 × V) to 2 times (2 × V). Reference numerals 62 to 65 denote amplifiers, 66 denotes the electrode 1, and 67 denotes the electrode 2, respectively.

  The voltage conversion circuit 70 varies the output frequency by changing the input frequency, and enables driving suitable for the load. The transmission signal amplification circuit 60 has positive / negative or plural types (two types) of voltages. And can only operate during transmission. In this embodiment, it is constituted by a charge pump that can change the input frequency, and by changing the control frequency F, the voltage value (+ V, −V) of the transmission signal can be controlled, and the optimum output depending on the state of the environment. The signal can be set.

  FIG. 11 shows an example of a voltage conversion circuit 70 configured as a charge pump circuit, and shows an example in which 10V is output from VOUT from 3.3V and 1.8V supplied to the electric field communication transceiver 1. The switch here is preferably composed of a low-loss FET. In the initial state, all switches are OFF. The operation of the switch is shown below.

(1) First, S1a, S1b, and S1c are turned ON, and C1 and C2 are charged with 3.3V and 1.8V.
(2) Next, S1a, S1b and S1c are turned off, S1d, S1e and S1f are turned on, and C3 is charged with 3.3V + 1.8V = 5.1V.
(3) When C3 is sufficiently charged, S1d, S1e, and S1f are turned off, S2a and S3b are turned on, and C4 is charged to 5V.
(4) When C4 is sufficiently charged, S2a and S3b are turned off, S2b and S3a are turned on, and Cout is charged to 10V. When the battery is sufficiently charged, S2b and S3a are turned off and the process from (1) is performed. However, the processes from (1) to (2) and (3) to (4) can be performed at the same time, and CK1 (S1a, S1b, S1c and S1d, S1e, S1f) and CK2 (S2a, S3b and S2b, S3a) operate at two types of clock timing.
(5) Two circuits can be created, one can be + 10V and the other can be −10V. Also, in order to reduce the number of elements, + 10V can be inverted by one circuit to create −10V.
(6) The voltage and current applied to the load can be changed by controlling the clocks CK1 and CK2, and the transmission power of the transmission signal amplifier circuit 60 can be controlled.

  Although the embodiments of the present invention have been described in detail with reference to the drawings, the present invention is not limited to the embodiments and can be implemented in various modes within the scope of the configurations described in the claims.

DESCRIPTION OF SYMBOLS 1, 1 'Electric field communication transceiver 2 Electric field transmission medium 4 ID data response part 10 Reception signal detection circuit 20 Power control circuit 30 Reception signal demodulation circuit 40 Transmission / reception switching circuit 50 Transmission signal modulation circuit 60 Transmission signal amplification circuit 70 Voltage conversion circuit

Claims (9)

In the electric field communication transceiver that demodulates the received signal by the synchronous detection method,
A reception signal detection circuit that detects a carrier wave and a modulation signal of a reception signal received via an electric field transmission medium from a transmission-side electric field communication signal from other carrier waves and signals while detecting the reception signal intermittently;
A power control circuit for supplying a clock to the reception signal demodulation circuit only when the received signal detection circuit detects the reception signal,
And the reception signal demodulation circuit operates, for demodulating the received signal by the power control circuit,
A transmission signal modulation circuit that modulates data as a transmission signal;
A transmission signal amplifier circuit for amplifying the transmission signal;
A voltage conversion circuit for supplying a voltage necessary for electric field communication to the transmission signal amplification circuit,
The received signal demodulation circuit detects a plurality of periods without distortion of the signal wave, calculates and detects a phase change point from the interval of each period and a previously known modulation time, and demodulates.
Electric field communication transceiver characterized by. In the electric field communication transceiver that demodulates the received signal by the synchronous detection method,
A reception signal detection circuit that detects a carrier wave and a modulation signal of a reception signal received via an electric field transmission medium from a transmission-side electric field communication signal from other carrier waves and signals while detecting the reception signal intermittently;
A power control circuit for supplying a clock to the reception signal demodulation circuit only when the received signal detection circuit detects the reception signal,
And the reception signal demodulation circuit operates, for demodulating the received signal by the power control circuit,
A transmission signal modulation circuit that modulates data as a transmission signal;
A transmission signal amplifier circuit for amplifying the transmission signal;
A voltage conversion circuit for supplying a voltage necessary for electric field communication to the transmission signal amplification circuit,
The reception signal demodulation circuit includes an analog / digital converter, an edge detection / clock extraction circuit, a phase detection circuit, and a plurality of register units,
The analog / digital converter converts the received signal into a digital signal;
The edge detection / clock extraction circuit calculates a positive / negative signal peak of the received signal converted into a digital signal based on a difference from the received signal one clock before, creates a received clock synchronized with the received signal, and generates the received clock To operate at an integer multiple,
The phase detection circuit determines a phase value based on a counter self-running with the integer multiple of the reception clock and a value sampled with the reception clock;
A phase value determined by the phase detection circuit is input to each of the plurality of register units for each reception clock, and a phase change point is obtained as a phase change point at any of the register units. Demodulating the digital signal for each number of carrier symbols generated by
Electric field communication transceiver characterized by. The received signal detection circuit includes an edge detection circuit that extracts an edge of a signal, a counter that counts the number of signal edges within a certain time opened by a gate signal, an upper limit comparator, and a lower limit comparator. When detecting a carrier wave having the counted number of edges within a range of a value comparator and a lower limit comparator, supplying a clock to the reception signal demodulating circuit to operate it;
The electric field communication transceiver according to claim 1 or 2 . The transmission signal amplifier circuit is configured as a bridge class E amplifier circuit;
The electric field communication transceiver according to any one of claims 1 to 3 . The transmission signal amplifier circuit includes upper transistors T1 and T3 and lower transistors T2 and T4. The control signal D input to the upper transistor T1 and the control signal E input to the lower transistor T2. Is driven so that no through current flows through the upper transistor T1 and the lower transistor T2, and the control signal F input to the upper transistor T3 and the control signal G input to the lower transistor T4. Is configured to be driven such that no through current flows through the upper transistor T3 and the lower transistor T4.
The electric field communication transceiver according to claim 4 . The output voltage of the transmission signal amplifier circuit is amplified 1.5 to 2 times at both ends of the electrode;
The electric field communication transceiver according to claim 4 or 5 . The voltage conversion circuit is composed of a charge pump circuit capable of changing the frequency, and changing the input frequency to vary the output voltage, enabling a drive adapted to the load,
The electric field communication transceiver according to any one of claims 1 to 6 . The voltage conversion circuit supplies positive or negative or two kinds of voltages to the transmission signal amplifier circuit;
The electric field communication transceiver according to claim 7 . The charge pump circuit of the voltage conversion circuit is formed in two circuits, the output voltage of one circuit is positive and the output voltage of the other circuit is negative, or the output voltages of both circuits are added,
The electric field communication transceiver according to claim 7 or 8 .

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