JP6582710B2 - Impulse transmitter - Google Patents

Description

  The embodiments referred to herein relate to impulse transmitters.

  In recent years, with the explosive increase of Internet users, or the increase in capacity and diversification of contents such as high-definition images, video and audio data, an increase in transmission capacity is also desired in wireless communication.

  As a large-capacity wireless communication system, for example, it is suitable to use a millimeter wave band in which there are few commercial wireless stations and a wide frequency band can be easily secured. In recent years, an impulse radio communication system using RF pulses as a transmission medium has attracted attention as an application to a broadband radio communication system.

  An impulse transmission wireless transmission device (impulse transmitter: impulse transmitter) obtains a high-frequency pulse signal from a low-frequency pulse signal by multiplication, so that the band-pass filter has a larger bandwidth compared to the conventional method and a local oscillator. And no need for a mixer.

  Therefore, the impulse transmitter can simplify the configuration of the radio unit and reduce the cost as compared with a narrow-band radio transmission apparatus using a carrier wave system. Further, for example, an impulse radio communication system (impulse radio communication system) is expected as a means for realizing large-capacity radio communication exceeding 10 gigabits per second (10 Gbps).

  In the impulse radio communication system, data is transmitted by performing ON / OFF modulation and envelope detection for transmitting millimeter wave pulses to data “1” and “0”. Here, the amount of data (transmission speed) that can be transmitted per second is determined by the pass frequency bandwidth of the bandpass filter.

  Furthermore, for example, using a millimeter wave band (30 GHz to 300 GHz) to which several wide frequency bandwidths such as several gigahertz (GHz) to several tens GHz are allocated for wireless communication, several tens of gigabits per second (Gbps) are used. It is suitable for realizing large-capacity communication with a simple system.

  By the way, conventionally, various proposals have been made as a wireless communication system and a communication apparatus using an impulse system.

JP 2006-229677 A JP 2009-239895 A JP 2000-323966 A JP 2008-288732 A JP2013-157660A JP 2004-208110 A

  As described above, for example, an impulse radio communication system that performs large-capacity communication using a millimeter wave band has been researched and developed. Further, in recent transmitters of impulse transmitters, for example, so-called bipolar RZ (return zero) that generates a pulse having a polarity opposite to the polarity of “1” immediately before is generated in order to avoid limiting transmission power due to the bright line spectrum. ) Type short pulse generators have appeared.

  However, a problem of the impulse radio communication system including the bipolar RZ type is that the number of transmission bits per frequency bandwidth to be used is small, that is, the frequency utilization efficiency is low.

  That is, in the impulse radio communication system, since ON / OFF modulation is performed, for example, when a frequency bandwidth of 10 GHz is used, only data transmission of about 10 Gbps can be performed.

  In addition, there is a need for a communication system with high frequency utilization efficiency when wireless communication systems are close to each other and mutual interference becomes a problem or when it is required to increase the transmission speed using the same frequency band. .

  By the way, in order to improve frequency use efficiency in an impulse radio communication system, one pulse (impulse) is arranged within one symbol period, and a position (phase) where a pulse is arranged (phase) according to transmission data is changed. ) Modulation is considered.

  However, for example, when phase modulation is performed using a millimeter wave band, particularly, a high frequency of 60 GHz or more, the position modulation delay time corresponding to the phase difference is, for example, several ps. This delay time of several ps is shorter than a delay time (for example, about 10 ps) by a general CMOS (Complementary Metal Oxide Semiconductor) buffer.

  That is, in the millimeter-wave band impulse radio communication system, it is difficult to use, for example, a low-cost CMOS buffer in order to improve the frequency utilization efficiency by performing phase modulation.

  In other words, for example, it is difficult to realize an impulse radio communication system capable of reducing cost and maintaining high communication quality by using a general CMOS technology while improving the utilization efficiency by performing phase modulation. ing.

According to one embodiment, an impulse transmitter for transmitting a multiplexed bipolar impulse signal with varying phases, a baseband signal generator, a trigger flip-flop with a position modulation function , a bandpass filter, An impulse transmitter is provided.

The baseband signal generator generates a data signal in a time slot unit of a communication clock, and the trigger flip-flop with a position modulation function generates a bipolar short pulse generated by inverting the polarity based on the data signal. Apply different delays and change phase. The bandpass filter receives the bipolar short pulse and passes only a predetermined frequency bandwidth to generate the bipolar impulse signal.

The trigger flip-flop with position modulation function is a master-slave type, and the slave latch unit includes a plurality of phase control paths, one of which is selected based on a selection signal from a selector, and the plurality of phase control paths Includes a plurality of delay circuits connected in cascade. Wherein the plurality of phase control path plurality of delay circuits are selectively controlled by two delay control signal even without low. The trigger flip-flop with a position modulation function uses a delay time difference between a first delay time of a first phase control path and a second delay time of a second phase control path, which is included in the plurality of phase control paths. The delay time difference is shorter than the first delay time and the second delay time.

  According to the disclosed impulse transmitter, the communication quality can be improved and the cost can be reduced.

FIG. 1 is a diagram for explaining an example of an impulse radio communication system. FIG. 2 is a diagram for explaining an impulse transmitter in the impulse radio communication system. FIG. 3 is a diagram (part 1) for describing a bipolar RZ type impulse transmitter. FIG. 4 is a diagram (part 2) for explaining a bipolar RZ type impulse transmitter. FIG. 5 is a diagram (part 3) for explaining the bipolar RZ type impulse transmitter. FIG. 6 is a diagram showing a short pulse generator in an example of an impulse transmitter as a related technique. FIG. 7 is a block diagram illustrating an example of an impulse receiver that receives a signal from the impulse transmitter illustrated in FIG. 6. FIG. 8 is a diagram showing a short pulse generator in another example of the impulse transmitter as the related art. FIG. 9 is a block diagram illustrating an example of an impulse receiver that receives a signal from the impulse transmitter illustrated in FIG. 8. FIG. 10 is a block diagram showing T-FF in one embodiment of the impulse transmitter. FIG. 11 is a block diagram illustrating an example of a delay control signal generation circuit used in the delay control unit of the T-FF illustrated in FIG. FIG. 12 is a diagram for explaining an example of the delay circuit.

  First, before describing this embodiment in detail, an example of an impulse radio communication system, an example of an impulse transmitter as a related technique, and problems thereof will be described with reference to FIGS.

  FIG. 1 is a diagram for explaining an example of an impulse radio communication system, FIG. 1 (a) is a block diagram showing an example of an impulse radio communication system, and FIG. 1 (b) is a diagram of a bandpass filter. It is a figure for demonstrating a pass frequency band.

  As shown in FIG. 1A, the impulse radio communication system (impulse radio communication system) includes an impulse transmitter Tx and an impulse receiver Rx. The impulse transmitter Tx includes a baseband signal generator 101, a short pulse generator 102, a bandpass filter 103, a transmission amplifier 104, and a transmission antenna 105.

  The baseband signal generator 101 generates a data signal for each time slot of the communication clock and outputs the data signal to the short pulse generator 102. Here, for example, the value of “1” is a high level “H”, and the value of “0” is a low level “L”.

  The communication clock is, for example, 5 GHz. In this case, the communication speed of the data signal is, for example, 5 gigabits / second (Gbps). For example, the short pulse generator 102 generates a short pulse when the data signal becomes high level in a time slot. The band pass filter 103 performs filtering that allows only a predetermined pass frequency band to pass through the short pulse, and outputs, for example, a millimeter wave pulse.

  In FIG. 1B, reference numeral 131 indicates a frequency characteristic (short pulse characteristic) of a short pulse, and 132 indicates a pass frequency band of the bandpass filter 103. As shown in FIG. 1B, the millimeter wave pulse output from the bandpass filter 103 has frequency components only in the pass frequency band 132 portion of the short pulse characteristic 131.

  By the way, for example, in UWB (Ultra Wide Band), the usable frequency band is limited, and the band pass filter 103 is used so as to satisfy the limitation of the frequency band. In the pass frequency band 132, for example, the pass lower limit frequency f1 is 80 GHz, the pass upper limit frequency f2 is 90 GHz, and the pass frequency bandwidth is f2-f1 = 90-80 = 10 GHz.

  FIG. 2 is a diagram for explaining an impulse transmitter in an impulse radio communication system. FIG. 2A shows a short pulse generator (unipolar RZ (return zero) type short pulse generator) 102 and a bandpass filter. The signal generated at 103 is shown.

  2B shows the filter characteristics (pass frequency band) of the bandpass filter 103, and FIG. 2C shows the emission line spectrum when the unipolar RZ short pulse generator 102 is used.

  Here, in FIG.2 (c), a horizontal axis shows a frequency (GHz) and a vertical axis | shaft shows electric power spectral density (dBm / Hz). FIG. 2C shows a case where fc is 83.5 GHz and Bw = 5 GHz (81 GHz to 86 GHz). 2A to 2C, fc indicates the center frequency in the pass frequency band of the bandpass filter 103, and Bw indicates, for example, the pass bandwidth where the power is reduced by 3 dB.

As shown in FIG. 2A, the short pulse generator (unipolar RZ type short pulse generator) 102 generates, for example, a positive pulse with a narrow width. This narrow pulse includes a wide range of frequency components including high frequency components, and, for example, a millimeter wave pulse is generated by passing through the band pass filter 103. That is, as shown in FIG. 2B, the millimeter wave pulse that has passed through the bandpass filter 103 becomes a vibration signal (pulse signal) having a width Bw ⁻¹ that vibrates at a frequency fc.

  Referring again to FIG. 1A, the output of the bandpass filter 103 is input to the transmission amplifier 104, for example, a millimeter wave pulse is amplified, and the transmission signal is wirelessly transmitted via the transmission antenna 105. . The transmission signal represents “1” or “0” data depending on the presence / absence (ON / OFF) of a millimeter wave pulse. At this time, as shown in FIG. 2C, the transmission signal (power spectral density) includes, for example, the bright line spectrum Sb.

  As shown in FIG. 1A, the impulse receiver Rx includes a reception antenna 121, a reception amplifier 122, a detector 123, a limit amplifier 124, and a baseband signal regenerator 125.

  The reception amplifier 122 amplifies the reception signal received wirelessly via the reception antenna 121 and outputs the amplified signal to the detector 123. The detector 123 detects the envelope of the reception signal (millimeter wave pulse) amplified by the reception amplifier 122 and outputs it to the limit amplifier 124.

  The limit amplifier 124 amplifies the signal detected by the detector 123 and outputs the amplified signal to the baseband signal regenerator 125. Then, the baseband signal regenerator 125 receives the signal amplified by the limit amplifier 124 and reproduces, for example, 5 Gbps received data.

  As described above, the impulse radio communication system can be used for ultra-wideband radio communication including, for example, a microwave band, a quasi-millimeter wave band, and UWB, as well as the millimeter wave band.

  Since this impulse radio communication system does not require an oscillator or a mixer and the configuration of the RF unit is simple and low in cost as compared with a radio communication system of a narrow band communication system, for example, in the millimeter wave band where a wide band can be used, 10 Gbps Realization of wideband wireless communication exceeding that is expected.

  Here, assuming that the frequency bandwidth allocated to the impulse radio communication system is Bmax, the maximum communication speed Bmax can be obtained when the pass frequency bandwidth Bbpf of the bandpass filter 103 is equal to Bmax.

  For example, when the frequency bandwidth Bmax is 10 GHz, as shown in FIG. 1B, the pass frequency bandwidth Bbpf of the bandpass filter 103 is f2-f1 = 90-80 = 10 GHz, and data signal communication The speed will be 10 Gbps.

  By the way, in many wireless communication systems, for example, the signal strength per unit frequency (power spectral density) is defined by laws and regulations such as a signal strength of 0 dBm per frequency of 1 dBm (= 1 mW / MHz). .

  Therefore, as shown in FIG. 2C, for example, the transmission signal (power spectral density) includes the bright line spectrum Sb. When the signal intensity of the bright line spectrum Sb is limited to the power spectral density, a situation occurs in which the average power in the entire frequency band cannot be increased.

  Specifically, for example, when the assigned frequency band Bmax is 10 GHz (= 10000 MHz) and the transmission spectrum intensity is constant within the frequency band, an output of 1 (mW / MHz) × 10000 (MHz) = 10 W is obtained. It becomes possible.

  However, if the transmission signal includes the bright line spectrum Sb of 1 mW / MHz, the bright line spectrum Sb is also limited by the signal intensity based on, for example, the Radio Law, so that only small power is allowed.

  In general, in order to transmit a signal over a long distance without error, it is preferable to secure a signal intensity margin (S / N ratio) against noise or the like by maximizing the spectrum power in all frequency bands. However, when the transmission power is limited by the bright line spectrum Sb, it becomes difficult to secure a sufficient S / N ratio.

  As described above, when the transmission power is limited by the bright line spectrum Sb, high-quality wireless communication is disadvantageous at a long distance. Therefore, it is required to realize an impulse radio communication system in which the bright line spectrum Sb does not occur. Therefore, a bipolar return zero (RZ) type impulse radio communication system that does not include the bright line spectrum Sb in the transmission signal and is suitable for long-distance high-quality radio communication has been proposed.

  3 to 5 are diagrams for explaining a bipolar RZ type impulse transmitter. Here, FIG. 3A is a block diagram showing an example of a short pulse generator 102 used in a bipolar RZ type impulse transmitter (B-RZ impulse transmitter). Shown with generation filter 506 and pulse (wideband) amplifier 507.

  The pulse generation filter 506 corresponds to the band pass filter 103, and the pulse amplifier 507 corresponds to the transmission amplifier 104. FIG. 3B shows a circuit diagram of an example of the trigger flip-flop (T-FF) 504 shown in FIG.

  4A shows a positive pulse generated by the short pulse generator 102 and a positive millimeter wave pulse (impulse signal) generated via the pulse generation filter 506 (bandpass filter 103). ) Example. Further, FIG. 4B shows an example of the negative polarity pulse generated by the short pulse generator 102 and the negative polarity millimeter wave pulse generated via the pulse generation filter 506.

  FIG. 5A is a time chart for explaining operations of the short pulse generator 102 and the pulse generation filter 506 shown in FIG. 3A, and FIG. 5B is a bipolar RZ short pulse. It is a figure which shows an emission line spectrum (notch) at the time of using the generator 102. FIG.

  In FIG. 5B, the horizontal axis indicates the frequency (GHz), and the vertical axis indicates the power spectrum density (dBm / Hz). FIG. 5B shows a case where fc is 83.5 GHz and Bw = 5 GHz (81 GHz to 86 GHz).

  As shown in FIG. 3A, the bipolar RZ short pulse generator 102 includes input buffers 501 and 502, NRZ (Non-Return to Zero) -RZ (Return to Zero). A conversion unit (NRZ-RZ conversion unit) 503, a trigger flip-flop (T-FF) 504, and an edge shaping (shaping) circuit 505 are included.

  The edge shaping circuit 505 includes, for example, an even number of inverters connected in series, and the output signal edge-shaped by the edge shaping circuit 505 is input to the pulse generation filter 506 (103).

  The data signal A is a non-return zero signal, the input buffer 501 buffers the non-return zero signal A, and the clock buffer 502 buffers the clock signal Clock.

  An NRZ (Non-Return to Zero) -RZ (Return to Zero) conversion unit 503 converts a non-return zero signal A into a return zero signal B. Specifically, the NRZ-RZ conversion unit 503 is, for example, a logical product (AND) circuit, takes a logical product of the non-return zero signal A and the clock signal CLK, and outputs the logical product signal as a return zero signal B. .

  The T-FF 504 is realized by, for example, a master-slave type flip-flop circuit using the return zero signal B as a transfer gate signal, as shown in FIG. That is, the T-FF 504 includes a master latch by inverters 602 and 603 whose inputs and outputs are cross-connected, a slave latch by inverters 605 and 606, and an inverter 607 provided in the feedback path of the output of the slave latch.

  The T-FF 504 further includes transfer gates 601 and 604 formed of transistors. The transfer gate 601 is provided in a path for feeding back the output of the slave latch to the master latch via the inverter 607, and the gate 604 is provided between the output of the master latch and the input of the slave latch.

  The conduction state of transfer gate 601 is controlled by a return zero signal B, and the conduction state of transfer gate 604 is controlled by an inverted signal / B of return zero signal B. As a result, the T-FF 504 functions as a frequency divider for the return zero signal B that inverts the output signal C every time the return zero signal B changes by one cycle.

  For example, every time the return zero signal B changes by one cycle such as “H” → “L” → “H”, the logic level of the output signal C is inverted. That is, as shown in FIG. 5A, the output signal C is logically inverted in synchronization with the rising edge of the return zero signal B.

  The edge shaping circuit 505 generates a signal in which the rising edge and the falling edge of the output signal C of the T-FF 504 are steep, and outputs the signal to the pulse generation filter 506. Here, the signal in which the output signal C is steep becomes a signal having a short rise time and fall time, and a signal including a spectrum up to a higher frequency.

  As described above, the edge shaping circuit 505 can be realized by, for example, an even number of inverters connected in series. Further, the edge shaping circuit 505 may be further provided with an inductor for giving peaking so that a steeper edge can be obtained.

  An inverter connects a p-channel MOS transistor and an n-channel MOS transistor in series between power supplies, applies an input signal to the gates of the two transistors, and obtains an inverted signal from a connection node between the pMOS transistor and the nMOS transistor It is realized with. The same applies to inverters used in other parts.

  The pulse generation filter 506 is a high-pass filter or a band-pass filter. The pulse generation filter 506 removes the low frequency component of the output signal of the edge shaping circuit 505 to determine whether or not there is a pulse corresponding to the value of the data signal A (value of data “1”). A signal D in which negative pulses are alternately generated is output. Here, as the pulse generation filter 506, for example, capacitor elements connected in series can be applied.

  The pulse amplifier 507 (104) is a wideband amplifier or a distributed amplifier, amplifies the output signal D of the pulse generation filter 506, and outputs the amplified signal to the transmission antenna 105 of FIG. Note that the edge shaping circuit 505 may be deleted when the edge of the signal C is sufficiently steep. Further, if the magnitude of the signal D is sufficient, the pulse amplifier 507 can be deleted.

  The bipolar short pulse output from the short pulse generator 102 to the bandpass filter 103 (pulse generation filter 506) is the presence or absence of a pulse corresponding to the value of the data signal, and alternately generates a positive pulse and a negative pulse. Pulse.

  In the bipolar short pulse, for example, a positive pulse or a negative pulse is generated when the value of the data signal is “1”, and becomes a reference voltage when the value of the data signal is “0”. The positive pulse is a pulse having a positive voltage with respect to the reference voltage, and the negative pulse is a pulse having a negative voltage with respect to the reference voltage. That is, the bipolar short pulse becomes a pulse having a polarity opposite to that of the immediately preceding pulse.

  Here, as is clear from the comparison between FIG. 5B and FIG. 2C described above, the emission line spectrum Sb when the unipolar RZ short pulse in FIG. 2C is used is shown in FIG. As described above, the notch Sn is obtained by using a bipolar RZ short pulse. As a result, the signal intensity of the bright line spectrum Sb is not restricted by the power spectral density (transmission signal), and the average power in all frequency bands can be increased.

  As described above, when the bipolar short pulse is used, a notch (recess) is generated at a frequency equal to an integral multiple of the communication speed (10 Gbps), and the power spectral density is reduced. Therefore, the maximum value of the signal strength per unit frequency can be reduced as compared with the case where unipolar short pulses are used, and transmission power can be easily secured, which is advantageous for long-distance / high-quality communication.

  By the way, the impulse radio communication system including the unipolar RZ system and the bipolar RZ system has a problem that the number of transmission bits per frequency bandwidth to be used is small, that is, the frequency utilization efficiency is low.

  That is, in the impulse radio communication, since ON / OFF modulation is performed, when a frequency bandwidth of 10 GHz is used, only data transmission of 10 Gbps can be performed. In addition, for example, when wireless communication systems are close to each other and mutual interference becomes a problem, and there is a demand to increase the transmission speed using the same frequency band, a communication system with high frequency utilization efficiency is required.

  For example, in order to improve the frequency utilization efficiency of a wireless communication device, it is considered that a method of putting information of a plurality of bits on one symbol, so-called multi-leveling, is effective. Therefore, in the case of pulse transmission, pulse position modulation (PPM) that transmits information by changing the appearance position of a pulse has been researched and developed.

  That is, when performing pulse position modulation in an impulse radio communication system, for example, one pulse (impulse) may be arranged within one period, and the position (phase) where the pulse is arranged may be changed according to transmission data. .

  FIG. 6 is a diagram showing a short pulse generator in an example of an impulse transmitter as a related technique, in which the phase in which pulses are arranged in one period is changed (−π, −π / 2, reference (0), + π / 2, + π) is an example of transmitting 2-bit data (an example of multiplicity of “2”). For example, it is preferable that a quarter period (for example, 3 ps) in one period (for example, 12 ps) corresponds to a phase (arrangement) of π / 2.

  FIG. 6A is a block diagram showing an example of the short pulse generator 102 used in the B-RZ impulse transmitter. The short pulse generator 102 is connected to the pulse generation filter 506 (103) and the pulse ( Shown with a wideband amplifier 507 (104). FIG. 6B shows a circuit diagram of an example of the T-FF (trigger flip-flop with position modulation function) 504 shown in FIG.

  As apparent from the comparison between FIG. 6A and FIG. 3A described above, the short pulse generator 102 in the related art example includes a selector 701, a clock buffer 502, a T-FF 702, and an edge shaping ( And a shaping) circuit 505.

  The clock buffer 502, the edge shaping circuit 505, the pulse generation filter 506, and the pulse amplifier 507 are the same as those described with reference to FIG.

  The selector 701 generates five selection signals p, q, r, s, and t based on the 2-bit data pattern of the serial transmission data Data and the divide-by-2 signal M of the communication clock Clock.

  That is, when the multiplicity is “2”, five phase control paths (signal paths) SLp˜ are used to generate signals having phases of −π, −π / 2, reference (0), + π / 2, + π. SLt is provided, and one of them can be selected by five selection signals p, q, r, s, and t. As the frequency-divided signal M, for example, a signal generated as the output of the inverter 712 of the T-FF 702 shown in FIG. 6B can be used.

  The T-FF 702 has a circuit configuration as shown in FIG. 6B, for example, and outputs a divided signal obtained by dividing the communication clock clock by two. The changing edge of the frequency-divided signal changes in phase by π / 2 (for example, 3 ps) according to the selection signals p, q, r, s, and t.

  The T-FF 702 has a master latch by inverters 712 and 713 whose inputs and outputs are cross-connected, a slave latch including inverters 715 and 716, and an inverter 717 provided in a feedback path of the output of the slave latch.

  The T-FF 702 further includes transfer gates 711 and 714. The transfer gate 711 is provided in a path for feeding back the output of the slave latch to the master latch via the inverter 717, and the transfer gate 714 is provided between the output of the master latch and the input of the slave latch.

  The transfer gate 711 is controlled to be conductive by the clock signal Clock, and the transfer gate 714 is controlled by the inverted signal / Clock of the clock signal Clock.

  The T-FF 702 further includes a variable delay unit 720 connected between the output of the inverter 715 and the input of the inverter 716 (the output node of the T-FF 702 with a position modulation function) in the slave latch.

  The variable delay unit 720 includes first to fifth phase control paths SLp to SLt connected in parallel between the output of the inverter 715 and the input of the inverter 716. Here, the first phase control path SLp has only the transfer gate 721, and the selection signal p is input to the gate of the transfer gate 921.

  Second phase control path SLq has transfer gates 722 and 724 and buffer 723 connected in series, and selection signal q is input to the gates of transfer gates 722 and 724. The third phase control path SLr includes transfer gates 725 and 727 connected in series and a buffer row 726 connecting two buffers, and a selection signal q is input to the gates of the transfer gates 725 and 727. The

  The fourth phase control path SLs includes transfer gates 728 and 730 connected in series, and a buffer row 729 in which three buffers are connected. The selection signal s is input to the gates of the transfer gates 728 and 730. .

  The fifth phase control path SLt includes transfer gates 731 and 733 connected in series and a buffer row 732 in which four buffers are connected. The selection signal t is input to the gates of the transfer gates 731 and 733. . Here, the buffer 723 and the buffer rows 726, 729, and 732 have different numbers of connected buffers, and the delay amount is increased based on the number of buffers.

  Thereby, for example, when the output of the third phase control path SLr is set to the reference (0), the phase at the output of the first phase control path SLp is set to −π, and the phase at the output of the second phase control path SLq is set to It can be set to −π / 2.

  Further, for example, when the output of the third phase control path SLr is set to the reference (0), the phase at the output of the fourth phase control path SLs is set to + π / 2, and the phase at the output of the fifth phase control path SLt is set to It can be set to + π.

  Thus, in the impulse transmitter in the example of the related art shown in FIG. 6, for example, the variable delay unit 720 in the T-FF 702 with a position modulation function has the first to fifth phase control paths SLp to SLt.

  FIG. 7 is a block diagram illustrating an example of an impulse receiver that receives a signal from the impulse transmitter illustrated in FIG. 6. An impulse receiver that receives a bipolar impulse signal that is multiplexed by changing a phase and that is output from an impulse transmitter in an example of the related art described with reference to FIG. 6 has, for example, the configuration shown in FIG. .

  As shown in FIG. 7, the impulse receiver includes a reception antenna 121, a reception amplifier 122, a detector 123, a limit amplifier 124, and a baseband signal regenerator 125.

  The detector 123 includes a unipolar short pulse generator 801, a band pass filter 802, a first mixer (mixer) 803A, a second mixer (mixer) 803B, and a π / 2 phase shifter 804. The unipolar short pulse generator 801 generates a short pulse every half cycle of the frequency signal (divided by 2 signal) obtained by dividing the communication clock Clock by the multiplicity (here, “2”).

  That is, the unipolar short pulse generator 801 generates a short pulse of a local oscillation signal having a center frequency (for example, 83.5 GHz) of the pass band of the bandpass filter 103 of the impulse transmitter, for example.

  The bandpass filter 802 has the same pass characteristics as the bandpass filter 103 of the transmitter, receives the output signal of the bipolar short pulse generator 805, is an oscillation signal having the same frequency as the vibration signal, and has a short envelope. A pulse signal corresponding to the pulse signal is generated.

  The first mixer 803A performs detection by mixing the output signal of the reception amplifier 122 with the pulse signal output from the bandpass filter 802. The second mixer 803B shifts the phase of the pulse signal output from the bandpass filter 802 by π / 2 by the π / 2 phase shifter 804 to the output signal of the reception amplifier 122, and mixes the phase-shifted signal. And detect. This provides an intermediate frequency (IF) signal.

  The limit amplifier 124 includes a first amplifier 124A that amplifies the output of the first mixer 803A, and a second amplifier 124B that amplifies the output of the second mixer 803B. Here, the local oscillation signals mixed by the first mixer 803A and the second mixer 803B are out of phase by π / 2 (for example, 3 ps), and the IF signal (Q signal) is output from the first amplifier 124A. An IF signal (I signal) is output from the second amplifier 124B.

  The baseband signal regenerator 125 includes an analog-to-digital converter (ADC) 851, a phase detector 852, and a data regenerator 853. The ADC 851 converts the IF signal (Q) and the IF signal (I) into digital data.

  The phase detector 852 detects the phase of the received impulse signal from the digital data of the IF signal (Q) and the IF signal (I). The data reproducing unit 853 reproduces data from the detected phase and the received clock phase.

  FIG. 8 is a diagram showing a short pulse generator in another example of an impulse transmitter as a related technique. The phase at which pulses are arranged in one period is changed (−π / 2, reference (0), + π / 2, + π), and an example of transmitting 2-bit data (an example where the multiplicity is “2”) is shown. For example, it is preferable that a quarter period (for example, 3 ps) in one period (for example, 12 ps) corresponds to a phase (arrangement) of π / 2.

  Here, FIG. 8A is a block diagram showing an example of the short pulse generator 102 used in the B-RZ impulse transmitter. The short pulse generator 102 includes a pulse generation filter 506 (103) and a pulse amplifier. 507 (transmission amplifier 104). FIG. 8B shows a circuit diagram of an example of the T-FF (trigger flip-flop with position modulation function) 504 shown in FIG.

  As shown in FIG. 8A, the short pulse generator 102 in another example of the related art includes a selector 901, a clock buffer 502, a T-FF 902, and an edge shaping (shaping) circuit 505. .

  Here, the edge shaping circuit 505 includes, for example, an even number of inverters connected in series, and the output signal edge-formed by the edge shaping circuit 505 is input to the pulse generation filter 506 (103). The clock buffer 502, the pulse generation filter 506, and the pulse (broadband) amplifier 507 are the same as those described with reference to FIG. 3, for example, and description thereof is omitted.

  The selector 901 generates four selection signals e, f, g, and h in accordance with the 2-bit data pattern of the serial transmission data Data. Here, one of the four selection signals e, f, g, and h is selectively turned on (high level “H”), and the remaining three are turned off (low level “L”).

  Note that, as is clear from the comparison between FIG. 8A and FIG. 6A described above, the selector 901 in another example of the related art does not use the divide-by-2 signal M of the communication clock Clock. Selection signals e, f, g, and h are generated from the transmission data Data.

  The T-FF 902 has a circuit configuration as shown in FIG. 8B, for example, and outputs a frequency-divided signal obtained by dividing the communication clock clock by two (C). The change edge of the frequency-divided signal changes in phase by π / 2 (for example, 3 ps) according to the selection signals e, f, g, and h.

  The T-FF 902 includes a master latch by inverters 912 and 913 whose inputs and outputs are cross-connected, a slave latch by inverters 915 and 916, and an inverter 917 provided in an output feedback path of the slave latch.

  The T-FF 902 further includes transfer gates 911 and 914. The transfer gate 911 is inserted in a path for feeding back the output of the slave latch to the master latch via the inverter 917. The transfer gate 914 is inserted between the output of the master latch and the input of the slave latch.

  Here, the conduction state of the transfer gate 911 is controlled by the clock signal Clock, and the conduction state of the transfer gate 914 is controlled by the inverted signal / Clock of the clock signal Clock.

  The T-FF 902 further includes a variable delay unit 920 provided between the output of the inverter 915 and the input of the inverter 916 (the output node of the T-FF 902 with position modulation function) in the slave latch.

  Variable delay section 920 has first to fourth phase control paths SLe to SLh connected in parallel between the output of inverter 915 and the input of inverter 916. The first phase control path SLe has only the transfer gate 921, and the selection signal e is input to the gate of the transfer gate 921.

  The second phase control path SLf has a transfer gate 922 and a buffer 923 connected in series, and the selection signal f is input to the gate of the transfer gate 922. The third phase control path SLg has a transfer gate 924 connected in series and a buffer row 925 in which two buffers are connected. The selection signal g is input to the gate of the transfer gate 924.

  The fourth phase control path SLg includes a transfer gate 926 connected in series and a buffer row 927 in which three buffers are connected. The selection signal h is input to the gate of the transfer gate 926. Here, the number of buffers connected to the buffers 923 and 925 and 927 is different, and the delay amount is increased based on the number of buffers.

  Thereby, for example, when the output of the second phase control path SLf is set to the reference (0), the output phase of the first phase control path SLe is −π / 2, and the output phase of the third phase control path SLg is + π / 2. The output phase of the fourth phase control path SLh can be set to + π.

  Here, for example, when the center frequency of the pass frequency band of the pulse generation filter 506 (bandpass filter 103) is fc and the period T is T = 1 / fc, the phase difference “π / 2 ”(difference in delay time) is set to T / 4 (for example, about 3 ps).

  For example, when the output of the second phase control path SLf is used as a reference, the output of the first phase control path SLe is set to −3 ps (−T / 4: −π / 2), and the output of the third phase control path SLg The output is set to +3 ps (+ T / 4: + π / 2).

  In the variable delay unit 920, the output of the first phase control path SLe is selected for the selection signal e of the selector 901, and the output of the second phase control path SLf is selected for f. Further, the output of the third phase control path SLg is selected for the selection signal g, and the output of the fourth phase control path SLg is selected for h.

  FIG. 9 is a block diagram illustrating an example of an impulse receiver that receives a signal from the impulse transmitter illustrated in FIG. 8, and performs multiplexing by changing the phase output from the impulse transmitter according to another example of the related art. 1 shows an example of a receiver that receives a normalized bipolar impulse signal.

  Here, as described with reference to FIG. 1, the impulse receiver includes a reception antenna 121, a reception amplifier 122, a detector 123, a limit amplifier 124, and a baseband signal regenerator 125. The reception amplifier 122 is realized by, for example, a low noise amplifier.

  The detector 123 includes a bipolar short pulse generator 805, a bandpass filter 802, a first mixer 803A, a second mixer 803B, and a π / 2 phase shifter 804. The bipolar short pulse generator 805 generates a short pulse whose polarity changes every half cycle of the frequency signal (divided by 2 signal) obtained by dividing the communication clock Clock by the multiplicity (here, “2”).

  That is, the bipolar short pulse generator 805 is, for example, a local oscillation signal having a center frequency (for example, 83.5 GHz) in the pass band of the bandpass filter 103 of the impulse transmitter, and a bipolar having a positive polarity and a negative polarity alternately changing. Generate short pulses.

  As described above, the impulse receiver shown in FIG. 9 uses the bipolar short pulse generator 805 instead of the unipolar short pulse generator 801 in the detector 123 as the impulse receiver described with reference to FIG. The point is different.

  The bandpass filter 802 has the same pass characteristics as the bandpass filter 103 of the transmitter, receives the output signal of the bipolar short pulse generator 805, is an oscillation signal having the same frequency as the vibration signal, and has a short envelope. A pulse signal corresponding to the pulse signal is generated.

  The first mixer 803A performs detection by mixing the output signal of the reception amplifier 122 with the pulse signal output from the bandpass filter 802. The second mixer 803B shifts the phase of the pulse signal output from the bandpass filter 802 by π / 2 by the π / 2 phase shifter 804 to the output signal of the reception amplifier 122, and mixes the phase-shifted signal. And detect. This provides an intermediate frequency (IF) signal.

  The limit amplifier 124 includes a first amplifier 124A that amplifies the output of the first mixer 803A, and a second amplifier 124B that amplifies the output of the second mixer 803B. Here, the local oscillation signals mixed by the first mixer 803A and the second mixer 803B are out of phase by π / 2 (for example, 3 ps), and the IF signal (Q signal) is output from the first amplifier 124A. An IF signal (I signal) is output from the second amplifier 124B.

  Here, since the bipolar short pulse generator 805 generates a bipolar short pulse in which the positive polarity and the negative polarity are alternately changed, the output of the bandpass filter 802 is also alternately changed in the positive polarity and the negative polarity.

  As described above, an impulse signal output from an impulse transmitter in another example of the related art is also input to the first mixer 803A and the second mixer 803B via the reception amplifier 122, and the bandpass filter 802 Is detected by the output of.

  That is, the first mixer 803A and the second mixer 803B are bipolar signals whose polarity changes alternately (the output signal of the bandpass filter 802 and the signal shifted by π / 2 from the output signal, and the polarity changes alternately). Signal).

  As a result, the signal by phase modulation by the output signal (C) of any of the four phase control paths SLe to SLh selected by the four selection signals e to h is detected without error, and the IF signals (Q and I Signal).

  The baseband signal regenerator 125 includes an analog-to-digital converter (ADC) 851, a phase detector 852, and a data regenerator 853. The ADC 851 converts the IF signal (Q) and the IF signal (I) into digital data.

  The phase detector 852 detects the phase of the received impulse signal from the digital data of the IF signal (Q) and the IF signal (I). The data reproducing unit 853 reproduces data from the detected phase and the received clock phase.

  By the way, the impulse transmitter (trigger flip-flop with position modulation function: T-FF) as an example of the related technology described with reference to FIG. 6B and the related technology described with reference to FIG. In another example of the impulse transmitter, there are the following three problems.

  First, as a first problem, for example, when a delay buffer is formed with a low-cost device such as a CMOS (CMOS inverter), in the millimeter wave band, the delay time unit of position modulation is several ps, and the CMOS buffer Less than the delay time (-10 ps). This makes it difficult to use a single CMOS buffer to obtain a delay time unit.

  Further, as a second problem, for example, when the delay time due to the transmission line is used, the length of the transmission line becomes longer, the occupied area becomes larger, and space restrictions are imposed. Further, as a third problem, for example, a variation in delay time due to temperature and process fluctuations affects transmission characteristics, so that communication quality may be deteriorated.

  Hereinafter, the impulse transmitter according to the present embodiment will be described in detail with reference to the accompanying drawings. FIG. 10 is a block diagram showing a T-FF (trigger flip-flop with position modulation function) in an embodiment of an impulse transmitter.

  Here, the embodiment shown in FIG. 10 corresponds to the T-FF 902 in the impulse transmitter of another example of the related art shown in FIG. 8B, and is used when the multiplicity is “2”. An example in which −π / 2, reference (0), + π / 2, + π is generated is shown.

  The short pulse generator 102 to which the T-FF 902 is applied, the impulse transmitter to which the short pulse generator 102 is applied, and the impulse radio communication system to which the impulse transmitter is applied are the same as described above. The description is omitted.

  In the variable delay unit 920 of the T-FF shown in FIG. 8B, no buffer is provided in the first phase control path SLe. In this embodiment, for example, the delay time difference between two delay circuits is calculated. In order to set the delay time (phase) by using it, a delay control unit 928 is provided.

  Furthermore, this embodiment can be applied not only to the T-FF (variable delay unit) of the related technology shown in FIG. 8B but also to the variable delay unit of the related technology shown in FIG. 6B. Further, the present invention can be applied to a variable delay unit or the like when the multiplicity is larger than “2”.

  As apparent from the comparison between FIG. 10 and FIG. 8B, the T-FF 902 of the impulse transmitter according to the present embodiment is different from the T-FF shown in FIG. The configuration of the variable delay unit 920 is different.

  That is, in the variable delay unit 920 of the present embodiment, the first phase control path SLe is provided with the first delay control unit (buffer array) 928, and the second phase control path SLf is provided with the second delay control unit ( Buffer column) 923 is provided. Further, the third phase control path SLg is provided with a third delay control section (buffer string) 925, and the fourth phase control path SLh is provided with a fourth delay control section (buffer string) 927.

  Here, the first to fourth delay control units 928, 923, 925, and 927 provided in the first to fourth phase control paths SLe to SLh respectively include three delay circuits, a buffer, a transfer gate, including. Note that the number of delay circuits provided in each delay control unit varies depending on the multiplicity, that is, in accordance with the position (phase) where the pulse is arranged in one cycle.

  The first delay control unit 928 includes delay circuits De1, De2, De3 whose amount of delay is controlled by the first delay control signal DS1, a buffer BFe, and a transfer gate (second transfer gate) 921 ′.

  The second delay control unit 923 includes a delay circuit Df1 whose delay amount is controlled by the second delay control signal DS2, delay circuits Df2 and Df3 whose delay amount is controlled by the first delay control signal DS1, a buffer BFf, and , Including a transfer gate 922 ′.

  Further, the third delay control unit 925 includes delay circuits Dg1 and Dg2 whose delay amount is controlled by the second delay control signal DS2, delay circuit Dg3 whose delay amount is controlled by the first delay control signal DS1, buffer BFg, , Including a transfer gate 924 ′.

  The fourth delay control unit 927 includes delay circuits Dh1, Dh2, Dh3, a buffer BFh, and a transfer gate 926 ′ whose delay amount is controlled by the second delay control signal DS2.

  Here, the transfer gates (second transfer gates) 921 ′, 922 ′, 924 ′, and 926 ′ of each phase control path have the same selection signals e, as the transfer gates (first transfer gates) 921, 922, 924, and 926, respectively. Controlled by f, g, and h. Further, the buffers BFe to BFh included in the delay control units 928, 923, 935, and 927 of the phase control paths SLe to SLh are all equivalent.

  FIG. 11 is a block diagram illustrating an example of a delay control signal generation circuit used in the delay control unit of the T-FF illustrated in FIG. 10, and illustrates a circuit that generates the first delay control signal DS1 and the second delay control signal DS2. An example is shown.

  As shown in FIG. 11, the delay control signal generation circuit includes two DLL (Delay Locked Loop) circuits 301 and 302. The first DLL circuit 301 includes a first variable delay circuit 311, a first phase detector (PD) 312, a first low pass filter (LPF) 313, and an amplifier 314.

  The second DLL circuit 302 includes a second variable delay circuit 321, a second phase comparator (PD) 322, a second low-pass filter (LPF) 323 and an amplifier 324. The reference oscillator 300 is provided in common for the first DLL circuit 301 and the second DLL circuit 302. In FIG. 11, two DLL circuits 301 and 302 are illustrated, but three or more DLL circuits may be provided.

  The first variable delay circuit 311 is formed by cascading m + 1 delay circuits D11 to D1m + 1 having a variable delay time φ1, and the second variable delay circuit 321 has a variable delay time φ2. It is formed by cascading n + 1 delay circuits D21 to D2n + 1.

  The first phase comparator 312 compares the phase difference between the output of the first variable delay circuit 311 (for example, the output of the m-th delay circuit D1m) and the output of the reference oscillator 300. The second phase comparator 322 compares the phase difference between the output of the second variable delay circuit 321 (for example, the output of the nth stage delay circuit D2n) and the output of the reference oscillator 300.

  The first low-pass filter 313 extracts the low-frequency component of the output of the first phase comparator 312, and the extracted low-frequency component is amplified by the first amplifier 314 and output as the first delay control signal DS1. The

  The first delay control signal DS1 is input to the delay circuits De1 to De3, Df2, Df3, and Dg3 in FIG. 10 described above, and is fed back to the m + 1 delay circuits D11 to D1m + 1 in the first variable delay circuit 311. Is done.

  The second low-pass filter 323 extracts the low frequency component of the output of the second phase comparator 322, and the extracted low frequency component is amplified by the second amplifier 324 as the second delay control signal DS2. Is output.

  The second delay control signal DS2 is input to the delay circuits Df1, Dg1, Dg2, and Dh1 to Dh3 in FIG. 10 described above, and is fed back to the n + 1 delay circuits D11 to D1n + 1 in the second variable delay circuit 321. Is done. As described above, the reference oscillator 300 is shared by the first DLL circuit 301 and the second DLL circuit 302.

  The total delay time by the first variable delay circuit 311 of the first DLL circuit 301 (the delay time by the m delay circuits D11 to D1m) is adjusted to be an integral multiple M of the oscillation period T0 of the reference oscillator 300. Further, the total delay time by the second variable delay circuit 321 of the second DLL circuit 302 (delay time by the n delay circuits D21 to D2n) is adjusted to be an integral multiple N of the oscillation period T0 of the reference oscillator 300.

  Here, in order to simplify the description, in the case of M = N = 1, that is, the total delay time by the first variable delay circuit 311 and the total delay time by the second variable delay circuit 321 are both oscillated by the reference oscillator 300. Consider a case where adjustment is made to be equal to the period T0.

  At this time, the delay time of each delay circuit D11 to D1m (D1m + 1) in the first variable delay circuit 311 is φ1, and the delay time of each delay circuit D21 to D2n (D2n + 1) in the second variable delay circuit 321 is φ2. Each parameter is determined so that φ2−φ1 = φ0.

Φ0 is a position modulation delay time unit (= fc ⁻¹ / k), fc indicates the center frequency in the pass frequency band of the bandpass filter 103, and k indicates the number of phase (position) modulations. , K = 4.

Therefore, the following relationship is established between the delay time φ1 and the stage number m of the delay circuit in the first variable delay circuit 311 and the delay time φ2 and the stage number n of the delay circuit in the second variable delay circuit 321.
T0 = m × φ1 = n × φ2
Therefore,
n = m × φ1 / (φ1 + φ0)

Specifically, as an example, consider a case where the impulse radio apparatus uses the 80 GHz band (81 GHz to 86 GHz). In this case, φ0 = fc ^-1 /4=(83.5GHz) is ^{-1 /4ps~3.0ps, φ0 = (1GHz)} -1 = 1000ps at .phi.1 = 10 ps, when m = 100, φ2 = 13 0.0 ps, n = 77.

  With this configuration, the difference between the delay time φ1 of the two types of delay circuits D1 (D11 to D1m + 1 and the delay time φ2 of the delay circuits D2 (D21 to D2n + 1) (φ1 to φ2) is always kept equal to φ0. It is slack (φ2−φ1 = φ0).

  That is, for example, when four pulses are arranged within one period (−π / 2, reference (0), + π / 2, + π), one period (for example, 12 ps) with respect to the phase difference (π / 2). ) Corresponding to a quarter period (for example, 3 ps).

  At this time, φ2−φ1 = 13−10 = 3 ps is obtained. That is, a delay time difference of 3 ps can be obtained by using the delay circuit D1 of the first variable delay circuit 311 that gives a delay time of 10 ps and the delay circuit D2 of the second variable delay circuit 321 that gives a delay time of 13 ps. It becomes possible.

  Referring to FIG. 10 again, first, the first delay control unit 928 provided in the first phase control path SLe includes three delay circuits De1 to De3 whose delay amount is controlled by the first delay control signal DS1. .

  Further, the second delay control unit 923 provided in the second phase control path SLf includes two delay circuits Df2 and Df3 whose delay amount is controlled by the first delay control signal DS1, and the second delay control signal DS2. One delay circuit Df1 whose delay amount is controlled is included.

  That is, in the second delay control unit 923, the delay circuit De1 whose delay amount is controlled by the first delay control signal DS1 in the first delay control unit 928 is the delay circuit whose delay amount is controlled by the second delay control signal DS2. It is replaced by Df1.

  As a result, the output of the second phase control path SLf is shifted by +3 ps (+ π / 2) from the output of the first phase control path SLe. Accordingly, when the output of the second phase control path SLf is set to the reference (0), the output of the first phase control path SLe is shifted by −π / 2 (−3 ps).

  Further, when comparing the second delay control unit 923 of the second phase control path SLf and the third delay control unit 925 of the third phase control path SLg, Df2 that is delay-controlled by DS1 is Dg2 that is delay-controlled by DS2 Has been replaced. As a result, the output of the third phase control path SLg is shifted by +3 ps (+ π / 2) from the output of the second phase control path SLf.

  Further, when the third delay control unit 925 of the third phase control path SLg and the fourth delay control unit 927 of the fourth phase control path SLh are compared, Dg3 that is delay-controlled by DS1 is Dh3 that is delay-controlled by DS2 Has been replaced.

  In other words, comparing the second delay control unit 923 of the second phase control path SLf and the fourth delay control unit 927 of the fourth phase control path SLh, De2 and De3 that are delay-controlled by DS1 are delay-controlled by DS2. Replaced by Dh2 and Dh3. As a result, the output of the fourth phase control path SLh is shifted by +6 ps (+ π) from the output of the second phase control path SLf.

  Thus, even when a device (for example, a CMOS inverter) that provides a delay time (for example, 10 ps, 13 ps) longer than a desired delay time difference (for example, 3 ps) is used, the desired delay time difference (for example, 3 ps) ) Signal can be obtained.

  Here, according to the present embodiment, the delay times of the delay circuits D1 and D2 are delayed if, for example, the reference oscillator 300 is stable and compensated for temperature even if the temperature, power supply voltage, process, and the like vary. The variation of the time difference (φ0 = φ2−φ1) can be suppressed to a minute one. Further, according to the present embodiment, a device having a buffer delay time larger than the position modulation delay time unit φ0, such as a CMOS inverter (CMOS technology), can be used.

  The output C of the T-FF 902 in which the delay time difference (phase difference) of 3 ps (π / 2) is controlled will be described with reference to FIG. 1 and FIG. 8A (FIG. 6A), for example. As described above, the signal is output via the edge shaping circuit 505, the pulse generation filter 506, and the transmission antenna 105.

  As described above, according to the present embodiment, for example, a device such as a CMOS having a buffer delay time larger than the position modulation unit can be applied, and position modulation due to temperature, power supply voltage fluctuation, process variation, etc. A decrease in accuracy can be prevented. This makes it possible to realize a compact impulse transmitter with high communication quality and low cost.

  In the above-described embodiment, an example in which two DLL circuits are used has been described. However, more DLL circuits may be applied, and for example, a larger delay time difference may be obtained by using a third DLL circuit. .

  In the above-described embodiments, only the example using two DLL circuits has been described. However, for example, a PLL (Phase Locked Loop) circuit can be applied instead of the DLL circuit. Furthermore, the circuit for generating such a minute delay time (phase difference) is not limited to application to a bipolar RZ type impulse transmitter, and can be widely applied to various electronic devices. .

  FIG. 12 is a diagram for explaining an example of the delay circuit. The delay circuits D11 to D1m + 1 and D21 to D2n + 1 of the first and second variable delay circuits 311 and 312, and the phase control paths SLe to SLh delay circuits De1, De2, De3-Dh1, Dh2, Dh3 are shown.

  FIG. 12A shows a plurality of cascaded inverters I1, I2,..., Ij, Ij + 1, which are substantially variable delay circuits 311 (D11 to D1m + 1), 312 (D21 to D2n + 1) and delay circuits De1, De2, De3 to Dh1, Dh2, Dh3.

FIG. 12B shows an example of one inverter (delay time variable inverter) I in the plurality of cascaded inverters I1, I2,..., Ij, Ij + 1 in FIG.
As shown in FIG. 12B, the delay time variable inverter I includes a p-channel MOS transistor Qp and an n-channel MOS transistor Qn (CMOS) connected between the high potential power line Vdd and the low potential power line Vss. Inverter) and varactor VD.

  Here, the varactor (varactor diode) VD is provided between the output node of the CMOS inverter and the low-potential power supply line Vss, and the capacitance value is variably controlled by the control voltages (delay control signals DS1, DS2). Yes.

  Thus, by providing the varactor VD between the output node of the CMOS inverter (Qp, Qn) and the low potential power supply line Vss and controlling the capacitance value by the control voltage (delay control signals DS1, DS2), the delay time can be reduced. Variable control can be performed. Note that FIG. 12 is merely an example, and it is needless to say that various other circuits can be applied.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
An impulse transmitter for transmitting a multiplexed bipolar impulse signal with changing phase,
A baseband signal generator that generates a data signal in units of time slots of a communication clock;
A trigger flip-flop that changes the phase by giving different delays to the bipolar short pulse generated by inverting the polarity based on the data signal;
A bandpass filter that receives the bipolar short pulse and passes only a predetermined frequency bandwidth to generate the bipolar impulse signal;
The trigger flip-flop is a master-slave type, and the slave latch unit includes a plurality of phase control paths, one of which is selected based on a selection signal from a selector,
The plurality of phase control paths each include a plurality of delay circuits connected in cascade,
Selectively controlling the plurality of delay circuits in each of the phase control paths by at least two delay control signals;
An impulse transmitter characterized by that.

(Appendix 2)
Each said phase control path is
A first transfer gate provided in front of the plurality of delay circuits;
A buffer for receiving the outputs of the plurality of delay circuits;
A second transfer gate provided at a subsequent stage of the plurality of delay circuits,
The first and second transfer gates in the phase control path are selected by the same selection signal;
The impulse transmitter as set forth in Appendix 1, wherein

(Appendix 3)
Each delay time of the delay circuit is:
Greater than the minimum time difference between signals generated by the phase control path;
The impulse transmitter according to appendix 1 or appendix 2, characterized in that.

(Appendix 4)
The sum or difference of delay times by the respective delay circuits controlled by the at least two delay control signals is equal to a position modulation delay unit.
The impulse transmitter according to any one of Supplementary Note 1 to Supplementary Note 3, wherein:

(Appendix 5)
The at least two delay control signals are generated by at least two DLL circuits having different delay circuit configurations.
The impulse transmitter according to any one of Supplementary Note 1 to Supplementary Note 4, wherein:

(Appendix 6)
The at least two delay control signals are generated by at least two DLL circuits that receive a signal from a common reference oscillator and have different stages for cascading the delay circuits.
The impulse transmitter according to appendix 1 to appendix 5, wherein

(Appendix 7)
The delay control signal includes a first delay control signal and a second delay control signal,
The delay in each of the phase control paths is
Defined based on the number of the delay circuits that are delay-controlled by the first delay control signal and the number of the delay circuits that are delay-controlled by the second delay control signal.
The impulse transmitter according to any one of Supplementary Note 1 to Supplementary Note 4, wherein:

(Appendix 8)
The phase control paths are four of the first to fourth phase control paths, and output signals having phases different from each other by π / 2.
The impulse transmitter according to appendix 7, which is characterized in that.

(Appendix 9)
The phase control path includes three delay circuits connected in cascade,
In the first phase control path, three delay circuits are controlled by the first delay control signal,
In the second phase control path, two delay circuits are controlled by the first delay control signal, and one delay circuit is controlled by the second delay control signal,
In the third phase control path, one delay circuit is controlled by the first delay control signal, two delay circuits are controlled by the second delay control signal,
In the fourth phase control path, three delay circuits are controlled by the second delay control signal.
The impulse transmitter according to appendix 8, wherein

(Appendix 10)
The first and second delay control signals are generated by two DLL circuits having different delay circuit configurations.
The impulse transmitter according to any one of appendix 7 to appendix 9, which is characterized by the above.

(Appendix 11)
The first and second delay control signals are generated by first and second DLL circuits that receive signals from a common reference oscillator and differ in the number of stages for cascading the delay circuits.
The impulse transmitter according to any one of Supplementary Note 7 to Supplementary Note 10, wherein:

DESCRIPTION OF SYMBOLS 101 Baseband signal generator 102 Short pulse generator 103 Band pass filter 104 Transmission amplifier 105 Transmission antenna 121 Reception antenna 122 Reception amplifier 123 Detector 124 Limit amplifier 125 Baseband signal regenerator 300 Reference oscillator 301 1st DLL circuit 302 2nd DLL circuit 311 First variable delay circuit 321 Second variable delay circuit 312 First phase comparator (PD)
322 Second phase comparator (PD)
313 First low-pass filter (LPF)
323 Second low-pass filter (LPF)
314 First amplifier 324 Second amplifier 505 Edge shaping (shaping) circuit 506 Pulse generation filter (band pass filter)
507 Pulse amplifier (transmission amplifier)
701, 901 Selector 702, 902 Trigger flip-flop with position modulation function (T-FF: short pulse generator)
720, 920 Variable delay unit 801 Unipolar short pulse generator 802 Band pass filter 803A Mixer (first mixer)
803B mixer (second mixer)
804 π / 2 phase shifter 805 bipolar short pulse generator 923, 925, 927, 928 delay control unit De 1 to De 3, Df 1 to Df 3, Dg 1 to Dg 3, Dh 1 to Dh 3, D 1, D 11 to D 1 m + 1, D 2, D 21 To D2n + 1 delay circuit DS1 first delay control signal DS2 second delay control signal SLe to SLh, SLp to SLt phase control path

Claims (6)

An impulse transmitter for transmitting a multiplexed bipolar impulse signal with changing phase,
A baseband signal generator that generates a data signal in units of time slots of a communication clock;
A trigger flip-flop with a position modulation function that changes the phase by giving different delays to the bipolar short pulse generated by inverting the polarity based on the data signal;
A bandpass filter that receives the bipolar short pulse and passes only a predetermined frequency bandwidth to generate the bipolar impulse signal;
The trigger flip-flop with the position modulation function is a master-slave type, and the slave latch unit includes a plurality of phase control paths, one of which is selected based on a selection signal from a selector,
The plurality of phase control paths each include a plurality of delay circuits connected in cascade,
Wherein said plurality of delay circuits in the plurality of phase control path is selectively controlled by the two delay control signal even without low,
The trigger flip-flop with a position modulation function uses a delay time difference between a first delay time of a first phase control path and a second delay time of a second phase control path, which is included in the plurality of phase control paths. And
The delay time difference is shorter than the first delay time and the second delay time ,
An impulse transmitter characterized by that. Each said phase control path is
A first transfer gate provided in front of the plurality of delay circuits;
A buffer for receiving the outputs of the plurality of delay circuits;
A second transfer gate provided at a subsequent stage of the plurality of delay circuits,
The first and second transfer gates in the phase control path are selected by the same selection signal;
The impulse transmitter according to claim 1. The delay control signal includes a first delay control signal and a second delay control signal,
The delay in each of the phase control paths is
Defined based on the number of the delay circuits that are delay-controlled by the first delay control signal and the number of the delay circuits that are delay-controlled by the second delay control signal.
The impulse transmitter according to claim 1 or 2, characterized by the above. The phase control paths are four of the first to fourth phase control paths, and output signals having phases different from each other by π / 2.
The impulse transmitter according to claim 3. The phase control path includes three delay circuits connected in cascade,
In the first phase control path, three delay circuits are controlled by the first delay control signal,
In the second phase control path, two delay circuits are controlled by the first delay control signal, and one delay circuit is controlled by the second delay control signal,
In the third phase control path, one delay circuit is controlled by the first delay control signal, two delay circuits are controlled by the second delay control signal,
In the fourth phase control path, three delay circuits are controlled by the second delay control signal.
The impulse transmitter according to claim 4. The first and second delay control signals are generated by first and second DLL circuits that receive signals from a common reference oscillator and differ in the number of stages for cascading the delay circuits.
The impulse transmitter according to any one of claims 3 to 5, wherein the impulse transmitter is provided.

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