JP6578172B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and can be suitably used for a semiconductor device having a nonvolatile memory, for example.

  As an electrically writable / erasable nonvolatile memory, an EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used. These storage devices represented by flash memories that are currently widely used have a conductive floating gate electrode or a trapping insulating film surrounded by an oxide film under the gate electrode of the MISFET. Alternatively, the charge accumulation state in the trapping insulating film is used as memory information and is read out as the threshold value of the transistor. This trapping insulating film refers to an insulating film capable of accumulating charges, and examples thereof include a silicon nitride film. The threshold value of the MISFET is shifted by such charge injection / release to / from the charge storage region to operate as a memory element. As this flash memory, there is a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. In such a memory, by using a silicon nitride film as a charge storage region, it is superior in data retention reliability because it accumulates charges discretely compared to a conductive floating gate film, and also in data retention reliability. Therefore, the oxide films above and below the silicon nitride film can be made thinner, and the voltage of the write / erase operation can be lowered.

  The split gate type memory cell has a control gate electrode (selection gate electrode) formed on the semiconductor substrate via the first gate insulating film, and a second gate insulating film including a charge storage region on the semiconductor substrate. And a memory gate electrode formed. Furthermore, the split gate type memory cell has a pair of semiconductor regions (a source region and a drain region) formed on the surface of the semiconductor substrate so as to sandwich the control gate electrode and the memory gate electrode. It is provided on the gate insulating film.

  In Japanese Patent Application Laid-Open No. 2006-41354 (Patent Document 1), a convex active region is formed on the surface of a semiconductor substrate, and a control gate electrode and a memory gate electrode are provided so as to straddle the convex active region. An arranged split gate memory cell is disclosed. Data writing is performed by a source side injection (SSI) writing method in which hot electrons generated in a semiconductor substrate are injected into a charge storage region, and data erasing is performed by a band-to-band tunnel phenomenon. This is performed by a hot hole (Band-To-Band Tunneling: BTBT) erasing method in which holes generated in a semiconductor substrate are injected into a charge storage region.

JP 2006-41354 A

  The present inventor has developed a control gate electrode and a memory gate arranged so as to straddle a convex-shaped active region (referred to as a “fin”) formed on the surface of a semiconductor substrate in developing a next-generation nonvolatile memory cell. A fin-type nonvolatile memory cell having electrodes is being studied.

  The periphery of the fin protruding from the surface of the semiconductor substrate is covered with an element isolation film formed on the surface of the semiconductor substrate, and the fin protrudes from the element isolation film. The fin is a cuboid protrusion, has a width in the first direction of the main surface of the semiconductor substrate, extends in a second direction orthogonal to the first direction, and has a main surface (upper surface) and side surfaces. Yes. The control gate electrode extends in the first direction, is formed along the main surface and the side surface of the fin via the first gate insulating film, and extends on the element isolation film around the fin. . The memory gate electrode is disposed adjacent to the control gate electrode, is formed along the main surface and the side surface of the fin via the second gate insulating film, and extends on the element isolation film around the fin. Exist. The second gate insulating film has a charge storage layer. A pair of semiconductor regions (a source region and a drain region) are formed in the fin so as to sandwich the control gate electrode and the memory gate electrode.

  Writing into the memory cell is performed by an SSI (Source Side Injection) method in which hot electrons (electrons) generated on the surface of the semiconductor substrate are injected into the charge storage layer, and erasing is performed by FN (Fowler- Nordheim) tunnels are used to inject holes from the memory gate electrode into the charge storage layer.

  According to the study of the present inventor, in the fin type nonvolatile memory cell, charge accumulation located at the upper end of the fin at the time of writing due to electric field concentration at the corner of the tip of the fin and the corner of the lower end of the memory gate electrode. Electrons are efficiently injected into the layer, and at the time of erasing, holes are efficiently injected into the charge storage layer located at the lower end of the memory gate electrode. In other words, there is a mismatch between the electron distribution and the hole distribution in the charge storage layer, and after erasure, electrons injected into the charge storage layer at a position away from the lower end of the memory gate electrode remain without being erased. It turns out that there is a problem of deterioration. Here, endurance is the number of times data can be rewritten. When the number of remaining electrons increases, the electric field between the memory gate electrode and the semiconductor substrate is weakened by the influence, and data cannot be written or erased.

  That is, further improvement in performance is desired in a semiconductor device having a fin-type nonvolatile memory.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes a semiconductor substrate, an element isolation film formed on the upper surface of the semiconductor substrate, and a part of the semiconductor substrate, penetrating the element isolation film and perpendicular to the upper surface. And having fins extending in a second direction orthogonal to the first direction, having side surfaces facing each other in the first direction of the upper surface and a main surface connecting the facing side surfaces. Further, the control gate electrode is disposed on the side surface through the gate insulating film and extends in the first direction, and the gate electrode is disposed on the side surface through the gate insulating film including the charge storage layer and extends in the first direction. And an existing memory gate electrode. In the direction orthogonal to the upper surface, the first overlap length in which the memory gate electrode overlaps the side surface is smaller than the second overlap length in which the control gate electrode overlaps the side surface.

  According to one embodiment, the performance of a semiconductor device can be improved.

It is a figure which shows the layout structural example of the semiconductor device (semiconductor chip) which is one Embodiment. It is a principal part top view of the semiconductor device which is one embodiment. It is principal part sectional drawing of the semiconductor device which is one Embodiment. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one Embodiment. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one Embodiment. FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; It is an equivalent circuit diagram of a memory cell. 6 is a table showing an example of voltage application conditions to each part of a selected memory cell during “write”, “erase”, and “read”. (A) is sectional drawing which shows the electric charge trapping region of the memory cell which is one Embodiment. (B) is sectional drawing which shows the electric charge trapping region of the memory cell which is a comparative example. It is a principal part top view of the semiconductor device which is one embodiment. FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to Modification 1. 10 is a fragmentary cross-sectional view of the semiconductor device according to Modification 1 during the manufacturing process thereof. FIG. FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; 10 is a plan view of a principal part of a semiconductor device according to Modification 2. FIG. FIG. 11 is a cross-sectional view of a principal part of a semiconductor device according to Modification 2. 12 is a fragmentary cross-sectional view of a semiconductor device according to Modification 2 during the manufacturing process thereof. FIG. FIG. 34 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 34; FIG. 36 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 35; FIG. 37 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 36; FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37; 10 is an equivalent circuit diagram of a memory cell according to Modification 2. FIG. 12 is a table showing an example of conditions for applying a voltage to each part of a selected memory cell during “write” and “erase” in Modification 2. FIG. 10 is a main part sectional view of a semiconductor device in Modification 3; 10 is a fragmentary cross-sectional view of a semiconductor device according to Modification 3 during the manufacturing process thereof. FIG.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the mentioned number, and may be more or less than the mentioned number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment)
<Semiconductor chip layout configuration example>
A semiconductor device having a nonvolatile memory in this embodiment will be described with reference to the drawings. First, a layout configuration of a semiconductor device (semiconductor chip) in which a system including a nonvolatile memory is formed will be described. FIG. 1 is a diagram showing a layout configuration example of a semiconductor chip CHP in the present embodiment. In FIG. 1, a semiconductor chip CHP includes a CPU (Central Processing Unit) 100, a RAM (Random Access Memory) 200, an analog circuit 300, an EEPROM (Electrically Erasable Programmable Read Only Memory) 400, a flash memory 500, and an I / O (Input / Input). An output) circuit 600 is included to constitute a semiconductor device.

  The CPU (circuit) 100 is also called a central processing unit, which reads and decodes instructions from a storage device, and performs various operations and controls based on the instructions.

  The RAM (circuit) 200 is a memory that can read stored information at random, that is, read stored information at any time, or write new stored information, and is also called a memory that can be written and read at any time. As the RAM, an SRAM (Static RAM) using a static circuit is used.

  The analog circuit 300 is a circuit that handles voltage or current signals that change continuously in time, that is, analog signals, and includes, for example, an amplifier circuit, a conversion circuit, a modulation circuit, an oscillation circuit, and a power supply circuit.

  The EEPROM 400 and the flash memory 500 are a kind of non-volatile memory that can be electrically rewritten for both writing and erasing operations, and are also called electrically erasable programmable read-only memories. The memory cells of the EEPROM 400 and the flash memory 500 are composed of, for example, a MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistor or a MNOS (Metal Nitride Oxide Semiconductor) type transistor for storage (memory). The difference between the EEPROM 400 and the flash memory 500 is that the EEPROM 400 is a non-volatile memory that can be erased in units of bytes, for example, whereas the flash memory 500 is a non-volatile memory that can be erased in units of words, for example. is there. In general, the flash memory 500 stores a program for the CPU 100 to execute various processes. On the other hand, the EEPROM 400 stores various data with high rewrite frequency. The EEPROM 400 or the flash memory 500 includes a memory cell array in which a plurality of nonvolatile memory cells are arranged in a matrix, and other address buffers, row decoders, column decoders, verify sense amplifier circuits, sense amplifier circuits, write circuits, etc. Have.

  The I / O circuit 600 is an input / output circuit, and outputs data from the semiconductor chip CHP to a device connected to the outside of the semiconductor chip CHP, or from a device connected to the outside of the semiconductor chip CHP to the semiconductor chip. This is a circuit for inputting the data.

  The semiconductor device of this embodiment has a memory cell formation region and a logic circuit formation region. A memory cell array in which a plurality of nonvolatile memory cells are arranged in a matrix is formed in the memory cell formation region, and the CPU 100, RAM 200, analog circuit 300, I / O circuit 600, and The address buffer, row decoder, column decoder, verify sense amplifier circuit, sense amplifier circuit, write circuit, etc. of the EEPROM 400 or the flash memory 500 are formed.

<Device structure of semiconductor device>
FIG. 2 is a plan view of a main part of the semiconductor device according to the present embodiment. In FIG. 2, the memory cell portion A is a plan view of the main part of a memory cell array in which a plurality of memory cells are arranged in a matrix, and the logic portion B is a transistor Tr constituting a logic circuit in a logic circuit formation region. The principal part top view of is shown. As the transistor Tr, an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) is exemplified. FIG. 3 is a cross-sectional view of a main part of the semiconductor device according to the present embodiment. FIG. 3 shows three cross-sectional views of the memory cell portion A and two cross-sectional views of the logic portion B. The memory cell portion A1 is a cross-sectional view taken along A1-A1 ′ in FIG. 2, the memory cell portion A2 is a cross-sectional view taken along A2-A2 ′ in FIG. 2, and the memory cell portion A3 is taken along A3-A3 ′ in FIG. A sectional view taken along the line B1-B1 'in FIG. 2 and a logic part B2 taken along a line B2-B2' in FIG.

  As shown in FIG. 2, in the memory cell portion A, a plurality of fins FA extending in the X direction are arranged at equal intervals in the Y direction. The fin FA is, for example, a rectangular parallelepiped protrusion (projection) that selectively protrudes from the main surface (surface, upper surface) 1 a of the semiconductor substrate 1, and the lower end portion of the fin FA covers the main surface of the semiconductor substrate 1. It is surrounded by an element isolation film STM. The fin FA is a part of the semiconductor substrate 1 and is an active region of the semiconductor substrate 1. Therefore, in plan view, between the adjacent fins FA is filled with the element isolation film STM, and the periphery of the fin FA is surrounded by the element isolation film STM. The fin FA is an active region for forming the memory cell MC.

  A plurality of control gate electrodes CG and a plurality of memory gate electrodes MG extending in the Y direction (a direction orthogonal to the X direction) are disposed on the plurality of fins FA. A drain region MD is formed on the control gate electrode CG side and a source region MS is formed on the memory gate electrode MG side so as to sandwich the control gate electrode CG and the memory gate electrode MG. The drain region MD and the source region MS are n-type semiconductor regions. The drain region MD is formed between two adjacent control gate electrodes CG in the X direction, and the source region MS is formed between two adjacent memory gate electrodes MG in the X direction. The memory cell MC has a control gate electrode CG, a memory gate electrode MG, a drain region MD, and a source region MS. The memory cell MC includes a control transistor CT having a control gate electrode CG and a memory transistor MT connected to the control transistor CT and having a memory gate electrode MG. The memory cell MC is a split gate type cell (split gate type memory cell).

  In two memory cells MC adjacent in the X direction, the drain region MD or the source region MS is shared. The two memory cells MC sharing the drain region MD are mirror-symmetric with respect to the drain region MD in the X direction, and the two memory cells MC sharing the source region MS are It is mirror-symmetric in the X direction.

  Each fin FA has a plurality of memory cells MC formed in the X direction. The drain regions MD of the plurality of memory cells MC arranged in the X direction have plug electrodes PG formed in the contact holes CNT. And is connected to a source line SL formed of a metal wiring MW extending in the X direction. Further, the source regions MS of the plurality of memory cells MC arranged in the Y direction are connected to the bit line BL made of the metal wiring MW extending in the Y direction. Preferably, a metal wiring of a layer different from that of the bit line BL is used for the source line SL.

  Moreover, the logic part B is formed with, for example, fins FB extending in the X direction. The fin FB is an active region of the semiconductor substrate 1 like the fin FA, and the lower end portion of the fin FB is surrounded by an element isolation film STL that covers the main surface of the semiconductor substrate 1. A gate electrode GE extending in the Y direction is arranged on the fin FB, and a drain region LD and a source region LS are formed in the fin FB so as to sandwich the gate electrode GE. The drain region LD and the source region LS are n-type semiconductor regions. The transistor Tr has a gate electrode GE, a drain region LD, and a source region LS. The gate electrode GE, the drain region LD, and the source region LS are each connected to the metal wiring MW via the plug electrode PG formed in the contact hole CNT. The fin FB is an active region for forming the transistor Tr. Note that the fin FB may extend in the Y direction and the gate electrode GE may extend in the X direction.

  The fins FA and FB are, for example, cuboid protrusions that protrude from the main surface 1a of the semiconductor substrate 1 in a direction perpendicular to the main surface 1a. The fins FA and FB have an arbitrary length in the long side direction, an arbitrary width in the short side direction, and an arbitrary height in the height direction. The fins FA and FB do not necessarily need to be rectangular parallelepipeds, and include shapes in which rectangular corners are rounded in a cross-sectional view in the short side direction. Further, the direction in which the fins FA and FB extend in plan view is the long side direction, and the direction orthogonal to the long side direction is the short side direction. That is, the length is larger than the width. Fins FA and FB may be any shape as long as they have protrusions having a length, a width, and a height. Each of the fins FA and FB has an opposing side surface and a main surface (upper surface) that connects the opposing side surfaces in the width direction. For example, the meander pattern is also included in the plan view.

  Next, the structure of the memory cell MC and the transistor Tr will be described with reference to FIG.

  In the memory cell portion A of the semiconductor substrate 1, a fin FA that is a protruding portion of the semiconductor substrate 1 is formed. The lower part of the fin FA is surrounded by an element isolation film STM formed on the main surface 1 a of the semiconductor substrate 1. That is, as shown in FIG. 2, the fins FA are separated by the element isolation film STM. A p-type well PW1 which is a p-type semiconductor region is formed below the fin FA. In other words, the fin FA is formed in the p-type well PW1. Actually, a plurality of fins FA are formed in the p-type well PW1.

  A control gate electrode CG is formed on the main surface FAa and the side surface FAs of the fin FA via a gate insulating film GIt. In the long side direction of the fin FA, a region adjacent to the control gate electrode CG has a gate. A memory gate electrode MG is formed through the insulating film GIm. The control gate electrode CG and the memory gate electrode MG are electrically separated by this gate insulating film GIm. The control gate electrode CG and the memory gate electrode MG may be electrically isolated by interposing an insulating film different from the gate insulating film GIm.

  Here, the gate insulating film GIt is a thermal oxide film (silicon oxide film) formed by thermally oxidizing the main surface FAa and the side surface FAs of the fin FA which is the protruding portion of the semiconductor substrate 1 made of silicon. Is 2 nm. Further, the gate insulating film GIm is a thermal oxide film (silicon oxide film) having a thickness of 4 nm formed by thermally oxidizing the main surface FAa and the side surface FAs of the fin FA which is the protruding portion of the semiconductor substrate 1 made of silicon. The insulating film IF1, the insulating film IF2 formed on the insulating film IF1, and the insulating film IF3 formed on the insulating film IF2. The insulating film IF2 is made of a silicon nitride film that is a charge storage layer (charge storage portion, charge storage region), and the insulating film IF3 is made of a silicon oxynitride film that covers the surface of the silicon nitride film. The silicon nitride film has a thickness of 7 nm, and the silicon oxynitride film has a thickness of 9 nm. That is, the gate insulating film GIm has a stacked structure of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, and has a thickness of 20 nm, which is thicker than the gate insulating film GIt below the control gate electrode CG. . The gate insulating film GIm may have a stacked structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film. Further, as the gate insulating film GIm, a stacked film in which a silicon oxide film (SiO), a silicon nitride film (SiN), an aluminum oxide film (AlOx), a hafnium oxide film (HfOx), and a silicon oxynitride film (SiON) is used. May be. For example, a laminated structure such as SiO / SiON / HfOx / AlOx, AlOx / SiON / HfOx / AlOx, or SiON / SiO / HfOx / AlOx may be used from the semiconductor substrate 1 side.

  As shown in the memory cell portion A2, in the short side direction of the fin FA, the control gate electrode CG extends along the main surface FAa of the fin FA and the opposite side surface FAs via the gate insulating film GIt. , Extending over the element isolation film STM that surrounds (pinches) the lower portion of the fin FA. Similarly, as shown in the memory cell portion A3, in the short side direction of the fin FA, the memory gate electrode MG extends along the main surface FAa of the fin FA and the opposite side surface FAs via the gate insulating film GIm. And extending over the element isolation film STM surrounding (flanking) the fin FA. In the extending direction of the memory gate electrode MG, a pad insulating film PAD is interposed between the element isolation film STM and the memory gate electrode MG. The pad insulating film PAD is interposed between the insulating film IF2 and the insulating film IF3. The pad insulating film PAD is formed outside the fin FA, between the element isolation film STM and the memory gate electrode MG, and between the main surface FAa of the fin FA and the memory gate electrode MG. Absent. Further, the pad insulating film PAD is not formed between the control gate electrode CG and the element isolation film STM and between the control gate electrode CG and the main surface FAa of the fin FA. That is, by forming the pad insulating film PAD between the memory gate electrode MG and the element isolation film STM outside the fin FA, the height (length) of the region where the control gate electrode CG and the side surface FAs of the fin FA overlap with each other. ) (In other words, without reducing the drive capability of the control transistor CT), the region where the memory gate electrode MG and the side surface FAs of the fin FA overlap is reduced. The pad insulating film PAD is formed in a region other than the fin FA and the control gate electrode CG in the memory cell portion A shown in FIG. It is sufficient that the pad insulating film PAD remains between the memory gate electrode MG and the element isolation film STM, and the pad insulating film PAD in other regions may be removed.

  A silicide layer SC is formed on the main surfaces of the control gate electrode CG and the memory gate electrode MG.

In addition, a source region MS and a drain region MD are provided outside the control gate electrode CG and the memory gate electrode MG so as to sandwich the control gate electrode CG and the memory gate electrode MG. The source region MS has an n ⁻ type semiconductor region EX1 and an n ⁺ type semiconductor region SD1, and the drain region MD has an n ⁻ type semiconductor region EX2 and an n ⁺ type semiconductor region SD2. The source region MS and the drain region MD are formed in the entire area of the fin FA exposed from the element isolation film STM in the short side direction and the height direction.

  Over the side walls of the control gate electrode CG and the memory gate electrode MG, a side wall spacer (side wall, side wall insulating film) SW and an interlayer insulating film IL1 are formed. The control gate electrode CG, the memory gate electrode MG, and the source region An interlayer insulating film IL2 is formed on the interlayer insulating film IL1 so as to cover the MS and the drain region MD. A metal wiring MW is formed on the interlayer insulating film IL2, and the metal wiring MW is connected to the source region MS and the drain via the plug electrode PG provided in the contact hole CNT formed in the interlayer insulating films IL2 and IL1. It is electrically connected to the region MD.

  The memory cell MC has a control gate electrode CG, a memory gate electrode MG, a drain region MD, and a source region MS. The distance between the drain region MD and the source region MS in the long side direction corresponds to the channel length of the memory cell MC, and the control gate electrode CG or the memory gate electrode MG in the short side direction is the main surface FAa of the fin FA. The region facing (overlapping) the side surface FAs corresponds to the channel width of the memory cell MC. Since the memory cell MC includes the control transistor CT and the memory transistor MT, the length of the control gate electrode CG on the main surface FAa of the fin FA corresponds to the gate length of the control transistor CT, and the short side A region where the control gate electrode CG in the direction faces (overlaps) the main surface FAa and the side surface FAs of the fin FA corresponds to the channel width of the control transistor CT. The length of the memory gate electrode MG on the main surface FAa of the fin FA corresponds to the gate length of the memory transistor MT, and the memory gate electrode MG in the short side direction faces the main surface FAa and the side surface FAs of the fin FA ( The overlapping region corresponds to the channel width of the memory transistor MT.

  A fin FB that is a protruding portion of the semiconductor substrate 1 is formed in the logic portion B of the semiconductor substrate 1. The lower part of the fin FB is surrounded by an element isolation film STL formed on the main surface 1a of the semiconductor substrate 1. Although not shown, a plurality of fins FB are formed in the logic part B, and the fins FB are separated by an element isolation film STL. A p-type well PW2 that is a p-type semiconductor region is formed below the fin FB. In other words, the fin FB is formed in the p-type well PW2.

  A gate electrode GE is formed on the main surface FBa and the side surface FBs of the fin FB via the gate insulating film GIL and the insulating film HK. As shown in the logic part B2, in the short side direction of the fin FB, the gate electrode GE extends along the main surface FBa and the side surface FBs of the fin FB via the gate insulating film GIL and the insulating film HK. , Extending over the element isolation film STL surrounding the fin FB. The gate electrode GE has a stacked structure of metal films ME1 and ME2. In the logic part B, the pad insulating film PAD is not formed.

Further, the source region LS and the drain region LD provided outside the gate electrode GE so as to sandwich the gate electrode GE have an n ⁻ type semiconductor region EX3 and an n ⁺ type semiconductor region SD3, respectively. The source region LS and the drain region LD are formed in the entire region of the fin FB exposed from the element isolation film STL in the short side direction and the height direction.

  A sidewall spacer SW and an interlayer insulating film IL1 are formed on the side wall of the gate electrode GE, and an interlayer insulating film IL2 is formed on the gate electrode GE and the interlayer insulating film IL1. An insulating film 16 is formed between the interlayer insulating film IL1 and the interlayer insulating film IL2 so as to cover the gate electrode GE. A metal wiring MW is formed on the interlayer insulating film IL2, and the metal wiring MW is connected to the source region LS and the drain via the plug electrode PG provided in the contact hole CNT formed in the interlayer insulating films IL2 and IL1. It is electrically connected to the region LD.

  The transistor Tr has a gate electrode GE, a drain region LD, and a source region LS. The distance between the drain region LD and the source region LS in the long side direction corresponds to the channel length of the transistor Tr, and the gate electrode GE in the short side direction faces the main surface FBa and the side surface FBs of the fin FB. Corresponds to the channel width of the transistor Tr.

  Note that the p-type wells PW1 and PW2 shown in FIG. 3 are omitted in FIGS.

<About semiconductor device manufacturing process>
4 to 22 are fragmentary cross-sectional views of the semiconductor device according to the present embodiment during the formation process.

  First, the manufacturing process of the fin FA of the memory cell part A and the fin FB of the logic part B will be described.

  FIG. 4 is a diagram for explaining the step of forming the mask film 4 (step S1) for specifying the regions where the fins FA and FB are to be formed.

  Insulating films 2 and 3 are deposited on the semiconductor substrate 1. The semiconductor substrate 1 is made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm. The insulating film 2 is made of a silicon oxide film and has a thickness of about 2 to 10 nm. The insulating film 3 is made of a silicon nitride film and has a thickness of about 20 to 100 nm. Next, an amorphous silicon film is deposited on the insulating film 3 and then patterned into a desired shape, thereby forming a mask film 4 made of an amorphous silicon film. The film thickness of the mask film 4 is 20 to 200 nm. Since the fins FA or FB are formed at both ends of the mask film 4, the interval between the adjacent fins FA or the interval between the adjacent fins FB can be determined by the width of the mask film 4.

  FIG. 5 is a drawing for explaining the formation process (step S2) of the hard mask film 5 for forming the fins FA and FB.

  A silicon oxide film having a thickness of 10 to 40 nm is deposited on the semiconductor substrate 1 so as to cover the upper surface and side surfaces of the mask film 4, and then anisotropic dry etching is performed on the silicon oxide film to thereby form the mask film 4. A hard mask film 5 is formed on the side wall. The width of the hard mask film 5 is 10 to 40 nm. After the hard mask film 5 is formed, the mask film 4 is removed.

  FIG. 6 is a diagram for explaining the step of forming the fins FA and FB (step S3).

  The insulating films 3 and 2 and the semiconductor substrate 1 are subjected to anisotropic dry etching using the hard mask film 5 as a mask, and the insulating films 3 and 2 having the same shape as the hard mask film 5 in plan view, and the fin FA And FB. In addition, fins FA and FB having a height of 100 to 250 nm from the main surface 1a of the semiconductor substrate 1 can be formed by digging the semiconductor substrate 1 in a region exposed from the hard mask film 5 by 100 to 250 nm. Of course, the width WA of the fin FA of the memory cell portion A is equal to the width WB of the fin FB of the logic portion B. Here, the width of the fin FA or FB is the length in the direction in which the aforementioned control gate electrode CG or gate electrode GE intersects. After the formation of the fins FA and FB, the hard mask film 5 is removed.

  Next, the process for forming the element isolation films STM and STL (step S4) will be described.

  An insulating film made of a silicon oxide film or the like is deposited on the semiconductor substrate 1 so as to completely fill the fins FA and FB and the insulating films 2 and 3, and a CMP (Chemical Mechanical Polishing) process is performed on the insulating film. Then, the main surface of the insulating film 3 is exposed. Thus, as shown in FIG. 7, the insulating film 6 having the uniform main surface 6 a is formed on the main surface 1 a of the semiconductor substrate 1. After forming the insulating film 6, the insulating films 3 and 2 are removed. Only the insulating film 3 may be removed.

  Next, as shown in FIG. 8, the insulating film 6 is etched, the main surface 6 a of the insulating film 6 is retracted (lowered) in the height direction, and a part of the side surfaces and main surfaces of the fins FA and FB are removed. Expose. Thus, the element isolation film STM is formed below the fin FA of the memory cell part A, and the element isolation film STL is formed below the fin FB of the logic part B. Here, in the memory cell part A and the logic part B, the retraction amounts of the insulating film 6 are the same, so the exposed heights of the fins FA and FB are the same. The height HA of the fin FA of the memory cell portion A is the distance from the main surface (upper surface, surface) STMa of the element isolation film STM to the main surface FAa of the fin FA, and the height HB of the fin FB of the logic portion B is The distance from the main surface (upper surface, surface) STLa of the element isolation film STL to the main surface FBa of the fin FB. The height HB of the fin FB is equal to the height of the fin FA. Thus, the process for forming the element isolation films STM and STL (step S4) is completed.

  Next, with reference to FIGS. 9 to 22, the manufacture of the memory cell MC and the transistor Tr will be described. 9 to 22 show memory cell portions A1, A2, and A3, and logic portions B1 and B2, as in FIG.

  As shown in FIG. 9, the memory cells A1, A2, and A3 are provided with fins FA, and the logic parts B1 and B2 are provided with fins FB. The width WA of the fin FA is equal to the width WB of the fin FB (WA = WB), and the height HA of the fin FA is equal to the height HB of the fin FB (HA = HB). Note that the p-type wells PW1 and PW2 shown in FIG. 3 are performed after the step of forming the element isolation films STM and STL (step S4) shown in FIG. 8 and before step 5 described later.

  FIG. 10 shows the step of forming the insulating film 7, the conductor film 8, and the insulating film 9 (step S5). First, the insulating film 7 is formed on the main surfaces FAa and FBa and the side surfaces FAs and FBs of the fins FA and FB. The insulating film 7 thermally oxidizes the main surfaces FAa and FBa and the side surfaces FAs and FBs of the fins FA and FB to form a silicon oxide film of about 2 nm. Next, a conductor film 8 having a thickness equal to or greater than the heights of the fins FA and FB is deposited on the insulating film 7, and the conductor film 8 is subjected to CMP treatment to form a conductor film 8 having a flat main surface. To do. Next, an insulating film 9 is deposited on the main surface of the conductor film 8. The conductor film 8 is a polysilicon film (silicon film), and the insulating film 9 is a silicon nitride film. In the CMP process of the conductor film 8, it is important that the conductor film 8 remains on the main surfaces of the fins FA and FB.

  FIG. 11 shows the step of forming the control gate electrode CG (step S6). A resist film PR1 is selectively formed on the insulating film 9. In the memory cell portion A, the resist film PR1 has a pattern that covers the formation region of the control gate electrode CG and exposes other regions. Further, the resist film PR1 has a pattern covering the logic part B. A dry etching process is performed on the insulating film 9 and the conductor film 8 to remove the insulating film 9 and the conductor film 8 in regions exposed from the resist film PR1, thereby forming the control gate electrode CG. The insulating film 7 is processed by a dry etching process or a subsequent cleaning process, whereby a gate insulating film GIt is formed under the control gate electrode CG. In the memory cell portion A3, the insulating film 9, the conductor film 8, and the insulating film 7 are removed, and the main surface FAa and the side surface FAs of the fin FA are exposed. The resist film PR1 is removed after the insulating film 9 is patterned or after the insulating film 9 and the conductor film 8 are patterned.

  FIG. 12 shows the step of forming the insulating films 10 and 11 (step S7). First, the insulating films 10 and 11 are sequentially formed on the main surface FAa and the side surface FAs of the fin FA exposed from the control gate electrode CG. The insulating film 10 is a silicon oxide film formed by thermally oxidizing the main surface FAa and the side surface FAs of the fin FA, and the film thickness thereof is 4 nm, which is larger than the film thickness of the gate insulating film GIt. Next, the insulating film 11 is made of a silicon nitride film and has a thickness of 7 nm. Here, the side surfaces of the control gate electrode CG and the gate insulating film GIt are covered with the insulating film 11.

  FIG. 12 shows a part of the process of forming the pad insulating film PAD (step S8) described later. In the memory cell portion A3, the insulating film 12 having a film thickness equal to or larger than the height of the fin FA is formed so as to cover the main surface FAa and the side surface FAs of the fin FA. The insulating film 12 is made of, for example, a silicon oxide film. In order to form the insulating film 12, a silicon oxide film is deposited on the insulating film 11, and this silicon oxide film is subjected to CMP polishing to form the insulating film 11 formed on the control gate electrodes CG of the memory cell portions A1 and A2. Then, the insulating film 12 is formed. That is, in this CMP polishing step, the polishing is stopped by detecting that the insulating film 11 is exposed.

  FIG. 13 shows a part of the pad insulating film PAD formation process (step S8) subsequent to FIG. Isotropic etching is performed on the insulating film 12 to remove the insulating film 12 on the main surface FAa of the fin FA. Further, isotropic etching is continued to selectively leave the insulating film 12 on the element isolation film STM and form the pad insulating film PAD. For example, the thickness of the pad insulating film PAD is preferably ½ or more of the height of the fin FA. That is, in the height direction, the portion above the center of the fin FA exposed from the element isolation film STM is exposed from the pad insulating film PAD. In the logic part B, since the insulating film 12 is removed over the entire area, the pad insulating film PAD is not formed. Further, after the pad insulating film PAD is formed, a resist film (not shown) having a pattern slightly enlarged from the pattern of the memory gate electrode MG shown in FIG. 2 is formed, and the adjacent fin FA shown in FIG. It is also possible to remove the insulating film 12 in a region sandwiched between adjacent control gate electrodes CG and a region sandwiched between memory fin electrodes MG adjacent to adjacent fins FA.

  In this pad insulating film PAD formation process, in the memory cell portion A1, all of the insulating film 12 on the fin FA is removed, but the side surfaces of the control gate electrode CG and the gate insulating film GIt are insulating films 11 made of a silicon nitride film. Therefore, side etching of the gate insulating film GIt can be prevented.

  FIG. 14 shows the step of forming the insulating film 13 (step S9). An insulating film 13 is formed on the insulating film 11 and on the pad insulating film PAD of the memory cell portion A3. The insulating film 13 is made of, for example, a silicon oxynitride film and has a thickness of 9 nm.

  FIG. 15 shows a part of the process of forming the memory gate electrode MG (step S10) described later. A conductor film 14 is formed on the insulating film 13. The conductor film 14 is deposited after depositing a conductor film 14 having a thickness equal to or greater than the height of the stack of the control gate electrode CG and the insulating film 9 and the height of the fin FA of the memory cell portion A3. As shown in FIG. 15, the conductor film 14 is selectively formed in the region exposed from the control gate electrode CG of the memory cell portion A by performing the CMP process to expose the insulating film 11 on the control gate electrode CG. It is formed. The conductor film 14 is made of a polysilicon film (silicon film). In the logic part B, the conductor film 14 is removed and the insulating film 11 is exposed. In the memory cell portion A1, the conductor film 14 is formed on the side wall of the control gate electrode CG and on the fin FA via the insulating films 10, 11, and 13. In the memory cell portion A3, the insulating film 10, 11, and 13 are formed on the main surface FAa and the side surface FAs of the fin FA.

  FIG. 16 shows a part of the process of forming the memory gate electrode MG (step S10) described later. First, the conductor film 14 is etched back (isotropic etching) to reduce the height of the main surface of the conductor film 14. After the etch back process, the main surface of the conductor film 14 has a height substantially equal to the main surface of the control gate electrode CG, for example. Next, after depositing a silicon nitride film on the sidewalls of the insulating films 9 and 11 on the control gate electrode CG and on the conductor film 14, the insulating film 9 on the control gate electrode CG is subjected to anisotropic dry etching. A mask film 15 is formed on the side wall. In the anisotropic dry etching process for forming the mask film 15, the insulating film 11 on the control gate electrode CG and the logic part B is removed. Next, the conductive film 14 exposed from the mask film 15 is removed by etching, so that the memory gate electrode MG and the spacer are formed on the side wall of the control gate electrode CG via the insulating films 10, 11, and 13. SP is formed. The spacer SP has the same structure as that of the memory gate electrode MG, but has a name different from that of the memory gate electrode MG because it is removed in a process described later.

  FIG. 17 shows the spacer SP removal and gate insulating film GIm formation step (step S11). First, using a resist film (not shown) that covers the memory gate electrode MG and exposes the spacer SP, the mask film 15 and the spacer SP on the spacer SP shown in FIG. 16 are removed by wet etching, for example. Subsequently, the insulating films 13, 11 and 10 in the region exposed from the memory gate electrode MG are removed by, for example, a wet etching process, and below the memory gate electrode MG (that is, between the memory gate electrode MG and the fin FA). In addition, the gate insulating film GIm made of the insulating films IF3, IF2 and IF1 is selectively formed while leaving the insulating films 13, 11 and 10. Note that the gate insulating film GIm is formed not only between the main surface FAa of the fin FA and the memory gate electrode MG but also between the control gate electrode CG and the memory gate electrode MG. As shown in FIG. 17, the gate insulating film GIm is formed along the main surface FAa and the side surface FAs of the fin FA.

FIG. 18 shows a step (step S12) of forming the dummy gate DG and the n ⁻ type semiconductor regions (impurity diffusion layers) EX1, EX2, and EX3. First, in the logic part B, the insulating film 9 and the conductor film 8 are patterned to form a dummy gate DG made of the conductor film 8. The insulating film 9 on the dummy gate DG and the insulating film 7 below the dummy gate DG also have the same planar pattern as the dummy gate DG.

Next, for example, n-type impurities such as arsenic (As) or phosphorus (P) are introduced into the fins FA and FB by ion implantation, so that the n ⁻ -type semiconductor regions EX1 and EX2 are formed in the fin FA. The n ⁻ type semiconductor region EX3 is formed in the fin FB. The n ⁻ type semiconductor regions EX1 and EX2 are formed in self alignment with the control gate electrode CG and the memory gate electrode MG. That is, since the n-type impurity is implanted into the main surface and the side surface of the fin FA exposed from the control gate electrode CG and the memory gate electrode MG, the n ⁻ -type semiconductor regions EX1 and EX2 are connected to the control gate electrode CG and the memory gate. It is formed on both sides of the electrode MG so as to sandwich the control gate electrode CG and the memory gate electrode MG. Since impurities are diffused by the heat treatment after the ion implantation, the n ⁻ type semiconductor region EX1 partially overlaps with the memory gate electrode MG and the n ⁻ type semiconductor region EX2 partially overlaps with the control gate electrode CG.

The n ⁻ type semiconductor region EX3 is formed in self alignment with the dummy gate DG. That is, since the n-type impurity is implanted into the main surface and the side surface of the fin FB exposed from the dummy gate DG, the n ⁻ -type semiconductor region EX3 is formed on both sides of the dummy gate DG so as to sandwich the dummy gate DG. Is done. Since the impurity diffuses in the heat treatment after the ion implantation, the n ⁻ type semiconductor region EX3 partially overlaps with the dummy gate DG.

FIG. 19 shows a step (step S13) of forming sidewall spacers (sidewalls, sidewall insulating films) SW and n ⁺ -type semiconductor regions (impurity diffusion layers) SD1, SD2, SD3. For example, an insulating film made of, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof is deposited on the semiconductor substrate 1 so as to cover the main surfaces FAa and FBa of the fins FA and FB. Perform isotropic dry etching. Thus, in the memory cell portion A1, the sidewall spacer SW is formed on the sidewalls of the control gate electrode CG and the insulating film 9 and on the sidewalls of the memory gate electrode MG and the mask film 15. In the logic part B1, side wall spacers SW are formed on the side walls of the dummy gate DG and the insulating film 9. By the above-described anisotropic dry etching, the insulating film for forming the sidewall spacer SW is removed in the memory cell portions A2 and A3 and the logic portion B2, and the insulating film 9 or the mask film 15 is exposed.

Next, an n-type impurity such as arsenic (As) or phosphorus (P) is applied to the fin FA using the control gate electrode CG, the memory gate electrode MG, and the sidewall spacer SW as a mask (ion implantation blocking mask). By introducing by ion implantation, n ⁺ type semiconductor regions SD1 and SD2 are formed. At the same time, an n-type impurity such as arsenic (As) or phosphorus (P) is introduced into the fin FB by ion implantation using the dummy gate electrode DG and the side wall spacer SW as a mask (ion implantation blocking mask). Thus, the n ⁺ type semiconductor region SD3 is formed so as to sandwich the dummy gate DG.

In this manner, n ^- -type semiconductor region EX1 and than by the n ⁺ -type semiconductor regions SD1 of the high impurity concentration, n type semiconductor regions functioning as a source region MS of the memory cell MC is formed, n ^- -type a semiconductor region EX2 than by the n ⁺ -type semiconductor region SD2 of the high impurity concentration, n type semiconductor regions serving as the drain region MD of the memory cell MC is formed. In addition, the n ⁻ type semiconductor region EX3 and the n ⁺ type semiconductor region SD3 having a higher impurity concentration form an n type semiconductor region that functions as the source region LS and the drain region LD of the transistor Tr in the logic part B. The

  FIG. 20 shows the step of forming the interlayer insulating film IL1 (step S14). An interlayer insulating film IL1 is formed (deposited) on the semiconductor substrate 1. The interlayer insulating film IL1 is composed of a single film of a silicon oxide film or a laminated film of a silicon nitride film and a silicon oxide film formed thicker than the silicon nitride film on the silicon nitride film. Can be used. Next, the upper surface of the interlayer insulating film IL1 is polished (polishing process) using a CMP method or the like. As shown in FIG. 20, the upper surfaces of the control gate electrode CG, the memory gate electrode MG, and the dummy gate DG are exposed. That is, in this polishing process, the insulating film 9 and the mask film 15 formed on the control gate electrode CG, the memory gate electrode MG, and the dummy gate DG are completely removed. Of course, the sidewall SW located on the side walls of the insulating film 9 and the mask film 15 is also partially removed.

  FIG. 21 shows a step of forming the gate insulating film GIL and the gate electrode GE (Step S15). First, a process of removing the exposed dummy gate DG shown in FIG. 20 is performed. By removing the dummy gate DG, the trench TR1 is formed in the interlayer insulating film IL1. The bottom (bottom surface) of the trench TR1 is formed by the top surface of the insulating film 7, and the sidewall (side surface) of the trench TR1 is the side surface of the sidewall spacer SW (side surface that is in contact with the dummy gate DG before the dummy gate DG is removed). It is formed by.

  Next, as shown in FIG. 21, the insulating film HK, the metal film ME1, and the metal film ME2 are sequentially deposited on the semiconductor substrate 1, that is, on the insulating film 7 inside the trench TR1 (on the bottom and side walls). A step of forming the insulating film HK, the metal film ME1, and the metal film ME2 to be performed is performed. Further, a CMP process is performed on the insulating film HK, the metal film ME1, and the metal film ME2, and the insulating film HK, the metal film ME1, and the metal film ME2 on the interlayer insulating film IL1 are removed. Thus, a stacked structure of the gate insulating film GIL, the insulating film HK, the metal film ME1, and the metal film ME2 made of the insulating film 7 is selectively formed in the trench TR1. Here, the insulating film HK is an insulating material film having a dielectric constant (relative dielectric constant) higher than that of silicon nitride, a so-called High-k film (high dielectric constant film). Alternatively, after the step of removing the dummy gate DG, the insulating film 7 may be removed, a gate insulating film GIL may be newly formed on the main surface FBa of the fin FB, and then the insulating film HK may be formed.

  As the insulating film HK, a metal oxide film such as a hafnium oxide film, a zirconium oxide film, an aluminum oxide film, a tantalum oxide film, or a lanthanum oxide film can be used. The insulating film HK can be formed by, for example, an ALD (Atomic layer Deposition) method or a CVD method.

  For example, the metal film ME1 can be a titanium aluminum (TiAl) film, and the metal film ME2 can be an aluminum (Al) film. Further, a threshold voltage of the transistor Tr may be adjusted by interposing a titanium (Ti) film, a titanium nitride (TiN) film, or a laminated film thereof between the metal film ME1 and the metal film ME2.

  The insulating film HK is formed on the bottom (bottom) and the side wall of the trench TR1, and the bottom (bottom) and the side wall (side) of the gate electrode GE are adjacent to the insulating film HK. An insulating film GIL and an insulating film HK are interposed between the gate electrode GE and the fin FB of the semiconductor substrate 1, and an insulating film HK is interposed between the gate electrode GE and the sidewall spacer SW. Yes. The gate insulating film GIL and the insulating film HK immediately below the gate electrode GE function as the gate insulating film of the transistor Tr. However, since the insulating film HK is a high dielectric constant film, it functions as a high dielectric constant gate insulating film.

  FIG. 22 shows the silicide layer SC formation step (step S16). First, a step of forming an insulating film 16 having a predetermined pattern on the semiconductor substrate 1 is performed. The insulating film 16 is made of, for example, a silicon oxide film, and can be formed using a CVD method or the like. The insulating film 16 has a pattern (planar shape) that covers the gate electrode GE of the transistor Tr in the logic part B and exposes the memory cell part A in plan view.

  Next, a metal film is deposited on the semiconductor substrate 1 and subjected to heat treatment, thereby forming a silicide layer SC on the main surfaces of the control gate electrode CG and the memory gate electrode MG. The silicide layer SC is preferably a cobalt silicide layer (when the metal film is a cobalt film), a nickel silicide layer (when the metal film is a nickel film), or a platinum-added nickel silicide layer (the metal film is a nickel platinum alloy film). If). Thereafter, the unreacted metal film is removed by wet etching or the like. FIG. 22 shows a cross-sectional view at this stage. Further, after the unreacted metal film is removed, further heat treatment can be performed. Further, no silicide layer is formed on the gate electrode GE.

  Next, the step of forming the interlayer insulating film IL2, the plug electrode PG, and the metal wiring MW (step S17) will be described with reference to FIG. An interlayer insulating film IL2 is formed on the silicide layer SC. As the interlayer insulating film IL2, for example, a silicon oxide insulating film mainly composed of silicon oxide can be used. After the formation of the interlayer insulating film IL2, the upper surface of the interlayer insulating film IL2 may be polished by CMP to improve the flatness of the upper surface of the interlayer insulating film IL2.

  Next, contact holes (openings, through holes) CNT are formed in the interlayer insulating films IL1 and IL2. The contact hole CNT exposes the surfaces of the source region MS and drain region MD of the memory cell MC and the source region LS and drain region LD of the transistor Tr.

  Next, a conductive plug electrode PG made of tungsten (W) or the like is formed in the contact hole CNT as a conductive member for connection. The plug electrode PG has a laminated structure of a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof) and a main conductor film (tungsten film) located on the barrier conductor film. The plug electrode PG is in contact with and electrically connected to the source region MS and drain region MD of the memory cell MC and the source region LS and drain region LD of the transistor Tr.

  Next, a metal wiring MW is formed on the interlayer insulating film IL2. The metal wiring MW has a laminated structure of a barrier conductor film (for example, a titanium nitride film, a tantalum film, or a tantalum nitride film) and a main conductor film (copper film) formed on the barrier conductor film. In FIG. 3, for simplification of the drawing, the metal wiring MW is shown by integrating the barrier conductor film and the main conductor film. The same applies to the plug electrode PG.

<Operation of nonvolatile memory>
Next, an operation example of the nonvolatile memory will be described with reference to FIG.

  FIG. 23 is an equivalent circuit diagram of the memory cell MC of the nonvolatile memory. FIG. 24 is a table showing an example of voltage application conditions to each part of the selected memory cell at the time of “write”, “erase”, and “read”. The table of FIG. 24 shows the voltage Vmg applied to the memory gate electrode MG of the memory cell (selected memory cell) as shown in FIG. 23 and the source region at the time of “write”, “erase”, and “read”. A voltage Vs applied to the MS, a voltage Vcg applied to the control gate electrode CG, a voltage Vd applied to the drain region MD, and a voltage Vb applied to the p-type well PW1 are described. Note that the table shown in the table of FIG. 24 is a preferred example of the voltage application conditions, and the present invention is not limited to this, and various changes can be made as necessary. In the present embodiment, the electron injection into the insulating film IF2 (silicon nitride film which is a charge storage layer) in the gate insulating film GIm of the memory transistor is “writing”, and the hole is injected. Is defined as “erase”.

  As a writing method, a so-called SSI (Source Side Injection) method called a writing method (hot electron injection writing method) in which writing is performed by hot electron injection by source side injection can be used. For example, a voltage as shown in the “write” column of FIG. 24 is applied to each part of the selected memory cell to be written, and electrons are injected into the insulating film IF2 in the gate insulating film GIm of the selected memory cell. To write. At this time, hot electrons are generated in a channel region (between the source and drain) between the two gate electrodes (memory gate electrode MG and control gate electrode CG), and are a charge storage layer below the memory gate electrode MG. It is injected into the insulating film IF2. That is, hot electrons (electrons) are injected into the insulating film IF2 from the semiconductor substrate 1 side. The injected hot electrons (electrons) are captured by the trap level in the insulating film IF2, and as a result, the threshold voltage of the memory transistor rises. That is, the memory transistor is in a write state.

  The erasing method is based on a so-called FN tunnel method. That is, erasing is performed by injecting holes from the memory gate electrode MG into the insulating film IF2 that is the charge storage layer. For example, a voltage as shown in the “erase” column of FIG. 24 is applied to each part of the selected memory cell to be erased, holes are injected into the insulating film IF2 of the selected memory cell, and the injected electrons and The threshold voltage of the memory transistor is lowered by recombination. That is, the memory transistor is in an erased state.

  At the time of reading, for example, a voltage as shown in the “read” column of FIG. 24 is applied to each part of the selected memory cell to be read. By setting the voltage Vmg applied to the memory gate electrode MG at the time of reading to a value between the threshold voltage of the memory transistor in the writing state and the threshold voltage of the memory transistor in the erasing state, the writing state and the erasing state Can be discriminated.

  Next, FIG. 25A is a cross-sectional view showing a charge trap region of the memory cell of the present embodiment. FIG. 25B is a cross-sectional view showing a charge trapping region of a memory cell which is a comparative example. 25A and 25B show the electron trap region TR (e) and the hole trap region TR (h) included in the insulating film IF2 along one side surface FAs of the fin FA. The electron capture region TR (e) indicates a region where the amount of captured electrons is large, and electrons are captured in regions other than the electron capture region TR (e). The same applies to the hole capture region TR (h). A similar charge trap region is also formed in the insulating film IF2 along the other side surface FAs of the fin FA. Furthermore, although the charge trapping region is also formed in the insulating film IF2 along the main surface FAa, description thereof is omitted.

  As described above, at the time of writing, electrons generated in the substrate 1 (or the well region PW1) are injected into the insulating film IF2 that is a charge storage layer by an electric field between the semiconductor substrate 1 and the memory gate electrode MG. As shown in FIGS. 25A and 25B, since the electric field E (W) is concentrated at the corner of the upper end of the fin FA, the electron trapping region TR (e) is formed in the insulating film IF2 located in the vicinity thereof. Is formed. At the time of erasing, holes in the memory gate MG are injected into the insulating film IF2 which is a charge storage layer by an electric field between the memory gate electrode MG and the semiconductor substrate 1, but FIGS. 25 (a) and 25 (b). As shown in FIG. 2, the electric field E (E) concentrates on the corner of the lower end of the memory gate electrode MG, so that the hole trapping region TR (e) is formed in the insulating film IF2 located in the vicinity thereof.

  As shown in FIG. 25A, in the memory cell MC of the present embodiment, a pad insulating film PAD is formed between the memory gate electrode MG and the element isolation film STM, and the lower end of the memory gate electrode MG is the main of the FA. By raising to the surface FAa side, the hole trapping region TR (h) can be brought close to and overlapped with the electron trapping region TR (e). Therefore, mismatch between the electron distribution and the hole distribution can be reduced, and the endurance of the fin-type nonvolatile memory cell can be improved.

  In the comparative example of FIG. 25B, since the hole trapping region TR (h) is separated from the electron trapping region TR (e), a mismatch between the electron distribution and the hole distribution occurs, and the endurance of the fin-type nonvolatile memory cell. Decreases.

<Main features and effects>
FIG. 26 is a plan view of an essential part of the semiconductor device according to the present embodiment. FIG. 26 is a fragmentary cross-sectional view of the memory cell portions A2 and A3 and the logic portion B2.

  First, the memory cell portions A2 and A3 will be described.

  Unlike the height Hcg of the lower surface of the control gate electrode CG, the height Hmg of the lower surface of the memory gate electrode MG is higher than the height Hcg of the lower surface of the control gate electrode CG. Here, the height is based on the back surface 1 b of the semiconductor substrate 1. Further, the lower surface means the lower surface at the corner portion outside the fin FA and where the memory gate electrode MG or the control gate electrode CG is close to both the fin FA and the element isolation film STM.

The height Hmg of the lower surface of the memory gate electrode MG is higher than the height Hcg of the lower surface of the control gate electrode CG by the film thickness of the insulating film IF2, the pad insulating film PAD, and the insulating film IF3. Formula (Formula 1) holds.
Hmg = Hcg + D (IF2 + IF3 + PAD) (Formula 1)
Here, D (IF2 + IF3 + PAD) is the total film thickness of the insulating film IF2, the insulating film IF3, and the pad insulating film PAD. That is, the insulating film IF2, the pad insulating film PAD, and the insulating film IF3 exist between the memory gate electrode MG and the element isolation film STM, and do not exist between the control gate electrode CG and the element isolation film STM.

Further, since the pad insulating film PAD is not formed under the control gate electrode CG but under the memory gate electrode MG, the following relational expression (Formula 2) also holds.
Hmg> Hcg + D (IF2 + IF3) (Formula 2)
Here, D (IF2 + IF3) is the total film thickness of the insulating film IF2 and the insulating film IF3.

  Further, the overlap amount OLmg between the memory gate electrode MG and the side surface FAs of the fin FA is different from the overlap amount OLcg between the control gate electrode CG and the side surface FAs of the fin FA and is smaller than the overlap amount OLcg. Note that the overlap amount is sometimes called an overlap length, an overlap amount, and an overlap length.

Further, the insulating film IF2, the pad insulating film PAD, and the insulating film IF3 exist between the memory gate electrode MG and the element isolation film STM, but do not exist between the control gate electrode CG and the element isolation film STM. Further, in the step of forming the insulating film IF1, the main surface FAa of the fin FA below the memory gate electrode MG is lowered by the film thickness of the insulating film IF1, so the following relational expression (Formula 3) is established.
OLmg = OLcg-D (IF1 + IF2 + IF3 + PAD) (Formula 3)
Here, D (IF1 + IF2 + IF3 + PAD) is the total film thickness of the insulating film IF1, the insulating film IF2, the insulating film IF3, and the pad insulating film PAD.

Further, since the pad insulating film PAD is not formed under the control gate electrode CG but is formed under the memory gate electrode MG, the following relational expression (Formula 4) also holds.
OLmg <OLcg-D (IF1 + IF2 + IF3) (Formula 4)
Here, D (IF1 + IF2 + IF3) is the total film thickness of the insulating film IF1, the insulating film IF2, and the insulating film IF3.

  Due to the above feature, since the pad insulating film PAD is not formed under the control gate electrode CG but under the memory gate electrode MG, for example, the overlap amount of the control gate electrode CG and the fin FA The amount of overlap between the memory gate electrode MG and the fin FA can be reduced without reducing. Therefore, the drive capability of the control transistor CT and the endurance of the memory transistor MT can be improved. That is, the performance of a semiconductor device having a fin-type nonvolatile memory can be improved.

  Further, by using the fin type nonvolatile memory, the subthreshold characteristic is improved, and high-speed reading is possible.

  Next, the memory cell part A3 and the logic part B2 will be described.

  The logic part B2 is not provided with the pad insulating film PAD. That is, the pad insulating film PAD exists between the memory gate electrode MG and the element isolation film STM, and does not exist between the gate electrode GE and the element isolation film STL. The height Hmg of the lower surface of the memory gate electrode MG is different from the height Hge of the lower surface of the gate electrode GE, and is higher than the height Hge of the lower surface of the gate electrode GE.

  Further, the overlap amount OLge between the gate electrode GE and the side surface FBs of the fin FB is different from the overlap amount OLmg between the memory gate electrode MG and the side surface FAs of the fin FA. Greater than amount OLmg.

  By increasing the overlap amount OLge between the gate electrode GE of the transistor Tr of the logic part B and the side surface FBs of the fin FB, the driving capability of the transistor Tr can be improved and high-speed operation is possible. In addition, the driving capability of the transistor Tr can be improved, and the endurance of the memory transistor MT can be improved.

  Further, according to the manufacturing method of the present embodiment, since the pad insulating film PAD is formed on the insulating film 11, in the step of forming the pad insulating film PAD (step S8), the gate below the control gate electrode CG It can be prevented that side etching enters the insulating film GIt and the characteristics of the control transistor CT deteriorate.

  That is, as shown in FIG. 12, the insulating film 11 made of a silicon nitride film is interposed between the insulating film 12 made of a silicon oxide film and the gate insulating film GIt for forming the pad insulating film PAD. Therefore, as shown in FIG. 13, when the insulating film 12 is isotropically etched to form a pad insulating film PAD lower than the fin FA, the insulating film 11 functions as an etching stopper. The side etching of GIt can be prevented.

<Modification 1>
Modification 1 is a modification of the above-described embodiment, and the formation position of the pad insulating film PAD2 is different. Other features are the same as in the above embodiment. FIG. 27 is a cross-sectional view of a main part of the semiconductor device according to the first modification. In the memory cell portion A3, the pad insulating film PAD2 is disposed under the insulating film IF2. In other words, it is disposed between the insulating film IF2 and the element isolation film STM. The pad insulating film PAD2 has the same film quality (film material) and film thickness as the pad insulating film PAD of the above embodiment. The pad insulating film PAD2 is formed under the memory gate electrode MG, and is not formed over the main surface FAa of the fin FA, under the control gate electrode CG, and in the logic part B.

  Next, a method for manufacturing the semiconductor device of Modification 1 will be described. 28 to 30 are main-portion cross-sectional views during the manufacturing process of the semiconductor device in Modification 1.

  In the above embodiment, the formation process (step S8) of the pad insulation film PAD is performed after the formation process (step S7) of the insulation films 10 and 11 described with reference to FIG. After the step of forming the pad insulating film PAD2 (Step S8), the step of forming the insulating films 10 and 11 (Step S7) is performed. The other steps are the same as in the above embodiment.

  FIG. 28 shows a part of the process of forming the pad insulating film PAD2 (step S8) described later. After the above-described control gate electrode CG formation step (step S6), in the memory cell portion A3, the insulating film 12 having a film thickness equal to or larger than the height of the fin FA is formed so as to cover the main surface FAa and the side surface FAs of the fin FA. Form. The insulating film 12 is made of, for example, a silicon oxide film. In order to form the insulating film 12, a silicon oxide film is deposited on the main surface FAa and the side surface FAs of the fin FA, and this silicon oxide film is subjected to CMP polishing on the control gate electrodes CG of the memory cell portions A1 and A2. The insulating film 12 is formed by exposing the formed insulating film 9.

  FIG. 29 shows a part of the process of forming the pad insulating film PAD2 (step S8) following FIG. Isotropic etching is performed on the insulating film 12 to remove the insulating film 12 on the main surface FAa of the fin FA. Further, isotropic etching is continued to selectively leave the insulating film 12 on the element isolation film STM and form the pad insulating film PAD2. The film thickness of the pad insulating film PAD2 and the formation region in plan view are the same as those of the pad insulating film PAD.

  FIG. 30 shows a step of forming insulating films 10 and 11 (step S7) and a step of forming insulating film 13 (step S9) following the step of forming pad insulating film PAD2. Insulating films 10 and 11 are formed in this order on main surface FAa and side surface FAs of fin FA. The insulating film 10 is a silicon oxide film formed by thermally oxidizing the main surface FAa and the side surface FAs of the fin FA, and the film thickness thereof is 4 nm, which is larger than the film thickness of the gate insulating film GIt. Next, the insulating film 11 is made of a silicon nitride film and has a thickness of 7 nm. Next, the insulating film 13 is formed on the insulating film 11. The insulating film 13 is made of, for example, a silicon oxynitride film and has a thickness of 9 nm. The insulating films 11 and 13 are formed on the pad insulating film PAD2 in the memory cell portion A3. After this, the process after step S10 of the said embodiment is implemented.

  According to the method of manufacturing the semiconductor device of the first modification, after the pad insulating film PAD2 is formed, the insulating film 11 serving as the charge storage layer is formed, so that the surface of the insulating film 11 is in the process of forming the pad insulating film PAD2. No etching damage. That is, it is possible to prevent deterioration of charge retention characteristics due to etching damage of the insulating film 11.

<Modification 2>
Modified example 2 is a modified example of the above embodiment, and the above embodiment is a split gate type cell. However, modified example 2 is a nonvolatile memory composed of a single gate type cell. It is. The gate electrode structure of the transistor in the logic part is also different.

  In the second modification, symbols such as the memory cell MC2, the memory gate electrode MG2, the pad insulating film PAD3, the transistor Tr2, and the gate electrode GE2 are used. In addition, the same code | symbol is attached | subjected to the part which is common in the said embodiment.

  FIG. 31 is a main part plan view of the semiconductor device according to the second modification. FIG. 32 is a cross-sectional view of main parts of a semiconductor device according to Modification 2. In FIG. 32, two cross-sectional views of the memory cell portion A and two cross-sectional views of the logic portion B are shown. The memory cell portion A1 is a cross-sectional view taken along A1-A1 ′ in FIG. 31, the memory cell portion A3 is a cross-sectional view taken along A3-A3 ′ in FIG. 31, and the logic portion B1 is taken along B1-B1 ′ in FIG. The cross-sectional view and the logic part B2 are cross-sectional views taken along B2-B2 'of FIG.

  As shown in FIG. 31, in the memory cell portion A, a plurality of fins FA extending in the X direction are arranged at equal intervals in the Y direction. A plurality of memory gate electrodes MG2 extending in the Y direction (direction orthogonal to the X direction) are arranged on the plurality of fins FA so as to intersect the plurality of fins FA. A drain region MD and a source region MS are formed at both ends of the memory gate electrode MG2 so as to sandwich the memory gate electrode MG2. That is, the memory cell MC2 is a single gate type cell.

  Further, the transistor Tr2 in the logic part B has the gate electrode GE2 and the drain region LD and the source region LS formed in the fin FB at both ends of the gate electrode GE2 so as to sandwich the gate electrode GE2. .

  Next, the structure of the memory cell MC2 and the transistor Tr2 will be described with reference to FIG.

  The memory cell MC2 has a memory gate electrode (gate electrode) MG2, a drain region MD, and a source region MS. The memory gate electrode (gate electrode) MG2 is formed along the main surface FAa and the side surface FAs of the fin FA, and there is a gate between the memory gate electrode MG2 and the semiconductor substrate 1 (or the p-type well PW1). An insulating film GIm is interposed. The gate insulating film GIm has a stacked structure of the above-described insulating films IF1, IF2, and IF3. In the memory cell portion A, a pad insulating film PAD3 is formed outside (around) the fin FA.

  In the logic part B, the gate electrode GE2 is formed on the main surface FBa and the side surface FBs of the fin FB via the gate insulating film GIL, and the fin FB includes a drain region so as to sandwich the gate electrode GE2. LD and source region LS are formed. In the logic part B, the pad insulating film PAD3 is not formed.

  Next, a method for manufacturing the semiconductor device of Modification 2 will be described. 33 to 38 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of Modification 2.

  First, steps S1 to S4 of the above embodiment are performed to prepare the semiconductor substrate 1 having the fins FA and FB shown in FIG.

  Next, as shown in FIG. 34, step S7 of the above embodiment is performed. The aforementioned insulating films 10 and 11 are formed in this order on the main surface FAa and side surface FAs of the fin FA and the main surfaces FBa and FBs of the fin FB.

  FIG. 34 shows a part of the process of forming a pad insulating film PAD3 (step S8) described later. In the memory cell portion A3 and the logic portion B2, the insulating film 12 having a film thickness equal to or greater than the height of the fins FA and FB is formed so as to cover the main surface FAa and the side surface FAs of the fin FA and the main surface FBa and the side surface FBs of the fin FB. Form. The insulating film 12 is made of, for example, a silicon oxide film. In order to form the insulating film 12, a silicon oxide film is deposited on the insulating film 11, and this silicon oxide film is subjected to CMP polishing, and the insulating film 11 formed on the memory gate electrodes MG of the memory cell portions A1 and A3. The insulating film 12 is formed by exposing.

  FIG. 35 shows a part of the process of forming the pad insulating film PAD3 (step S8) following FIG. A pad insulating film PAD3 is formed as in the above embodiment. In the second modification, the pad insulating film PAD3 is also formed in the logic part B2.

  Next, as shown in FIG. 35, the step of forming the insulating film 13 (step S9) is performed. An insulating film 13 is formed on the pad insulating film PAD3.

  Next, as shown in FIG. 36, for example, the insulating films 13, 11, and 10 of the logic part B are covered with a resist film (not shown) that covers the memory cell part A and exposes the logic part B as a mask. In addition, after the pad insulating film PAD3 is removed and the main surface FBa and the side surface FBs of the fin FB are exposed, the insulating film 20 is formed on the main surface FBa and the side surface FBs of the fin FB. The insulating film 20 is made of a silicon oxide film, a silicon oxynitride film, a high-k film, or a laminated film thereof. Note that the resist film that covers the memory cell portion A and exposes the logic portion B is removed before the insulating film 20 is formed.

  Next, as shown in FIG. 37, the step of forming the memory gate electrode MG (step S10) is performed. After the conductor film 14 is deposited on the insulating film 13 and the insulating film 20, the conductor film 14 is subjected to CMP treatment to flatten the surface of the conductor film 14. Next, the conductive film 14 is patterned to form the memory gate electrode MG2 in the memory cell portion A and the gate electrode GE2 in the logic portion B. Furthermore, the insulating films 13, 11, and 10 are etched to form insulating films IF3, IF2, and IF1 having a planar shape equal to the memory gate electrode MG2. The insulating films IF3, IF2, and IF1 function as the gate insulating film GIm of the memory cell MC2. In the logic part B, the insulating film 20 is processed into a planar shape equal to the gate electrode GE2, thereby forming the gate insulating film GIL.

In addition, as shown in FIG. 37, the step of forming n ⁻ type semiconductor regions (impurity diffusion layers) EX1, EX2 and EX3 (step S12) is performed, and n ⁻ type semiconductor regions EX1 and EX2 are formed at both ends of the memory gate electrode MG2. In EX2, n ⁻ type semiconductor regions EX3 are formed at both ends of the gate electrode GE2.

Next, as shown in FIG. 38, a step of forming sidewall spacers SW and n ⁺ type semiconductor regions (impurity diffusion layers) SD1, SD2, SD3 (step S13) is performed. Then, sidewall spacers SW are formed on the sidewalls of the memory gate electrode MG2 and the gate electrode GE2. Further, n ⁺ type semiconductor regions SD1 and SD2 are formed at both ends of the memory gate electrode MG2, and n ⁺ type semiconductor regions SD3 are formed at both ends of the gate electrode GE2.

  Further, the silicide layer SC forming step (step S16) and the step of forming the interlayer insulating film IL2, the plug electrode PG, and the metal wiring MW (step S17) are performed, and the semiconductor device of the modified example 2 shown in FIG. 32 is completed. To do.

  Next, an operation example of the nonvolatile memory according to Modification 2 will be described with reference to FIG.

  FIG. 39 is an equivalent circuit diagram of the memory cell MC2 of the second modification. FIG. 40 is a table showing an example of voltage application conditions to each part of the selected memory cell at the time of “write” and “erase”. In the table of FIG. 40, the voltage Vmg applied to the memory gate electrode MG2 of the memory cell (selected memory cell) as shown in FIG. 39 and the source region MS are applied at the time of “write” and “erase”. The voltage Vs, the voltage Vd applied to the drain region MD, and the voltage Vb applied to the p-type well PW1 are described. Note that what is shown in the table of FIG. 40 is a preferred example of voltage application conditions, and is not limited to this, and can be variously changed as necessary. Further, in the present embodiment, the injection of electrons into the insulating film IF2 (silicon nitride film that is a charge storage layer) in the gate insulating film GIm of the memory cell MC2 is “writing”, and holes (holes) are formed. The injection is defined as “erase”.

  As the writing method, a so-called CHE (Channel Hot Electron: Channel Hot Electron Injection) method can be used. For example, a voltage as shown in the “write” column of FIG. 40 is applied to each part of the selected memory cell to be written, and electrons are injected into the insulating film IF2 in the gate insulating film GIm of the selected memory cell. To write. At this time, hot electrons are generated in the channel region (between the source and drain) under the memory gate electrode MG2, and injected into the insulating film IF2 which is a charge storage layer under the memory gate electrode MG2. That is, hot electrons (electrons) are injected into the insulating film IF2 from the semiconductor substrate 1 side. The injected hot electrons (electrons) are captured by the trap level in the insulating film IF2, and as a result, the threshold voltage of the memory cell rises. That is, the memory cell is in a write state.

  The erasing method is based on a so-called FN tunnel method. That is, erasing is performed by injecting holes from the memory gate electrode MG2 into the insulating film IF2 that is the charge storage layer. For example, a voltage as shown in the “erase” column of FIG. 40 is applied to each part of the selected memory cell to be erased, holes are injected into the insulating film IF2 of the selected memory cell, and the injected electrons and The threshold voltage of the memory cell is lowered by recombination. That is, the memory cell is in an erased state.

  As described above, at the time of “writing”, electrons are injected from the semiconductor substrate 1 side into the insulating film IF2 that is the charge storage layer, and at the time of “erasing”, holes are injected from the memory gate electrode MG2 to the insulating film IF2. Therefore, it is effective to provide the pad insulating film PAD3 even in the fin-type nonvolatile memory cell of the second modification. That is, even in the single gate type cell in which the memory gate electrode MG2 and the insulating film IF2 that is the charge storage layer are formed along the main surface FAa and the side surface FAs of the fin FA, when the pad insulating film PAD3 is not provided, FIG. This is because, as described in (b), a mismatch between the electron distribution and the hole distribution occurs, and the endurance of the fin-type nonvolatile memory cell is lowered.

  Also in the second modification, the pad insulating film PAD3 exists between the memory gate electrode MG2 and the element isolation film STM, and does not exist between the gate electrode GE2 and the element isolation film STL. Therefore, the relationship between the memory gate electrode MG and the gate electrode GE of the transistor Tr in the logic portion B2 described in the above embodiment with reference to FIG. That is, the height Hmg2 of the lower surface of the memory gate electrode MG2 is different from the height Hge2 of the lower surface of the gate electrode GE2, and is higher than the height Hge2 of the lower surface of the gate electrode GE2. Further, the overlap amount OLge2 between the gate electrode GE2 and the side surface FBs of the fin FB is different from the overlap amount OLmg2 between the memory gate electrode MG and the side surface FAs of the fin FA. Greater than amount OLmg2.

  By reducing the overlap amount OLmg2 between the memory gate electrode MG2 and the side surface FAs of the fin FA, the endurance of the memory cell MC2 can be improved. Further, by increasing the overlap amount OLge2 between the gate electrode GE of the transistor Tr of the logic part B and the side surface FBs of the fin FB, the driving capability of the transistor Tr can be improved, and high-speed operation is possible.

<Modification 3>
Modified example 3 is a modified example of the above-described embodiment, and is a semiconductor device having a non-volatile memory composed of a single gate type cell as in modified example 2, but instead of the pad insulating film PAD3 of modified example 2 being absent. The difference is that the element isolation film STM2 of the memory cell portion A is thickened. FIG. 41 is a cross-sectional view of a principal part of the semiconductor device of the third modification. 42 is a main-portion cross-sectional view of the semiconductor device of Modification 3 during the manufacturing process.

  As shown in FIG. 41, the element isolation film STM2 of the memory cell part A is thicker than the element isolation film STL of the logic part B. That is, the film thickness of the element isolation film STM2 in the memory cell part A is equal to the film thickness of the element isolation film STL in the logic part B plus the film thickness of the pad insulating film PAD3 in Modification 2. Accordingly, the amount of overlap between the memory gate electrode MG2 and the side surface FAs of the fin FA, the height of the lower surface of the memory gate electrode MG2, the amount of overlap between the gate electrode GE2 and the side surface FBs of the fin FB, and the lower surface of the gate electrode GE2 Is the same as that of the second modification.

  Next, a method for manufacturing the semiconductor device of Modification 3 will be described. In the above embodiment, in the step of forming the element isolation films STM and STL in FIG. 8 (step S4), the insulating film 6 is subjected to an etching process, and the main surface 6a of the insulating film 6 is retracted to isolate the elements having the same height. Films STM and STL were formed. In the third modification, the insulating film 6 is etched in two stages. That is, in the first stage, the element isolation film STM2 of the memory cell part A is formed in the memory cell part A and the logic part B, and in the second stage, the memory cell part A is covered with, for example, a resist film (not shown). In this state, by selectively etching the insulating film 6 of the logic part B, the element isolation film STL of the logic part B is formed. Thus, the element isolation films STM2 and STL having different thicknesses can be formed. That is, the semiconductor substrate 1 having the fins FA and FB having different exposure heights from the element isolation films STM2 and STL can be prepared.

  Next, the semiconductor device of Modification 3 can be manufactured by the same manufacturing method as that of Modification 2. However, the formation process of the pad insulating film PAD3 of Modification 2 is not performed.

  In the manufacturing method of Modification 3, since the pad insulating film is not formed by increasing the thickness of the element isolation film STM2, the insulating film 11 serving as the charge storage layer is subjected to etching damage as in Modification 1. And the deterioration of charge retention characteristics can be prevented.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In addition, a part of the contents described in the above embodiment will be described below.

[Appendix 1]
A protrusion protruding from the upper surface of the semiconductor substrate in a direction perpendicular to the upper surface, having a width in the first direction of the upper surface, and extending in a second direction orthogonal to the first direction;
An element isolation film located on the upper surface of the semiconductor substrate so as to be in contact with the protruding portion and surround a lower end portion of the protruding portion;
A first gate electrode disposed in the first region of the upper surface of the semiconductor substrate and extending in the first direction on the protrusion and the element isolation film;
A second gate electrode disposed in a second region different from the first region on the upper surface of the semiconductor substrate and extending in the first direction on the protrusion and the element isolation film;
A method of manufacturing a semiconductor device having
(A) preparing a semiconductor substrate having the protrusion and the element isolation film;
(B) forming the first gate electrode on the side surface of the protrusion in the first region via a first gate insulating film;
(C) forming a second gate insulating film having a charge storage layer on the side surface of the protruding portion, the element isolation film, and the first gate electrode in the second region;
(D) after depositing a first insulating film on the second gate insulating film, removing the first insulating film formed on the protruding portion and the first gate electrode, and in the second region, Forming a pad insulating film made of the first insulating film on the element isolation film;
(E) forming the second gate electrode on the second gate insulating film and on the element isolation film formed on the side surface of the protrusion in the second region;
A method for manufacturing a semiconductor device, comprising:

[Appendix 2]
In the method for manufacturing a semiconductor device according to attachment 1,
The method of manufacturing a semiconductor device, wherein in the step (d), the first gate electrode and the first gate insulating film are covered with the second gate insulating film.

[Appendix 3]
In the method for manufacturing a semiconductor device according to attachment 2,
The method for manufacturing a semiconductor device, wherein the first gate insulating film and the first insulating film are made of a silicon oxide film, and the second gate insulating film is made of a silicon nitride film.

[Appendix 4]
In the method for manufacturing a semiconductor device according to attachment 1,
Between the step (d) and the step (e),
(F) forming a second insulating film on the second insulating film and on the pad insulating film of the protrusion in the second region;
A method for manufacturing a semiconductor device, comprising:

[Appendix 5]
A protrusion protruding from the upper surface of the semiconductor substrate in a direction perpendicular to the upper surface, having a width in the first direction of the upper surface, and extending in a second direction orthogonal to the first direction;
An element isolation film located on the upper surface of the semiconductor substrate so as to be in contact with the protruding portion and surround a lower end portion of the protruding portion;
A first gate electrode disposed in the first region of the upper surface of the semiconductor substrate and extending in the first direction on the protrusion and the element isolation film;
A second gate electrode disposed in a second region different from the first region on the upper surface of the semiconductor substrate and extending in the first direction on the protrusion and the element isolation film;
A method of manufacturing a semiconductor device having
(A) preparing a semiconductor substrate having the protrusion and the element isolation film;
(B) forming the first gate electrode on the side surface of the protrusion in the first region via a first gate insulating film;
(C) After depositing a first insulating film so as to cover the protruding portion, the first insulating film formed on the protruding portion and the first gate electrode is removed, and in the second region, Forming a pad insulating film made of the first insulating film on the element isolation film;
(D) forming a second gate insulating film having a charge storage layer on the side surface of the protruding portion and the pad insulating film in the second region;
(E) forming the second gate electrode on the second gate insulating film and on the element isolation film formed on the side surface of the protrusion in the second region;
A method for manufacturing a semiconductor device, comprising:

[Appendix 6]
(A) a first protrusion projecting in a direction perpendicular to the upper surface thereof, formed in a first region of the upper surface, a second protrusion formed in a second region different from the first region, and the first A semiconductor having a first element isolation film that contacts a lower part of the protrusion and surrounds the first protrusion, and a second element isolation film that contacts the lower part of the second protrusion and surrounds the second protrusion Preparing a substrate,
(B) forming a first insulating film having a charge storage layer on the first protrusion, the first element isolation film, the second protrusion, and the second element isolation film;
(C) After depositing a second insulating film on the first insulating film, etching is performed on the second insulating film, and the second insulating film is formed on the first element separating film and the second element separating film. Forming a pad insulating film made of an insulating film;
(D) forming a third insulating film on the first protrusion, the pad insulating film on the first element isolation film, the second protrusion, and the pad insulating film on the second element isolation film; The process of
(E) removing the third insulating film and the second insulating film in the second region;
(F) forming a first conductor film on the third insulating film in the one region;
(G) forming a second conductor film on the second protrusions in the two regions;
A method for manufacturing a semiconductor device, comprising:

[Appendix 7]
(A) a semiconductor projecting in a direction perpendicular to the upper surface, and having a first projecting portion formed in a first region of the upper surface and a second projecting portion formed in a second region different from the first region; Preparing a substrate,
(B) a first element isolation film that contacts the lower portion of the first protrusion and surrounds the first protrusion; and a second element isolation that contacts the lower portion of the second protrusion and surrounds the second protrusion. Forming a film;
(C) forming a first insulating film having a charge storage layer on the first protrusion and the first element isolation film;
(D) forming a first conductor film on the second insulating film after forming a second insulating film on the first insulating film;
(E) forming a second conductor film on the third insulating film after forming a third insulating film on the second projecting portion;
Have
The method of manufacturing a semiconductor device, wherein the first element isolation film is thicker than the second element isolation film.

A, A1, A2, A3 Memory cell portion B, B1, B2 Logic portion BL Bit line CG Control gate electrode CHP Semiconductor chip CNT Contact hole CT Control transistor DG Dummy gate EX1, EX2, EX3 n ^- type semiconductor region FA, FB Fin FAa, FBa Main surface FAs, FBs Side surface GE, GE2 Gate electrode GIm, GIt, GIL Gate insulating film HK Insulating film IF1, IF2, IF3 Insulating film IL1, IL2 Interlayer insulating film LD Drain region LS Source region MC, MC2 Memory cell MD drain region ME1, ME2 metal film MG memory gate electrode MS source region MT memory transistors MW metal interconnect pAD pad insulating film PG plug electrode PR1 resist film PW1, PW2 p-type well SC silicide layer SD1, SD2, SD3 ^{n +} -type half Conductor region SL Source line SP Spacer STM, STM2, STL Element isolation film STMa, STLa Main surface SW Side wall spacer Tr, Tr2 Transistor TR1 Groove 1 Semiconductor substrate 1a Main surface (upper surface)
1b Back surface 2, 3, 6, 7, 9, 10, 11, 12, 13, 16 Insulating film 4, 15 Mask film 5 Hard mask film 6a Main surface 8, 14 Conductor film 100 CPU
200 RAM
300 Analog circuit 400 EEPROM
500 Flash memory 600 I / O circuit

Claims (7)

A semiconductor substrate having an upper surface;
An element isolation film formed on the upper surface of the semiconductor substrate;
A part of the semiconductor substrate, penetrating the element isolation film, protruding in a direction perpendicular to the upper surface, and opposing the first side surface and the second side surface, and the first side surface and the second side surface. A first protrusion having a first main surface to be connected;
A part of the semiconductor substrate, penetrating the element isolation film, protruding in a direction perpendicular to the top surface, and facing the third side surface and the fourth side surface, and the third side surface and the fourth side surface. A second protrusion having a second main surface to be connected;
A first gate electrode disposed on the first side surface via a first insulating film, a second insulating film serving as a charge storage layer, and a third insulating film;
A second gate electrode disposed on the third side surface via a fourth insulating film;
A first semiconductor region and a second semiconductor region formed in the first protrusion so as to sandwich the first gate electrode;
A third semiconductor region and a fourth semiconductor region formed in the second protrusion so as to sandwich the second gate electrode;
A fifth insulating film disposed between the element isolation film and the first gate electrode;
Have
Wherein in the direction perpendicular to the top surface, the first overlap length the first gate electrode overlaps the first aspect, rather smaller than the second overlap length the second gate electrode overlaps with the third aspect,
The semiconductor device, wherein the fifth insulating film is not disposed between the element isolation film and the second gate electrode . The semiconductor device according to claim 1 ,
The second insulating film extends on the element isolation film,
The fifth insulating film is disposed between said first gate electrode and the second insulating film, the semiconductor device. The semiconductor device according to claim 1 ,
The second insulating film extends on the element isolation film,
The fifth insulating film is a semiconductor device disposed between the second insulating film and the element isolation film. The semiconductor device according to claim 1 ,
The semiconductor device, wherein the second insulating film is made of a silicon nitride film. The semiconductor device according to claim 4 ,
The semiconductor device, wherein the first insulating film and the third insulating film are made of a silicon oxide film. A semiconductor substrate having an upper surface;
An element isolation film formed on the upper surface of the semiconductor substrate;
A part of the semiconductor substrate, penetrating the element isolation film, protruding in a direction perpendicular to the upper surface, and opposing the first side surface and the second side surface, and the first side surface and the second side surface. A first protrusion having a first main surface to be connected;
A part of the semiconductor substrate, penetrating the element isolation film, protruding in a direction perpendicular to the top surface, and facing the third side surface and the fourth side surface, and the third side surface and the fourth side surface. A second protrusion having a second main surface to be connected;
A first gate electrode disposed on the first side surface via a first insulating film, a second insulating film serving as a charge storage layer, and a third insulating film;
A second gate electrode disposed on the third side surface via a fourth insulating film;
A first semiconductor region and a second semiconductor region formed in the first protrusion so as to sandwich the first gate electrode;
A third semiconductor region and a fourth semiconductor region formed in the second protrusion so as to sandwich the second gate electrode;
Have
In a direction perpendicular to the top surface, the first overlap length where the first gate electrode overlaps the first side surface is smaller than the second overlap length where the second gate electrode overlaps the third side surface,
A semiconductor device, wherein a thickness of the element isolation film overlapping the first gate electrode is larger than a thickness of the element isolation film overlapping the second gate electrode. The semiconductor device according to claim 6.
The height of the portion of the first protrusion exposed from the element isolation film is lower than the height of the portion of the second protrusion exposed from the element isolation film.

Images