JP6563601B2 - Multi-level pulser and related apparatus and method - Google Patents

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a "MULTI--" filed on Dec. 2, 2015 under Attorney Docket No. B1348.70019US00, which is incorporated herein by reference in its entirety. We continue to allege the benefit of US Patent Application No. 14 / 957,382, entitled “LEVEL PULSER AND RELATED APPARATUS AND METHODS”.

[0002] This application is also referred to as “LEVEL SHIFTER AND RELATED METHODS AND, filed Dec. 2, 2015 under Attorney Docket No. B1348.70020US00, which is incorporated herein by reference in its entirety. US Patent Application No. 14 / 957,398, entitled “APPARATUS (Level Shifters and Related Methods and Apparatus)”, continues to claim the benefit of Section 120 of the US Patent Act.

[0003] The present application relates to an ultrasonic device having a multi-level pulser and / or a level shifter.

[0004] Ultrasound devices can be used to perform diagnostic imaging and / or treatment. Ultrasound imaging can be used to view internal soft tissue body structures. Ultrasound imaging can be used to find pathogens or to eliminate any lesions. Ultrasound devices use sound waves having a frequency higher than that audible to humans. An ultrasound image is created by transmitting a pulse of ultrasound into the tissue using a probe. Sound waves reflect off tissue and different tissues reflect varying degrees of sound. These reflected sound waves can be recorded and displayed as an image to the operator. The intensity (amplitude) of the acoustic signal and the time it takes for the wave to travel through the body provide information used to generate the image.

[0005] Many different types of images can be formed using an ultrasound device. The image can be a real-time image. For example, an image can be generated that shows a two-dimensional cross-section of the tissue, blood flow, tissue movement over time, blood location, the presence of certain molecules, tissue stiffness, or the structure of a three-dimensional region.

[0006] According to an aspect of the present application, at least one ultrasonic transducer and a multi-level pulsar coupled to the at least one ultrasonic transducer, the plurality of inputs configured to receive respective input voltages A first transistor having a first conductivity type coupled to the first diode and a second diode coupled in parallel, the output terminal configured to provide an output voltage, and a first transistor having a first conductivity type coupled to the first diode; An apparatus and method directed to the apparatus is provided that includes a multi-level pulser that includes a signal path between a first input terminal and an output terminal that includes a second transistor having two conductivity types.

[0007] According to an aspect of the present application, a plurality of input terminals configured to receive respective input voltages, an output terminal configured to provide an output voltage, and a first diode coupled A multi-channel including a signal path between a first input terminal and an output terminal, comprising a transistor having a first conductivity type and a transistor having a second conductivity type coupled to a second diode connected in parallel Devices and methods for level pulsars are provided.

[0008] According to an aspect of the present application, an apparatus is provided comprising at least one ultrasonic transducer on a substrate and a level shifter on the substrate coupled to the at least one ultrasonic transducer. The level shifter includes an input terminal configured to receive an input voltage, an output terminal configured to provide an output voltage level shifted from the input voltage, and a capacitor coupled between the input terminal and the output terminal. including. The level shifter further includes a diode coupled in a reverse bias configuration between the input to the active high voltage device and the first voltage of the high voltage power supply. In some such embodiments, the input of the active high voltage element is coupled to the output of the capacitor.

[0009] According to an aspect of the present application, an input terminal configured to receive an input voltage, an output terminal configured to provide an output voltage level-shifted from the input voltage, the input terminal and the output terminal A level shifter is provided comprising a capacitor coupled between and a diode coupled in a reverse bias configuration between the input to the active high voltage device and the first voltage of the high voltage power supply. In some embodiments, the input of the active high voltage element is coupled to the output of the capacitor.

[0010] Various aspects and embodiments of the application are described with reference to the following figures. It should be understood that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference number in all figures.

[0011] FIG. 1 is a block diagram of an ultrasound device including a multi-level pulser and / or level shifter according to a non-limiting embodiment of the present application. [0012] FIG. 4 is a non-limiting circuit diagram of a multi-level pulsar according to a non-limiting embodiment of the present application. [0013] FIG. 6 is a circuit diagram of a first embodiment of a level shifter according to a non-limiting embodiment of the present application; [0014] FIG. 6 is a circuit diagram of a second embodiment of a level shifter according to a non-limiting embodiment of the present application. [0015] FIG. 3 is a non-limiting equivalent circuit of the circuit of FIG. 2 in a first stage of multi-level pulse formation according to a non-limiting embodiment of the present application. [0016] FIG. 3 is a non-limiting equivalent circuit of the circuit of FIG. 2 in a second stage of multi-level pulse formation according to a non-limiting embodiment of the present application. [0017] FIG. 3 is a non-limiting equivalent circuit of the circuit of FIG. 2 in a third stage of multi-level pulse formation according to a non-limiting embodiment of the present application. [0018] FIG. 6 is a non-limiting equivalent circuit of the circuit of FIG. 2 in a fourth stage of multi-level pulse formation according to a non-limiting embodiment of the present application. [0019] FIG. 6 is a non-limiting equivalent circuit of the circuit of FIG. 2 in a fifth stage of multi-level pulse formation according to a non-limiting embodiment of the present application. [0020] FIG. 6 is a non-limiting equivalent circuit of the circuit of FIG. 2 in the sixth stage of multi-level pulse formation according to a non-limiting embodiment of the present application. [0021] FIG. 7 is a graph illustrating non-limiting examples of time-dependent multi-level pulses and control signals according to a non-limiting embodiment of the present application.

[0022] The inventors have recognized and understood that the power required to transmit a high intensity pulse can be significantly reduced by forming an electrical pulse having multiple levels.

[0023] Aspects of the present application may be used to treat diseased or damaged tissue by focusing high intensity ultrasound energy on a target and selectively raising the temperature of the target or a region surrounding the target. It relates to a high intensity focused ultrasound (HIFU) procedure. The HIFU procedure can be used for therapeutic or ablation purposes. The pulsed signal can be used to generate a HIFU. According to aspects of the present application, the generation of such high intensity pulses may require drive voltages of tens to hundreds of volts.

[0024] The power consumption associated with generating a typical two-level pulse having a "low" voltage and a "high" voltage is proportional to the square of the high voltage. For example, the generation of a two-level pulse having a “low” voltage equal to 0 requires power equal to P ₍₂₎ = C ^* V ^{2 *} f. Where P ₍₂₎ is the power required to generate the two-level pulse, C is the capacitance of the load that receives the pulse, V is the “high” voltage, and f is the two-level pulse. It is a repetition frequency.

[0025] According to aspects of the present application, the power consumption associated with generating pulses for the HIFU procedure can exceed tens to thousands of watts, thus causing the circuit to generate a significant amount of heat.

[0026] Aspects of the present application relate to a multi-level pulsar designed to reduce power consumption and heat dissipation.

[0027] Further aspects of the present application relate to a level shifter circuit configured to drive a multi-level pulsar. The level shifters disclosed herein can dissipate significantly less power compared to typical level shifters. That is, power can be dissipated only when the level is switched, while static power consumption can be negligible.

[0028] The aspects and embodiments described above, as well as additional aspects and embodiments, are further described below. Since this application is not limited in this respect, these aspects and / or embodiments may be used individually, all together, or in any combination of two or more.

[0029] FIG. 1 shows a circuit for processing a received ultrasound signal according to a non-limiting embodiment of the present application. The circuit 100 includes N ultrasonic transducers 102a ... n, where N is an integer. The ultrasonic transducer is a sensor that, in some embodiments, generates an electrical signal representative of the received ultrasonic signal. The ultrasonic transducer may also transmit an ultrasonic signal in some embodiments. The ultrasonic transducer may be a capacitive micromachined ultrasonic transducer (CMUT) in some embodiments. The ultrasonic transducer may be a piezoelectric micromachined ultrasonic transducer (PMUT) in some embodiments. In other embodiments, further alternative types of ultrasonic transducers may be used.

[0030] The circuit 100 further includes N circuit channels 104a ... 104n. A circuit channel may correspond to each ultrasonic transducer 102a ... n. For example, there may be eight ultrasonic transducers 102a ... n and eight corresponding circuit channels 104a ... n. In some embodiments, the number of ultrasonic transducers 102a ... n may be greater than the number of circuit channels.

[0031] According to aspects of the present application, the circuit channels 104a ... 104n may include transmission circuitry. The transmission circuit may include level shifters 106a ... 106n coupled to respective multi-level pulsars 108a ... 108n. The multi-level pulsars 108a... 108n may control the respective ultrasonic transducers 102a.

[0032] The circuit channels 104a ... n may also include a receiving circuit. The receiving circuits of the circuit channels 104a ... n may receive electrical signal outputs from the respective ultrasonic transducers 102a ... n. In the example shown, each circuit channel 104a ... n includes a respective receiving switch 110a ... n and amplifier 112a ... n. The receiving switches 110a ... 110n may be controlled to enable / disable reading electrical signals from a given ultrasonic transducer 102a ... n. More generally, the receiving switches 110a... 110n may be receiving circuits because alternative switches may be employed to perform the same function. The amplifiers 112a to 112n may be transimpedance amplifiers (TIAs).

[0033] The circuit 100 further comprises an averaging circuit 114, also referred to herein as an adder or summing amplifier. In some embodiments, the averaging circuit 114 is a buffer or amplifier. The averaging circuit 114 may receive output signals from one or more of the amplifiers 112a ... n and may provide an averaged output signal. The averaged output signal can be formed in part by adding or subtracting signals from the various amplifiers 112a ... 112n. The averaging circuit 114 may include a variable feedback resistor. The value of the variable feedback resistor can be dynamically adjusted based on the number of amplifiers 112a ... 112n from which the averaging circuit receives signals. The averaging circuit 114 is coupled to the auto zero block 116.

[0034] The autozero block 116 is coupled to a time gain compensation circuit 118 that includes an attenuator 120 and a fixed gain amplifier 122. Time gain compensation circuit 118 is coupled to analog-to-digital converter (ADC) 126 via ADC driver 124. In the example shown, the ADC driver 124 includes a first ADC driver 125a and a second ADC driver 125b. The ADC 126 digitizes the signal (s) from the averaging circuit 114.

[0035] Although FIG. 1 illustrates several components as part of the circuitry of an ultrasound device, the various aspects described herein are not limited to the exact components or component configurations shown. It should be understood that it is not limited. For example, aspects of the present application relate to multi-level pulsars 108a ... n and level shifters 106a ... n.

[0036] The components of FIG. 1 may be located on a single substrate or on different substrates. For example, as shown, the ultrasonic transducers 102a ... n may be on the first substrate 128a and the remaining components shown may be on the second substrate 128b. The first and / or second substrate may be a semiconductor substrate such as a silicon substrate. In an alternative embodiment, the components of FIG. 1 may be on a single substrate. For example, the ultrasonic transducers 102a ... n and the circuits shown may be monolithically integrated on the same semiconductor die. Such integration can be facilitated by using CMUT as an ultrasonic transducer.

[0037] According to embodiments, the components of FIG. 1 form part of an ultrasound probe. The ultrasound probe may be handheld. In some embodiments, the components of FIG. 1 form part of an ultrasound patch configured to be worn by a patient.

[0038] FIG. 2 shows a circuit diagram of a multi-level pulser according to an aspect of the present application. In some embodiments, the multi-level pulsar 200 may be configured to send a pulse to the capacitor C. Capacitor C may represent the capacitance associated with the ultrasonic transducer. For example, the capacitor C may represent a capacitive micromachined ultrasonic transducer (CMUT). However, the multi-level pulser 200 may be configured to transmit pulses to a resistor, a resistor network, or a network that represents any suitable combination of resistor and reactance elements.

[0039] In the non-limiting embodiment shown in FIG. 2, the multi-level pulsar 200 is configured to provide N-level pulses. Here, N can be assumed to be any value greater than 2. The power consumption P _(N) associated with the transmission of the N level pulser to the capacitor C is equal to P _(N) = C ^* V ^{2 *} f / (N-1). Here, f is the repetition frequency of the pulse waveform. Thus, power consumption is reduced by a factor N-1 compared to a typical two-level pulser.

[0040] In some embodiments, the N-level pulser 200 may comprise 2N-2 transistors and 2N-4 diodes. However, any suitable number of transistors may be used. Of the 2N-2 transistors, N-1 may exhibit one type of conductivity and N-1 may exhibit the opposite type of conductivity. However, any other suitable combination of conductive types may be used. For example, the N−1 transistors may be nMOS, and the N−1 transistors may be pMOS. However, any other suitable type of transistor may be used.

[0041] The N-level pulser 200 may include N circuit blocks 201 ₁ , 201 ₂ ... 201 _N. N circuit blocks may be connected to the node 202. One terminal of capacitor C may also be connected to node 202. The second terminal of the capacitor C may be connected to ground. The circuit block 201 ₁ may include a pMOS transistor T ₁ having a source connected to the reference voltage V _DD and a drain connected to the node 202. The reference voltage V _DD may be a voltage source. The gate of the transistors _{T 1} may be driven by a signal _{V G1.}

[0042] circuit block 201 _N may comprise an nMOS transistor _{T 2N-2} having a drain connected to the source and the node 202 is connected to a reference voltage _{V SS.} In some embodiments, the reference voltage V _SS may be less than the reference voltage V _DD . However, the pulsar 200 is not limited to this point. Further, the reference voltage V _SS may be equal to positive, negative or zero. The gate of transistor T _2N-2 may be driven by signal V _G2N-2 .

[0043] In some embodiments, the circuit block 201 ₂ may comprise two transistors _{T 2} and _{T 3} and two diodes _{D 2} and _{D 3.} Transistor T ₂ and the diode D ₂ may be connected in series, the transistors T ₃ and diode D ₃ may also be connected in series. The two systems may be connected in parallel. In some embodiments, T ₂ may be a pMOS transistor having a source connected to a reference voltage V _MID2 and a drain connected to the anode of D ₂ , and T ₃ is connected to V _MID2 it may be an nMOS transistor having a drain connected to the cathode of the source and D _3. In some embodiments, V _MID2 may be greater than V _{ss and} less than V _DD . The cathode of D ₂ and the anode of D ₃ may be connected to node 202. Further, the gate of T ₂ may be driven by signal V _G2 and the gate of T ₃ may be driven by signal V _G3 .

[0044] In some embodiments, circuit block 201 _i may include two transistors T _2i-2 and T _2i-1 and two diodes D _2i-2 and D _2i-1 . Here, it can be assumed that i is an arbitrary value between 3 and N-1. The transistor T _2i-2 and the diode D _2i-2 may be connected in series, and the transistor T _2i-1 and the diode D _2i-1 may be connected in series. The two systems may be connected in parallel. In some embodiments, T _2i-2 may be a pMOS transistor having a source connected to a reference voltage _VMIDi and a drain connected to the anode of D _2i-2 , where T _2i-1 is It may be an nMOS transistor having a source connected to _VMIDi and a drain connected to the cathode of D _2i-1 . In some _{embodiments, V MIDI is} greater than _{V SS,} it may be less than _{V MID2.} The cathode of D _2i-2 and the anode of D _2i-1 may be connected to node 202. Further, the gate of T _2i-2 may be driven by signal V _G2i-2 and the gate of T _2i-1 may be driven by signal V _G2i-1 .

[0045] For any value of i, V _DD , V _SS and V _MIDi have a value between about −300V and _300V , a value between about −200V and _200V , or any suitable value or value range. May be. Other values are possible.

[0046] FIGS. 3A and 3B illustrate two non-limiting embodiments of level shifter circuits according to aspects of the present application. In some embodiments, the level shifter 301 shown in FIG. 3A may be integrated on the same chip as the pulser 200. In some embodiments, the level shifter 301 can be used to drive any of the pMOS transistors of the pulser 200. For example, level shifter 301 can be used to output the signal _{V G2i-2} drives the gate of the transistor _{T 2i-2.} The input voltage V _IN2i-2 to the level shifter 301 may be a control signal having two possible voltage levels V _SS and V _SS + δV, where δV may be assumed to be any suitable value or value range. . In some embodiments, the control signal V _IN2i-2 may be generated by a circuit integrated on the same chip as the level shifter 301. However, the control signal V _IN2i-2 may also be generated by a circuit integrated on another chip. In some embodiments, the level shifter 301 may include an inverter I _M1 followed by a capacitor C _M. The power supply pin of the inverter I _M1 may be connected to the voltages V _SS and V _SS + δV. The capacitor C _M, may be followed by a series of several inverters. In some embodiments, the capacitor C _M is followed by three inverters I _M2 , I _M3 and I _M4 . The “−” and “+” power supply pins of inverters I _M2 , I _M3 and I _M4 may be connected to voltages V _MDi−− V and V _MDi , respectively. In some non-limiting embodiments, the level shifter 301 may comprise a diode D _M. The cathode of the diode _{D M} may be connected to the output of the capacitor _{C M,} the anode may be connected to _{V MIDI} - [Delta] V rail. Level shifter 301 comprises four inverters in the non-limiting embodiment of FIG. 3A, but any number of inverters may be used otherwise. The output voltage V _G2i-2 may be assumed to be two possible voltages V _MDi−ΔV and V _MDii .

[0047] In some embodiments, the level shifter 302 shown in FIG. 3B may be integrated on the same chip as the pulser 200. In some embodiments, the level shifter 302 can be used to drive any of the nMOS transistors of the pulser 200. For example, level shifter 302 can be used to output the signal _{V G2i-1} drives the gate of the transistor _{T 2i-1.} The input voltage V _IN2i-1 to the level shifter 302 may be a control signal having two possible voltage levels V _SS and V _SS + δV. In some embodiments, the control signal V _IN2i-1 may be generated by a circuit integrated on the same chip as the level shifter 302. However, the control signal V _IN2i-1 may be generated by a circuit integrated on another chip. In some embodiments, the level shifter 302 may comprise subsequent inverter I _P1 to the capacitor C _P is followed. The power supply pin of the inverter I _P1 may be connected to the voltages V _SS and V _SS + δV. The capacitor C _P, may be followed by a series of several inverters. In some embodiments, the capacitor _{C P,} 2 two inverters _{I P2} and _{I P3} followed. The power pins of inverters I _M2 and I _M3 may be connected to voltages V _MIDi and V _MIDi + ΔV. In some non-limiting embodiments, the level shifter 302 may comprise a diode DP. The cathode of the diode D _P may be connected to the output of the capacitor C _P, the anode may be connected to V _MIDI rail. The level shifter 302 comprises three inverters in the non-limiting embodiment of FIG. 3B, otherwise any suitable number of inverters may be used. The output voltage V _G2i-i can be assumed to be two possible voltages V _MIDi and V _MIDi + ΔV.

[0048] According to aspects of the present application, level shifters 301 and 302 may dissipate power only when the level is switched, while static power may be negligible. Capacitors C _M and C _P can be used to shift the voltage level by storing a constant voltage drop through them. For example, the static power consumption may be less than 100 mW, less than 1 mW, less than 1 μW or any suitable value.

[0049] FIGS. 4A, 4B, 4C, 4D, 4E, and 4F show six snapshots of the pulsar 200 corresponding to the six stages associated with the formation of a four-level pulse, according to aspects of the present application. Show. In the figure, only active blocks are shown. In a non-limiting example, N is equal to 4, otherwise any other suitable value of N may be used, such as N being greater than 2. In this example, V _SS is set to 0.

[0050] FIG. 5 illustrates a non-limiting example of a generated multi-level pulse 500 according to aspects of the present application. In a non-limiting example, pulse 500 shows four levels of 0, V _MID3 , V _MID2 and V _DD . Further, FIG. 5 shows six control signals V _G1 , V _G2 , V _G3 , V _G4 , V _G4 , which are used to drive the gates of transistors T ₁ , T ₂ , T ₃ , T ₄ , T ₅ and T ₆ , respectively. V _G5 and V _G6 are shown. The process associated with pulse generation can be driven in six stages. Between t ₁ and t ₂ , the pulse 500 can be increased from 0 to V _MID3 by providing a negative pulse 504 through V _G4 to transistor T ₄ as shown in FIG. FIG. 4A shows the pulsar 201 between t ₁ and t ₂ . During this period, the gate of the transistor _{T 4 may} be driven by a voltage equal to _{V MID3} - [Delta] V. ΔV may be selected to create a conductive channel and drive the current between the source diodes through which transistor T ₄ passes through diode D ₄ . Such a current may charge capacitor C such that the output voltage of V _MID3 is obtained while ignoring any voltage drop at T ₄ and D ₄ . The pulse 504 may be acquired through the level shifter 301.

[0051] Between t ₂ and t ₃ , pulse 500 may be increased from V _MID3 to V _MID2 by providing a negative pulse 502 to transistor T ₂ through V _G2 as shown in FIG. . FIG. 4B shows the pulsar 201 between t ₂ and t ₃ . During this period, the gate of the transistor _{T 2 are,} may be driven by a voltage equal to _{V MID2- ΔV.} ΔV creates a conductive channel as transistor T ₂ drives the source-drain current through the diode D _2, it may be selected. Such current may charge the capacitor C so that the output voltage of the V _MID2 while ignoring any voltage drop in the T ₂ and D ₂ are obtained. The pulse 502 may be acquired through the level shifter 301.

[0052] Between t ₃ and t ₄ , the pulse 500 may be increased from V _MID2 to V _DD by providing a negative pulse 501 to the transistor T ₁ through V _G1 as shown in FIG. . Figure 4C shows the pulser 201 between _{t 3} and _{t 4.} During this period, the gate of the transistors _{T 1 may} be driven by a voltage equal to _{V DD-} [Delta] V. ΔV creates a conductive channel as transistors T ₁ to drive the current between the source and the drain may be selected. Such a current may charge capacitor C such that an output voltage of V _DD is obtained while ignoring any voltage drop at T ₁ . The pulse 501 may be acquired through the level shifter 301.

[0053] Between t ₄ and t ₅ , pulse 500 may be reduced from V _DD to V _MID2 by providing a positive pulse 503 to transistor T ₃ through V _G3 as shown in FIG. . FIG. 4D shows the pulsar 201 between t ₄ and t ₅ . During this period, the gate of the transistor _{T 3 may} be driven by a voltage equal to _{V MID2} + [Delta] V. ΔV creates a conductive channel as transistor T ₃ drives the drain-source current may be selected. Such a current may discharge capacitor C such that the output voltage of V _MID2 is obtained while ignoring any voltage drop at T ₃ and D ₃ . The pulse 503 may be acquired through the level shifter 302.

[0054] between _{t 5} and _{t 6,} the pulse 500 by providing through _{V G5} to the transistor _{T 5} a positive pulse 505 as shown in FIG. _5, it is reduced from _{V MID2} in _{V MID3} Good. Figure 4E shows the pulser 201 between _{t 5} and _{t 6.} During this period, the gate of the transistor _{T 5 may} be driven by a voltage equal to _{V MID3} + [Delta] V. ΔV creates a conductive channel as transistor T ₅ drives the drain-source current may be selected. Such a current may discharge capacitor C such that the output voltage of V _MID3 is obtained while ignoring any voltage drop at T ₅ and D ₅ . The pulse 505 may be acquired through the level shifter 302.

[0055] After _{t 6,} the pulse 500 by providing through _{V G6} to the transistor _{T 6} a positive pulse 506 as shown in FIG. _5, may be reduced from _{V MID3} to 0. Figure 4F shows the pulser 201 after _{t 6.} During this period, the gate of the transistor T ₆ may be driven by a voltage equal to [Delta] V. ΔV may be selected to create a conductive channel and transistor T ₆ drives the drain-source current. Such current may discharge the capacitor C as the output voltage of 0 while ignoring any voltage drop at T ₆ is obtained. The pulse 506 may be acquired through the level shifter 302.

[0056] In a non-limiting example related to FIG. 5, pulse 500 is unipolar. However, the multi-level pulsar 200 is not limited in this respect. The multi-level pulser 200 may alternatively be configured to transmit bipolar pulses that indicate levels having a positive voltage and a negative voltage. In accordance with another aspect of the present application, the multi-level pulser 200 includes a multi-level charge reuse waveform generator in that charge reuse occurs in a decrement step when charge moves back from the output capacitance to the power source. Can be considered. According to another aspect of the present application, the multi-level pulser has been described as being used to drive a capacitive output, but may also be used to drive a resistive output.

[0057] The amount of power savings when using a level shifter of the type described herein can be substantial. In some embodiments, utilizing a level shifter of the type described herein may provide significant power savings by setting static power consumption to about zero. Thus, power can only be dissipated when switching states.

[0058] Although several aspects and embodiments of the techniques of this application have been described in this manner, it will be appreciated by those skilled in the art that various changes, modifications, and improvements will readily occur. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described in this application. Accordingly, the foregoing embodiments are presented by way of example only, and embodiments of the invention may be practiced other than those specifically described within the scope of the appended claims and their equivalents. Will be understood.

[0059] As described, some aspects may be embodied as one or more methods. The acts performed as part of the method (s) may be ordered in any suitable manner. Thus, embodiments may be configured in which actions are performed in a different order than illustrated, which includes performing several actions simultaneously even though they are shown as sequential actions in the specific example. obtain.

[0060] It is understood that all definitions defined and used herein are directed to lexical definitions, definitions in documents incorporated by reference, and / or the ordinary meaning of a defined term. Should.

[0061] As used herein and within the claims, the phrase “and / or” (and / or) refers to “either or both” of the elements so coordinated, ie, in some cases. Should be understood to mean elements that exist in a connected manner and in other cases in a disjunctive manner.

[0062] As used herein and in the claims, the phrase "at least one" when referring to a list of one or more elements is any 1 in the list of elements. It should be understood to mean at least one element selected from one or more elements, but does not necessarily include at least one of each element specifically listed in the list of elements, but a list of elements It does not exclude any combination of elements in.

[0063] As used herein, the term "between" used in a numerical context is inclusive unless stated otherwise. For example, “between A and B” includes A and B unless stated otherwise.

[0064] Within the scope of the claims and the above-mentioned specification, “comprising”, “including”, “carrying”, “having”, “containing” Any transitional phrase such as “involved”, “holding”, “composed of”, etc. means non-limiting, ie, including but not limited to Will be understood. Only transition phrases such as “consisting of” and “consisting essentially of” are restricted transition phrases or semi-restricted transition phrases, respectively.

Claims (43)

At least one ultrasonic transducer on the substrate;
A multi-level pulsar on the substrate connected to the at least one ultrasonic transducer;
A plurality of input terminals configured to receive respective input voltages;
An output terminal configured to provide an output voltage;
Comprising a second transistor connected to the first transistor and connected in parallel to become a second diode connected to the first diode, between the first input terminal and the output terminal of said plurality of input terminals And a signal path of
The first transistor is a pMOS transistor or an nMOS transistor. When the first transistor is a pMOS transistor, the second transistor is an nMOS transistor, and when the first transistor is an nMOS transistor, the first transistor is an nMOS transistor. 2 of the transistor is a multi-level pulsar Ru pMOS transistor der,
An apparatus comprising: The apparatus of claim 1, further comprising a controller configured to control charging and discharging of an output capacitance associated with the ultrasound transducer to provide charge recycling. The multi-level pulsar includes a plurality of signal paths between the input terminals and the output terminals of the plurality of input terminals, and each signal path is connected in parallel with a pMOS or nMOS transistor connected to a first diode. to look including the connected pMOS or nMOS transistor to a second diode comprising, when said connected pMOS or nMOS transistor to the first diode is pMOS transistors, the pMOS connected to said second diode Alternatively, the nMOS transistor is an nMOS transistor, and when the pMOS or nMOS transistor connected to the first diode is an nMOS transistor, the pMOS or nMOS transistor connected to the second diode is a pMOS transistor. In a device of claim 1.   The apparatus of claim 1, wherein the output voltage is equal to a predetermined input voltage.   The apparatus of claim 1, further comprising a capacitor connected to the output terminal.   The apparatus of claim 1, further comprising a resistor connected to the output terminal. The device of claim 1, wherein the first transistor is a pMOS and the second transistor is an nMOS.   The apparatus of claim 1, wherein the first diode has an anode connected to the first transistor and a cathode connected to the output terminal.   The apparatus of claim 1, wherein the second diode has a cathode connected to the second transistor and an anode connected to the output terminal. A multi-level pulser configured to be connected to an ultrasonic transducer,
A plurality of input terminals configured to receive respective input voltages;
An output terminal configured to provide an output voltage;
Comprising a second transistor connected to the first transistor and connected in parallel to become a second diode connected to the first diode, between the first input terminal and the output terminal of said plurality of input terminals The first transistor is a pMOS transistor or an nMOS transistor, and when the first transistor is a pMOS transistor, the second transistor is an nMOS transistor, and the first transistor is when the second transistor is an nMOS transistor, the signal path is a pMOS transistor ;
A capacitor connected to the output terminal;
A multi-level pulsar with   The multi-level pulsar of claim 10, further comprising a controller connected to the output terminal and configured to control charging and discharging of the capacitor to provide charge recycling. A plurality of signal paths between each of the plurality of input terminals and the output terminal, each signal path being connected in parallel with a pMOS or nMOS transistor connected to a first diode; the connected pMOS or nMOS transistor diode seen including, when said connected pMOS or nMOS transistor to the first diode is pMOS transistor, said pMOS or nMOS transistor connected to the second diode nMOS transistor , and the time the connected pMOS or nMOS transistor to the first diode is an nMOS transistor, said pMOS or nMOS transistor connected to the second diode are pMOS transistors, Bei a plurality of signal paths That, multilevel pulser of claim 10.   The multi-level pulsar according to claim 10, wherein the output voltage is equal to a predetermined input voltage.   The multi-level pulsar according to claim 10, further comprising a resistor connected to the output terminal. The multilevel pulsar according to claim 10, wherein the first transistor is a pMOS and the second transistor is an nMOS.   The multi-level pulsar according to claim 10, wherein the first diode has an anode connected to the first transistor and a cathode connected to the output terminal.   11. The multi-level pulsar according to claim 10, wherein the second diode has a cathode connected to the second transistor and an anode connected to the output terminal.   An apparatus for generating ultrasonic pulses,
  A level shifter having an input terminal and an output terminal configured to receive an input signal having two or more states, the level shifter configured to output one or more control signals to the output terminal;
  A pulser configured to receive the one or more control signals from the level shifter and provide a plurality of multi-level pulses corresponding to the one or more control pulses received from the level shifter;
  A capacitive micromachined ultrasonic transducer (CMUT) configured to receive the plurality of multilevel pulses from the pulser and convert each of the plurality of multilevel pulses into an acoustic ultrasonic signal, The ultrasonic signal includes one of the plurality of multi-level pulses and a corresponding capacitive micromachined ultrasonic transducer;
  The level shifter and the pulser are configured to dissipate heat when an ultrasonic signal level changes corresponding to the plurality of multi-level pulses.
  apparatus.   19. The apparatus of claim 18, wherein the level shifter and the pulsar are integrated on a solid state chip.   The apparatus of claim 19, wherein the level shifter, the pulsar, and the CMUT are integrated on a solid state chip.   The apparatus of claim 18, wherein the level shifter further comprises an inverter connected to a capacitor, the level shifter receiving at least two input voltages.   The level shifter is
  A voltage input terminal for receiving an input voltage; and
  An output voltage terminal providing an output voltage level-shifted from the input voltage;
  One or more capacitors connected between the voltage input terminal and the output voltage terminal;
  The apparatus of claim 18, further comprising one or more diodes connected in a reverse bias configuration between an input to the active high voltage element and a first voltage of the high voltage power supply.   24. The apparatus of claim 22, wherein the active high voltage element comprises an inverter.   The pulsar is
  A plurality of input terminals configured to receive respective input voltages;
  An output terminal configured to provide an output voltage;
  A first transistor having a first conductivity type connected to the first diode and a second transistor having a second conductivity type connected to a second diode connected in parallel; The apparatus of claim 18, further comprising a signal path between an input terminal and the output terminal.   25. The apparatus of claim 24, wherein the pulser comprises a controller that controls charging and discharging of an output capacitance to provide charge recycling.   A plurality of signal paths are provided between the first input terminal and the output terminal of the pulser, and each signal path is connected in parallel with a transistor having a first conductivity type connected to a first diode. 25. The apparatus of claim 24, comprising a transistor having a second conductivity type connected to the second diode.   27. The device of claim 26, wherein the first conductivity type is a pMOS and the second conductivity type is an nMOS.   25. The apparatus of claim 24, wherein the output voltage is equal to a predetermined input voltage.   The first diode has an anode connected to the first transistor and a cathode connected to the output terminal of the pulsar, and the second diode is a cathode connected to the second transistor. 25. The apparatus of claim 24, further comprising an anode connected to the output terminal of the pulsar.   At least one ultrasonic transducer on the first substrate;
  A multi-level pulser on a second substrate different from the first substrate connected to the at least one ultrasonic transducer;
  A plurality of input terminals configured to receive respective input voltages;
  An output terminal configured to provide an output voltage;
  Between the first input terminal of the plurality of input terminals and the output terminal, including a first transistor connected to the first diode and a second transistor connected to the second diode connected in parallel. And a signal path of
  The first transistor is a pMOS transistor or an nMOS transistor. When the first transistor is a pMOS transistor, the second transistor is an nMOS transistor, and when the first transistor is an nMOS transistor, the first transistor is an nMOS transistor. The second transistor is a multi-level pulser that is a pMOS transistor,
  An apparatus comprising:   32. The apparatus of claim 30, further comprising a controller configured to control charging and discharging of an output capacitance associated with the ultrasound transducer to provide charge recycling.   The multi-level pulsar includes a plurality of signal paths between the input terminals and the output terminals of the plurality of input terminals, and each signal path is connected in parallel with a pMOS or nMOS transistor connected to a first diode. When the pMOS or nMOS transistor connected to the first diode is a pMOS transistor, the pMOS or nMOS transistor connected to the second diode is connected to the second diode. The nMOS transistor is an nMOS transistor. When the pMOS or nMOS transistor connected to the first diode is an nMOS transistor, the pMOS or nMOS transistor connected to the second diode is a pMOS transistor. In a device of claim 30.   32. The apparatus of claim 30, wherein the output voltage is equal to a predetermined input voltage.   32. The apparatus of claim 30, further comprising a capacitor connected to the output terminal.   32. The apparatus of claim 30, further comprising a resistor connected to the output terminal.   32. The apparatus of claim 30, wherein the first transistor is a pMOS and the second transistor is an nMOS.   32. The apparatus of claim 30, wherein the first diode has an anode connected to the first transistor and a cathode connected to the output terminal.   32. The apparatus of claim 30, wherein the second diode has a cathode connected to the second transistor and an anode connected to the output terminal.   At least one ultrasonic transducer on the first substrate;
  A level shifter on a second substrate different from the first substrate connected to the at least one ultrasonic transducer;
  An input terminal configured to receive an input voltage;
  An output terminal configured to provide an output voltage level shifted from the input voltage;
  A capacitor connected between the input terminal and the output terminal;
  A diode connected in a reverse bias configuration between an input to the active high voltage element and a first voltage of the high voltage power supply;
  The input of the active high voltage element is a level shifter connected to the output of the capacitor;
  An apparatus comprising:   40. The apparatus of claim 39, wherein the first substrate is a semiconductor substrate.   40. The apparatus of claim 39, wherein the at least one ultrasonic transducer is a capacitive micromachined ultrasonic transducer (CMUT).   40. The apparatus of claim 39, further comprising a pulsar connected to the level shifter and mounted on the second substrate.   40. The apparatus of claim 39, comprising a plurality of ultrasonic transducers including the at least one ultrasonic transducer, wherein the plurality of ultrasonic transducers are configured to emit high intensity focused ultrasound (HIFU).

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