JP6556574B2 - Waveform shaping filter and radiation detection apparatus - Google Patents

Description

  Embodiments described herein relate generally to a waveform shaping filter and a radiation detection apparatus.

  Generally, the radiation detector has a low-pass characteristic. For this reason, a blunt signal pulse is output from the radiation detector. Therefore, conventionally, a waveform shaping filter has been used to suppress the dullness of the signal pulse from the radiation detector.

JP 2001-274641 A JP 09-139638 A JP 2006-254118 A

IEEE Transaction On Nuclear Science, Vol.46, No.3, pp.150-155, June, 1999 IEEE Transactions on Nuclear Science, Vol.NS-28, No.1, pp.603-609, Feb.1981 IEEE JSSC Vol.48, No.7, pp.1605-1614, July 2013 IEEE JSSC Vol.33, No.12, pp.1887-1897, Dec. 1998

  A low-power consumption waveform shaping filter and a radiation detection device are provided.

  A waveform shaping filter according to an embodiment includes a first resistor, a first transistor, a first capacitor, and a first amplifier. The first resistor includes one end to which a signal current is input and the other end. The first transistor includes a first terminal connected to the other end of the first resistor, a second terminal, and a control terminal. The first capacitor includes one end connected to the other end of the first resistor and the other end. The first amplifier includes an input terminal connected to one end of the first resistor, and an output terminal connected to the control terminal of the first transistor.

The figure which shows the waveform shaping filter which concerns on 1st Embodiment. The figure which shows 1st Example of the waveform shaping filter of FIG. The figure which shows 2nd Example of the waveform shaping filter of FIG. The figure which shows 3rd Example of the waveform shaping filter of FIG. The figure which shows the waveform shaping filter which concerns on 2nd Embodiment. The figure which shows 1st Example of the waveform shaping filter of FIG. The figure which shows 2nd Example of the waveform shaping filter of FIG. The figure which shows 3rd Example of the waveform shaping filter of FIG. The figure which shows the waveform shaping filter which concerns on 3rd Embodiment. The figure which shows 1st Example of the waveform shaping filter of FIG. The figure which shows the modification of the waveform shaping filter of FIG. The figure which shows 2nd Example of the waveform shaping filter of FIG. The figure which shows 3rd Example of the waveform shaping filter of FIG. The figure which shows 4th Example of the waveform shaping filter of FIG. The figure which shows the waveform shaping filter which concerns on 4th Embodiment. The figure which shows the modification of the waveform shaping filter of FIG. The figure which shows the waveform shaping filter which concerns on 5th Embodiment. The figure which shows the waveform shaping filter which concerns on 6th Embodiment. The figure which shows the waveform shaping filter which concerns on 7th Embodiment. The figure which shows 1st Example of the waveform shaping filter of FIG. The figure which shows 2nd Example of the waveform shaping filter of FIG. The figure which shows 3rd Example of the waveform shaping filter of FIG. The figure which shows the waveform shaping filter which concerns on 8th Embodiment. The figure which shows the waveform shaping filter which concerns on 8th Embodiment. The figure which shows the waveform shaping filter which concerns on 9th Embodiment. The figure which shows the modification of the waveform shaping filter of FIG. The figure which shows 1st Example of the waveform shaping filter of FIG. The figure which shows the waveform shaping filter which concerns on 10th Embodiment. The figure which shows 1st Example of the waveform shaping filter of FIG. The figure which shows the waveform shaping filter which concerns on 11th Embodiment. The figure which shows the waveform shaping filter which concerns on 12th Embodiment. The figure which shows the waveform shaping filter which concerns on 13th Embodiment. The figure which shows the waveform shaping filter which concerns on 14th Embodiment. The figure which shows the waveform shaping filter which concerns on 15th Embodiment. A figure showing a waveform shaping filter concerning a 16th embodiment. The figure which shows the waveform shaping filter which concerns on 17th Embodiment. The figure which shows the modification of the waveform shaping filter of FIG. The figure which shows the waveform shaping filter which concerns on 18th Embodiment. The figure which shows the modification of the waveform shaping filter of FIG. The figure which shows the waveform shaping filter which concerns on 19th Embodiment. The figure which shows the modification of the waveform shaping filter of FIG. The figure which shows the modification of the waveform shaping filter of FIG. The figure which shows the waveform shaping filter which concerns on 20th Embodiment. The figure which shows the waveform shaping filter which concerns on 21st Embodiment. The figure which shows the waveform shaping filter which concerns on 22nd Embodiment. The figure which shows the waveform shaping filter which concerns on 23rd Embodiment. The figure which shows the waveform shaping filter which concerns on 24th Embodiment. The figure which shows the waveform shaping filter which concerns on 25th Embodiment. A figure showing a waveform shaping filter concerning a 26th embodiment. The figure which shows the waveform shaping filter which concerns on 27th Embodiment. The figure which shows the waveform shaping filter which concerns on 28th Embodiment. The figure which shows the waveform shaping filter which concerns on 29th Embodiment. The figure which shows the waveform shaping filter which concerns on 30th Embodiment. A figure showing a waveform shaping filter concerning a 31st embodiment. The figure which shows the modification of the amplifier of FIG. FIG. 56 is a diagram showing a first example of the level shift circuit of FIG. 55. FIG. 56 is a diagram showing a second embodiment of the level shift circuit in FIG. 55. FIG. 56 is a diagram showing a third embodiment of the level shift circuit of FIG. 55. FIG. 56 is a diagram showing a fourth embodiment of the level shift circuit in FIG. 55. The figure which shows the waveform shaping filter which concerns on 32nd Embodiment. Schematic which shows the radiation detection apparatus which concerns on 33rd Embodiment. The figure which shows the simulation result of the radiation detection apparatus of FIG. FIG. 62 is a diagram showing a first example of the filter circuit of FIG. 61. FIG. 62 is a diagram illustrating a second embodiment of the filter circuit in FIG. 61. FIG. 62 is a diagram showing a third embodiment of the filter circuit in FIG. 61. FIG. 62 is a diagram showing a fourth embodiment of the filter circuit in FIG. 61.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
The waveform shaping filter according to the first embodiment will be described with reference to FIGS. FIG. 1 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 1, the waveform shaping filter according to the present embodiment includes a resistor R1, a transistor M1, a capacitor C1, and an amplifier A1. The current source Isignal in FIG. 1 is a current source that inputs the signal current Isignal to the waveform shaping filter.

  The resistor R1 (first resistor) has one end and the other end. One end of the resistor R1 is connected to the input terminal of the amplifier A1 and the current source Isignal. Thereby, the input current Isignal is input to the resistor R1 from one end. The other end of the resistor R1 is connected to the source terminal of the transistor M1 and one end of the capacitor C1.

  The transistor M1 (first transistor) is an N-channel MOS transistor (hereinafter referred to as “NMOS”), and includes a source terminal (first terminal), a gate terminal (control terminal), and a drain terminal (second terminal). . The source terminal is connected to the other end of the resistor R1 and one end of the capacitor C1. The gate terminal is connected to the output terminal of the amplifier A1. The transistor M1 outputs an output current Iout from the drain terminal.

  The capacitor C1 (first capacitor) has one end and the other end. One end of the capacitor C1 is connected to the other end of the resistor R1 and the source terminal of the transistor M1. The other end of the capacitor C1 is grounded. Grounding means connecting to a ground line (first reference voltage line).

  The amplifier A1 (first amplifier) is an inverting amplifier and includes an input terminal and an output terminal. The input terminal is connected to one end of the resistor R1 and the current source Isignal. Thus, the amplifier A1 receives the signal current Isignal or the terminal voltage at one end of the resistor R1 from the input terminal. The output terminal is connected to the gate terminal of the transistor M1.

  Next, the operation of the waveform shaping filter according to this embodiment will be described.

  As described above, the waveform shaping filter is configured such that the output of the amplifier A1 is fed back to the amplifier A1 through the transistor M1 and the resistor R1. For this reason, the input terminal of the amplifier A1 becomes a virtual ground point, and the voltage becomes substantially constant.

  At this time, the input impedance of the waveform shaping filter as viewed from the current source Isignal is (1 + gm1 × R1) / {gm1 (1 + A1)} when the amplifier A1 is a voltage input type. Here, gm1 is the transconductance of the transistor M1, and A1 is the gain of the amplifier A1. In general, since the gain of the amplifier A1 is very large, the input impedance of the waveform shaping filter is very small.

  Therefore, when the signal current Isignal is input from the current source Isignal, the signal current Isignal flows through the resistor R1, and a voltage of Isignal × R1 is generated at the source terminal of the transistor M1. Here, Isignal is the current value of the signal current Isignal, and R1 is the resistance value of the resistor R1.

  Further, when a voltage is generated at the source terminal of the transistor M1, a current Isignal × R1 × sC1 proportional to the time differentiation of the signal current Isignal flows through the capacitor C1. Here, s is a Laplace variable, and C1 is a capacitance value of the capacitor C1.

  As a result, a current of Isignal × (1 + sC1 × R1), which is the sum of Isignal and Isignal × R1 × sC1, flows through the transistor M1, and this current is output from the drain terminal as the output current Iout.

  As described above, the waveform shaping filter according to this embodiment superimposes and outputs the differential component of the signal current Isignal on the input signal current Isignal. Thereby, the filter characteristic which emphasized the high frequency component of signal current Isignal is realizable.

  In the present embodiment, the load of the amplifier A1 is only the gate of the transistor M1. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current drive capability of the amplifier A1, and the power consumption of the waveform shaping filter can be reduced.

  Note that the waveform shaping filter preferably has a time constant equal to the time constant of the low-pass characteristic of the signal current Isignal. In the present embodiment, the time constant of the waveform shaping filter is C1 × R1. Thereby, the low-pass characteristic can be removed from the signal current Isignal and the pulse width can be narrowed.

(First embodiment)
FIG. 2 is a diagram illustrating a first example of the waveform shaping filter according to the present embodiment. In this embodiment, the amplifier A1 is a current input type amplifier. As shown in FIG. 2, the amplifier A1 includes transistors M11, M12, M13, and M14, and current sources Ib11 and Ib12.

  The transistor M11 is an NMOS having a source terminal, a gate terminal, and a drain terminal. The source terminal of the transistor M11 is connected to the current source Ib11, the drain terminal is connected to the drain terminal of the transistor M13 and the output terminal Out of the amplifier A1, and a predetermined bias voltage Vbias is applied to the gate terminal.

  The transistor M12 is an NMOS having a source terminal, a gate terminal, and a drain terminal. The source terminal of the transistor M12 is connected to the current source Ib12 and the input terminal In of the amplifier A1, the drain terminal is connected to the drain terminal of the transistor M14 and the gate terminals of the transistors M13 and M14, and the gate terminal is a predetermined bias voltage. Vbias is applied.

  The transistor M13 is a P-channel MOS transistor (hereinafter referred to as “PMOS”) having a source terminal, a gate terminal, and a drain terminal. The source terminal of the transistor M13 is connected to the power supply, the drain terminal is connected to the drain terminal of the transistor M11 and the output terminal Out of the amplifier A1, and the gate terminal is the gate terminal and drain terminal of the transistor M14 and the drain of the transistor M12. Connected to the terminal.

  The transistor M14 is a PMOS having a source terminal, a gate terminal, and a drain terminal. The source terminal of the transistor M14 is connected to the power supply, the drain terminal is connected to the gate terminals of the transistors M13 and M14 and the drain terminal of the transistor M12, and the gate terminal is connected to the gate terminal of the transistor M13 and the drain terminal of the transistor M14. Is done.

  The current source Ib11 supplies a predetermined bias current Ib11 to the transistor M11. The current source Ib12 supplies a predetermined bias current Ib12 to the transistor M12.

  Next, the operation of the amplifier A1 will be described. Hereinafter, it is assumed that the sizes of the transistors M11 and M12 are equal, the sizes of the transistors M13 and M14 are equal, and the current values of the bias currents Ib11 and Ib12 are equal to Ib1 (Ib11 = Ib12 = Ib1).

  When a current ΔI is supplied from the input terminal In of the amplifier A1, a current of ΔI + Ib1 flows through the transistors M12 and M14. This current is folded back by a current mirror circuit constituted by the transistors M13 and M14. As a result, a current of ΔI + Ib1 flows through the transistor M13.

  On the other hand, only the bias current Ib1 supplied from the current source Ib11 flows through the transistor M11.

  When ΔI> 0, that is, when the voltage at the input terminal In of the amplifier A1 decreases and current flows from the input terminal In to one end of the resistor R1, the current supplied from the drain terminal of the transistor M13 is Since it becomes larger than the current drawn from the drain terminal, the gate voltage of the transistor M1 connected to the output terminal Out rises.

  When the gate voltage of the transistor M1 increases, the source voltage of the transistor M1 increases, and the voltage at one end of the resistor R1 (the voltage at the input terminal In of the amplifier A1) increases. Thus, feedback is applied so that the current ΔI becomes 0, and the source voltage of the transistor M12 (the voltage at the input terminal In of the amplifier A1) becomes substantially equal to the source voltage of the transistor M11.

  On the other hand, when ΔI <0, that is, when the voltage at the input terminal In of the amplifier A1 rises and current flows from one end of the resistor R1 to the input terminal In, the current supplied from the drain terminal of the transistor M13 is Since the current is smaller than the current drawn from the drain terminal of M11, the gate voltage of the transistor M1 connected to the output terminal Out decreases.

  When the gate voltage of the transistor M1 decreases, the source voltage of the transistor M1 decreases, and the voltage at one end of the resistor R1 (the voltage at the input terminal In of the amplifier A1) decreases. Thus, feedback is applied so that the current ΔI becomes 0, and the source voltage of the transistor M12 (the voltage at the input terminal In of the amplifier A1) becomes substantially equal to the source voltage of the transistor M11.

  Therefore, the input terminal In of the amplifier A1 becomes a virtual ground point as described above, and the voltage becomes substantially constant. Thereby, the waveform shaping filter can be operated as described above.

  As described above, a current input type amplifier can be used as the amplifier A1. When the current input type amplifier A1 is used, the single input impedance of the amplifier A1 is 1 / gm12, and the input impedance of the waveform shaping filter viewed from the current source Isignal is (1 + gm1 × R1) / {gm1 (1 + A1 ) + Gm12 (1 + gm1 × R1)}. Here, gm12 is the transconductance of the transistor M12.

  Therefore, by using the current input type amplifier A1, it is possible to make the input impedance of the waveform shaping filter smaller than when the voltage input type amplifier A1 is used, and to suppress fluctuations in the voltage at the input terminal In of the amplifier A1. it can. Thereby, the error of the output current Iout due to the fluctuation of the input voltage of the waveform shaping filter can be reduced.

(Second embodiment)
FIG. 3 is a diagram illustrating a second example of the waveform shaping filter according to the present embodiment. In the present embodiment, the waveform shaping filter further includes a current source Idc1. Other configurations are the same as those in FIG.

  The current source Idc1 (first current source) is a direct current source having one end and the other end. One end of the current source Idc1 is connected to the other end of the resistor R1, the source terminal of the transistor M1, and one end of the capacitor C1. In FIG. 3, the other end of the current source Idc1 is grounded, but may be connected to a power source. The current source Idc1 supplies an arbitrary DC current Idc1 that turns on the transistor M1.

  With this configuration, according to the present embodiment, the response speed when the pulsed signal current Isignal is input to the waveform shaping filter can be improved. The reason is as follows.

  The pulsed signal current Isignal is a current in which a pulsed input signal (high frequency component) is superimposed on a bias current. Therefore, when the input signal has not arrived, only the bias current is input to the waveform shaping filter as the signal current Isignal. For this reason, when the bias current is small, the transistor M1 may not be sufficiently turned on until an input signal arrives. When an input signal arrives at such a transistor M1, the response is delayed.

  However, by turning on the transistor M1 in advance by the current source Idc1 as in the present embodiment, the delay as described above can be suppressed and the response speed to the input signal can be improved.

(Third embodiment)
FIG. 4 is a diagram illustrating a third example of the waveform shaping filter according to the present embodiment. In the present embodiment, the waveform shaping filter further includes a resistor R1a. Other configurations are the same as those in FIG.

  The resistor R1a (second resistor) has one end and the other end. One end of the resistor R1a is connected to the other end of the capacitor C1, and the other end of the resistor R1a is grounded.

  With this configuration, in this embodiment, the filter characteristic of the waveform shaping filter is {1 + sC1 (R1 + R1a)} / (1 + sC1 × R1a). That is, when the signal current Isignal is input to the waveform shaping filter, Isingal × {1 + sC1 (R1 + R1a)} / (1 + sC1 × R1a) is output as the output current Iout. A filter characteristic that emphasizes the high-frequency component of the signal current Isignal (hereinafter, referred to as “emphasis characteristic”) is realized by 1 + sC1 (R1 + R1a).

  Therefore, by making the capacitance value C1 in FIGS. 1 and 4 the same and making the resistance value R1 in FIG. 1 and the resistance value R1 + R1a in FIG. 4 the same, the emphasis characteristics in FIGS. 1 and 4 can be matched. That is, according to the waveform shaping filter according to the present embodiment, the resistance value R1 for obtaining a predetermined enhancement characteristic can be made smaller by the resistance value R1a than the waveform shaping filter of FIG.

  When the resistance value R1 is decreased, the voltage applied to the resistor R1 is decreased, and the source voltage of the transistor M1 is decreased. Therefore, the power supply voltage of the waveform shaping filter can be lowered and the power consumption can be reduced.

Here, the case where the signal current Isignal has a low-pass characteristic having two time constants will be considered. At this time, the current value of the signal current Isignal is represented by Isignal = Is {a / (1 + sτ ₁ ) + b / (1 + sτ ₂ )} (where τ ₁ > τ ₂ ). τ ₁ and τ ₂ are time constants.

The above equation can be modified as Isignal = (a + b) {1 + s (aτ ₂ + bτ ₁ ) / (a + b)} / {(1 + sτ ₁ ) × (1 + sτ ₂ )}. Here, when C1, R1, and R1a are selected so that τ ₁ = C1 (R1 + R1a), (aτ ₂ + bτ ₁ ) / (a + b) = C1 × R1a, the output current Iout is 1 / (1 + sτ ₂ ) The current is proportional to.

By inputting this output current Iout to a waveform shaping filter having a filter characteristic of 1 + sτ ₂ , the low-pass characteristic can be removed from the signal current Isignal. A waveform shaping filter having a filter characteristic of 1 + sτ ₂ can be realized by the waveform shaping filter according to the present embodiment. For example, C1 and R1 of the waveform shaping filter of FIG. 1 may be selected to be τ2 = C1 × R1, or C1, R1 and R1a of the waveform shaping filter of FIG. 4 are τ2 = C1 × (R1 + R1a ) May be selected.

  As described above, the waveform shaping filter according to this embodiment adjusts the capacitance value and the resistance value to reduce the low frequency from the signal current Isignal having the low-pass characteristics in the case of one time constant or two time constants. Pass characteristics can be eliminated.

(Second Embodiment)
A waveform shaping filter according to the second embodiment will be described with reference to FIGS. FIG. 5 is a diagram illustrating the waveform shaping filter according to the present embodiment. As shown in FIG. 5, the waveform shaping filter according to this embodiment includes a resistor R2, transistors M2 and M3, a capacitor C2, and an amplifier A2. The current source Isignal in FIG. 5 is a current source that inputs the signal current Isignal to the waveform shaping filter.

  The resistor R2 (first resistor) has one end and the other end. One end of the resistor R2 is connected to the input terminal of the amplifier A2 and the current source Isignal. Thereby, the input current Isignal is input to the resistor R2 from one end. The other end of the resistor R2 is connected to the drain terminal of the transistor M2 and one end of the capacitor C1.

  The transistor M2 (first transistor) is an NMOS and includes a drain terminal (first terminal), a gate terminal (control terminal), and a source terminal (second terminal). The drain terminal is connected to the other end of the resistor R2 and one end of the capacitor C2. The gate terminal is connected to the output terminal of the amplifier A2. The source terminal is grounded.

  The transistor M3 (second transistor) is an NMOS and includes a drain terminal (first terminal), a gate terminal (control terminal), and a source terminal (second terminal). The gate terminal is connected to the gate terminal of the transistor M2 and the output terminal of the amplifier A2. The source terminal is grounded. The transistor M3 outputs an output current Iout from the drain terminal.

  The capacitor C2 (first capacitor) has one end and the other end. One end of the capacitor C2 is connected to the other end of the resistor R2 and the drain terminal of the transistor M2. The other end of the capacitor C2 is grounded.

  The amplifier A2 (first amplifier) is a non-inverting amplifier and includes an input terminal and an output terminal. The input terminal is connected to one end of the resistor R2 and the current source Isignal. Thus, the amplifier A2 receives the signal current Isignal or the terminal voltage at one end of the resistor R2 from the input terminal. The output terminal is connected to the gate terminals of the transistors M2 and M3.

  Next, the operation of the waveform shaping filter according to this embodiment will be described.

  As described above, the waveform shaping filter is configured such that the output of the amplifier A2 is fed back to the amplifier A2 via the transistor M2 and the resistor R2. For this reason, the input terminal of the amplifier A2 becomes a virtual ground point, and the voltage is substantially constant.

  At this time, the input impedance of the waveform shaping filter viewed from the current source Isignal is (1 / gm2) / A2 when the amplifier A2 is a voltage input type. Here, gm2 is the transconductance of the transistor M2, and A2 is the gain of the amplifier A2. In general, since the gain of the amplifier A2 is very large, the input impedance of the waveform shaping filter is very small.

  Therefore, when the signal current Isignal is input from the current source Isignal, the signal current Isignal flows through the resistor R2, and a voltage of Isignal × R2 is generated at the drain terminal of the transistor M2. Here, R2 is the resistance value of the resistor R2.

  Further, when a voltage is generated at the drain terminal of the transistor M2, a current Isignal × R2 × sC2 proportional to the time differentiation of the signal current Isignal flows through the capacitor C2. Here, C2 is a capacitance value of the capacitor C2.

  As a result, a current of Isignal × (1 + sC2 × R2) that is the sum of Isignal and Isignal × R2 × sC2 flows through the transistor M2.

  In the present embodiment, since the gate voltages and the source voltages of the transistors M2 and M3 are equal, a current that is twice the device size ratio of the current flowing through the transistor M2 flows through the transistor M3. Accordingly, when the sizes of the transistors M2 and M3 are the same, a current of Isignal × (1 + sC2 × R2) is output as the output current Iout from the drain terminal of the transistor M3.

  As described above, the waveform shaping filter according to the present embodiment superimposes and outputs the differential component of the signal current Isignal on the input signal current Isignal, as in the first embodiment. Thereby, the filter characteristic which emphasized the high frequency component of signal current Isignal is realizable.

  In the present embodiment, the load of the amplifier A2 is only the gate of the transistor M2. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current driving capability of the amplifier A2, and the power consumption of the waveform shaping filter can be reduced.

(First embodiment)
FIG. 6 is a diagram illustrating a first example of the waveform shaping filter according to the present embodiment. In this embodiment, the amplifier A2 is a current input type amplifier. As shown in FIG. 6, the amplifier A2 includes a transistor M21 and current sources Ib21 and Ib22.

  The transistor M21 is a PMOS having a source terminal, a gate terminal, and a drain terminal. The transistor M21 has a drain terminal connected to the current source Ib21 and the output terminal Out of the amplifier A2, a source terminal connected to the current source Ib22 and the input terminal In of the amplifier A2, and a gate terminal applied with a predetermined bias voltage Vbias. Is done.

  Current sources Ib21 and Ib22 supply predetermined bias currents Ib21 and Ib22 to the transistor M21, respectively.

  Next, the operation of the amplifier A2 will be described. In the following, it is assumed that the current values of the bias currents Ib21 and Ib22 are equal to Ib2 (Ib21 = Ib22 = Ib2).

  When the current ΔI is supplied from the input terminal In of the amplifier A2, a current of ΔI + Ib2 flows through the transistor M21. On the other hand, the bias current Ib2 is supplied to the transistor M21 from the current sources Ib21 and Ib22.

  When ΔI> 0, that is, when the voltage at the input terminal In of the amplifier A2 increases and current flows from one end of the resistor R2 to the input terminal In, the current supplied from the drain terminal of the transistor M21 is the current source Ib21. Therefore, the gate voltage of the transistors M2 and M3 connected to the output terminal Out rises.

  When the gate voltage of the transistor M2 increases, the drain voltage of the transistor M2 decreases and the voltage at one end of the resistor R2 (the voltage at the input terminal In of the amplifier A2) decreases. Thereby, feedback is applied so that the current ΔI becomes zero. That is, the source voltage of the transistor M21 (the voltage at the input terminal In of the amplifier A2) is substantially equal to the higher voltage than the bias voltage Vbias by the gate-source voltage Vgs21 when the bias current Ib2 flows through the transistor M21. .

  On the other hand, when ΔI <0, that is, when the voltage at the input terminal In of the amplifier A2 decreases and current flows from the input terminal In to one end of the resistor R2, the current supplied from the drain terminal of the transistor M21 is current. Since it is smaller than the current Ib2 drawn by the source Ib21, the gate voltages of the transistors M2 and M3 connected to the output terminal Out are lowered.

  When the gate voltage of the transistor M2 decreases, the drain voltage of the transistor M2 increases and the voltage at one end of the resistor R2 (the voltage at the input terminal In of the amplifier A2) increases. Thereby, feedback is applied so that the current ΔI becomes zero. That is, the source voltage of the transistor M21 (the voltage at the input terminal In of the amplifier A2) is substantially equal to the higher voltage than the bias voltage Vbias by the gate-source voltage Vgs21 when the bias current Ib2 flows through the transistor M21. .

  Therefore, the input terminal In of the amplifier A2 becomes a virtual ground point as described above, and the voltage is substantially constant. Thereby, the waveform shaping filter can be operated similarly to the first embodiment.

  As described above, a current input type amplifier can be used as the amplifier A2. When the current input type amplifier A2 is used, the single input impedance of the amplifier A2 is 1 / gm21, and the input impedance of the waveform shaping filter viewed from the current source Isignal is 1 / (A2 × gm2 + gm21). Here, gm21 is the transconductance of the transistor M21.

  Therefore, by using the current input type amplifier A2, it is possible to make the input impedance of the waveform shaping filter smaller than when the voltage input type amplifier A2 is used, and to suppress fluctuations in the voltage at the input terminal In of the amplifier A2. it can. Thereby, the error of the output current Iout due to the fluctuation of the input voltage of the waveform shaping filter can be reduced.

(Second embodiment)
FIG. 7 is a diagram illustrating a second example of the waveform shaping filter according to the present embodiment. In the present embodiment, the waveform shaping filter further includes a current source Idc2. Other configurations are the same as those in FIG.

  The current source Idc2 (first current source) is a DC current source having one end and the other end. One end of the current source Idc2 is connected to the other end of the resistor R2, the drain terminal of the transistor M2, and one end of the capacitor C2. In FIG. 7, the other end of the current source Idc2 is connected to the power source, but may be grounded. The current source Idc2 supplies an arbitrary DC current Idc2 that turns on the transistor M2.

  With this configuration, according to the present embodiment, the response speed when the pulsed signal current Isignal is input to the waveform shaping filter can be improved. The reason is as described in the second example of the first embodiment.

(Third embodiment)
FIG. 8 is a diagram illustrating a third example of the waveform shaping filter according to the present embodiment. In the present embodiment, the waveform shaping filter further includes a resistor R2a. Other configurations are the same as those in FIG.

  The resistor R2a (second resistor) has one end and the other end. One end of the resistor R2a is connected to the other end of the capacitor C2, and the other end of the resistor R2a is grounded.

  With such a configuration, in this embodiment, the filter characteristic of the waveform shaping filter is {1 + sC2 (R2 + R2a)} / (1 + sC2 × R2a). Thereby, the same effect as the third example of the first embodiment can be obtained. That is, according to the waveform shaping filter according to the present embodiment, the resistance value R2 for obtaining a predetermined enhancement characteristic can be made smaller by the resistance value R2a than the waveform shaping filter of FIG. Therefore, the power supply voltage of the waveform shaping filter can be lowered and the power consumption can be reduced.

(Third embodiment)
A waveform shaping filter according to the third embodiment will be described with reference to FIGS. FIG. 9 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 9, the waveform shaping filter according to the present embodiment includes resistors R1 and R1b, a transistor M1, a capacitor C1, and an amplifier A1. The current source Isignal in FIG. 9 is a current source that inputs the signal current Isignal to the waveform shaping filter.

  The resistor R1 (sixth resistor) has one end and the other end. The resistor R1 has one end grounded and the other end connected to the negative input terminal of the amplifier A1, the other end of the capacitor C1, and the source terminal of the transistor M1.

  The resistor R1b (fifth resistor) includes one end and the other end. The resistor R1b has one end grounded and the other end connected to the positive input terminal of the amplifier A1 and the current source Isignal. Thereby, the resistor R1b receives the input current Isignal from the other end.

  The capacitor C1 (seventh capacitor) has one end and the other end. The capacitor C1 has one end grounded and the other end connected to the other end of the resistor R1, the negative input terminal of the amplifier A1, and the source terminal of the transistor M1.

  The transistor M1 (sixteenth transistor) is an NMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The gate terminal is connected to the output terminal of the amplifier A1. The source terminal is connected to the negative input terminal of the amplifier A1, the other end of the capacitor C1, and the other end of the resistor R1. The transistor M1 outputs an output current Iout from the drain terminal.

  The amplifier A1 (fourth amplifier) is a differential amplifier, and includes a positive input terminal (first input terminal), a negative input terminal (second input terminal), and an output terminal. The positive input terminal is connected to the other end of the resistor R1b and the current source Isignal. Thereby, the amplifier A1 receives the terminal voltage of the other end of the resistor R1b from the positive input terminal. The negative input terminal is connected to the other end of the capacitor C1, the other end of the resistor R1, and the source terminal of the transistor M1. The output terminal is connected to the gate terminal of the transistor M1.

  Next, the operation of the waveform shaping filter according to this embodiment will be described.

  As described above, the waveform shaping filter is configured such that the output of the amplifier A1 is fed back to the negative input terminal of the amplifier A1 via the transistor M1. Due to this negative feedback, the positive input terminal and the negative input terminal of the amplifier A1 are virtually shorted, and the voltage at the negative input terminal becomes substantially equal to the voltage at the positive input terminal.

  A signal current Isignal from the current source Isignal flows through the resistor R1b and is converted into a voltage. Therefore, the voltage at the positive input terminal of the amplifier A1 is Isignal × R1b. Since the voltage at the positive input terminal is substantially equal to the voltage at the negative input terminal, the voltage at the negative input terminal is also Isignal × R1b. Therefore, a current of Isignal × R1b / R1 flows through the resistor R1, and a current of Isignal × R1b × sC1 flows through the capacitor C1. As a result, the transistor M1 outputs a current of Isignal × R1b × (1 + sC1R1) / R1 that is the sum of Isignal × R1b / R1 and Isignal × R1b × sC1 as the output current Iout.

  As described above, the waveform shaping filter according to this embodiment outputs the current component proportional to the input signal current Isignal superimposed on the differential component of the signal current Isignal. Thereby, the filter characteristic which emphasized the high frequency component of signal current Isignal is realizable.

  In the present embodiment, the load of the amplifier A1 is only the gate of the transistor M1. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current drive capability of the amplifier A1, and the power consumption of the waveform shaping filter can be reduced.

(First embodiment)
FIG. 10 is a diagram illustrating a first example of the waveform shaping filter according to the present embodiment. In this embodiment, the amplifier A1 is a current input type amplifier. As shown in FIG. 10, the amplifier A1 includes transistors MA1 and MA2, and current sources Ib1, Ib2, Ib3, and Ib4.

  The transistors MA1 and MA2 are NMOSs having a source terminal, a gate terminal, and a drain terminal.

  The drain terminal of the transistor MA1 is an output terminal of the amplifier A1, and is connected to the current source Ib1 and the gate terminal of the transistor M1. The gate terminal of the transistor MA1 is connected to the gate terminal of the transistor MA2 and the current source Ib2. The source terminal of the transistor MA1 is a positive input terminal of the amplifier A1, and is connected to the current source Ib3 and the other end of the resistor R1b.

  The drain terminal of the transistor MA2 is connected to the current source Ib2, the gate terminal of the transistor MA2, and the gate terminal of the transistor MA1. The gate terminal of the transistor MA2 is connected to the drain terminal of the transistor MA2, the gate terminal of the transistor MA1, and the current source Ib2. The source terminal of the transistor MA2 is a negative input terminal of the amplifier A1, and is connected to the current source Ib4, the other end of the resistor R1, the other end of the capacitor C1, and the source terminal of the transistor M1. The gate terminal and the drain terminal of the transistor MA2 are connected.

  Current sources Ib1, Ib2, Ib3, and Ib4 supply predetermined bias currents Ib1, Ib2, Ib3, and Ib4 to the transistors MA1 and MA2, respectively.

  Next, the operation of the amplifier A1 will be described. In the following, it is assumed that the current values of the bias currents Ib1, Ib2, Ib3, and Ib4 are equal to Ib (Ib1 = Ib2 = Ib3 = Ib4 = Ib). The sizes of the transistors MA1 and MA2 are assumed to be equal. Further, it is assumed that the resistance values of the resistor R1b and the resistor R1 are equal (R1b = R1).

  When the voltage at the other end of the resistor R1b increases, that is, when the source terminal voltage of the transistor MA1 increases, the gate-source voltage of the transistor MA1 decreases. As a result, the current flowing through the transistor MA1 is reduced from Ib by ΔI to become Ib−ΔI. That is, a current ΔI flows from the other end of the resistor R1b toward the positive input terminal of the amplifier A1. Since Ib−ΔI is smaller than the current Ib supplied from the current source Ib1, the drain terminal voltage of the transistor MA1 which is the output terminal of the amplifier A1 increases. Therefore, the gate terminal voltage of the transistor M1 increases.

  Along with this, the source terminal voltage of the transistor M1, that is, the source terminal voltage of the transistor MA2 increases. The transistor MA2 is supplied with the current from the current sources Ib2 to Ib, and the gate-source voltage of the transistor MA2 is substantially constant. For this reason, when the source terminal voltage of the transistor MA2 increases, the gate terminal voltage of the transistor MA2 also increases. Since the gate terminal of the transistor MA1 is connected to the gate terminal of the transistor MA2, the gate terminal voltage of the transistor MA1 increases, the gate-source voltage of the transistor MA1 increases, and the bias current Ib flows again.

  Since the transistors MA1 and MA2 are equal in size and both have a bias current Ib flowing, the gate-source voltages of the transistors MA1 and MA2 are substantially equal. As a result, the source terminal voltage of the transistor MA2 becomes the source terminal voltage of the transistor MA1. Operates to be approximately equal.

  On the other hand, when the voltage at the other end of the resistor R1b decreases, that is, when the source terminal voltage of the transistor MA1 decreases, the gate-source voltage of the transistor MA1 increases. Thereby, the current flowing through the transistor MA1 increases from Ib by ΔI, and becomes Ib + ΔI. That is, a current ΔI flows from the positive input terminal of the amplifier A1 toward the other end of the resistor R1b. Since Ib + ΔI is larger than the current Ib supplied from the current source Ib1, the drain terminal voltage of the transistor MA1 that is the output terminal of the amplifier A1 decreases. Therefore, the gate terminal voltage of the transistor M1 is lowered.

  Along with this, the source terminal voltage of the transistor M1, that is, the source terminal voltage of the transistor MA2 also decreases. The transistor MA2 is supplied with the current from the current sources Ib2 to Ib, and the gate-source voltage of the transistor MA2 is substantially constant. For this reason, when the source terminal voltage of the transistor MA2 decreases, the gate terminal voltage of the transistor MA2 also decreases. Since the gate terminal of the transistor MA1 is connected to the gate terminal of the transistor MA2, the gate terminal voltage of the transistor MA1 also decreases, the gate-source voltage of the transistor MA1 decreases, and the bias current Ib flows again. .

  Since the transistors MA1 and MA2 are equal in size and both have a bias current Ib flowing, the gate-source voltages of the transistors MA1 and MA2 are substantially equal. As a result, the source terminal voltage of the transistor MA2 becomes the source terminal voltage of the transistor MA1. Operates to be approximately equal.

  Therefore, as described above, the voltage at the source terminal of the transistor MA2 that is the negative input terminal of the amplifier A1 is substantially equal to the voltage at the source terminal of the transistor MA1 that is the positive input terminal of the amplifier A1, and the positive input terminal of the amplifier A1 It is a virtual short circuit with the negative input terminal. Thereby, the waveform shaping filter can be operated as described above.

  In FIG. 10, current sources Ib3 and Ib4 are provided to draw a bias current from the source terminals of the transistors MA1 and MA2. However, as shown in FIG. 11, the bias current flowing through the transistors MA1 and MA2 is supplied to the resistors R1b and R1. It is good also as a structure.

(Second embodiment)
FIG. 12 is a diagram illustrating a second example of the waveform shaping filter according to the present embodiment. In the present embodiment, the waveform shaping filter further includes a current source Idc1. Other configurations are the same as those in FIG.

  The current source Idc1 (sixth current source) is a direct current source having one end and the other end. One end of the current source Idc1 is connected to the negative input terminal of the amplifier A1, the other end of the resistor R1, the source terminal of the transistor M1, and the other end of the capacitor C1. In FIG. 12, the other end of the current source Idc1 is grounded, but may be connected to a power source. The current source Idc1 supplies an arbitrary DC current Idc1 that turns on the transistor M1.

  With this configuration, according to the present embodiment, as described with reference to FIG. 3, the response speed when the pulse-shaped signal current Isignal is input to the waveform shaping filter can be improved.

(Third embodiment)
FIG. 13 is a diagram illustrating a third example of the waveform shaping filter according to the present embodiment. In the present embodiment, the waveform shaping filter further includes a resistor R1a. Other configurations are the same as those in FIG.

  The resistor R1a (seventh resistor) includes one end and the other end. One end of the resistor R1a is connected to the other end of the capacitor C1, and the other end of the resistor R1a is connected to the negative input terminal of the amplifier A1.

  With this configuration, in this embodiment, the filter characteristic of the waveform shaping filter is R1b {1 + sC1 (R1 + R1a)} / {(1 + sC1R1a) R1}. That is, when the signal current Isignal is input to the waveform shaping filter, Isingal × R1b {1 + sC1 (R1 + R1a)} / {(1 + sC1R1a) R1} is output as the output current Iout. The emphasis characteristic that emphasizes the high frequency component of the signal current Isignal is realized by 1 + sC1 (R1 + R1a).

  Therefore, by making the capacitance value C1 of FIGS. 9 and 13 the same and making the resistance value R1 of FIG. 9 and the resistance value R1 + R1a of FIG. 13 the same, the emphasis characteristics of FIGS. 9 and 13 can be matched. That is, according to the waveform shaping filter according to the present embodiment, the resistance value R1 for obtaining a predetermined enhancement characteristic can be made smaller by the resistance value R1a than the waveform shaping filter of FIG.

  When the resistance value R1 is decreased, the voltage applied to the resistor R1 is decreased, and the source voltage of the transistor M1 is decreased. Therefore, the power supply voltage of the waveform shaping filter can be lowered and the power consumption can be reduced.

(Fourth embodiment)
FIG. 14 is a diagram illustrating a fourth example of the waveform shaping filter according to the present embodiment. In the present embodiment, the waveform shaping filter further includes a capacitor C1a. Other configurations are the same as those in FIG.

  The capacitor C1a (eighth capacitor) has one end and the other end. The capacitor C1a has one end grounded and the other end connected to the other end of the resistor R1b, the current source Isignal, and the positive input terminal of the amplifier A1.

  With such a configuration, according to the present embodiment, a low-pass characteristic is realized by the resistor R1b and the capacitor C1a. The cut-off frequency of the low-pass filter is 1 / (2π × R1b × C1a). By setting the capacitance value C1a so that the cutoff frequency is higher than the high frequency component to be emphasized, unnecessary high frequency noise superimposed on the signal current Isignal can be removed.

(Fourth embodiment)
A waveform shaping filter according to the fourth embodiment will be described with reference to FIGS. FIG. 15 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 15, the waveform shaping filter according to the present embodiment is a modification of the first embodiment, and further includes transistors Mcm1 and Mcm2 and a current source Idcm. Hereinafter, the difference from the first embodiment will be mainly described.

  The transistor Mcm1 is an NMOS, the source terminal is grounded, the drain terminal is connected to one end of the capacitor C1, and the gate terminal is connected to the current source Idcm and the gate terminal of the transistor Mcm2. The transistor Mcm1 has a gate terminal connected to a drain terminal.

  The transistor Mcm2 is an NMOS, the source terminal is grounded, the gate terminal is connected to the current source Idcm, the gate terminal of the transistor Mcm1, the drain terminal is connected to the other end of the capacitor C1, the other end of the resistor R1, and the transistor And connected to the source terminal of M1.

  The transistors Mcm1 and Mcm2 constitute a current mirror circuit (first current mirror circuit). The input terminal of the current mirror circuit is the drain terminal of the transistor Mcm1, and the output terminal is the drain terminal of the transistor Mcm2. If the sizes of the transistors Mcm1 and Mcm2 are equal, the current flowing through the transistor Mcm1 is equal to the current flowing through the transistor Mcm2.

  The current source Idcm supplies a bias current Idcm for operating the current mirror circuit formed by the transistors Mcm1 and Mcm2.

  In the present embodiment, the capacitor C1 has one end connected to the drain and gate terminals of the transistor Mcm1, the gate terminal of the transistor Mcm2, and the current source Idcm, and the other end connected to the other end of the resistor R1 and the transistor The source terminal of M1 and the drain terminal of the transistor Mcm2 are connected.

  With such a configuration, assuming that the sizes of the transistors Mcm1 and Mcm2 are equal, the current flowing through the transistor M1 is the signal current Isignal, the current Isignal × R1 × sC1 flowing through the capacitor C1, and the current flowing through the capacitor C1 as a current mirror circuit. Is the sum of the current Isignal × R1 × sC1 folded (inverted polarity) and Isignal × (1 + 2sC1R1).

  As can be seen from the above formula, according to the present embodiment, the capacitance value C1 can be halved compared to the first embodiment. That is, a time constant similar to that of the first embodiment can be realized with a capacitance value C1 that is half that of the first embodiment.

  In the above, the case where the sizes of the transistors Mcm1 and Mcm2 are equal has been described as an example. However, in the present embodiment, the sizes of the transistors Mcm1 and Mcm2 may be different. By setting the channel width of the transistor Mcm2 to k times the channel width of the transistor Mcm1, the capacitance value C1 can be 1 / (1 + k) times that of the first embodiment. Thus, the circuit area can be reduced by reducing the capacitance value C1 of the capacitor C1.

  In the example of FIG. 15, the other end of the capacitor C1 is connected to the current mirror circuit. However, a configuration in which the capacitor C1 is divided and only a part thereof is connected to the current mirror circuit is also possible.

  Further, the current Idcm supplied from the current source Idcm as the bias current of the current mirror circuit also flows through the transistor M1. Therefore, as described with reference to FIG. 3, the current source Idcm can also be used as a direct current for improving the response speed when the pulsed signal current Isignal is input to the waveform shaping filter. .

  Furthermore, the input impedance of the current mirror circuit is the reciprocal of the transconductance of the transistor Mcm1, and if the input impedance is large, the time constant of the filter is affected. Therefore, as shown in FIG. 16, a transistor Mcm3 and a current source Idcm2 may be added to the current mirror circuit.

  The transistor Mcm3 is a PMOS, the gate terminal is applied with an iris voltage Vb, the source terminal is connected to the current source Idcm, one end of the capacitor C1, and the drain terminal of the transistor Mcm1, and the drain terminals are the transistors Mcm1 and Mcm2. And the current source Idcm2. The current source Idcm2 supplies a bias current Idcm2 for operating the transistor Mcm3.

  With such a configuration, a change in the drain terminal voltage of the transistor Mcm1 can be amplified and applied to the gate terminal of the transistor Mcm1. Thereby, the input impedance of the current mirror circuit can be lowered and the influence on the time constant of the filter can be reduced.

(Fifth embodiment)
A waveform shaping filter according to the fifth embodiment will be described with reference to FIG. FIG. 17 is a diagram illustrating the waveform shaping filter according to the present embodiment. As illustrated in FIG. 17, the waveform shaping filter according to the present embodiment is a modification of the second embodiment, and includes transistors Mcm1 and Mcm2 and a current source Idcm. Other configurations are the same as those in FIG. The configuration of the current mirror circuit (first current mirror circuit) configured by the transistors Mcm1 and Mcm2 and the current source Idcm is the same as that in FIG. The capacitor C2 in this embodiment corresponds to the capacitor C1 in FIG.

  With this configuration, according to the present embodiment, the capacitance value C2 can be halved compared to the second embodiment. That is, a time constant similar to that of the second embodiment can be realized with a capacitance value C2 that is half that of the second embodiment.

(Sixth embodiment)
A waveform shaping filter according to the sixth embodiment will be described with reference to FIG. FIG. 18 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 18, the waveform shaping filter according to the present embodiment is a modification of the third embodiment, and includes transistors Mcm1 and Mcm2 and a current source Idcm. Other configurations are the same as those in FIG. The configuration of the current mirror circuit (third current mirror circuit) configured by the transistors Mcm1 and Mcm2 and the current source Idcm is the same as that in FIG.

  With this configuration, according to the present embodiment, the capacitance value C1 can be halved compared to the third embodiment. That is, a time constant similar to that of the third embodiment can be realized with a capacitance value C1 that is half that of the third embodiment.

(Seventh embodiment)
A waveform shaping filter according to the seventh embodiment will be described with reference to FIGS. FIG. 19 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 19, the waveform shaping filter according to this embodiment is a modification of the second embodiment, and further includes a low input impedance circuit Z. Hereinafter, the difference from the second embodiment will be mainly described.

  In the present embodiment, the other end of the capacitor C2 is connected to the drain terminal of the transistor M3.

  The low input impedance circuit Z is connected to the drain terminal of the transistor M3 and the end of the capacitor C2. The low input impedance circuit Z adds the current flowing from the other end of the capacitor C2 to the output current output from the drain terminal of the transistor M3.

  With such a configuration, the current flowing through the low input impedance circuit Z includes a current Isignal × (1 + sC2R2) obtained by copying the sum of the current Isignal × R2 × sC2 and the signal current Isignal flowing from one end of the capacitor C2 into the transistor M2, and the capacitor C2. Is the sum of the current Isignal × R2 × sC2 flowing into the capacitor C2 from the other end. That is, Isignal × (1 + 2sC2R2) flows through the low input impedance circuit Z as the output current of the waveform shaping filter.

  As can be seen from the above formula, according to the present embodiment, the capacitance value C2 can be halved compared to the second embodiment. That is, a time constant similar to that of the second embodiment can be realized with a capacitance value C2 that is half that of the second embodiment.

  In the example of FIG. 19, the other end of the capacitor C2 is connected to the drain terminal of the transistor M3. However, a configuration in which the capacitor C2 is divided and only a part thereof is connected to the drain terminal of the transistor M3 is also possible.

(First embodiment)
FIG. 20 is a diagram showing a first embodiment of the waveform shaping filter of FIG. In FIG. 20, the low input impedance circuit Z is realized by a grounded gate amplifier circuit. The common-gate amplifier circuit includes a transistor MC.

  The transistor MC is an NMOS, the bias voltage Vb is applied to the gate terminal, the source terminal is connected to the other end of the capacitor C2 and the other end of the transistor M3, and the output current Iout is output from the drain terminal.

  The input impedance of the grounded-gate amplifier circuit is almost determined by the reciprocal of the transconductance of the transistor MC. Therefore, by increasing the channel width / channel length of the transistor MC, the transconductance can be increased and the input impedance can be lowered.

(Second embodiment)
FIG. 21 is a diagram showing a second embodiment of the waveform shaping filter of FIG. In FIG. 21, the low input impedance circuit Z is realized by a regulated cascode circuit. The regulated cascode circuit includes a transistor MC and an inverting amplifier AC.

  The inverting amplifier AC has an input terminal connected to the other end of the capacitor C2 and the drain terminal of the transistor M3, and an output terminal connected to the gate terminal of the transistor MC. The inverting amplifier AC inverts and amplifies the source terminal voltage of the transistor MC and applies it to the gate terminal of the transistor MC. The gain of the inverting amplifier AC is AC. Other configurations are the same as those in FIG.

  With such a configuration, the input impedance of the low input impedance circuit Z is a reciprocal of AC times the transconductance of the transistor MC. That is, in the example of FIG. 21, the input impedance of the low input impedance circuit Z can be 1 / AC times that of FIG.

(Third embodiment)
FIG. 22 is a diagram showing a third embodiment of the waveform shaping filter of FIG. In FIG. 22, the low input impedance circuit Z is realized by a transimpedance circuit. The transimpedance circuit includes an inverting amplifier AC and a resistor RT.

  The inverting amplifier AC has an input terminal connected to the other end of the capacitor C2, the other end of the transistor M3, and one end of the resistor RT, and the other end connected to the other end of the resistor RT. That is, the resistor RT is connected between the input terminal and the output terminal of the inverting amplifier AC. Even with such a configuration, the low input impedance circuit Z can be realized.

(Eighth embodiment)
A waveform shaping filter according to the eighth embodiment will be described with reference to FIGS. In the present embodiment, a waveform shaping filter that combines the fourth embodiment and the seventh embodiment will be described. FIG. 23 is a diagram illustrating a waveform shaping filter in which the current mirror circuit and the low input impedance circuit Z are applied to the first embodiment.

  As shown in FIG. 23, the waveform shaping filter includes transistors Mcm1 and Mcm2 and a low input impedance circuit Z. Hereinafter, the difference from the first embodiment will be mainly described.

  The transistor Mcm1 is a PMOS, the source terminal is connected to the power supply line (second reference voltage line), the gate terminal is connected to the gate terminal of the transistor Mcm2, and the drain terminal is connected to the drain terminal of the transistor M1. . The transistor Mcm1 has a gate terminal connected to a drain terminal.

  The transistor Mcm2 is a PMOS, the source terminal is connected to the power supply line, the gate terminal is connected to the gate terminal of the transistor Mcm1, and the drain terminal is connected to the other end of the capacitor C1 and the low input impedance circuit Z. .

  The transistors Mcm1 and Mcm2 constitute a current mirror circuit (second current mirror circuit). The input terminal of this current mirror circuit is the drain terminal of the transistor Mcm1, and the output terminal is the drain terminal of the transistor Mcm2. If the sizes of the transistors Mcm1 and Mcm2 are equal, the current flowing through the transistor Mcm1 is equal to the current flowing through the transistor Mcm2.

  The low input impedance circuit Z is connected to the other end of the capacitor C1 and the drain terminal of the transistor Mcm2. The low input impedance circuit Z adds the current flowing from the other end of the capacitor C1 to the output current output from the drain terminal of the transistor Mcm2.

  In the present embodiment, a current Isignal × (1 + sC1R1) that is the sum of the signal current Isignal and the current Isignal × R1 × sC1 flowing through the capacitor C1 flows through the transistor M1. This is the same as in FIG.

  Here, if the sizes of the transistors Mcm1 and Mcm2 are equal, the current flowing through the transistor Mcm2 is the current flowing through the transistor Mcm1, that is, the current flowing through the transistor M1, and is Isignal × (1 + sC1R1). On the other hand, the current flowing out from the other end of the capacitor C1 is Isignal × sC1R1.

  Therefore, the current Isignal × (1 + 2sC1R1) which is the sum of the current Isignal × (1 + sC1R1) flowing through the transistor Mcm2 and the current Isignal × sC1R1 flowing out from the other end of the capacitor C1 flows through the low input impedance circuit Z.

  As can be seen from the above formula, the configuration of FIG. 23 can reduce the capacitance value C1 by half compared to the first embodiment. That is, a time constant similar to that of the first embodiment can be realized with a capacitance value C1 that is half that of the first embodiment.

  FIG. 24 is a diagram illustrating a waveform shaping filter in which a current mirror circuit (fourth current mirror circuit) and a low input impedance circuit Z are applied to the third embodiment. The configurations of the current mirror circuit and the low input impedance circuit Z are the same as those in FIG. That is, the input terminal of the current mirror circuit in FIG. 24 is the drain terminal of the transistor M1, and the output terminal is the drain terminal of the transistor Mcm2. Other configurations are the same as those in FIG.

  In the example of FIG. 24, as in FIG. 23, the current flowing through the low input impedance circuit Z is the sum of the current Isignal × (1 + sC1R1) flowing through the transistor M1 and the current Isignal × sC1R1 flowing out from the other end of the capacitor C1. Become. This is the same as FIG.

  Therefore, with the configuration of FIG. 24, the capacitance value C1 can be halved compared to the third embodiment. That is, a time constant similar to that of the third embodiment can be realized with a capacitance value C1 that is half that of the third embodiment.

  In the present embodiment, the other end of the capacitor C1 is connected to the current mirror circuit. However, a configuration in which the capacitor C1 is divided and only a part thereof is connected to the current mirror circuit is also possible. Further, the low input impedance circuit Z can be realized by the grounded gate amplifier circuit, the regulated cascode circuit, the transimpedance circuit, and the like described with reference to FIGS.

(Ninth embodiment)
A waveform shaping filter according to the ninth embodiment will be described with reference to FIGS. FIG. 25 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 25, the waveform shaping filter according to this embodiment further includes a resistor R11, a capacitor C11, and a voltage buffer VB11. Other configurations are the same as those in FIG.

  The resistor R11 (eighth resistor) has one end and the other end. The resistor R11 has one end connected to the source terminal of the transistor M1 and one end of the capacitor C11, and the other end connected to the other end of the resistor R1, the negative input terminal of the amplifier A1, one end of the capacitor C1, and a voltage. And is connected to the input terminal of the buffer VB11.

  The capacitor C11 (the ninth capacitor) has one end and the other end. The capacitor C11 has one end connected to the source terminal of the transistor M1 and one end of the resistor R11, and the other end connected to the output terminal of the voltage buffer VB11.

  The voltage buffer VB11 includes an input terminal and an output terminal. The voltage buffer VB11 has an input terminal connected to the other end of the resistor R1, one end of the capacitor C1, the other end of the resistor R11, and a negative input terminal of the amplifier A1, and an output terminal connected to the other end of the capacitor C11. Connected to.

  Next, the operation of the waveform shaping filter according to this embodiment will be described.

  As described above, the waveform shaping filter is configured such that the output of the amplifier A1 is fed back to the negative input terminal of the amplifier A1 via the transistor M1 and the resistor R11. Due to this negative feedback, the positive input terminal and the negative input terminal of the amplifier A1 are virtually shorted, and the voltage at the negative input terminal becomes substantially equal to the voltage at the positive input terminal.

  The signal current Isignal from the current source Isignal flows through the resistor R1b and is converted into a voltage. For this reason, the positive input terminal voltage of the amplifier A1 is Isignal × R1b. Since the voltage at the positive input terminal is substantially equal to the voltage at the negative input terminal, the voltage at the negative input terminal is also Isignal × R1b. Therefore, a current of Isignal × R1b / R1 flows through the resistor R1, and a current of Isignal × R1b × sC1 flows through the capacitor C1.

  Since the current flowing through the resistor R1 and the capacitor C1 flows through the resistor R11, the voltage at one end of the resistor R11 (the source terminal voltage of the transistor M1) is Isignal × R1b [1+ (1 + sC1R1) R11 / R1]. The voltage applied to the capacitor C11 is Isignal × R1b [1+ (1 + sC1R1) R11 / R1] −Isignal × R1b = Isignal × R1b × R11 × (1 + sC1R1) / R1, and the current flowing in the capacitor C11 is Isignal × R1b × R1 sC11 (1 + sC1R1) / R1.

  As a result, a current of Isignal × R1b × (1 + sC1R1) (1 + sC11R11) / R1 that is the sum of currents flowing through the resistor R11 and the capacitor C11 flows through the transistor M1, and is output as an output current Iout from the drain terminal.

  As described above, the waveform shaping filter according to the present embodiment includes a current obtained by superimposing the differential component of the signal current Isignal on a current proportional to the input signal current Isignal, a current proportional to the differential component of the superimposed current, Output the sum of. With such a configuration, it is possible to realize a filter characteristic that emphasizes a high-frequency component, which is suitable when the signal current Isignal has a frequency characteristic that has passed through the first-order low-pass filter twice.

  In the present embodiment, the load of the amplifier A1 is only the gate of the transistor M1. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current drive capability of the amplifier A1, and the power consumption of the waveform shaping filter can be reduced.

  Further, as shown in FIG. 26, resistors R1a and 11a are respectively connected in series with capacitors C1 and C11, the resistance values R1 and R11 are reduced, the voltage applied to the resistors R1 and R11 is reduced, and the transistor M1 The source terminal voltage may be lowered. Thereby, the power supply voltage of a waveform shaping filter can be reduced and power consumption can be further reduced.

(First embodiment)
FIG. 27 is a diagram illustrating a first example of the waveform shaping filter according to the present embodiment. In this embodiment, the voltage buffer VB11 includes transistors MB11a and MB11b and current sources Ib11a and Ib11b.

  The transistor MB11a is a PMOS, the drain terminal is connected to the current source Ib11b and the gate terminal of the transistor MB11b, the source terminal is the drain terminal of the transistor MB11b, the current source Ib11a, and the other end of the capacitor C11. The gate terminal is connected to the other end of the resistor R1, one end of the capacitor C1, the negative input terminal of the amplifier A11, and the other end of the resistor R11. The gate terminal of the transistor MB11a is an input terminal of the voltage buffer VB11, and the source terminal is an output terminal of the voltage buffer VB11.

  The transistor MB11b is an NMOS, the source terminal is grounded, the gate terminal is connected to the current source Ib11b and the drain terminal of the transistor MB11a, and the drain terminal is connected to the current source Ib11a and the source terminal of the transistor MB11a. And the other end of the capacitor C11. The drain terminal of the transistor MB11b is the output terminal of the voltage buffer VB11.

  Current sources Ib11a and Ib11b supply bias currents Ib11a and Ib11b to the transistors MB11a and MB11b, respectively.

  Feedback is applied to the transistor MB11a by the transistor MB11b so that the bias current Ib11b supplied from the current source Ib11b flows. For example, when the voltage at the gate terminal of the transistor MB11a increases (decreases), at that moment, the gate-source voltage of the transistor MB11a decreases (increases), and the current flowing through the transistor MB11a decreases (increases) from the bias current Ib11b. .

  As a result, the gate terminal voltage of the transistor MB11b decreases (rises), the current flowing through the transistor MB11b decreases (increases), the ratio of the current supplied from the current source Ib11a to the transistor MB11a increases (decreases), and the source terminal of the transistor MB11a The voltage increases (decreases), and the bias current Ib11b flows through the transistor MB11a.

  Thus, since feedback is applied so that the current flowing through the transistor MB11a becomes the bias current Ib11b, the gate-source voltage of the transistor MB11a becomes substantially constant. Therefore, the source terminal voltage of the transistor MB11a is a voltage level-shifted by the gate-source voltage in accordance with the voltage applied to the gate terminal. Thereby, the function of the voltage buffer VB11 is realized.

  Since feedback is applied so that the current flowing through the transistor MB11a becomes the bias current Ib11b, the current flowing out from the other end of the capacitor C11 flows through the transistor MB11b.

(10th Embodiment)
A waveform shaping filter according to the tenth embodiment will be described with reference to FIGS. FIG. 28 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 28, the waveform shaping filter according to this embodiment includes a resistor R12, a capacitor C12, and a current buffer IB12. Other configurations are the same as those in FIG.

  The resistor R12 (the ninth resistor) has one end and the other end. The resistor R12 has one end connected to the negative input terminal of the amplifier A1 and one end of the capacitor C12, and the other end connected to the other end of the resistor R1, the source terminal of the transistor M1, and one end of the capacitor C1. And is connected to the output terminal of the buffer IB12.

  The capacitor C12 (tenth capacitor) has one end and the other end. The capacitor C12 has one end connected to the negative input terminal of the amplifier A1 and one end of the resistor R12, and the other end connected to the input terminal of the current buffer IB12.

  The current buffer IB12 includes an input terminal and an output terminal. The current buffer IB12 has an input terminal connected to the other end of the capacitor C12, and an output terminal connected to the other end of the resistor R1, the source terminal of the transistor M1, one end of the capacitor C1, and the other end of the resistor R12. Connected.

  Next, the operation of the waveform shaping filter according to this embodiment will be described.

  As described above, the waveform shaping filter is configured such that the output of the amplifier A1 is fed back to the negative input terminal of the amplifier A1 via the transistor M1 and the resistor R12. Due to this negative feedback, the positive input terminal and the negative input terminal of the amplifier A1 are virtually shorted, and the voltage at the negative input terminal becomes substantially equal to the voltage at the positive input terminal.

  The signal current Isignal from the current source Isignal flows through the resistor R1b and is converted into a voltage. Therefore, the voltage at the positive input terminal of the amplifier A1 is Isignal × R1b. Since the voltage at the positive input terminal is substantially equal to the voltage at the negative input terminal, the voltage at the negative input terminal is also Isignal × R1b. The other end of the capacitor C12 is connected to the input terminal of the current buffer IB12. Since the input impedance of the current buffer IB12 is low, a current of Isignal × R1b × sC12 flows through the capacitor C12.

  Since this current flows through the resistor R12, the voltage at one end of the resistor R12 is Isignal × R1b + Isignal × R1b × sC12R12 = Isignal × R1b × (1 + sC12R12). Therefore, a current of Isignal × R1b × (1 + sC12R12) / R1 flows through the resistor R1, and a current of Isignal × R1b × (1 + sC12R12) × sC1 flows through the capacitor C1.

  The current Isignal × R1b × sC12 flowing through the resistor R12 has the same magnitude and is canceled at one end of the resistor R12 by the output current of the current buffer IB12 having the opposite polarity. Therefore, a current of Isignal × R1b × (1 + sC12R12) (1 + sC1R1) / R1 that is the sum of currents flowing through the resistor R1 and the capacitor C1 flows through the transistor M1, and is output as an output current Iout from the drain terminal.

  As described above, the waveform shaping filter according to the present embodiment has a current in which a differential component of the signal current Isignal is superimposed on a current proportional to the input signal current Isignal, a current proportional to the differential component of the superimposed signal, Output the sum of. With such a configuration, it is possible to realize a filter characteristic that emphasizes a high-frequency component, which is suitable when the signal current Isignal has a frequency characteristic that has passed through the first-order low-pass filter twice.

  In the present embodiment, the load of the amplifier A1 is only the gate of the transistor M1. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current drive capability of the amplifier A1, and the power consumption of the waveform shaping filter can be reduced.

(First embodiment)
FIG. 29 is a diagram illustrating a first example of the waveform shaping filter according to the present embodiment. In the present embodiment, as shown in FIG. 29, the current buffer IB12 includes transistors MB12a and MB12b and current sources Ib12a, Ib12b, and Ib12c.

  The transistor MB12a is a PMOS, and has a drain terminal connected to the current source Ib12b, the source terminal of the transistor M1, one end of the capacitor C1, the other end of the resistor R1, and the other end of the resistor R12, and a gate terminal. Are connected to the drain terminal of the transistor MB12b and the current source Ib12c, and the source terminal is connected to the current source Ib12a, the gate terminal of the transistor MB12b, and the other end of the capacitor C12. The drain terminal of the transistor MB12a is an output terminal of the current buffer IB12, and the source terminal of the transistor MB12a is an input terminal of the current buffer IB12.

  The transistor MB12b is a PMOS, the drain terminal is connected to the current source Ib12c and the gate terminal of the transistor MB12a, and the gate terminal is connected to the source terminal of the transistor MB12a, the current source Ib12a, and the other end of the capacitor C12. The source terminal is connected to the power supply line. The gate terminal of the transistor MB12b is an input terminal of the current buffer IB12.

  Current sources Ib12a, Ib12b, and Ib12c supply bias currents Ib12a, Ib12b, and Ib12c to the transistors MB12a and MB12b, respectively.

  With such a configuration, the current buffer IB12 in the present embodiment can be configured.

(Eleventh embodiment)
A waveform shaping filter according to the eleventh embodiment will be described with reference to FIG. FIG. 30 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 30, the waveform shaping filter according to the present embodiment includes a resistor R11 (tenth resistor), a capacitor C11 (an eleventh capacitor), and a voltage buffer VB11. Other configurations are the same as those in FIG. The configurations of the resistor R11, the capacitor C11, and the voltage buffer VB11 are the same as those in FIG.

  With this configuration, when the signal current Isignal is input from the current source Isignal, the signal current Isignal flows through the resistor R1, and the voltage at the other end of the resistor R1 is Isignal × R1. Therefore, a current of Isignal × R1 × sC1 flows through the capacitor C1. A current of Isignal × (1 + sC1R1) that is the sum of the current flowing through the resistor R1 and the current flowing through the capacitor C1 flows through the resistor R11.

  Therefore, the source terminal voltage of the transistor M1 is Isignal × R1 + Isignal × R11 × (1 + sC1R1). A voltage of Isignal × R1 is applied to the voltage at the other end of the capacitor C11 via the voltage buffer VB11. Therefore, a voltage of Isignal × R11 × (1 + sC1R1) is applied to the capacitor C11, and the flowing current is Isignal × sC11R11 × (1 + sC1R1). A current of Isignal × (1 + sC1R1) (1 + sC11R11), which is the sum of the current flowing through the resistor R11 and the current flowing through the capacitor C11, flows through the transistor M1, and is output as an output current Iout from the drain terminal.

  As described above, the waveform shaping filter according to the present embodiment includes a current obtained by superimposing the differential component of the signal current Isignal on a current proportional to the input signal current Isignal, a current proportional to the differential component of the superimposed current, Output the sum of. With such a configuration, it is possible to realize a filter characteristic that emphasizes a high-frequency component, which is suitable when the signal current Isignal has a frequency characteristic that has passed through the first-order low-pass filter twice.

  In the present embodiment, the load of the amplifier A1 is only the gate of the transistor M1. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current drive capability of the amplifier A1, and the power consumption of the waveform shaping filter can be reduced.

(Twelfth embodiment)
A waveform shaping filter according to the twelfth embodiment will be described with reference to FIG. FIG. 31 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 31, the waveform shaping filter according to the present embodiment includes a resistor R11, a capacitor C11, and a voltage buffer VB11. Other configurations are the same as those in FIG. The configurations of the resistor R11, the capacitor C11, and the voltage buffer VB11 are the same as those in FIG.

  With this configuration, when the signal current Isignal is input from the current source Isignal, the signal current Isignal flows through the resistor R2, and the voltage at the other end of the resistor R2 is Isignal × R2. Therefore, a current of Isignal × R2 × sC2 flows through the capacitor C2. A current of Isignal × (1 + sC2R2) that is the sum of the current flowing through the resistor R2 and the current flowing through the capacitor C2 flows through the resistor R11.

  Therefore, the drain terminal voltage of the transistor M2 is Isignal × R2 + Isignal × R11 × (1 + sC2R2). A voltage of Isignal × R2 is applied to the voltage at the other end of the capacitor C11 via the voltage buffer VB11. Therefore, a voltage of Isignal × R11 × (1 + sC2R2) is applied to the capacitor C11, and the flowing current is Isignal × sC11R11 × (1 + sC2R2). A current of Isignal × (1 + sC2R2) (1 + sC11R11) which is the sum of the current flowing through the resistor R11 and the current flowing through the capacitor C11 flows through the transistor M2.

  In the present embodiment, since the gate terminal voltage and the source terminal voltage of the transistors M2 and M3 are equal, a current that is twice the device size ratio of the current flowing through the transistor M2 flows through the transistor M3. Therefore, when the sizes of the transistors M2 and M3 are the same, a current of Isignal × (1 + sC2R2) (1 + sC11R11) is output as the output current Iout from the drain terminal of the transistor M3.

  As described above, the waveform shaping filter according to the present embodiment includes a current obtained by superimposing the differential component of the signal current Isignal on a current proportional to the input signal current Isignal, a current proportional to the differential component of the superimposed current, Output the sum of. As a result, it is possible to realize a filter characteristic that emphasizes the high-frequency component, which is suitable when the signal current Isignal has a frequency characteristic that has passed through the first-order low-pass filter twice.

  In the present embodiment, the load of the amplifier A2 is only the gates of the transistors M2 and M3. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current driving capability of the amplifier A2, and the power consumption of the waveform shaping filter can be reduced.

(13th Embodiment)
A waveform shaping filter according to the thirteenth embodiment will be described with reference to FIG. FIG. 32 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 32, the waveform shaping filter according to this embodiment includes a resistor R13, a capacitor C13, and a current buffer IB13. Other configurations are the same as those in FIG.

  The resistor R13 (11th resistor) includes one end and the other end. The resistor R13 has one end connected to the other end of the resistor R1 and one end of the capacitor C13, and the other end connected to one end of the capacitor C1, the source terminal of the transistor M1, and the output terminal of the current buffer IB13. Connected.

  The capacitor C13 (the twelfth capacitor) has one end and the other end. The capacitor C13 has one end connected to the other end of the resistor R1 and one end of the resistor R13, and the other end connected to the input terminal of the current buffer IB13.

  The current buffer IB13 has an input terminal connected to the other end of the capacitor C13, and an output terminal connected to the source terminal of the transistor M1, the other end of the resistor R13, and one end of the capacitor C1.

  With this configuration, when the signal current Isignal is input from the current source Isignal, the signal current Isignal flows through the resistor R1, and the voltage at the other end of the resistor R1 is Isignal × R1. The other end of the capacitor C13 is connected to the input terminal of the current buffer IB13. Since the input impedance of the current buffer IB13 is low, a current of Isignal × R1 × sC13 flows through the capacitor C13. Since this current flows through the resistor R13, a current of Isignal × (1 + sC13R1) that is the sum of the current flowing through the resistor R1 and the current flowing through the capacitor C13 flows through the resistor R13.

  Therefore, the source terminal voltage of the transistor M1 is Isignal × R1 + Isignal × R13 × (1 + sC13R1), and a current of Isignal × sC1R1 + Isignal × sC1R13 × (1 + sC13R1) flows through the capacitor C1. The transistor M1 has a current of Isignal × (1 + sC1R1) + Isignal × sC1R13 (1 + sC13R1) obtained by subtracting the current flowing through the capacitor C13 via the current buffer IB13 from the sum of the current flowing through the capacitor C1 and the current flowing through the resistor R13. Current flows. Here, if C13 = C1, the current flowing through the transistor M1 is Isignal × (1 + sC13R1) (1 + sC1R13), and this current is output as the output current Iout from the drain terminal.

  As described above, the waveform shaping filter according to the present embodiment includes a current obtained by superimposing the differential component of the signal current Isignal on a current proportional to the input signal current Isignal, a current proportional to the differential component of the superimposed current, Output the sum of. With such a configuration, it is possible to realize a filter characteristic that emphasizes a high-frequency component, which is suitable when the signal current Isignal has a frequency characteristic that has passed through the first-order low-pass filter twice.

  In the present embodiment, the load of the amplifier A1 is only the gate of the transistor M1. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current drive capability of the amplifier A1, and the power consumption of the waveform shaping filter can be reduced.

(14th Embodiment)
A waveform shaping filter according to the fourteenth embodiment will be described with reference to FIG. FIG. 33 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 33, the waveform shaping filter according to this embodiment includes a resistor R13, a capacitor C13, and a current buffer IB13. Other configurations are the same as those in FIG. The configurations of the resistor R13, the capacitor C13, and the current buffer IB13 are the same as those in FIG.

  With this configuration, when the signal current Isignal is input from the current source Isignal, the signal current Isignal flows through the resistor R2, and the voltage at the other end of the resistor R2 is Isignal × R2. The other end of the capacitor C13 is connected to the input terminal of the current buffer IB13. Since the input impedance of the current buffer IB13 is low, a current of Isignal × R2 × sC13 flows through the capacitor C13. Since this current flows through the resistor R13, Isignal × (1 + sC13R2) which is the sum of the current flowing through the resistor R2 and the current flowing through the capacitor C13 flows through the resistor R13.

  Therefore, the drain terminal voltage of the transistor M2 is Isignal × R2 + Isignal × R13 × (1 + sC13R2), and a current of Isignal × sC2R2 + Isignal × sC2R13 × (1 + sC13R2) flows through the capacitor C2. The transistor M2 has a current of Isignal × (1 + sC2R2) + Isignal × sC2R13 (1 + sC13R2) obtained by subtracting a current flowing through the capacitor C13 via the current buffer IB13 from the sum of the current flowing through the capacitor C2 and the current flowing through the resistor R13. Current flows. Here, if C13 = C2, the current flowing through the transistor M2 is Isignal × (1 + sC13R2) (1 + sC2R13).

  In the present embodiment, since the gate terminal voltage and the source terminal voltage of the transistors M2 and M3 are equal, a current that is twice the device size ratio of the current flowing through the transistor M2 flows through the transistor M3. Therefore, when the sizes of the transistors M2 and M3 are the same, a current of Isignal × (1 + sC13R2) (1 + sC2R13) is output as the output current Iout from the drain terminal of the transistor M3.

  As described above, the waveform shaping filter according to the present embodiment includes a current obtained by superimposing the differential component of the signal current Isignal on a current proportional to the input signal current Isignal, a current proportional to the differential component of the superimposed current, Output the sum of. With such a configuration, it is possible to realize a filter characteristic that emphasizes a high-frequency component, which is suitable when the signal current Isignal has a frequency characteristic that has passed through the first-order low-pass filter twice.

  In the present embodiment, the load of the amplifier A2 is only the gates of the transistors M2 and M3. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current driving capability of the amplifier A2, and the power consumption of the waveform shaping filter can be reduced.

(Fifteenth embodiment)
A waveform shaping filter according to the fifteenth embodiment will be described with reference to FIG. FIG. 34 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 34, the waveform shaping filter according to this embodiment includes a resistor R11 (a twelfth resistor), a capacitor C11 (a thirteenth capacitor), and a voltage buffer VB11. Other configurations are the same as those in FIG. The configurations of the resistor R11, the capacitor C11, and the voltage buffer VB11 are the same as those in FIG.

  As can be seen from FIG. 34, the waveform shaping filter according to the present embodiment is a modification of the eleventh embodiment. In the eleventh embodiment, the feedback circuit including the resistor R11, the capacitor C11, and the voltage buffer VB11 is connected between the transistor M1 and the resistor R1, whereas in the present embodiment, the resistor R1 and the current source are connected. It is connected to Isignal.

  With this configuration, when the signal current Isignal is input from the current source Isignal, the signal current Isignal flows through the resistor R11. Since the other end of the resistor R11 is connected to the input terminal of the amplifier A1, which is a virtual ground point, the voltage at the other end of the resistor R11 is substantially constant. On the other hand, the voltage at one end of the resistor R11 is Isignal × R11. One end of the capacitor C11 is also connected to the input terminal of the amplifier A1, which is a virtual ground point, and the voltage Isignal × R11 at one end of the resistor R11 is applied to the other end of the capacitor C11 via the voltage buffer VB11. .

  Therefore, a current of Isignal × R11 × sC11 flows through the capacitor C11. A current of Isignal × (1 + sC11R11) that is the sum of the current flowing through the resistor R11 and the current flowing through the capacitor C11 flows through the resistor R1. Therefore, the source terminal voltage of the transistor M1 is Isignal × R1 × (1 + sC11R11), and is applied to one end of the capacitor C1. Since the other end of the capacitor C1 is grounded, a voltage of Isignal × R1 × (1 + sC11R11) is applied to the capacitor C1. Therefore, the current flowing through the capacitor C1 is Isignal × sC1R1 × (1 + sC11R11). As a result, a current of Isignal × (1 + sC11R11) (1 + sC1R1), which is the sum of the current flowing through the resistor R1 and the current flowing through the capacitor C1, flows through the transistor M1, and this current is output as an output current Iout from the drain terminal. Is done.

  As described above, the waveform shaping filter according to the present embodiment includes a current obtained by superimposing the differential component of the signal current Isignal on a current proportional to the input signal current Isignal, a current proportional to the differential component of the superimposed current, Output the sum of. With such a configuration, it is possible to realize a filter characteristic that emphasizes a high-frequency component, which is suitable when the signal current Isignal has a frequency characteristic that has passed through the first-order low-pass filter twice.

  In the present embodiment, the load of the amplifier A1 is only the gate of the transistor M1. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current drive capability of the amplifier A1, and the power consumption of the waveform shaping filter can be reduced.

(Sixteenth embodiment)
A waveform shaping filter according to the sixteenth embodiment will be described with reference to FIG. FIG. 35 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 35, the waveform shaping filter according to this embodiment includes a resistor R11 (a twelfth resistor), a capacitor C11 (a thirteenth capacitor), and a voltage buffer VB11. Other configurations are the same as those in FIG. The configurations of the resistor R11, the capacitor C11, and the voltage buffer VB11 are the same as those in FIG.

  As can be seen from FIG. 35, the waveform shaping filter according to the present embodiment is a modification of the twelfth embodiment. In the twelfth embodiment, the feedback circuit including the resistor R11, the capacitor C11, and the voltage buffer VB11 is connected between the transistor M2 and the resistor R2. In the present embodiment, the resistor R2 and the current source are connected. It is connected to Isignal.

  With this configuration, when the signal current Isignal is input from the current source Isignal, the signal current Isignal flows through the resistor R11. Since the other end of the resistor R11 is connected to the input terminal of the amplifier A2, which is a virtual ground point, the voltage at the other end of the resistor R11 is substantially constant. On the other hand, the voltage at one end of the resistor R11 is Isignal × R11. One end of the capacitor C11 is also connected to the input terminal of the amplifier A2, which is a virtual ground point, and the voltage Isignal × R11 of one end of the resistor R11 is applied to the other end of the capacitor C11 via the voltage buffer VB11. Yes.

  Therefore, a current of Isignal × R11 × sC11 flows through the capacitor C11. In the resistor R2, Isignal × (1 + sC11R11) which is the sum of the current flowing in the resistor R11 and the current flowing in the capacitor C11 flows. Therefore, the drain terminal voltage of the transistor M2 is Isignal × R2 × (1 + sC11R11), and is applied to one end of the capacitor C2. Since the other end of the capacitor C2 is grounded, a voltage of Isignal × R2 × (1 + sC11R11) is applied to the capacitor C2. Therefore, the current flowing through the capacitor C2 is Isignal × sC2R2 × (1 + sC11R11). As a result, a current of Isignal × (1 + sC11R11) (1 + sC2R2) that is the sum of the current flowing through the resistor R2 and the current flowing through the capacitor C2 flows through the transistor M2.

  In the present embodiment, since the gate terminal voltage and the source terminal voltage of the transistors M2 and M3 are equal, a current that is twice the device size ratio of the current flowing through the transistor M2 flows through the transistor M3. Therefore, when the sizes of the transistors M2 and M3 are the same, a current of Isignal × (1 + sC11R11) (1 + sC2R2) is output as the output current Iout from the drain terminal of the transistor M3.

  As described above, the waveform shaping filter according to the present embodiment includes a current obtained by superimposing the differential component of the signal current Isignal on a current proportional to the input signal current Isignal, a current proportional to the differential component of the superimposed current, Output the sum of. With such a configuration, it is possible to realize a filter characteristic that emphasizes a high-frequency component, which is suitable when the signal current Isignal has a frequency characteristic that has passed through the first-order low-pass filter twice.

  In the present embodiment, the load of the amplifier A2 is only the gates of the transistors M2 and M3. The gate can be approximated as a small capacitive load. Therefore, it is not necessary to increase the current driving capability of the amplifier A2, and the power consumption of the waveform shaping filter can be reduced.

(17th Embodiment)
A waveform shaping filter according to the seventeenth embodiment will be described with reference to FIGS. FIG. 36 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 36, the waveform shaping filter according to this embodiment includes transistors Mcm1 and Mcm2, a current source Idcm, and a transistor MB11c. Other configurations are the same as those in FIG. The configuration of the current mirror circuit including the transistors Mcm1 and Mcm2 and the current source Idcm is the same as that in FIG.

  In the present embodiment, the capacitor C1 has one end connected to the drain terminal of the transistor Mcm2 that is the output terminal of the current mirror circuit, and the other end connected to the drain terminal of the transistor Mcm1 that is the input terminal of the current mirror circuit. Yes.

  With such a configuration, the current flowing through the resistor R11 is the sum of the current flowing through the resistor R1, the current flowing through the capacitor C1, and the current copied from the current flowing through the capacitor C1 by the current mirror circuit. For example, if the sizes of the transistors Mcm1 and Mcm2 are equal, the current flowing through the resistor R11 is Isignal × R1b × (1 + 2sC1R1) / R1. Therefore, compared with the ninth embodiment, the capacitance value C1 can be halved. That is, a time constant similar to that of the ninth embodiment can be realized with a capacitance value C1 that is half that of the ninth embodiment.

  In the above, the case where the sizes of the transistors Mcm1 and Mcm2 are equal has been described as an example. However, in the present embodiment, the sizes of the transistors Mcm1 and Mcm2 may be different. By setting the channel width of the transistor Mcm2 to k times the channel width of the transistor Mcm1, the capacitance value C1 can be 1 / (1 + k) times that of the ninth embodiment.

  In FIG. 36, the other end of the capacitor C1 is connected to the current mirror circuit, but a configuration in which the capacitor C1 is divided and only a part thereof is connected to the current mirror circuit is also possible.

  On the other hand, the transistor MB11c is an NMOS, the source terminal is grounded, the gate terminal is connected to the current source Ib11b, the drain terminal of the transistor MB11a, and the gate terminal of the transistor MB11b, and the drain terminal is connected to the transistor M1. The source terminal is connected to one end of the capacitor C11 and one end of the resistor R11.

  With such a configuration, the gate-source voltage of the transistor MB11c and the gate-source voltage of the transistor MB11b are equal. Here, for example, when the sizes of the transistors MB11b and MB11c are made equal, a current that replicates the current flowing through the transistor MB11b flows through the transistor MB11c, and this current is added to the current flowing into one end of the capacitor C11. As a result, a current twice as large as the current flowing into one end of the capacitor C11 flows through the transistor M1. Therefore, the capacitance value C11 can be halved compared to the ninth embodiment. That is, a time constant similar to that of the ninth embodiment can be realized with a capacitance value C11 that is half that of the ninth embodiment.

  In the above, the case where the sizes of the transistors MB11b and MB11c are equal has been described as an example. However, in the present embodiment, the sizes of the transistors MB11b and MB11c may be different. By setting the channel width of the transistor MB11c to k times the channel width of the transistor MB11b, the capacitance value C11 can be 1 / (1 + k) times that of the ninth embodiment.

  In the present embodiment, as shown in FIG. 37, a current source Idcm2 may be added to the current mirror circuit, or a current source Ib11d may be added to the voltage buffer 11VB. By adding the current source Idcm2, part or all of the bias current flowing through the transistor Mcm2 can be canceled so as not to flow through the resistor R11, and the DC voltage applied to the resistor R11 can be reduced. Further, by adding the current source Ib11d, part or all of the bias current flowing through the transistor MB11c can be canceled so as not to flow through the transistor M1, and the bias current flowing through the transistor M1 can be reduced.

(Eighteenth embodiment)
A waveform shaping filter according to the eighteenth embodiment will be described with reference to FIGS. 38 and 39. FIG. FIG. 38 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 38, the waveform shaping filter according to this embodiment includes transistors Mcm1 to Mcm7 and a current source Idcm. Other configurations are the same as those in FIG. A current mirror circuit including the transistors Mcm1 and Mcm2 and the current source Idcm is the same as that shown in FIG.

  In the present embodiment, the current buffer IB12 further includes transistors Mcm3 to Mcm7.

  The transistor Mcm3 is an NMOS, the source terminal is grounded, the gate terminal is connected to the gate terminals of the transistors Mcm4 and Mcm5, and the drain terminal is connected to the drain terminal of the transistor MB12a. The gate terminal and the drain terminal of the transistor Mcm3 are connected.

  The transistor Mcm4 is an NMOS, the source terminal is grounded, the gate terminal is connected to the gate terminals of the transistors Mcm3 and Mcm5, the drain terminal is the current source Ib12b, the negative input terminal of the amplifier A1, one end of the resistor R12, The capacitor C12 is connected to one end.

  The transistor Mcm5 is an NMOS, the source terminal is grounded, the gate terminal is connected to the gate terminals of the transistors Mcm3 and Mcm4, and the drain terminal is connected to the drain terminal of the transistor Mcm6.

  The transistor Mcm6 is a PMOS, the source terminal is connected to the power supply line, the gate terminal is connected to the gate terminal of the transistor Mcm7, and the drain terminal is connected to the drain terminal of the transistor Mcm5. In the transistor Mcm6, the gate terminal and the drain terminal are connected.

  The transistor Mcm7 is a PMOS, the source terminal is connected to the power supply line, the gate terminal is connected to the gate terminal of the transistor Mcm6, and the drain terminal is connected to the other end of the capacitor C1. The drain terminal of the transistor Mcm7 is the output terminal of the current buffer IB12.

  Transistors Mcm3 to Mcm7 form a current mirror circuit. The current source Ib12b supplies a bias current Ib12b for operating the current mirror.

  As described with reference to FIG. 29, the current flowing into the current buffer IB12 from the other end of the capacitor C12 is input to the source terminal of the transistor MB12a and output from the drain terminal of the transistor MB12a. The current output from the drain terminal of the transistor MB12a is input to the current mirror circuit from the drain terminal of the transistor Mcm3 and is duplicated by the transistors Mcm4 and Mcm5.

  Further, the current replicated by the transistor Mcm5 is folded (inverted polarity) by the transistors Mcm6 and Mcm7, and is output from the drain terminal of the transistor Mcm7. Here, as an example, if the sizes of the transistors Mcm3 to Mcm5 are equal and the size of the transistor Mcm7 is twice the size of the transistor Mcm6, a current having the same magnitude as the current flowing into the current buffer IB12 from the other end of the capacitor C12 is A current twice as large as the current flowing through the capacitor C12 flows through the resistor R12 drawn from the transistor Mcm4.

  On the other hand, a current twice as large as the current flowing into the current buffer IB12 from the other end of the capacitor C12 is supplied from the transistor Mcm7 to one end of the resistor R12 and supplied from the other end of the resistor R12 (2 of the current flowing through the capacitor C12). Times the current). As a result, the voltage at one end of the resistor R12 becomes Isignal × R1b × (1 + 2sC12R12). Therefore, the capacitance value C12 can be halved compared to the tenth embodiment. That is, a time constant similar to that of the tenth embodiment can be realized with a capacitance value C12 that is half that of the tenth embodiment.

  In the above description, the case where the sizes of the transistors Mcm3 to Mcm5 are equal and the size of the transistor Mcm7 is twice the size of the transistor Mcm6 has been described as an example. However, in the present embodiment, the size of each transistor is not limited thereto. . For example, the channel width of the transistor Mcm4 is k times the channel width of the transistor Mcm3, and the channel width of the transistor Mcm7 is (1 + k) times the channel width of the transistor Mcm6. 1 / (1 + k) times.

  In the present embodiment, the capacitor C1 has one end connected to the drain terminal of the transistor Mcm2 that is the output terminal of the current mirror circuit, and the other end connected to the drain terminal of the transistor Mcm1 that is the input terminal of the current mirror circuit. Yes. The current source Idcm supplies a bias current Idcm for operating the current mirror circuit.

  With such a configuration, if the sizes of the transistors Mcm1 and Mcm2 are equal, the transistor M1 has a signal Isignal × R1b × (1 + 2sC12R12) (1 + 2sC1R1) which is the sum of the current flowing through the resistor R1 and the current flowing through the capacitor C1. / R1 current flows and is output as an output current Iout from the drain terminal. Therefore, the capacitance value C1 can be halved compared to the tenth embodiment. That is, a time constant similar to that of the tenth embodiment can be realized with a capacitance value C1 that is half that of the tenth embodiment.

  In the above description, the case where the sizes of the transistors Mcm1 and Mcm2 are equal has been described as an example. However, in the present embodiment, the sizes of the transistors Mcm1 and Mcm2 may be different. For example, by setting the channel width of the transistor Mcm2 to be k times the channel width of the transistor Mcm1, the capacitance value C1 can be 1 / (1 + k) times that of the tenth embodiment.

  In FIG. 38, the other end of the capacitor C1 is connected to the current mirror circuit. However, a configuration in which the capacitor C1 is divided and only a part thereof is connected to the current mirror circuit is also possible.

  Furthermore, as shown in FIG. 39, a current source Idcm2 may be added to the current mirror circuit to increase the bias current flowing through the transistor M1.

(Nineteenth embodiment)
A waveform shaping filter according to the nineteenth embodiment will be described with reference to FIGS. FIG. 40 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 40, the waveform shaping filter according to this embodiment includes transistors Mcm1 and Mcm2 and a low input impedance circuit Z. Other configurations are the same as those in FIG. The configuration of the current buffer IB12 is the same as that in FIG. Further, the configuration of the current mirror circuit constituted by the transistors Mcm1 and Mcm2 and the low input impedance circuit Z is the same as that in FIG.

  With such a configuration, a current of Isignal × R1b × (1 + 2sC12R12) (1 + sC1R1) / R1 that is the sum of the current flowing through the resistor R1 and the current flowing through the capacitor C1 flows through the transistor M1. The low input impedance circuit Z has a signal Isignal × R1b × (the sum of a current copied from the transistor M1 by the current mirror circuit and a current Isignal × R1b × (1 + 2sC12R12) × sC1R1 / R1 flowing in the capacitor C1. The current of 1 + 2sC12R12) (1 + 2sC1R1) / R1 flows. Therefore, the capacitance values C1 and C12 can be halved compared to the tenth embodiment. That is, a time constant similar to that of the tenth embodiment can be realized with the capacitance values C1 and C12 that are half of those of the tenth embodiment.

  In FIG. 40, the current that is twice the current flowing through the capacitor C12 is canceled at the source terminal of the transistor M1, but it may be performed at the drain terminal of the transistor M1. This can be achieved by connecting the drain terminal of the transistor Mcm7, which is the output terminal of the current buffer IB21, to the source terminal of the transistor M1, as shown in FIG.

  Alternatively, the size of the transistor Mcm5 may be twice the size of the transistor Mcm3, and the current that is twice the current flowing through the capacitor C12 may be canceled at the input terminal of the low input impedance circuit Z. This is possible by removing the transistors Mcm6 and Mcm7 from the current buffer IB12 and connecting the drain terminal of the transistor Mcm6 as the output terminal of the current buffer IB12 to the input terminal of the low input impedance circuit Z as shown in FIG. is there.

  Furthermore, in the present embodiment, the current buffer IB12 may not include at least one of the current sources Ib12a and Ib12d, or may have a configuration similar to that in FIG.

(20th embodiment)
A waveform shaping filter according to the twentieth embodiment will be described with reference to FIG. FIG. 43 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 43, the waveform shaping filter according to the present embodiment includes transistors Mcm1 and Mcm2 and current sources Idcm1 and Idcm2. Other configurations are the same as those in FIG. In addition, the configuration of the current mirror circuit including the transistors Mcm1 and Mcm2 and the current sources Idcm1 and Idcm2 and the configuration of the voltage buffer VB11 are the same as those in FIG.

  In FIG. 43, one end of the capacitor C1 is connected to the drain terminal of the transistor Mcm2 that is the output terminal of the current mirror circuit, and the other end is connected to the drain terminal of the transistor Mcm1 that is the input terminal of the current mirror circuit. The current source Idcm1 supplies a bias current Idcm1 for operating the current mirror circuit. The current source Idcm2 cancels part or all of the bias current flowing through the transistor Mcm2, reduces the bias current flowing through the resistor R11, and reduces the DC voltage applied to the resistor R11.

  With this configuration, if the sizes of the transistors Mcm1 and Mcm2 are equal, the current flowing through the resistor R11 is a current mirror circuit that replicates the current flowing through the resistor R1, the current flowing through the capacitor C1, and the current flowing through the capacitor C1. It is the sum of the current. For example, if the sizes of the transistors Mcm1 and Mcm2 are equal, the current flowing through the resistor R11 is Isignal × (1 + 2sC1R1). Therefore, the capacitance value C1 can be halved compared to the eleventh embodiment. That is, a time constant similar to that of the eleventh embodiment can be realized with a capacitance value C1 that is half that of the eleventh embodiment.

  In the above, the case where the sizes of the transistors Mcm1 and Mcm2 are equal has been described as an example. However, in the present embodiment, the sizes of the transistors Mcm1 and Mcm2 may be different. For example, by setting the channel width of the transistor Mcm2 to be k times the channel width of the transistor Mcm1, the capacitance value C1 can be 1 / (1 + k) times that of the eleventh embodiment.

  In FIG. 43, the other end of the capacitor C1 is connected to the current mirror circuit, but a configuration in which the capacitor C1 is divided and only a part thereof is connected to the current mirror circuit is also possible.

  In FIG. 43, the gate terminal of the transistor MB11c is connected to the gate terminal of the transistor MB11b, and the source terminals of the transistors MB11b and MB11c are grounded. Therefore, the gate-source voltage of the transistor MB11c is equal to the gate-source voltage of the transistor MB11b.

  Here, for example, when the size of the transistor MB11c is made equal to the size of the transistor MB11b, a current that duplicates the current flowing through the transistor MB11b flows through the transistor MB11c, and this current is added to the current flowing into one end of the capacitor C11. As a result, a current twice as large as the current flowing into one end of the capacitor C11 flows through the transistor M1. Therefore, the capacitance value C11 can be halved compared to the eleventh embodiment. That is, a time constant similar to that of the eleventh embodiment can be realized with a capacitance value C11 that is half that of the eleventh embodiment.

  In the above, the case where the sizes of the transistors MB11b and MB11c are equal has been described as an example. However, in the present embodiment, the sizes of the transistors MB11b and MB11c may be different. For example, by setting the channel width of the transistor MB11c to k times the channel width of the transistor MB11c, the capacitance value C11 can be 1 / (1 + k) times that of the eleventh embodiment.

  In the present embodiment, all or part of the bias current flowing through the transistor MB11c is supplied by the current source Ib11d. Thereby, the design freedom of the bias current flowing through the transistor M1 can be improved.

(21st Embodiment)
A waveform shaping filter according to the twenty-first embodiment will be described with reference to FIG. FIG. 44 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 44, the waveform shaping filter according to this embodiment includes transistors Mcm1 and Mcm2 and current sources Idcm1 and Idcm2. Other configurations are the same as those in FIG. In addition, the configuration of the current mirror circuit including the transistors Mcm1 and Mcm2 and the current sources Idcm1 and Idcm2 and the configuration of the voltage buffer VB11 are the same as those in FIG.

  In FIG. 44, one end of the capacitor C2 is connected to the drain terminal of the transistor Mcm2 that is the output terminal of the current mirror circuit, and the other end is connected to the drain terminal of the transistor Mcm1 that is the input terminal of the current mirror circuit. The current source Idcm1 supplies a bias current Idcm1 for operating the current mirror circuit. The current source Idcm2 cancels part or all of the bias current flowing through the transistor Mcm2, reduces the bias current flowing through the resistor R11, and reduces the DC voltage applied to the resistor R11.

  With such a configuration, the current flowing through the resistor R11 is the sum of the current flowing through the resistor R2, the current flowing through the capacitor C2, and the current obtained by duplicating the current flowing through the capacitor C2 by the current mirror circuit. For example, if the sizes of the transistors Mcm1 and Mcm2 are equal, the current flowing through the resistor R11 is Isignal × (1 + 2sC2R2). Therefore, the capacitance value C2 can be halved compared to the twelfth embodiment. That is, a time constant similar to that of the twelfth embodiment can be realized with a capacitance value C2 that is half that of the twelfth embodiment.

  In the above, the case where the sizes of the transistors Mcm1 and Mcm2 are equal has been described as an example. However, in the present embodiment, the sizes of the transistors Mcm1 and Mcm2 may be different. For example, by setting the channel width of the transistor Mcm2 to be k times the channel width of the transistor Mcm1, the capacitance value C2 can be 1 / (1 + k) times that of the twelfth embodiment.

  In FIG. 44, the other end of the capacitor C2 is connected to the current mirror circuit. However, a configuration in which the capacitor C2 is divided and only a part thereof is connected to the current mirror circuit is also possible.

  In FIG. 44, the gate terminal of the transistor MB11c is connected to the gate terminal of the transistor MB11b, and the source terminals of the transistors MB11b and MB11c are grounded. Therefore, the gate-source voltage of the transistor MB11c is equal to the gate-source voltage of the transistor MB11b. Here, for example, when the size of the transistor MB11c is made equal to the size of the transistor MB11b, a current that duplicates the current flowing through the transistor MB11b flows through the transistor MB11c, and this current is added to the current flowing into one end of the capacitor C11. As a result, a current twice as large as the current flowing into one end of the capacitor C11 flows through the transistor M2. Therefore, the capacitance value C11 can be halved compared to the twelfth embodiment. That is, a time constant similar to that of the twelfth embodiment can be realized with a capacitance value C11 that is half that of the twelfth embodiment.

  In the above, the case where the sizes of the transistors MB11b and MB11c are equal has been described as an example. However, in the present embodiment, the sizes of the transistors MB11b and MB11c may be different. For example, by setting the channel width of the transistor MB11c to k times the channel width of the transistor MB11b, the capacitance value C11 can be 1 / (1 + k) times that of the twelfth embodiment.

(Twenty-second embodiment)
A waveform shaping filter according to the twenty-second embodiment will be described with reference to FIG. FIG. 45 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 45, the waveform shaping filter according to this embodiment includes transistors Mcm1 and Mcm2 and a current source Idcm. Other configurations are the same as those in FIG. The configuration of the current mirror circuit including the transistors Mcm1 and Mcm2 and the current source Idcm is the same as that in FIG.

  Further, the current buffer IB13 includes transistors Mcm3 to Mcm7, current sources Ib13a to Ib13d, and transistors MB13a and MB13b. The current buffer IB13 has the same configuration as the current buffer IB12 of FIG. 39, and the current sources Ib13a to Ib13d and the transistors MB13a and MB13b of the current buffer IB13 are respectively connected to the current sources Ib12a to Ib12d and the transistors MB12a and MB12b of the current buffer IB12. Correspond.

  In FIG. 45, the gate terminal and the drain terminal of the transistor Mcm3 are connected to the gate terminals of the transistors Mcm4 and Mcm5. The drain terminal of the transistor Mcm5 is connected to the gate terminal and drain terminal of the transistor Mcm6 and the gate terminal of the transistor Mcm7. The current source Ib13a supplies a bias current to the transistor Mcm4.

  As described with reference to FIG. 29, the current flowing from the other end of the capacitor C13 into the current buffer IB13 is input to the source terminal of the transistor MB13a and output from the drain terminal. The current output from the drain terminal of the transistor MB13a is input to the current mirror circuit from the drain terminal of the transistor Mcm3, which is the input terminal of the current mirror circuit, and is replicated by the transistors Mcm4 and Mcm5.

  Further, the current replicated in the transistor Mcm5 is folded (inverted in polarity) by a current mirror circuit composed of the transistors Mcm6 and Mcm7, and is output from the drain terminal of the transistor Mcm7.

  Here, as an example, if the sizes of the transistors Mcm3 to Mcm5 are equal and the size of the transistor Mcm7 is twice the size of the transistor Mcm6, a current having the same magnitude as the current flowing into the current buffer IB13 from the other end of the capacitor C13 is A current twice as large as the current flowing through the capacitor C13 flows through the resistor R13 drawn from the transistor Mcm4.

  That is, a current of Isignal × (1 + 2sC13R1) flows through the resistor R13. Therefore, the source terminal voltage of the transistor M1 is Isignal × R1 + Isignal × R13 × (1 + 2sC13R1). A current of Isignal × sC1R1 + Isignal × sC1R13 × (1 + 2sC13R1) flows through the capacitor C1.

  On the other hand, a current twice as large as the current flowing into the current buffer IB13 from the other end of the capacitor C13 is supplied from the transistor Mcm7 to the other end of the resistor R13 and supplied from one end of the resistor R13 (2 of the current flowing through the capacitor C13). Double current) Isignal × 2sC13R1 is canceled out.

  The capacitor C1 has one end connected to the drain terminal of the transistor Mcm2 that is the output terminal of the current mirror terminal, and the other end connected to the drain terminal of the transistor Mcm1 that is the input terminal of the current mirror circuit. The current source Idcm supplies a bias current Idcm for operating the current mirror circuit.

  With such a configuration, if the sizes of the transistors Mcm1 and Mcm2 are equal, the transistor M1 has a current flowing through the capacitor C13 from the sum of the current flowing through the resistor R13 and the current flowing twice through the capacitor C1. The current of Isignal × (1 + 2sC13R1) (1 + 2sC1R13) + Isignal × 2sR1 (C1−C13) flows, and is output as an output current Iout from the drain terminal.

  Here, by setting C13 = C1, Iout = Isignal × (1 + 2sC13R1) (1 + 2sC1R13). Therefore, in this embodiment, by setting C13 = C1, the capacitance values C1 and C13 can be halved compared to the thirteenth embodiment. In other words, a time constant similar to that of the thirteenth embodiment can be realized with half the capacitance values C1 and C13 of the thirteenth embodiment.

(23rd Embodiment)
A waveform shaping filter according to the twenty-third embodiment will be described with reference to FIG. FIG. 46 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 46, the waveform shaping filter according to this embodiment includes transistors Mcm1 and Mcm2 and a low input impedance circuit Z. Other configurations are the same as those in FIG. The configurations of the transistors Mcm1 and Mcm2 and the low input impedance circuit Z are the same as those in FIG. Further, the configuration of the current buffer IB13 is the same as that of FIG.

  As shown in FIG. 46, the waveform shaping filter according to the present embodiment uses the output terminal of the waveform shaping filter of FIG. 32 (the drain terminal of the transistor M1) as the input terminal of the current mirror circuit composed of the transistors Mcm1 and Mcm2 ( The output terminal of the current mirror circuit (the drain terminal of the transistor Mcm2) is connected to the low input impedance circuit. The other end of the capacitor C1 is connected to the output terminal of the current mirror circuit (the drain terminal of the transistor Mcm2) and the low input impedance circuit Z.

  As described above, Isignal × 2sC13R1, which is twice the current flowing through the capacitor C13, is canceled by the other end of the resistor R13, so that the transistor M1 has Isignal × (1 + 2sC13R1) (1 + sC1R13) + Isignal × 2sR1 ( C1-C13) current flows. In the low input impedance circuit Z, Isignal × (1 + 2sC13R1) (1 + 2sC1R13) + Isignal is a sum of a current obtained by replicating the current flowing in the transistor M1 by the current mirror circuit and a current Isignal × (1 + 2sC13R1) × sC1R13 flowing in the capacitor C1. A current of x2sR1 (C1-C13) flows.

  Here, if C13 = C1, the current input to the low input impedance is Isignal × (1 + 2sC13R1) (1 + 2sC1R13). Therefore, in this embodiment, by setting C13 = C1, the capacitance values C1 and C13 can be halved compared to the thirteenth embodiment. In other words, a time constant similar to that of the thirteenth embodiment can be realized with half the capacitance values C1 and C13 of the thirteenth embodiment.

(24th Embodiment)
A waveform shaping filter according to the twenty-fourth embodiment will be described with reference to FIG. FIG. 47 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 47, the waveform shaping filter according to this embodiment includes transistors Mcm1 and Mcm2 and a current source Idcm. Other configurations are the same as those in FIG. The configuration of the current mirror circuit including the transistors Mcm1 and Mcm2 and the current source Idcm is the same as that in FIG. Further, the configuration of the current buffer IB13 is the same as that of FIG.

  In FIG. 47, the gate terminal and the drain terminal of the transistor Mcm3 are connected to the gate terminals of the transistors Mcm4 and Mcm5. The drain terminal of the transistor Mcm5 is connected to the gate terminal and drain terminal of the transistor Mcm6 and the gate terminal of the transistor Mcm7. The current source Ib13a supplies a bias current to the transistor Mcm4.

  As described with reference to FIG. 29, the current flowing from the other end of the capacitor C13 into the current buffer IB13 is input to the source terminal of the transistor MB13a and output from the drain terminal. The current output from the drain terminal of the transistor MB13a is connected to the input terminal of the current mirror circuit (the drain terminal of the transistor Mcm3) and is replicated by the transistors Mcm4 and Mcm5. The current replicated in the transistor Mcm5 is folded (inverted in polarity) by a current mirror circuit composed of the transistors Mcm6 and Mcm7, and is output from the drain terminal of the transistor Mcm7.

  Here, as an example, if the sizes of the transistors Mcm3 to Mcm5 are equal and the size of the transistor Mcm7 is twice the size of the transistor Mcm6, a current having the same magnitude as the current flowing into the current buffer IB13 from the other end of the capacitor C13 is A current twice as large as the current flowing through the capacitor C13 flows through the resistor R13 drawn from the transistor Mcm4. That is, a current of Isignal × (1 + 2sC13R2) flows through the resistor R13. Therefore, the source terminal voltage of the transistor M2 is Isignal × R2 + Isignal × R13 × (1 + 2sC13R2). A current of Isignal × sC2R2 + Isignal × sC2R13 × (1 + 2sC13R2) flows through the capacitor C2.

  On the other hand, a current twice as large as the current flowing into the current buffer IB13 from the other end of the capacitor C13 is supplied from the transistor Mcm7 to the other end of the resistor R13 and supplied from one end of the resistor R13 (2 of the current flowing through the capacitor C13). Double current) Isignal × 2sC13R2. The capacitor C2 has one end connected to the output terminal of the current mirror terminal (the drain terminal of the transistor Mcm2) and the other end connected to the input terminal of the current mirror circuit (the drain terminal of the transistor Mcm1). The current source Idcm supplies a bias current Idcm for operating the current mirror circuit.

  With such a configuration, assuming that the sizes of the transistors Mcm1 and Mcm2 are equal, the transistor M2 has a current flowing through the capacitor C13 based on the sum of the current flowing through the resistor R13 and the current flowing twice through the capacitor C2. Current of Isignal × (1 + 2sC13R2) (1 + 2sC2R13) + Isignal × 2sR2 (C2−C13), which is a current that is twice the current, flows and is output as an output current Iout from the drain terminal.

  Here, when C13 = C2, Iout = Isignal × (1 + 2sC13R2) (1 + 2sC2R13). Therefore, in this embodiment, by setting C13 = C2, the capacitance values C2 and C13 can be halved compared to the fourteenth embodiment. That is, a time constant similar to that of the fourteenth embodiment can be realized with half the capacitance values C2 and C13 of the fourteenth embodiment.

(25th Embodiment)
A waveform shaping filter according to the twenty-fifth embodiment will be described with reference to FIG. FIG. 48 is a diagram illustrating a waveform shaping filter according to the present embodiment. As shown in FIG. 48, the waveform shaping filter according to this embodiment includes a low input impedance circuit Z. Other configurations are the same as those in FIG. The configuration of the current buffer IB13 is the same as that in FIG.

  As shown in FIG. 48, the waveform shaping filter according to this embodiment connects the drain terminal of the transistor M3, which is the output terminal of the waveform shaping filter of FIG. 33, to the input terminal of the low input impedance circuit. The other end of the capacitor C2 is connected to the low input impedance circuit.

  In the present embodiment, as described above, Isignal × 2sC13R2, which is twice the current flowing through the capacitor C13, is canceled out by the other end of the resistor R13, so that the transistor M2 has Isignal × (1 + 2sC13R2) (1 + sC2R13 ) + Isignal × 2sR2 (C2-C13) flows. The low input impedance circuit Z has a sum of Isignal × (1 + 2sC13R2) (1 + 2sC2R13) + Isignal × 2sR2 (C2−C13) which is the sum of the current flowing through the transistor M3 and the current Isignal × (1 + 2sC13R2) × sC2R13 flowing through the capacitor C2. Current flows.

  Here, if C13 = C2, the current input to the low input impedance circuit Z is Isignal × (1 + 2sC13R2) (1 + 2sC2R13). Therefore, in this embodiment, by setting C13 = C2, the capacitance values C2 and C13 can be halved compared to the fourteenth embodiment. That is, a time constant similar to that of the fourteenth embodiment can be realized with half the capacitance values C2 and C13 of the fourteenth embodiment.

(26th Embodiment)
A waveform shaping filter according to the twenty-sixth embodiment will be described with reference to FIG. FIG. 49 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 49, the waveform shaping filter according to this embodiment includes transistors Mcm1 and Mcm2 and current sources Idcm1 and Idcm2. Other configurations are the same as those in FIG. The configuration of the current mirror circuit and voltage buffer VB11 configured by the transistors Mcm1, Mcm2 and current sources Idcm1, Idcm2 is the same as that of FIG.

  In FIG. 49, the gate terminal of the transistor MB11c is connected to the gate terminal of the transistor MB11b, and the source terminals of the transistors MB11b and MB11c are grounded. Therefore, the gate-source voltage of the transistor MB11c is equal to the gate-source voltage of the transistor MB11b.

  Here, for example, when the size of the transistor MB11c is made equal to the size of the transistor MB11b, a current that replicates the current flowing through the transistor MB11b flows through the transistor MB11c, and this current is added to the current flowing into one end of the capacitor C11. . As a result, a current twice as large as the current flowing into one end of the capacitor C11 flows through the resistor R1. Therefore, a current of Isignal × (1 + 2sC11R11) flows through the resistor R1.

  On the other hand, in FIG. 49, one end of the capacitor C1 is connected to the output terminal of the current mirror circuit (the drain terminal of the transistor Mcm2), and the other end is connected to the input terminal of the current mirror circuit (the drain terminal of the transistor Mcm1). . The current source Idcm1 supplies a bias current Idcm1 for operating the current mirror circuit. The current source Idcm2 cancels part or all of the bias current flowing through the transistor Mcm2, and adjusts the bias current flowing through the transistor M1.

  With such a configuration, the current flowing through the transistor M1 is the sum of the current flowing through the resistor R1, the current flowing through the capacitor C1, and the current copied from the current flowing through the capacitor C1 by the current mirror circuit. For example, if the sizes of the transistors Mcm1 and Mcm2 are equal, the current flowing through the transistor M1 is Isignal × (1 + 2sC11R11) (1 + 2sC1R1), and is output as an output current Iout from the drain terminal. Therefore, the capacitance values C1 and C11 can be halved compared to the fifteenth embodiment. That is, a time constant similar to that of the fifteenth embodiment can be realized with the capacitance values C1 and C11 that are half of those of the fifteenth embodiment.

  In the above description, the case where the sizes of the transistors MB11b and MB11c are equal and the sizes of the transistors Mcm1 and Mcm2 are equal has been described as an example. However, in the present embodiment, the sizes of the transistors may be different. For example, by setting the channel width of the transistor MB11c to k times the channel width of the transistor MB11b, the capacitance value C11 can be 1 / (1 + k) times that of the fifteenth embodiment. By setting the channel width of the transistor Mcm2 to m times the channel width of the transistor Mcm1, the capacitance value C1 can be 1 / (1 + m) times that of the fifteenth embodiment.

  In FIG. 49, the other end of the capacitor C1 is connected to the current mirror circuit. However, a configuration in which the capacitor C1 is divided and only a part thereof is connected to the current mirror circuit is also possible. Further, a configuration in which the voltage buffer VB11 does not include the current source Ib11d is possible.

(27th Embodiment)
A waveform shaping filter according to the twenty-seventh embodiment will be described with reference to FIG. FIG. 50 is a diagram illustrating the waveform shaping filter according to the present embodiment. As shown in FIG. 50, the waveform shaping filter according to this embodiment includes transistors Mcm1 and Mcm2 and a low input impedance circuit Z. Other configurations are the same as those in FIG. Further, the configuration of the current mirror circuit constituted by the transistors Mcm1 and Mcm2 and the low input impedance circuit Z are the same as those in FIG. Further, the configuration of the voltage buffer VB11 is the same as that of FIG.

  As shown in FIG. 50, the drain terminal of the transistor M1 is connected to the input terminal of the current mirror circuit composed of the transistors Mcm1 and Mcm2 (the drain terminal of the transistor Mcm1). The output terminal of the current mirror circuit (the drain terminal of the transistor Mcm2) is connected to the low input impedance circuit Z. The other end of the capacitor C1 is connected to the output terminal of the current mirror circuit (the drain terminal of the transistor Mcm2) and the low input impedance circuit Z.

  As described with reference to FIG. 49, when the size of the transistor MB11c is equal to the size of the transistor MB11b, a current of Isignal × (1 + 2sC11R11) flows through the resistor R1. Therefore, the source terminal voltage of the transistor M1 is Isignal × R1 × (1 + 2sC11R11), and this voltage is applied to one end of the capacitor C1.

  The current flowing from one end of the capacitor C1 into the transistor M1 is Isignal × sC1R1 × (1 + 2sC11R11). Therefore, a current of Isignal × (1 + 2sC11R11) (1 + sC1R1) that is the sum of the current flowing through the resistor R1 and the current flowing through the capacitor C1 flows through the transistor M1, and is output from the drain terminal. This current is replicated by a current mirror circuit composed of transistors Mcm1 and Mcm2. Then, a current of Isignal × (1 + 2sC11R11) (1 + 2sC1R1), which is the sum of the copied current and the current Isignal × sC1R1 × (1 + 2sC11R11) flowing out from the other end of the capacitor C1, flows to the low input impedance circuit Z. Become.

  Therefore, the capacitance values C1 and C11 can be halved compared to the fifteenth embodiment. That is, a time constant similar to that of the fifteenth embodiment can be realized with the capacitance values C1 and C11 that are half of those of the fifteenth embodiment.

  In the above description, the case where the sizes of the transistors MB11b and MB11c are equal and the sizes of the transistors Mcm1 and Mcm2 are equal has been described as an example. However, in the present embodiment, the sizes of the transistors may be different. For example, by setting the channel width of the transistor MB11c to k times the channel width of the transistor MB11b, the capacitance value C11 can be 1 / (1 + k) times that of the fifteenth embodiment. By setting the channel width of the transistor Mcm2 to m times the channel width of the transistor Mcm1, the capacitance value C1 can be 1 / (1 + m) times that of the fifteenth embodiment.

  In FIG. 50, the other end of the capacitor C1 is connected to the current mirror circuit. However, a configuration in which the capacitor C1 is divided and only a part thereof is connected to the current mirror circuit is also possible. Furthermore, a configuration in which the voltage buffer VB11 does not include the current source Ib73 is also possible.

(Twenty-eighth embodiment)
A waveform shaping filter according to the twenty-eighth embodiment will be described with reference to FIG. FIG. 51 is a diagram showing a waveform shaping filter according to the present embodiment. As shown in FIG. 51, the waveform shaping filter according to this embodiment includes transistors Mcm1 and Mcm2 and current sources Idcm1 and Idcm2. Other configurations are the same as those in FIG. The configuration of the current mirror circuit and voltage buffer VB11 configured by the transistors Mcm1, Mcm2 and current sources Idcm1, Idcm2 is the same as that of FIG.

  In FIG. 51, the gate terminal of the transistor MB11c is connected to the gate terminal of the transistor MB11b. The source terminals of the transistors MB11b and MB11c are grounded. Therefore, the gate-source voltage of the transistor MB11c is equal to the gate-source voltage of the transistor MB11b.

  For example, when the size of the transistor MB11c is made equal to that of the transistor MB11b, a current that duplicates the current flowing through the transistor MB11b flows through the transistor MB11c, and this current is added to the current flowing into one end of the capacitor C11. As a result, a current twice as large as that flowing into one end of the capacitor C11 flows through the resistor R2. Therefore, a current of Isignal × (1 + 2sC11R11) flows through the resistor R2.

  On the other hand, in FIG. 51, the capacitor C2 has one end connected to the output terminal of the current mirror circuit (the drain terminal of the transistor Mcm2) and the other end connected to the input terminal of the current mirror circuit (the drain terminal of the transistor Mcm1). . The current source Idcm1 supplies a bias current Idcm1 for operating the current mirror circuit. The current source Idcm2 cancels part or all of the bias current flowing through the transistor Mcm2, and adjusts the bias current flowing through the transistor M2.

  With such a configuration, the current flowing through the transistor M2 is the sum of the current flowing through the resistor R2, the current flowing through the capacitor C2, and the current obtained by duplicating the current flowing through the capacitor C2 by the current mirror circuit. For example, if the sizes of the transistors Mcm1 and Mcm2 are equal, the current flowing through the transistor M2 is Isignal × (1 + 2sC11R11) (1 + 2sC2R2). The current flowing through the transistor M2 is duplicated by the transistor M3 and output as the output current Iout from the drain terminal.

  Therefore, the capacitance values C2 and C11 can be halved compared to the sixteenth embodiment. In other words, a time constant similar to that of the sixteenth embodiment can be realized with half the capacitance values C2 and C11 of the sixteenth embodiment.

  In the above description, the case where the sizes of the transistors MB11b and MB11c are equal and the sizes of the transistors Mcm1 and Mcm2 are equal has been described as an example. However, in the present embodiment, the sizes of the transistors may be different. For example, by setting the channel width of the transistor MB11c to k times the channel width of the transistor MB11b, the capacitance value C11 can be 1 / (1 + k) times that of the sixteenth embodiment. By setting the channel width of the transistor Mcm2 to m times the channel width of the transistor Mcm1, the capacitance value C1 can be 1 / (1 + m) times that of the sixteenth embodiment.

  In FIG. 51, the other end of the capacitor C2 is connected to the current mirror circuit. However, a configuration in which the capacitor C2 is divided and only a part thereof is connected to the current mirror circuit is also possible. Further, a configuration in which the voltage buffer VB11 does not include the current source Ib11d is possible.

(Twenty-ninth embodiment)
A waveform shaping filter according to the twenty-ninth embodiment will be described with reference to FIG. FIG. 52 is a diagram showing a waveform shaping filter according to this embodiment. As shown in FIG. 52, the waveform shaping filter according to this embodiment includes a low input impedance circuit Z. Other configurations are the same as those in FIG. The configuration of the voltage buffer VB11 is the same as that in FIG.

  As shown in FIG. 52, the waveform shaping filter according to this embodiment connects the output terminal of the waveform shaping filter (the drain terminal of the transistor M3) to the low input impedance circuit Z. The other end of the capacitor C2 is connected to the input terminal of the low input impedance circuit Z.

  As described with reference to FIG. 51, a current of Isignal × (1 + 2sC11R11) flows through the resistor R2. A current of Isignal × sC2R2 × (1 + 2sC11R11) flows through the capacitor C2. Therefore, a current of Isignal × (1 + sC11R11) (1 + 2sC2R2) flows through the transistor M2. If the sizes of the transistors M2 and M3 are equal, a current equal to the current flowing through the transistor M2 flows through the transistor M3. As a result, the low input impedance circuit Z has a current Isignal × (1 + sC11R11) (1 + 2sC2R2) flowing through the transistor M3 and a current Isignal × sC2R2 × (1 + 2sC11R11) flowing out from the other end of the capacitor C2, Isignal × (1 + 2sC11R11). 1 + 2sC11R11) (1 + 2sC2R2) flows.

  Therefore, the capacitance values C2 and C11 can be halved compared to the sixteenth embodiment. In other words, a time constant similar to that of the sixteenth embodiment can be realized with half the capacitance values C2 and C11 of the sixteenth embodiment.

(Thirty Embodiment)
Next, a waveform shaping filter according to the thirtieth embodiment will be described with reference to FIG. FIG. 53 is a diagram showing a waveform shaping filter according to the present embodiment. As shown in FIG. 53, the waveform shaping filter according to this embodiment includes an input terminal In, a voltage-current converter Gm, and a low-pass filter LPF.

  The waveform shaping filter receives the signal current Isignal from the input terminal In. A current source Isignal in FIG. 53 is a current source that inputs the signal current Isignal to the waveform shaping filter. The output of the waveform shaping filter is the input terminal voltage V1.

  The voltage-current converter Gm includes a negative input terminal and an output terminal. The negative input terminal is connected to one end of the low-pass filter LPF, and the output terminal is connected to the input terminal In and the other end of the low-pass filter LPF. The voltage-current converter Gm converts the voltage input from the negative input terminal into a current and outputs the current from the output terminal. As shown in FIG. 53, the voltage-current converter Gm can be configured by a transistor M4.

  The transistor M4 (third transistor) is a PMOS having a source terminal, a gate terminal, and a drain terminal. The source terminal (first terminal) of the transistor M4 is connected to the power supply, the drain terminal (second terminal) is connected to the input terminal In and one end of the low-pass filter LPF, and the gate terminal (control terminal) is , And connected to the other end of the low-pass filter LPF. The drain terminal of the transistor M4 becomes an output terminal of the voltage-current converter Gm, and the gate terminal becomes a negative input terminal.

  Thus, the waveform shaping filter can be miniaturized by configuring the voltage-current converter Gm with the transistor M4.

  The low-pass filter LPF is connected between the input terminal In and the negative input terminal of the voltage-current converter Gm. That is, the low-pass filter LPF has one end connected to the input terminal In and the other end connected to the negative input terminal of the voltage-current converter Gm. The low-pass filter LPF applies a low-frequency component of the input terminal voltage V1 to the negative input terminal of the voltage-current converter Gm. As shown in FIG. 53, the low-pass filter LPF can be configured by a resistor R3 and a capacitor C3.

  The resistor R3 (third resistor) has one end and the other end. One end of the resistor R3 is connected to the input terminal In, and the other end is connected to the negative input terminal of the voltage-current converter Gm and one end of the capacitor C3. One end of the resistor R3 is one end of the low-pass filter LPF, and the other end is the other end of the low-pass filter LPF.

  The capacitor C3 (second capacitor) has one end and the other end. One end of the capacitor C3 is connected to the other end of the resistor R3 and the negative input terminal of the voltage-current converter Gm, and the other end is grounded. One end of the capacitor C3 is the other end of the low-pass filter LPF.

  In this way, by configuring the low-pass filter LPF with the resistor R3 and the capacitor C3 that are passive elements, the power consumption of the waveform shaping filter can be reduced.

Next, the operation of the waveform shaping filter according to this embodiment will be described. In the following, the current value of the signal current Isignal is Isignal (s), the voltage value of the input terminal voltage V1 is V1 (s), the transfer function of the low-pass filter LPF is H _LPF (s), and the voltage of the voltage-current converter Gm Let the current conversion coefficient be Gm. Further, H _LPF (s) = 1 / (1 + sτ). Here, τ is a time constant of the low-pass filter LPF. As shown in FIG. 53, when the low-pass filter LPF is configured by the resistor R3 and the capacitor C3, τ = C3 × R3.

When the signal current Isignal is input to the waveform shaping filter, the input terminal voltage V1 is V1 (s) = Isignal (s) / {Gm × H _LPF (s)} = Isignal (s) × (1 + sτ) / Gm. . That is, the input terminal voltage V1 is a voltage obtained by superimposing a voltage corresponding to the high frequency component of the signal current Isignal on a voltage corresponding to the signal current Isignal. Thereby, the filter characteristic which emphasized the high frequency component of signal current Isignal is realizable.

  Moreover, since the waveform shaping filter according to the present embodiment consumes only the signal current Isignal, the power consumption can be reduced.

(Thirty-first embodiment)
Next, a waveform shaping filter according to the thirty-first embodiment will be described with reference to FIGS. FIG. 54 is a diagram showing a waveform shaping filter according to the thirty-first embodiment. As shown in FIG. 54, the waveform shaping filter according to the present embodiment includes a resistor R4, a capacitor C4, an amplifier A3, and a resistor R5.

  The resistor R4 (fourth resistor) has one end and the other end. The resistor R4 receives the signal voltage Vsignal from one end. The other end of the resistor R4 is connected to the other end of the capacitor C4 and the negative input terminal of the amplifier A3.

  The capacitor C4 (third capacitor) has one end and the other end. One end of the capacitor C4 is connected to one end of the resistor R4. Thereby, the signal voltage Vsignal is input to the capacitor C4 from one end. The other end of the capacitor C4 is connected to the other end of the resistor R4, the negative input terminal of the amplifier A3, and one end of the resistor R5.

  The resistor R5 (fifth resistor) has one end and the other end. One end of the resistor R5 is connected to the other end of the resistor R4, the negative input terminal of the amplifier A3, and the other end of the capacitor C4. The other end of the resistor R5 is connected to the output terminal of the amplifier A3.

  The amplifier A3 (second amplifier) includes a negative input terminal, a positive input terminal, and an output terminal. The negative input terminal is connected to the other end of the resistor R4, the other end of the capacitor C4, and one end of the resistor R5. A predetermined voltage Vc is applied to the positive input terminal. The output terminal is connected to the other end of the resistor R5. The voltage output from the output terminal of the amplifier A3 becomes the output voltage Vout of the waveform shaping filter.

  In the present embodiment, the amplifier A3 includes an inverter circuit Inv and voltage generation circuits Gen1 and Gen2, as shown in FIG.

  The inverter circuit Inv (first inverter circuit) includes an input terminal VinM, an output terminal VoutP, and transistors M31 and M32. The input terminal VinM is a negative input terminal of the amplifier A3. The output terminal VoutP is an output terminal of the amplifier A3.

  The transistor M31 (fourth transistor) is an NMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to a source terminal of a transistor M33, which will be described later, and a drain terminal of a transistor M35. The drain terminal is connected to the output terminal VoutP and the drain terminal of the transistor M32. The gate terminal is connected to the input terminal VinM.

  The transistor M32 (fifth transistor) is a PMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to a source terminal of a transistor M34 described later and a drain terminal of the transistor M36. The drain terminal is connected to the output terminal VoutP and the drain terminal of the transistor M31. The gate terminal is connected to the input terminal VinM.

  The voltage generation circuit Gen1 (first voltage generation circuit) includes a current source Ib31 and transistors M33 and M35.

  One end of the current source Ib31 (second current source) is connected to the drain terminal of the transistor M33, and supplies a predetermined current Ib31 to the transistor M33.

  The transistor M33 (sixth transistor) is an NMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to the source terminal of the transistor M31 and the drain terminal of the transistor M35. The drain terminal is connected to the current source Ib31 and the gate terminal of the transistor M35. The gate terminal is connected to the input terminal VinP and a gate terminal of a transistor M34 described later. The input terminal VinP is a positive input terminal of the amplifier A3. Therefore, a predetermined voltage Vc is applied to the gate terminal of the transistor M33.

  The transistor M35 (seventh transistor) is an NMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is grounded. The drain terminal is connected to the source terminals of the transistors M31 and M33. The gate terminal is connected to the current source Ib31 and the drain terminal of the transistor M33.

  The voltage generation circuit Gen2 (second voltage generation circuit) includes a current source Ib32 and transistors M34 and M36.

  The current source Ib32 (third current source) has one end connected to the drain terminal of the transistor M34 and supplies a predetermined current Ib32 to the transistor M34.

  The transistor M34 (eighth transistor) is a PMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to the source terminal of the transistor M32 and the drain terminal of the transistor M36. The drain terminal is connected to the current source Ib32 and the gate terminal of the transistor M36. The gate terminal is connected to the input terminal VinP and the gate terminal of the transistor M33. Therefore, a predetermined voltage Vc is applied to the gate terminal of the transistor M34.

  The transistor M36 (9th transistor) is a PMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to a power source. The drain terminal is connected to the source terminals of the transistors M32 and M34. The gate terminal is connected to the current source Ib32 and the drain terminal of the transistor M34.

  Next, the operation of the amplifier A3 according to this embodiment will be described. Hereinafter, it is assumed that the size ratio between the transistors M34 and M32 is equal to the size ratio between the transistors M33 and M31. Further, it is assumed that the current Ib31 supplied from the current source Ib31 is equal to the current Ib32 supplied from the current source Ib32 (Ib31 = Ib32 = Ib3).

  The voltage generation circuit Gen1 is fed back so that the current Ib31 of the current source Ib31 flows to the transistor M33 regardless of the current flowing to the transistor M31 of the inverter circuit Inv.

  For example, when the current flowing through the transistor M33 becomes smaller than Ib31, the gate voltage of the transistor M35 increases and the current flowing through the transistor M33 increases.

  When the current flowing through the transistor M33 becomes larger than Ib31, the gate voltage of the transistor M35 decreases and the current flowing through the transistor M33 decreases.

  As a result, the current Ib31 flows through the transistor M33.

  Similarly, the voltage generation circuit Gen2 is fed back so that the current Ib32 of the current source Ib32 flows to the transistor M34 regardless of the current flowing to the transistor M32 of the inverter circuit Inv.

  For this reason, when the voltage Vc applied to the positive input terminal VinP of the amplifier is applied to the input terminal VinM of the inverter circuit Inv (the negative input terminal of the amplifier A3), the transistor M31 includes the transistors M33 and M31. The current Ib3 multiplied by the size ratio flows, and the current Ib3 multiplied by the size ratio of the transistors M34 and M32 flows through the transistor M32.

  Thus, the inverter circuit Inv operates as an inverting circuit with the voltage Vc applied to the positive input terminal VinP of the amplifier A3 as an operating point. The bias current of the inverter circuit Inv at the operating point is a current that is twice the size ratio of the current Ib31 between the transistor M33 and the transistor M31.

  When the voltage applied to the negative input terminal VinM of the amplifier A3 is higher than the voltage Vc, the current flowing through the transistor M31 is larger than the bias current, and the current flowing through the transistor M32 is smaller than the bias current. As a result, the difference between the current flowing through the transistor M31 and the current flowing through the transistor M32 is output from the output terminal VoutP of the amplifier A3, and the output voltage Vout of the amplifier A3 decreases.

  When the voltage applied to the negative input terminal VinM of the amplifier A3 is much higher than the voltage Vc, the transistor M32 is turned off, and the current Ib3 flows through the transistors M33, M34, and M36. A large current corresponding to the voltage applied to the negative input terminal VinM flows only in the transistors M31 and M35.

  On the other hand, when the voltage applied to the negative input terminal VinM of the amplifier A3 is lower than the voltage Vc, the current flowing through the transistor M31 is smaller than the bias current, and the current flowing through the transistor M32 is larger than the bias current. . As a result, the difference between the current flowing through the transistor M31 and the current flowing through the transistor M32 is output from the output terminal VoutP of the amplifier A3, and the output voltage Vout of the amplifier A3 increases.

  When the voltage applied to the negative input terminal VinM of the amplifier A3 is much lower than the voltage Vc, the transistor M31 is turned off, and the current Ib3 flows through the transistors M33, M34, and M35. A large current corresponding to the voltage applied to the negative input terminal VinM flows only in the transistors M32 and M36.

  As described above, the amplifier A3 can set the operating point voltage when the input AC signal is 0 by the voltage Vc applied to the positive input terminal VinP. The amplifier A3 can set the bias current of the inverter circuit Inv by adjusting the currents Ib31 and Ib32, the size ratio of the transistors M31 and M33, and the size ratio of the transistors M32 and M34. Furthermore, when the amplifier A3 outputs a large current, the path of the large current is limited to the transistors M31 and M35 or the transistors M32 and M36, so that power consumption can be reduced. Therefore, an efficient class AB amplifier circuit can be realized. Furthermore, since the amplifier A3 is composed of the inverter circuit Inv, the amplification operation can be speeded up.

  FIG. 55 is a diagram showing a modification of the amplifier A3 according to the present embodiment. As shown in FIG. 55, the amplifier A3 further includes level shift circuits LS1 and LS2. Other configurations are the same as those of the amplifier A3 in FIG.

  The level shift circuit LS1 is connected between the drain terminal of the transistor M33 and the gate terminal of the transistor M35. The level shift circuit LS1 level-shifts the voltage so that the drain voltage of the transistor M33 is higher than the gate voltage of the transistor M35.

  The level shift circuit LS2 is connected between the drain terminal of the transistor M34 and the gate terminal of the transistor M36. The level shift circuit LS2 level-shifts the voltage so that the drain voltage of the transistor M34 is lower than the gate voltage of the transistor M36.

  In the amplifier A3 of FIG. 54, the drain voltages of the transistors M33 and M34 coincide with the gate voltages of the transistors M35 and M36. For this reason, for example, when the voltage between the power supply Vdd and the ground is high, the gate-source voltage of the transistor M33 is constant, so the source voltage of the transistor M33 is high and the drain-source voltage of the transistor M35 is high. .

  Since the gate-source voltage of the transistor M35 is the sum of the drain-source voltage of the transistor M35 and the drain-source voltage of the transistor M33, the transistor M33 increases when the drain-source voltage of the transistor M35 increases. As a result, the drain-source voltage becomes lower.

  As a result, the drain-source voltage of the transistor M33 becomes lower than the overdrive voltage, and the voltage generation circuit Gen1 may not perform a desired operation. The same applies to the voltage generation circuit Gen2.

  On the other hand, in the amplifier A3 of FIG. 55, the sum of the gate-source voltage of the transistor M35 and the voltage boosted by the level shift circuits LS1 and LS2 is the drain-source voltage of the transistor M35 and the transistor This is the sum of the drain-source voltage of M33. As a result, the drain-source voltage of the transistors M33 and M36 can be secured, and the range of the power supply voltage Vdd at which the transistors M33 and M36 operate in the saturation region and the setting range of the operating point can be expanded.

(First embodiment of level shift circuit)
FIG. 56 is a diagram showing a first embodiment of the level shift circuits LS1 and LS2 in FIG. As shown in FIG. 56, the level shift circuit LS1 (LS2) includes a resistor R31 (R32) and a current source Ib33 (Ib34).

  The resistor R31 (R32) has one end and the other end. One end of the resistor R31 (R32) is connected to the drain terminal of the transistor M33 (M34) and the current source Ib31 (Ib32). The other end of the resistor R31 (R32) is connected to the gate terminal of the transistor M35 (M36) and the current source Ib33 (Ib34). The current source Ib33 (Ib34) supplies a predetermined current Ib33 (Ib34) to the resistor R31 (R32).

  With such a configuration, the drain voltage of the transistor M33 (M34) becomes higher (lower) by R31 × Ib33 (R32 × Ib34) than the gate voltage of the transistor M35 (M36).

(Second embodiment of the level shift circuit)
FIG. 57 is a diagram showing a second embodiment of the level shift circuits LS1 and LS2 in FIG. As shown in FIG. 57, the level shift circuit LS1 (LS2) includes a transistor M37 (M38) and a current source Ib33 (Ib34).

  The transistor M37 (M38) is a PMOS (NMOS). The source terminal of the transistor M37 (M38) is connected to the drain terminal of the transistor M33 (M34) and the current source Ib31 (Ib32). The drain terminal of the transistor M37 (M38) is connected to the gate terminal of the transistor M35 (M36) and the current source Ib33 (Ib34). A predetermined voltage is applied to the gate terminal of the transistor M37 (M38). The current source Ib33 (Ib34) supplies a predetermined current Ib33 (Ib34) to the transistor M37 (M38).

  With such a configuration, the drain voltage of the transistor M33 (M34) is higher (lower) than the gate voltage of the transistor M35 (M36) by the drain-source voltage of the transistor M37 (M38).

(Third embodiment of level shift circuit)
FIG. 58 is a diagram showing a third embodiment of the level shift circuits LS1 and LS2 in FIG. As shown in FIG. 58, the level shift circuit LS1 (LS2) is obtained by connecting the gate terminal of the transistor M37 (M38) of the level shift circuit LS1 (LS2) of FIG. 57 to the gate terminal of the transistor M33 (M34). It is. The voltage Vc is applied to the gate terminals of the transistors M37 and M38. With such a configuration, a new voltage source for applying a voltage to the gate terminals of the transistors M37 and M38 becomes unnecessary, and the circuit configuration can be simplified.

(Fourth embodiment of level shift circuit)
FIG. 59 is a diagram showing a fourth embodiment of the level shift circuits LS1 and LS2 in FIG. As shown in FIG. 59, the level shift circuit LS1 (LS2) includes a transistor M39 (M40) and a current source Ib33 (Ib34).

  The transistor M39 (M40) is an NMOS (PMOS). The source terminal of the transistor M39 (M40) is connected to the gate terminal of the transistor M35 (M36) and the current source Ib33 (Ib34). The drain terminal of the transistor M39 (M40) is connected to a power supply (ground). The gate terminal of the transistor M39 (M40) is connected to the drain terminal of the transistor M33 (M34) and the current source Ib31 (Ib32). The current source Ib33 (Ib34) supplies a predetermined current Ib33 (Ib34) to the transistor M39 (M40).

  With such a configuration, the drain voltage of the transistor M33 (M34) is higher (lower) than the gate voltage of the transistor M35 (M36) by the gate-source voltage of the transistor M39 (M40).

(Thirty-second embodiment)
Next, a waveform shaping filter according to the thirty-second embodiment will be described with reference to FIG. FIG. 60 is a diagram illustrating a waveform shaping filter according to the thirty-second embodiment. As shown in FIG. 60, the waveform shaping filter according to this embodiment includes a resistor R6, a capacitor C5, and an amplifier A3.

  The resistor R6 (sixth resistor) has one end and the other end. One end of the resistor R6 is connected to the negative input terminal of the amplifier A3 and one end of the capacitor C5. The other end of the resistor R6 is connected to the output terminal of the amplifier A3.

  The capacitor C5 (fourth capacitor) has one end and the other end. One end of the capacitor C4 is connected to the negative input terminal of the amplifier A3 and one end of the resistor R6. The other end of the capacitor C4 is grounded.

  The amplifier A3 (third amplifier) includes a negative input terminal, a positive input terminal, and an output terminal. The negative input terminal is connected to one end of the resistor R6 and one end of the capacitor C5. The signal voltage Vsingal is input to the positive input terminal. The output terminal is connected to the other end of the resistor R6. The voltage output from the output terminal of the amplifier A3 becomes the output voltage Vout of the waveform shaping filter.

  As shown in FIG. 60, the amplifier A3 has the same configuration as that of FIG. 54, and includes an inverter circuit Inv and voltage generation circuits Gen1 and Gen2.

  The inverter circuit Inv (second inverter circuit) includes an input terminal VinM, an output terminal VoutP, and transistors M31 and M32. The input terminal VinM is a negative input terminal of the amplifier A3. The output terminal VoutP is an output terminal of the amplifier A3.

  The transistor M31 (tenth transistor) is an NMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to the source terminal of the transistor M33 and the drain terminal of the transistor M35. The drain terminal is connected to the output terminal VoutP and the drain terminal of the transistor M32. The gate terminal is connected to the input terminal VinM.

  The transistor M32 (an eleventh transistor) is a PMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to the source terminal of the transistor M34 and the drain terminal of the transistor M36. The drain terminal is connected to the output terminal VoutP and the drain terminal of the transistor M31. The gate terminal is connected to the input terminal VinM.

  The voltage generation circuit Gen1 (third voltage generation circuit) includes a current source Ib31 and transistors M33 and M35.

  One end of the current source Ib31 (fourth current source) is connected to the drain terminal of the transistor M33, and supplies a predetermined current Ib31 to the transistor M33.

  The transistor M33 (the twelfth transistor) is an NMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to the source terminal of the transistor M31 and the drain terminal of the transistor M35. The drain terminal is connected to the current source Ib31 and the gate terminal of the transistor M35. The gate terminal is connected to the input terminal VinP and a gate terminal of a transistor M34 described later. The input terminal VinP is a positive input terminal of the amplifier A3. Therefore, the signal voltage Vsignal is applied to the gate terminal of the transistor M33.

  The transistor M35 (13th transistor) is an NMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is grounded. The drain terminal is connected to the source terminals of the transistors M31 and M33. The gate terminal is connected to the current source Ib31 and the drain terminal of the transistor M33.

  The voltage generation circuit Gen2 (fourth voltage generation circuit) includes a current source Ib32 and transistors M34 and M36.

  The current source Ib32 (fifth current source) has one end connected to the drain terminal of the transistor M34 and supplies a predetermined current Ib32 to the transistor M34.

  The transistor M34 (fourteenth transistor) is a PMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to the source terminal of the transistor M32 and the drain terminal of the transistor M36. The drain terminal is connected to the current source Ib32 and the gate terminal of the transistor M36. The gate terminal is connected to the input terminal VinP and the gate terminal of the transistor M33. Therefore, the signal voltage Vsignal is applied to the gate terminal of the transistor M34.

  The transistor M36 (fifteenth transistor) is a PMOS and includes a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to a power source. The drain terminal is connected to the source terminals of the transistors M32 and M34. The gate terminal is connected to the current source Ib32 and the drain terminal of the transistor M34.

  Next, the operation of the amplifier A3 according to this embodiment will be described. Hereinafter, it is assumed that the size ratio between the transistors M34 and M32 is equal to the size ratio between the transistors M33 and M31. Further, it is assumed that the current Ib31 supplied from the current source Ib31 is equal to the current Ib32 supplied from the current source Ib32 (Ib31 = Ib32 = Ib3).

  As described above, the voltage generation circuit Gen1 is fed back so that the current Ib31 of the current source Ib31 flows to the transistor M33 regardless of the current flowing to the transistor M31 of the inverter circuit Inv. The voltage generation circuit Gen2 is fed back so that the current Ib32 of the current source Ib32 flows to the transistor M34 regardless of the current flowing to the transistor M32 of the inverter circuit Inv.

  Therefore, when the same voltage as the signal voltage Vsignal applied to the positive input terminal VinP of the amplifier is applied to the input terminal VinM of the inverter circuit Inv (the negative input terminal of the amplifier A3), the transistor M31 includes the transistor M33 and The current Ib3 multiplied by the size ratio with the transistor M31 flows, and the current Ib3 multiplied by the size ratio of the transistors M34 and M32 flows through the transistor M32.

  Since the output voltage of the amplifier A3 is fed back to the negative input terminal via the resistor R6, the voltage at the negative input terminal VinM follows the signal voltage Vsignal applied to the positive input terminal VinP. As a result, the amplifier A3 operates as a non-inverting amplifier circuit. The bias current of the inverter circuit Inv is a current that is double the size of the current Ib31 between the transistor M33 and the transistor M31.

  When the voltage applied to the negative input terminal VinM of the amplifier A3 is higher than the signal voltage Vsignal, the current flowing through the transistor M31 is larger than the bias current, and the current flowing through the transistor M32 is smaller than the bias current. As a result, the difference between the current flowing through the transistor M31 and the current flowing through the transistor M32 is output from the output terminal VoutP of the amplifier A3, and the output voltage of the amplifier A3 decreases.

  When the voltage applied to the negative input terminal VinM of the amplifier A3 is much higher than the signal voltage Vsignal, the transistor M32 is turned off, and the current Ib3 flows through the transistors M33, M34, and M36. A large current corresponding to the voltage applied to the negative input terminal VinM flows only in the transistors M31 and M35.

  On the other hand, when the voltage applied to the negative input terminal VinM of the amplifier A3 is lower than the signal voltage Vsignal, the current flowing through the transistor M31 is smaller than the bias current, and the current flowing through the transistor M32 is larger than the bias current. Become. As a result, the difference between the current flowing through the transistor M31 and the current flowing through the transistor M32 is output from the output terminal VoutP of the amplifier A3, and the output voltage of the amplifier A3 increases.

  When the voltage applied to the negative input terminal VinM of the amplifier A3 is much lower than the signal voltage Vsignal, the transistor M31 is turned off, and the current Ib3 flows through the transistors M33, M34, and M35. A large current corresponding to the voltage applied to the negative input terminal VinM flows only in the transistors M32 and M36.

  As described above, the amplifier A3 can set the bias current of the inverter circuit Inv because the voltage at the negative input terminal VinM is equal to the voltage at the positive input terminal VinP. The amplifier A3 can set the bias current of the inverter circuit Inv by adjusting the currents Ib31 and Ib32, the size ratio of the transistors M31 and M33, and the size ratio of the transistors M32 and M34. Furthermore, when the amplifier A3 outputs a large current, the path of the large current is limited to the transistors M31 and M35 or the transistors M32 and M36, so that power consumption can be reduced. Therefore, an efficient class AB amplifier circuit can be realized. Furthermore, since the amplifier A3 is composed of the inverter circuit Inv, the amplification operation can be speeded up.

  In the above description, the amplifier A3 has the same configuration as that of FIG. 54, but may have any of the configurations of FIG. 55 to FIG.

(Thirty-third embodiment)
Next, a radiation detection apparatus according to the thirty-third embodiment will be described with reference to FIGS. FIG. 61 is a schematic diagram showing a radiation detection apparatus according to the present embodiment. As shown in FIG. 61, the radiation detection apparatus includes a photon detector and a filter circuit.

  The photon detector outputs a charge amount proportional to the energy of incident radiation photons as a pulsed signal current Isignal. As shown in FIG. 61, the photon detector includes a scintillator and a photomultiplier.

  The scintillator generates scintillation light corresponding to the energy of incident radiation photons. The scintillator has a low-pass characteristic due to the decay time of the scintillation light. Hereinafter, the time constant of the scintillator is τ1, and the low-pass characteristic is 1 / (1 + sτ1).

  The photomultiplier (SiPM) outputs a charge amount corresponding to the energy of the scintillation light generated by the scintillator as a pulsed signal current Isignal. In general, a photomultiplier has a low-pass characteristic. Hereinafter, the time constant of the photomultiplier is τ2, and the low-pass characteristic is 1 / (1 + sτ2).

  The filter circuit shapes and outputs the waveform of the signal current Isignal input from the photon detector. The filter circuit includes at least one waveform shaping filter according to the first to thirty-second embodiments. The filter circuit may include a plurality of waveform shaping filters having the same configuration, or may include a plurality of waveform shaping filters having different configurations.

  When the filter circuit includes the waveform shaping filter according to the thirty-first or thirty-second embodiment, the filter circuit may include a current-voltage conversion circuit that converts the signal current Isignal to the signal voltage Vsignal.

  Furthermore, the filter circuit preferably includes a waveform shaping filter having a time constant equal to the time constant of each configuration of the photon detector.

  For example, when the photon detector includes a scintillator with a time constant τ1 and a photomultiplier with a time constant τ2 as in the radiation detection apparatus of FIG. 61, the filter circuit has a first stage having a time constant τ1. And a second-stage waveform shaping filter having a time constant τ2. At this time, the enhancement characteristic of the first-stage waveform shaping filter is 1 + sτ1, and the enhancement characteristic of the second-stage waveform shaping filter is 1 + sτ2.

  With such a configuration, the low-pass characteristic of the signal current Isignal is canceled by the high-frequency emphasis characteristic of each waveform shaping filter of the filter circuit, and the signal current that is dulled by the low-pass characteristic (the pulse width is expanded). It is possible to remove the blunting of Signal and narrow the pulse width.

  Here, FIG. 62 is a diagram illustrating a simulation result of the radiation detection apparatus including the filter circuit having such a configuration. As shown in FIG. 62, the output voltage of the photon detector has a waveform in which a secondary low-pass characteristic is given to the pulse of the radiation photon. On the other hand, it can be seen that the output voltage of the waveform shaping filter at the second stage has a waveform proportional to the pulse of the original radiation photon with the low-pass characteristic of the signal voltage Vsignal removed.

  The same effect can be obtained by setting the time constant of the first-stage waveform shaping filter to τ2 and the time constant of the second-stage waveform shaping filter to τ1. Further, the filter circuit may include waveform shaping filters corresponding to the number of stages corresponding to the order of the low-pass characteristics of the signal current Isignal. For example, when the signal current Isignal has a first-order low-pass characteristic, the filter circuit may include only one stage of waveform shaping filter.

(First embodiment)
FIG. 63 is a diagram illustrating a first example of the filter circuit according to the present embodiment. As shown in FIG. 63, this filter circuit includes waveform shaping filters WSF1 and WSF2 and a comparator Comp.

  The waveform shaping filter WSF1 is a first-stage waveform shaping filter in which the waveform shaping filters of FIGS. 3 and 4 are combined. The transistor M1, the resistor R1, the capacitor C1, the amplifier A1, the current source Idc1, and the resistor R1a. The time constant of the waveform shaping filter WSF1 is C1 (R1 + R1a).

  When the signal current Isignal is input from the photon detector (current source Isignal), the waveform shaping filter WSF1 outputs a current of Isignal × {1 + sC1 (R1 + R1a)} from the drain terminal of the transistor M1.

  The waveform shaping filter WSF2 is a second-stage waveform shaping filter obtained by modifying the waveform shaping filter of FIG. 53, and includes a transistor M4, a resistor R3, and a capacitor C3. The above configuration is the same as FIG. The waveform shaping filter WSF2 further includes a current source Idc3, a capacitor C31, and a resistor R7.

  The current source Idc3 is connected to the gate terminal of the transistor M4 (the negative input terminal of the voltage / current conversion circuit Gm), one end of the capacitor C3, the other end of the resistor R3, and one end of the resistor R7. The current source Idc3 supplies a predetermined current Idc3 to the transistor M4 and the resistors R3 and R7. Thus, the transistor M4 can be turned on even when no input signal arrives, that is, when no radiation photons are detected by the photon detector.

  The capacitor C31 includes one end and the other end. One end of the capacitor C31 is connected to the other end of the capacitor C3, the negative input terminal of the comparator Comp, and the other end of the resistor R7. The other end of the capacitor C31 is grounded. The time constant of the waveform shaping filter WSF2 is R3 × C3 × C31 / (C3 + C31) depending on the combined capacitance in which the capacitors C3 and C31 are connected in series.

  The resistor R7 has one end and the other end. One end of the resistor R7 is connected to the gate terminal of the transistor M4, the other end of the resistor R3, one end of the capacitor C3, and the current source Idc3. The other end of the resistor R7 is connected to the other end of the capacitor C3, one end of the capacitor C31, and the negative input terminal of the comparator Comp.

  The comparator Comp includes a negative input terminal, a positive input terminal, and an output terminal. The negative input terminal is connected to the other end of the capacitor C3, one end of the capacitor C31, and the other end of the resistor R7. The positive input terminal is connected to the drain terminals of the transistors M1 and M4 and one end of the resistor R3.

  The comparator Comp compares the reference voltage applied to the negative input terminal with the output voltage (input terminal voltage V1) of the waveform shaping filter WSF2 applied to the positive input terminal, and outputs a binary signal. Here, the comparator Comp outputs 1 or 0. The comparator Comp outputs 1 when the output voltage of the waveform shaping filter WSF2 is lower than the reference voltage, that is, when an input signal arrives, and outputs 0 otherwise. That is, the filter circuit of FIG. 63 can shape the waveform of the signal current Isignal and detect the arrival of the input signal.

  As described above, the pulse width of the input signal can be narrowed by shaping the waveform of the signal current Isignal. Thereby, as shown in FIG. 62, the input signals piled up in the signal current Isignal can be separated from each other. Therefore, the filter circuit can accurately detect the arrival of each input signal.

  Further, since the reference voltage applied to the negative input terminal of the comparator Comp is a voltage at the voltage dividing point of the capacitor C3 and the capacitor C31, the AC component is reduced. Thereby, fluctuations in the reference voltage can be suppressed. The DC component of the reference voltage is set by the resistor R7.

  The output voltage of the waveform shaping filter WSF2 input to the positive input terminal of the comparator Comp is a voltage obtained by level shifting the gate voltage of the transistor M4 by R3 × Idc3. Therefore, by adjusting Idc3, it is possible to easily set a threshold for detecting arrival of an input signal (outputting 1). Therefore, even when there is a variation in the threshold voltage of the transistor M4 and an input offset of the comparator Comp, it is possible to accurately detect the arrival of the input signal.

  In this embodiment, the arrival of the input signal is detected by the comparator Comp. However, the filter circuit does not include the comparator Comp, and the output voltage of the waveform shaping filter WSF2 (the drain voltage of the transistor M4) is output. Good. Thereby, the input current Isignal can be shaped into a signal having a narrow pulse width. Further, the filter circuit Idc3 may be configured not to include the current source Idc3, the resistor R7, and the capacitor C31.

(Second embodiment)
FIG. 64 is a diagram illustrating a second example of the filter circuit according to the present embodiment. As shown in FIG. 64, the filter circuit includes waveform shaping filters WSF1 and WSF2 and an AD converter ADC.

  The waveform shaping filter WSF1 is a first-stage waveform shaping filter having the same configuration as the waveform shaping filter WSF1 of FIG.

  The waveform shaping filter WSF2 is a second-stage waveform shaping filter having the same configuration as the waveform shaping filter of FIG. 7, and includes transistors M2 and M3, a resistor R2, a capacitor C2, a current source Idc2, and an amplifier A2. . The time constant of the waveform shaping filter WSF2 is C2 × R2.

  The AD converter ADC includes a resistor Rv, a transistor M5, an amplifier A4, resistors Rref1 to Rref7, comparators Comp1 to Comp7, and a current source Iref.

  The resistor Rv has one end and the other end. One end of the resistor Rv is connected to the drain terminal of the transistor M3, one end of the resistor Rref1, and the input terminal of the amplifier A4. The other end of the resistor Rv is connected to the drain terminal of the transistor M5 and the positive input terminals of the comparators Comp1 to Comp7.

  The output current of the waveform shaping filter WSF2, that is, the current flowing through the transistor M3 is converted into the voltage Vout by the resistor Rv and applied to each positive input terminal of the comparators Comp1 to Comp7.

  The transistor M5 is an NMOS and includes a source terminal, a drain terminal, and a gate terminal. The source terminal is grounded. The drain terminal is connected to the other end of the resistor Rv and the positive input terminals of the comparators Comp1 to Comp7. The gate terminal is connected to the output terminal of the amplifier A4.

  The amplifier A4 is a non-inverting amplifier and includes a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal is connected to the drain terminal of the transistor M3 and one end of the resistors Rv and Rref1. The negative input terminal is grounded (not shown). The output terminal is connected to the gate terminal of the transistor M5. The input of the amplifier A4 is a virtual ground point, and the reference voltages Vref1 to Vref7 of the comparators Comp1 to Comp7 are generated based on the voltage of the virtual ground point.

  The resistors Rref1 to Rref7 each have one end and the other end. One end of the resistor Rref1 is connected to the drain terminal of the transistor M3, one end of the resistor Rv, and the positive input terminal of the amplifier A4. The other end of the resistor Rref1 is connected to one end of the resistor Rref2 and a negative input terminal of the comparator Comp1. One end of the resistor Rref7 is connected to the other end of the resistor Rref6 and the negative input terminal of the comparator Comp6. The other end of the resistor Rref7 is connected to the negative input terminal of the comparator Comp7 and the current source Iref.

  The resistors Rref2 to Rref6 are connected in series between the resistors Rref1 and Rref7. One ends of the resistors Rref2 to Rref6 are connected to the other ends of the resistors Rref1 to Rref5 and the negative input terminals of the comparators Comp1 to Comp5, respectively. The other ends of the resistors Rref2 to Rref6 are connected to one end of the resistors Rref3 to Rref7 and the negative input terminals of the comparators Comp2 to Comp6, respectively.

  The current source Iref is a direct current source and is connected to the other end of the resistor Rref7 and the negative input terminal of the comparator Comp7. Thus, the reference voltage VrefN of the comparator CompN (N = 1 to 7) is lower than the voltage at the virtual ground point of the amplifier A4 by Iref × (Rref1 +... + RrefN).

  As described above, since the reference voltage VrefN of the comparator CompN can be generated based on the voltage of the virtual ground point of the amplifier A4, even if the voltage of the virtual ground point varies due to element variation, it is appropriate for the comparator CompN. A reference voltage VrefN can be applied.

  Each of the comparators CompN (N = 1 to 7) includes a negative input terminal, a positive input terminal, and an output terminal. The positive input terminal of the comparator CompN is connected to the other end of the resistor Rv and the drain terminal of the transistor M5. The negative input terminals of the comparators Comp1 to Comp6 are connected to the other ends of the resistors Rref1 to Rref6 and one ends of the resistors Rref2 to Rref7, respectively. The negative input terminal of the comparator Comp7 is connected to the other end of the resistor Rref7 and the current source Iref.

  The comparator CompN compares the output voltage Vout applied to the positive input terminal with the reference voltage VrefN (threshold) applied to the negative input terminal, and outputs a binary digital signal DN. Here, the comparator CompN outputs 1 or 0.

  The comparator CompN outputs 1 when the output voltage Vout is lower than the reference voltage VrefN, and outputs 0 otherwise. That is, the AD converter ADC outputs a digital signal corresponding to the wave height of the output voltage Vout. When seven comparators CompN are provided as in the present embodiment, the AD converter ADC can AD convert the wave height of the input signal into seven gradations.

  As described above, the filter circuit of FIG. 64 can shape the waveform of the signal current Isignal, AD-convert the wave height of the signal current Isignal, and output a digital signal corresponding to the wave height.

  In FIG. 64, the AD converter ADC includes seven comparators CompN, but N can be arbitrarily selected. When N = 1, that is, when the AD converter ADC includes only one comparator CompN, the filter circuit can detect the arrival of the input signal as in the filter circuit of FIG. When N ≧ 2, the filter circuit can AD convert the wave height of the signal current Isignal to N gray levels.

(Third embodiment)
FIG. 65 is a diagram illustrating a third example of the filter circuit according to the present embodiment. As illustrated in FIG. 65, the AD converter ADC further includes counters Cnt1 to Cnt7. Other configurations are the same as those in FIG.

  Counters CntN (N = 1 to 7) are respectively connected to the output terminals of the comparator CompN, and count the output result of the comparator CompN. The counter CntN counts, for example, the number of times that the comparator CompN has output 1, that is, the number of times that the output voltage Vout lower than the reference voltage VrefN has been input to the comparator CompN. The counter CntN outputs a digital signal DN corresponding to the count value CntN at a predetermined time interval.

  With such a configuration, the subsequent circuit of the filter circuit calculates the difference between the count value CntN and the count value Cnt (N−1), so that the wave height is changed between the reference voltage VrefN and the reference voltage Vref (N−1). ) To obtain the histogram of the input signals.

(Fourth embodiment)
FIG. 66 is a diagram illustrating a fourth example of the filter circuit according to the present embodiment. As shown in FIG. 66, the AD converter ADC further includes an off period generation circuit OFF. Other configurations are the same as those in FIG.

  The off period generation circuit OFF stops wave height observation (AD conversion) during a predetermined off period after the filter circuit detects the arrival of the input signal. The reason is as follows.

  As described above, when the input signal is piled up in the signal current Isignal, the piled up input signal is separated by the waveform shaping filters WSF1 and WSF2. However, an error may occur in the wave heights of the separated input signals (for example, the second and third input signals in FIG. 62) due to the effect of pileup.

  Therefore, in this embodiment, after the input signal is detected, the counting by the counters Cnt2 to Cnt7 is stopped by the off period generation circuit OFF. Thereby, the detection error of the wave height can be suppressed. The off period can be arbitrarily set.

  The off period generation circuit OFF includes, for example, an off signal generator off and an AND circuit as shown in FIG.

  The off signal generator off receives the output signal of the comparator Comp1, and outputs a binary signal corresponding to the output signal. Specifically, the off signal generator off outputs 0 (off signal) during the off period after 1 is input from the comparator Comp1, and outputs 1 (on signal) during the other periods. To do.

  The AND circuits are provided between the comparators Comp2 to Comp7 and the counters Cnt2 to Cnt7, respectively. Each AND circuit receives the output signal of the comparator CompN and the output signal of the off signal generator off. The AND circuit outputs 1 when 1 is input from the comparator CompN and 1 is input from the off signal generator off, and outputs 0 in other cases. The output signal of each AND circuit is input to the counter ContN (N = 2 to 7). The counter CntN (N = 2 to 7) counts the number of times 1 is input from the AND circuit.

  Next, the operation of the off period generation circuit OFF will be described. When the input signal does not arrive at this filter circuit, the off signal generator off outputs 1 (on signal), and the comparators Comp1 to Comp7 output 0. For this reason, the counters Cnt1 to Cnt7 do not count.

  When the input signal arrives at the filter circuit, the comparator CompN (N = 1 to 7) outputs 1 or 0 according to the comparison result between the output voltage Vout and the reference voltage VrefN. At this time, since the off signal generator off outputs 1, the comparison result is counted by the counter CntN.

  Thereafter, when 1 is input from the comparator Comp1, the output signal of the off signal generator off becomes 0 (off signal). The off signal generator off continues to output 0 during the off period. Therefore, during the off period, the output of the AND circuit becomes 0, and the counting by the counters Cnt2 to Cnt7 stops.

  After the off period has elapsed, the output signal of the off signal generator off becomes 1 (on signal). Thereafter, the off signal generator off continues to output 1 until the next input signal arrives.

  With the above configuration, even if an input signal piled up during the off period arrives, the wave height is not detected. Therefore, the detection error of the wave height of the input signal piled up can be suppressed.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. Further, for example, a configuration in which some components are deleted from all the components shown in each embodiment is also conceivable. Furthermore, you may combine suitably the component described in different embodiment.

M: transistor, C: capacitance, Idc: current source, R: resistor, A: amplifier, Gm: voltage-current converter, LPF: low-pass filter, Inv: inverter, Gen: voltage generation circuit, Comp: comparator, WSF: waveform shaping filter, ADC: AD converter, Cnt: counter, OFF: off period generation circuit, off: off signal generator, Z: low input impedance circuit, VB: voltage buffer, IB: current buffer

Claims (19)

A first resistor having one end to which a signal current is input and the other end;
A first transistor comprising: a first terminal connected to the other end of the first resistor; a second terminal that outputs an output current corresponding to the signal current; and a first control terminal;
A first capacitor comprising one end connected to the other end of the first resistor and the other end set to a potential correlated with a reference potential;
A first amplifier comprising: an input terminal connected to the one end of the first resistor; and an output terminal connected to the first control terminal of the first transistor;
A waveform shaping filter comprising: The waveform shaping filter according to claim 1, wherein the first amplifier is an inverting amplifier. A first resistor having one end to which a signal current is input and the other end;
A first transistor comprising: a first terminal connected to the other end of the first resistor; a second terminal set to a reference potential; and a first control terminal;
A first capacitor including one end connected to the other end of the first resistor and the other end set to a potential correlated with the reference potential;
A first amplifier comprising: an input terminal connected to the one end of the first resistor; and an output terminal connected to the first control terminal of the first transistor;
A third terminal set to the reference potential; a fourth terminal that outputs an output current corresponding to the signal current; and a second control terminal connected to the first control terminal of the first transistor. A second transistor comprising:
The waveform shaping filter, wherein the first amplifier is a non-inverting amplifier. The other end of the first capacitor is connected to the fourth terminal of the second transistor;
An input terminal connected to the fourth terminal of the second transistor and the other end of the first capacitor, and the output current output from the fourth terminal of the second transistor includes The waveform shaping filter according to claim 3, further comprising a low input impedance circuit that adds a current flowing from the other end of the one capacitor. The waveform shaping filter according to claim 1, wherein the first amplifier is a current input type amplifier. The waveform shaping filter according to claim 1, further comprising a first current source connected to the first terminal of the first transistor.   7. The waveform shaping filter according to claim 1, further comprising a second resistor connected between the other end of the first capacitor and the reference potential. 8. 8. The waveform shaping filter according to claim 1, wherein the waveform shaping filter has a time constant equal to any one of one or a plurality of time constants of the low-pass characteristic of the signal current. . The product of the resistance value of the first resistor and the capacitance value of the first capacitor is equal to any one time constant of one or more time constants of the low-pass characteristic of the signal current. The waveform shaping filter according to any one of claims 1 to 8. A first current mirror circuit comprising: an input terminal connected to the other end of the first capacitor; and an output terminal connected to the one end of the first capacitor;
10. The waveform shaping filter according to claim 1, wherein the first current mirror circuit inverts and outputs a polarity of a current flowing through the first capacitor. 11. A second current mirror circuit comprising: an input terminal connected to the second terminal of the first transistor; and an output terminal connected to the other end of the first capacitor;
An input terminal connected to the output terminal of the second current mirror circuit is provided, and an output current output from the output terminal of the second current mirror circuit flows from the other end of the first capacitor. A low input impedance circuit for adding current,
Further comprising
3. The waveform shaping filter according to claim 1, wherein the second current mirror circuit inverts the polarity of the current flowing through the first transistor and outputs the inverted signal. A tenth resistor connected between the other end of the first resistor and the first terminal of the first transistor;
A voltage buffer comprising: an input terminal connected to the other end of the first resistor; and an output terminal;
An eleventh capacitor comprising one end connected to the first terminal of the first transistor and the other end connected to the output terminal of the voltage buffer;
The waveform shaping filter according to any one of claims 1 to 11, further comprising: An eleventh resistor connected between the other end of the first resistor and the first terminal of the first transistor;
A current buffer comprising: an output terminal connected to the first terminal of the first transistor; and an input terminal;
A twelfth capacitor including one end connected to the other end of the first resistor and the other end connected to the input terminal of the current buffer;
The waveform shaping filter according to any one of claims 1 to 11, further comprising: A twelfth resistor comprising one end connected to the one end of the first resistor and the other end;
A voltage buffer comprising: an input terminal connected to the other end of the twelfth resistor; and an output terminal;
A thirteenth capacitor including one end connected to the one end of the first resistor and the other end connected to the output terminal of the voltage buffer;
The waveform shaping filter according to any one of claims 1 to 11, further comprising: A photon detector that outputs a signal current according to the energy of the incident radiation photons;
A filter circuit comprising at least one stage of the waveform shaping filter according to any one of claims 1 to 14,
A radiation detection apparatus comprising: The photon detector is
A scintillator that generates scintillation light according to the energy of the radiation photons;
A photomultiplier that outputs the signal current according to the energy of the scintillation light,
The filter circuit is
The waveform shaping filter having a time constant equal to the time constant of the scintillator;
The waveform shaping filter having a time constant equal to the time constant of the photomultiplier;
The radiation detection apparatus according to claim 15. The radiation detection apparatus according to claim 15 or 16, wherein the filter circuit further includes N comparators that respectively compare outputs of the waveform shaping filter with N (≧ 1) threshold values. The radiation detection apparatus according to claim 17, wherein the filter circuit further includes a counter that counts an output result of the comparator. The radiation detection apparatus according to claim 18, wherein the filter circuit further includes an off period generation circuit that stops counting by a part of the counter for a predetermined off period after detecting an input signal.

Images