JP6552667B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and can be suitably used for manufacturing a semiconductor device including a power semiconductor element represented by, for example, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  Japanese Unexamined Patent Publication No. 2010-541212 (Patent Document 1) describes a power device including a plurality of pillars of the first and second conductivity types alternately arranged in each of the active region and the termination region. . In the power device, the pillars of the first conductivity type in the active region and the termination region have substantially the same width, and the pillars of the second conductivity type in the active region have a smaller width than the pillars of the second conductivity type in the termination region The breakdown voltage in the termination region is higher than the breakdown voltage in the active region.

JP-A-2010-541212

  A power MOSFET having a super junction structure has an advantage that the on-resistance can be reduced while ensuring a high breakdown voltage. However, in a semiconductor chip in which a power MOSFET is formed, an avalanche breakdown phenomenon is more likely to occur in a peripheral region (termination region, termination region) surrounding the outside of the cell region than in a cell region (active region) in which the power MOSFET is formed. For this reason, there is a problem that the avalanche current concentrates on the outer peripheral portion of the cell region and the power MOSFET is broken.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  The semiconductor device according to one embodiment has a cell region and a peripheral region formed outside the cell region, and n-type column regions and p-type column regions are alternately arranged in each of the cell region and the peripheral region. The n-type impurity concentration of the n-type column region of the cell region is higher than the n-type impurity concentration of the n-type column region of the peripheral region. Furthermore, the difference between the total charge amount in the p-type column region and the total charge amount in the n-type column region is within ± 10% of the total charge amount in the p-type column region, or the total charge amount in the p-type column region is n-type column Charge balance is established in each of the cell region and the peripheral region so as to be larger than the total charge amount of the region.

  In a method of manufacturing a semiconductor device according to one embodiment, a plurality of n-type column regions are formed to be separated from each other in an n-type epitaxial layer of a cell region, and n-type column regions adjacent to each other are sandwiched between the cell regions. Forming a plurality of p-type column regions in partial regions of the n-type epitaxial layer. Further, a plurality of p-type column regions are formed apart from each other in the n-type epitaxial layer in the peripheral region, and a plurality of partial regions of the n-type epitaxial layer sandwiched between adjacent p-type column regions in the peripheral region Forming an n-type column region of The impurity concentration, width, and pitch of each of the plurality of n-type column regions in the cell region, the plurality of p-type column regions in the cell region, and the plurality of p-type column regions in the peripheral region are adjusted to adjust the cell region and the peripheral region. Charge balance at each

  According to one embodiment, the reliability of a semiconductor device including a power semiconductor element can be improved.

1 is a schematic diagram showing a planar configuration of a semiconductor chip according to a first embodiment. FIG. 2 is a cross sectional view (cross sectional view cut along the line A-A in FIG. 1) showing the configuration of the semiconductor device according to the first embodiment. (A) is a graph which shows charge balance of the breakdown voltage (BVdss) of the pn junction in the semiconductor device by Embodiment 1. FIG. (B) As a comparative example, the peak of the breakdown voltage (BVdss) of the pn junction in the charge balance in the cell region and the peak of the breakdown voltage (BVdss) in the pn junction of the charge balance in the peripheral region studied by the present inventors It is a graph which shows the charge balance of the breakdown voltage (BVdss) of a pn junction in a semiconductor device. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment. FIG. FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4; FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 5; FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 8; FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 12; FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 17; FIG. 7 is a cross sectional view showing a configuration of a semiconductor device according to a second embodiment. FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment. FIG. 21 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 20; FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; FIG. 23 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 26; FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 27; FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 28; FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 29; FIG. 31 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 30; FIG. 32 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 31; FIG. 4 is a graph showing a charge balance of a breakdown voltage (BVdss) of a pn junction in a semiconductor device, a schematic diagram showing a total charge amount distribution of a pn junction, and a schematic diagram showing electric field strength of the pn junction. (A) shows the electric field strength and the like when the total charge amount (Qp) of the p-type column region and the total charge amount (Qn) of the n-type column region are substantially the same (Qp ≒ Qn). (B) shows the electric field strength and the like when the total charge amount (Qp) of the p-type column region is larger than the total charge amount (Qn) of the n-type column region (Qp> Qn). (C) shows the electric field strength and the like when the total charge amount (Qp) of the p-type column region is smaller than the total charge amount (Qn) of the n-type column region (Qp <Qn). FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment. FIG. 10 is a schematic diagram showing a total charge amount distribution at a pn junction in the semiconductor device according to the third embodiment and a schematic diagram showing an electric field intensity at the pn junction. (A) is a graph showing the total charge amount distribution and the electric field strength when the p-type impurity concentration in the p-type column region and the n-type impurity concentration in the n-type column region are uniform in the depth direction. (B) is a graph showing the total charge amount distribution and the electric field strength when the p-type impurity concentration in the p-type column region gradually decreases in the depth direction from the upper surface to the lower surface of the epitaxial layer. (C) is a graph showing the total charge amount distribution and the electric field strength when the n-type impurity concentration in the n-type column region gradually increases in the depth direction from the upper surface to the lower surface of the epitaxial layer. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. And some or all of the variations, details, and supplementary explanations.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential except in the case where they are particularly clearly shown and where they are considered to be obviously essential in principle. Needless to say.

  In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not something to do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

(Issues of power semiconductor devices)
For example, power semiconductor elements typified by power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors) are used as switching elements for driving a load. When the load includes an inductance, when the power semiconductor element is turned off, the power semiconductor element is reversed. An electromotive force is generated, and a voltage resulting from the back electromotive force is applied to the power semiconductor element. In this case, a voltage equal to or higher than the power supply voltage is applied to the power semiconductor element, and when this voltage exceeds the avalanche breakdown voltage, an avalanche breakdown phenomenon occurs in the power semiconductor element and an avalanche current flows. When the avalanche current exceeds the avalanche resistance (permissible current amount) of the power semiconductor element, the power semiconductor element is broken. This avalanche resistance indicates the allowable amount of avalanche current that flows until breakdown due to an avalanche breakdown phenomenon, and when local concentration of avalanche current occurs in a power semiconductor element, the avalanche resistance Destruction of the power semiconductor device is likely to occur.

  From this, in order to improve the reliability of the power semiconductor device, the device structure of the power semiconductor device is devised so as to avoid local current concentration of the avalanche current as much as possible and to prevent the avalanche current from exceeding the avalanche resistance. It is necessary to.

  For example, a semiconductor chip on which a power semiconductor element is formed generally has a cell region where the power semiconductor element is formed and a peripheral region surrounding the outside of the cell region. Here, focusing on the avalanche breakdown voltage, it is desirable that the source-drain breakdown voltage in the peripheral region is higher than the source-drain breakdown voltage in the cell region from the viewpoint of preventing the power semiconductor element from being destroyed. This is because when an avalanche breakdown phenomenon occurs in the peripheral region, avalanche current concentrates locally (for example, the outer peripheral portion of the cell region), and the power semiconductor device exceeds the avalanche resistance more than the case where the avalanche breakdown phenomenon occurs in the cell region. Destruction of the

  However, in the current device structure, the breakdown voltage between the source and drain in the peripheral region is lower than the breakdown voltage between the source and drain in the cell region, and an avalanche breakdown phenomenon occurs in the peripheral region. Or, even with the same source-drain breakdown voltage, there is no source-side contact in the peripheral region where current generated by avalanche breakdown flows, so avalanche current is generated at the source-side contact in the outer peripheral part of the cell region where holes flow. It is concentrated where the destruction of the power semiconductor components occurs. Therefore, in the power semiconductor device, in order to effectively prevent the destruction of the power semiconductor device due to the avalanche breakdown phenomenon and to improve the reliability of the semiconductor device including the power semiconductor device, the source / drain in the peripheral region is A device to lower the source-drain breakdown voltage in the cell region rather than the inter-breakdown voltage (in the case where reverse bias is applied between the source and drain, a device to cause an avalanche breakdown in the cell region first) is required.

(Basic thought in the present embodiment)
For example, in a pn junction device represented by a power MOSFET, an IGBT or a diode, the breakdown voltage of the device is determined by the breakdown voltage of the pn junction.

  Here, the breakdown voltage of the pn junction means an avalanche breakdown voltage at which an avalanche breakdown phenomenon occurs. For example, the withstand voltage of the pn junction in the power MOSFET is defined as a voltage at which an avalanche breakdown phenomenon occurs when a voltage is applied to the drain region with the gate electrode and the source region grounded.

  Specifically, the avalanche breakdown voltage is a voltage at which an avalanche breakdown phenomenon occurs when a reverse voltage (a voltage applied in a direction to increase the potential barrier formed in the junction) is applied to the pn junction. The yield phenomenon is a phenomenon that occurs under the following mechanism. That is, when a reverse voltage is applied to the pn junction, electrons and holes accelerated by a high electric field collide with the crystal lattice in the depletion layer formed in the pn junction. At that time, the covalent bond connecting the crystal lattices is broken, and a new pair of electrons and holes is generated (impact ionization). The newly generated electron-hole pair also obtains energy under a high electric field, collides with the crystal lattice, and generates a new electron-hole pair. This multiplication phenomenon grows and a large current flows through the depletion layer. This phenomenon is an avalanche breakdown phenomenon.

  The breakdown voltage of such a pn junction is approximated by, for example, (Equation 1) shown below.

V _B ⁶⁰⁶⁰ × (Eg / 1.1) ^3/2 × (N _B / 10 ¹⁶ ) ^−3/4 (Equation 1)
Here, V _B indicates the breakdown voltage of the pn junction, E g indicates a band gap, and N _B indicates a background concentration (lower impurity concentration in the pn junction). (Equation 1) shows that the breakdown voltage of the pn junction is proportional to the 3/2 power of the band gap and inversely proportional to the 3/4 power of the background concentration.

  Therefore, in the present embodiment, attention is paid to the background concentration given to the breakdown voltage of the pn junction. And, as is clear from (Expression 1), the lower the background concentration, the higher the breakdown voltage of the pn junction. In other words, the higher the background concentration, the lower the breakdown voltage of the pn junction. From this, in order to improve the breakdown voltage of the pn junction, it is sufficient to lower the background concentration.

  As described above, from the viewpoint of improving the reliability of the power semiconductor element, it is desirable that the avalanche breakdown phenomenon occurs not in the peripheral region but in the cell region. That is, from the viewpoint of preventing the breakdown of the power semiconductor device based on the avalanche breakdown phenomenon, it is desirable to lower the breakdown voltage between the source and drain in the cell region than the breakdown voltage between the source and drain in the peripheral region.

  Therefore, in this embodiment, in order to make the source-drain breakdown voltage in the cell region lower than the source-drain breakdown voltage in the peripheral region, the relationship between the breakdown voltage of the pn junction shown in (Equation 1) and the background concentration. And set the background concentration of the cell region higher than the background concentration of the peripheral region. As a result, the avalanche breakdown voltage in the cell region becomes lower than the avalanche breakdown voltage in the peripheral region, so that the avalanche breakdown phenomenon occurs in the cell region before the avalanche breakdown phenomenon occurs in the peripheral region. That is, according to the basic idea in the present embodiment, the avalanche breakdown phenomenon can be generated in the cell region, so that the destruction of the power semiconductor element caused by the avalanche breakdown phenomenon can be effectively prevented. The reliability of the semiconductor device including the power semiconductor element can be improved.

  In the present embodiment, a device is embodied to embody the above-mentioned basic idea.

Embodiment 1
<Configuration of semiconductor device>
In the first embodiment, a power MOSFET will be described as an example of a power semiconductor element. FIG. 1 is a view schematically showing a planar configuration of a semiconductor chip which is a component of the semiconductor device (power MOSFET) according to the first embodiment.

  As shown in FIG. 1, the semiconductor chip CHP according to the first embodiment has, for example, a rectangular shape, and has a cell region CR, a transition region TR, and a peripheral region PER. Then, the transition region TR is disposed so as to surround the outside of the cell region CR, and the peripheral region PER is further disposed so as to surround the transition region TR. In other words, the cell region CR is disposed in the inner region surrounded by the peripheral region PER via the transition region TR.

  In the cell region CR, for example, a plurality of power MOSFETs functioning as switching elements are formed. On the other hand, in the peripheral region PER, for example, a peripheral structure represented by a bevel structure, a diffused ring structure, a field ring structure, or a field plate structure in which the periphery is etched obliquely is formed. These peripheral structures are basically formed based on a design concept that makes it difficult for an avalanche breakdown phenomenon to occur due to electric field concentration.

  As described above, in the semiconductor chip CHP according to the first embodiment, the plurality of power MOSFETs are formed in the inner region including the central region, and the peripheral structure that is the electric field relaxation structure is formed in the outer region surrounding the inner region. There is.

  2 is a cross-sectional view taken along line AA in FIG. As shown in FIG. 2, in the semiconductor chip CHP, a cell region CR, a transition region TR, and a peripheral region PER are formed. The respective structures of the cell region CR, the transition region TR, and the peripheral region PER so that the breakdown voltage of the pn junction in the cell region CR> the withstand voltage of the pn junction in the transition region TR> the breakdown voltage of the pn junction in the peripheral region PER. Is designed. The structures of cell region CR, transition region TR and peripheral region PER will be described below.

(1) Structure of Cell Region CR As shown in FIG. 2, in the cell region CR, a plurality of first p-type column regions PC1 and a plurality of n-type column regions NC are formed on the epitaxial layer EPI on the main surface of the semiconductor substrate 1S. Are so-called super junction structures alternately arranged in the x direction. In the cell region CR according to the first embodiment, the width (dimension in the x direction), depth (dimension in the z direction) and depth (dimension in the y direction) of the first p-type column region PC1 and the width (dimension in the y direction) The dimension in the x direction), the depth (the dimension in the z direction) and the depth (the dimension in the y direction) are designed to be the same. Therefore, the first embodiment exemplifies a case where the ratio of the width of the first p-type column region PC1 of the cell region CR to the width of the n-type column region NC is 1: 1.

The details will be described below. For example, an epitaxial layer EPI is formed on the main surface of a semiconductor substrate 1S made of silicon containing an n-type impurity such as phosphorus (P) or arsenic (As). The epitaxial layer EPI is formed of, for example, a semiconductor layer whose main component is silicon in which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced. The n-type impurity concentration (Nep) of the epitaxial layer EPI is lower than the impurity concentration of the semiconductor substrate 1S, and is 2.4 × 10 ¹⁵ / cm ³ , for example.

In the epitaxial layer EPI, a plurality of n-type column regions NC are formed to be separated from each other in the x direction. Each of the n-type column regions NC has, for example, a columnar shape, and is formed of a semiconductor region into which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced. The n-type impurity concentration (Nn) of the n-type column region NC is higher than the n-type impurity concentration (Nep) of the epitaxial layer EPI, and is 3.0 × 10 ¹⁵ / cm ³ , for example. The plurality of n-type column regions NC and the semiconductor substrate 1S constitute the drain region of the power MOSFET.

Furthermore, a first p-type column region PC1 is formed in a partial region of the epitaxial layer EPI sandwiched between the n-type column regions NC adjacent to each other. Each of the first p-type column regions PC1 has a columnar shape, for example, and includes a semiconductor region into which a p-type impurity such as boron (B) is introduced. The p-type impurity concentration (Np1) of the first p-type column region PC1 is, for example, 3.0 × 10 ¹⁵ / cm ³ .

  The element portion is formed on the top surface of the epitaxial layer EPI in which the super junction structure is formed.

  In the element portion, a channel region CH in contact with the first p-type column region PC1 is formed on the upper surface of the epitaxial layer EPI, and a source region SR is formed to be included in the channel region CH. At this time, the channel region CH is constituted by a semiconductor region into which a p-type impurity such as boron (B) is introduced, and the source region SR is introduced with an n-type impurity such as phosphorus (P) or arsenic (As). The semiconductor region is composed of In addition, a body contact region BC reaching the channel region CH from the upper surface of the epitaxial layer EPI is formed in the central portion of the source region SR. Body contact region BC is formed of, for example, a semiconductor region into which a p-type impurity such as boron (B) is introduced, and the impurity concentration of body contact region BC is higher than the impurity concentration of channel region CH. .

  Further, the gate insulating film GOX is formed on the region sandwiched by the channel regions CH adjacent to each other, and the gate electrode GE is formed on the gate insulating film GOX. The gate insulating film GOX is formed of, for example, a silicon oxide film, but is not limited thereto, and may be formed of, for example, a high dielectric constant film having a dielectric constant higher than that of the silicon oxide film. Further, the gate electrode GE is formed of, for example, a polycrystalline silicon film. The gate electrode GE is formed to match the source region SR. Further, an interlayer insulating film IL made of, for example, a silicon oxide film is formed so as to cover the upper surface of the gate electrode GE and the side walls on both sides.

  Over the interlayer insulating film IL covering the plurality of gate electrodes GE, a source electrode SE made of, for example, a barrier conductor film made of a titanium tungsten film and an aluminum film is formed. As a result, the source electrode SE is electrically connected to the source region SR and is also electrically connected to the channel region CH via the body contact region BC.

  At this time, the body contact region BC has a function to ensure ohmic contact with the source electrode SE, and the presence of the body contact region BC makes the source region SR and the channel region CH have the same electric potential electrically. It will be connected.

  Therefore, it is possible to suppress the on operation of a parasitic npn bipolar transistor in which the source region SR is an emitter region, the channel region CH is a base region, and the n-type column region NC is a collector region. That is, that the source region SR and the channel region CH are electrically connected at the same potential means that there is no potential difference between the emitter region and the base region of the parasitic npn bipolar transistor. The on-operation of the parasitic npn bipolar transistor can be suppressed.

  A surface protection film PAS made of, for example, a silicon oxide film is formed to partially cover the source electrode SE, and a partial region of the source electrode SE is exposed from the surface protection film PAS. Further, a drain electrode DE made of a metal film is formed on the back surface of the semiconductor substrate 1S (the surface opposite to the main surface on which the epitaxial layer EPI is formed).

  As described above, a plurality of power MOSFETs are formed in the cell region CR.

(2) Structure of Transition Region TR As shown in FIG. 2, in the transition region TR, a plurality of second p-type column regions PC2 and a plurality of n-type column regions made of an epitaxial layer EPI are alternately arranged in the x direction. Also, it has a so-called super junction structure. In the transition region TR according to the first embodiment, the width (dimension in the x direction) of the second p-type column region PC2 is different from the width (dimension in the x direction) of the n-type column region formed of the epitaxial layer EPI. However, the depth (dimension in the z direction) and depth (dimension in the y direction) of the second p-type column region PC2 and the depth (dimension in the z direction) and depth (y direction) of the n-type column region composed of the epitaxial layer EPI. Are designed to be the same as each other.

The details will be described below. In the transition region TR as well as the cell region CR, the epitaxial layer EPI is formed on the main surface of the semiconductor substrate 1S. A plurality of second p-type column regions PC2 are formed to be separated from each other in the x direction in the epitaxial layer EPI. Each of the second p-type column regions PC2 has a columnar shape, for example, and includes a semiconductor region into which a p-type impurity such as boron (B) is introduced. The p-type impurity concentration (Np2) of the second p-type column region PC2 is, for example, 3.0 × 10 ¹⁵ / cm ³ . Then, a partial region of the epitaxial layer EPI sandwiched between the second p-type column regions PC2 adjacent to each other becomes an n-type column region.

  Further, the gate lead-out portion GPU formed of a polycrystalline silicon film in the same layer as the gate electrode GE formed in the cell region CR is formed on the channel region CH formed in the epitaxial layer EPI via the gate insulating film GOX. It is done. Then, an interlayer insulating film IL is formed to cover the upper surface and both side walls of the gate lead-out portion GPU, and an opening which exposes a portion of the upper surface of the gate lead-out portion GPU in a portion of the interlayer insulating film IL. Is formed.

  A gate lead electrode GPE made of a barrier conductor film made of, for example, a titanium tungsten film and an aluminum film is formed on the interlayer insulating film IL including the inside of the opening. Here, the gate lead-out part GPU is electrically connected to the plurality of gate electrodes GE, and the gate voltage applied to the gate lead-out electrode GPE is different from each of the plurality of gate electrodes GE through the gate lead-out part GPU. Applied to the

  Furthermore, on the top surface of the epitaxial layer EPI, a channel region CH extending from the cell region CR is formed, and a source lead region SPR is formed so as to be included inside the channel region CH. An interlayer insulating film IL is formed on the upper surface of the epitaxial layer EPI so as to cover the channel region CH, and an opening is formed in the interlayer insulating film IL to expose the source lead region SPR. . Then, the opening is buried, and over the interlayer insulating film IL, a source lead electrode SPE made of, for example, a barrier conductor film made of a titanium tungsten film and an aluminum film is formed.

  Also in the transition region TR, a surface protection film PAS made of, for example, a silicon oxide film is formed to partially cover the gate extraction electrode GPE and the source extraction electrode SPE, and a partial region of the gate extraction electrode GPE and the source extraction A partial region of the electrode SPE is exposed from the surface protective film PAS.

  As described above, the transition structure is formed in the transition region TR.

(3) Structure of Peripheral Region PER As shown in FIG. 2, in the peripheral region PER, a plurality of third p-type column regions PC3 and n-type column regions composed of a plurality of epitaxial layers EPI are alternately arranged in the x direction. Also, it has a so-called super junction structure. In the peripheral region PER according to the first embodiment, an n-type column including the width (dimension in the x direction), depth (dimension in the z direction) and depth (dimension in the y direction) of the third p-type column region PC3 and the epitaxial layer EPI. The width (dimension in the x direction), the depth (dimension in the z direction), and the depth (dimension in the y direction) of the region are designed to be the same. Therefore, Embodiment 1 exemplifies a case where the ratio of the width of the third p-type column region PC3 in the peripheral region PER to the width of the n-type column region formed of the epitaxial layer EPI is 1: 1.

The details will be described below. Similar to the cell region CR, the epitaxial layer EPI is formed on the main surface of the semiconductor substrate 1S also in the peripheral region PER. A plurality of third p-type column regions PC3 are formed to be separated from each other in the x direction in the epitaxial layer EPI. Each of the third p-type column regions PC3 has a columnar shape, for example, and includes a semiconductor region into which a p-type impurity such as boron (B) is introduced. The p-type impurity concentration (Np3) of the third p-type column region PC3 is lower than the p-type impurity concentration (Np2) of the second p-type column region PC2 of the transition region TR, and is 2.4 × 10 ¹⁵ / cm ³ , for example. Then, a partial region of the epitaxial layer EPI sandwiched by the third p-type column regions PC3 adjacent to each other becomes an n-type column region.

  Further, on the upper surface of the epitaxial layer EPI, a plurality of electrodes (dummy electrodes) FFP made of a polycrystalline silicon film of the same layer as the gate electrode GE formed in the cell region CR are formed. An interlayer insulating film IL is formed on the upper surface of the epitaxial layer EPI so as to cover the upper surfaces and sidewalls of both sides of the plurality of electrodes (dummy electrodes) FFP.

  Also in the peripheral region PER, a surface protective film PAS made of, for example, a silicon oxide film is formed.

  As described above, the peripheral structure is formed in the peripheral region PER.

<Advantages of super junction structure>
As described above, the power MOSFET according to the first embodiment has a super junction structure. According to such a power MOSFET having a super junction structure, the following advantages can be obtained.

  That is, in a normal power MOSFET, the withstand voltage is ensured by reducing the impurity concentration of the epitaxial layer EPI and extending the depletion layer formed in the epitaxial layer EPI when the power MOSFET is in the off state. Therefore, in order to realize a high breakdown voltage, it is necessary to increase the thickness of the low impurity concentration epitaxial layer EPI. On the other hand, if the thickness of the low impurity concentration epitaxial layer is increased, the on-resistance of the power MOSFET is increased. That is, in the power MOSFET, there is a trade-off between improvement in breakdown voltage and reduction in on-resistance.

  In this regard, in the power MOSFET having the super junction structure according to the first embodiment, the super junction structure including the periodic first p-type column region PC1 and the n-type column region NC is formed in the epitaxial layer EPI. In the power MOSFET of the super junction structure, in the off state, a depletion layer extends in the lateral direction also from the pn junction formed in the boundary region between the first p-type column region PC1 and the n-type column region NC. For this reason, in the power MOSFET having the super junction structure, even if the impurity concentration of the n-type column region NC which is a current path is increased, a depletion layer extending in the inner direction of the n-type column region NC sandwiched between the two boundary regions is connected. Thus, the entire n-type column region NC is easily depleted. As a result, the entire n-type column region NC is depleted in the off state, so that the withstand voltage can be secured. That is, in the power MOSFET of the super junction structure, the entire n-type column region NC can be depleted while the impurity concentration of the n-type column region NC which is a current passage is increased. As a result, in the power MOSFET of the super junction structure, there is obtained an advantage that the on resistance can be reduced while securing a high breakdown voltage.

<Features and Effects of Embodiment 1>
(1) Withstand voltage of pn junction In the semiconductor device according to the first embodiment, the n-type impurity concentration (Nn) of n-type column region NC of cell region CR is higher than the n-type impurity concentration (Nep) of epitaxial layer EPI of peripheral region PER. Is also high. That is, in the first embodiment, the n-type impurity concentration (Nn) in the n-type column region NC of the cell region CR is 3.0 × 10 ¹⁵ / cm ³ , and the n-type impurity concentration in the epitaxial layer EPI of the peripheral region PER (Nep ) Is 2.4 × 10 ¹⁵ / cm ³ . Thereby, the background concentration of the pn junction in the cell region CR (the junction between the first p-type column region PC1 and the n-type column region NC) is the pn junction in the peripheral region PER (the third p-type column region PC3 and the epitaxial layer Higher than the background concentration of the junction with EPI). Accordingly, considering the above-described (Equation 1) indicating the relationship between the avalanche breakdown voltage (pn junction breakdown voltage) and the band gap, the avalanche breakdown voltage in the cell region CR is lower than the avalanche breakdown voltage in the peripheral region PER.

  Therefore, for example, when a voltage higher than the power supply voltage is applied to the power MOSFET due to the influence of the inductance included in the load, the avalanche breakdown phenomenon occurs in the cell region CR without causing the avalanche breakdown phenomenon in the peripheral region PER. Can. That is, according to the power MOSFET of the first embodiment, the avalanche breakdown phenomenon can be generated in the cell region CR where the avalanche current is less likely to be concentrated locally than in the peripheral region PER. That is, before the avalanche breakdown phenomenon occurs in the peripheral region PER which easily exceeds the avalanche resistance of the power MOSFET, the avalanche breakdown phenomenon can be generated in the cell region CR which is less likely to exceed the avalanche resistance of the power MOSFET than the peripheral region PER. This is due to a difference in structure between a cell region where source side contacts through which an avalanche current flows exist at a high density and a peripheral region where source side contacts do not exist. As a result, even when a voltage exceeding the power supply voltage is applied to the power MOSFET and an avalanche breakdown phenomenon occurs, a situation that leads to the destruction of the power MOSFET can be avoided. Thereby, according to the first embodiment, the reliability of the semiconductor device including the power MOSFET can be improved.

  FIG. 3A is a graph showing the charge balance of the breakdown voltage (BVdss) of the pn junction in the semiconductor device according to the first embodiment. Here, the charge balance of the cell region and the peripheral region is shown.

  In the first embodiment, the n-type impurity concentration (Nn) of n-type column region NC of cell region CR is set higher than the n-type impurity concentration (Nep) of the n-type column region formed of epitaxial layer EPI of peripheral region PER. There is. As a result, as shown in FIG. 3A, the breakdown voltage (BVdss) of the pn junction in the cell region CR is lower than the breakdown voltage (BVdss) of the pn junction in the peripheral region PER.

  Further, the degree of decrease in the breakdown voltage (BVdss) of the pn junction in the cell region CR (curvature of the charge balance curve) is smaller than the degree of decrease in the breakdown voltage (BVdss) of the pn junction in the peripheral region PER. As a result, the charge balance of the cell region CR and the charge balance of the peripheral region PER do not overlap. Therefore, when considered with one semiconductor chip CHP, the breakdown voltage of the semiconductor chip CHP is determined by the charge balance of the cell region CR.

(2) Charge balance in each region In the super junction structure, when the charge balance between the total charge amount of the p-type column region constituting the pn junction and the total charge amount of the n-type column region is broken, the breakdown voltage of the pn junction is rapid. To drop. Therefore, it is desirable to set the total charge amount of the p-type column region and the total charge amount of the n-type column region in the cell region CR, the transition region TR, and the peripheral region PER, respectively.

  However, in consideration of the process margin at the time of manufacturing the semiconductor device, it is actually difficult to make the total charge amount of the p-type column region completely the same as the total charge amount of the n-type column region. Therefore, in general, in the super junction structure, the total charge amount (Qp) in the p-type column region and the total charge amount (Qn) in the n-type column region are the same (Qp = Qn), or the total charge amount in the p-type column region The p-type column region and the n-type column region are formed so that (Qp) is larger than the total charge amount (Qn) of the n-type column region (Qp> Qn). Furthermore, since it is actually difficult to make the total charge amount (Qp) of the p-type column region and the total charge amount (Qn) of the n-type column region exactly the same (Qp = Qn), the p-type column region The total charge amount (Qp) of the n-type column region and the total charge amount (Qn) of the n-type column region are substantially the same (Qp≈Qn). The total charge amount (Qp) of the p-type column region indicated by “Qp≈Qn” and the total charge amount (Qn) of the n-type column region are substantially the same. The difference between Qp) and the total charge amount (Qn) of the n-type column region is within ± 10% of the total charge amount (Qp) of the p-type column region.

  Therefore, in the first embodiment, in the cell region CR, the total charge amount (CQp) of the first p-type column region PC1 is substantially the same as the total charge amount (CQn) of the n-type column region NC (CQp≈CQn). Alternatively, each total charge amount is set so as to be larger than the total charge amount (CQn) of the n-type column region NC (CQp> CQn). Further, in the transition region TR, the total charge amount (TQp) of the second p-type column region PC2 is substantially the same as the total charge amount (TQn) of the n-type column region consisting of the epitaxial layer EPI (TQp ≒ TQn) or epitaxial Each total charge amount is set so as to be larger than the total charge amount (TQn) of the n-type column region formed of the layer EPI (TQp> TQn). Further, in the peripheral region PER, the total charge amount (PEQp) of the third p-type column region PC3 is substantially the same as the total charge amount (PEQn) of the n-type column region consisting of the epitaxial layer EPI (PEQp ≒ PEQn) or epitaxial Each total charge amount is set so as to be larger than the total charge amount (PEQn) of the n-type column region formed of the layer EPI (PEQp> PEQn).

  Thereby, ideal charge balance can be achieved in each of the cell region CR, the transition region TR, and the peripheral region PER.

Furthermore, in the first embodiment, the total charge amount (CQp) of the first p-type column region PC1 of the cell region CR and the total charge amount (CQn) of the n-type column region NC are respectively the second p-type column region PC2 of the transition region TR. Each total charge amount is set to be larger than the total charge amount (TQp) of the n-type column region including the epitaxial layer EPI and the total charge amount (TQn) of the n-type column region. Further, the total charge amount (TQp) of the second p-type column region PC2 in the transition region TR and the total charge amount (TQn) of the n-type column region formed of the epitaxial layer EPI are the total of the third p-type column region PC3 in the peripheral region PER, respectively. Each total charge amount is set to be larger than the charge amount (PEQp) and the total charge amount (PEQn) of the n-type column region formed of the epitaxial layer EPI. That is, in the cell region CR, the transition region TR, and the peripheral region PER, while maintaining the charge balance,
CQp>TQp> PEQp, CQn>TQn> PEQn (Equation 2)
Each total charge amount is set in the cell region CR, the transition region TR, and the peripheral region PER so that

  In the first embodiment, as described with reference to FIG. 3A, when considering one semiconductor chip CHP, the withstand voltage of the semiconductor chip CHP is determined by the charge balance of the cell region CR. Accordingly, in the cell region CR, the total charge amount (CQp) of the first p-type column region PC1 is the same as the total charge amount (CQn) of the n-type column region NC (CQp = CQn) or the total charge of the n-type column region NC. The process conditions are set so that a breakdown voltage of the pn junction that is larger than the quantity (CQn) (CQp> CQn) and equal to or higher than the target value is obtained.

  Here, if the relationship of (Equation 2) is satisfied, the total charge in the transition region TR in the ideal total charge amount region ((CQp = CQn) and (CQp> CQn) region) of the cell region CR. The quantities are in the states of (TQp = TQn) and (TQp> TQn), and the breakdown voltage of the pn junction in the cell region CR is always lower than the breakdown voltage of the pn junction in the transition region TR. Further, in the region of the ideal total charge amount of the cell region CR (the region of (CQp = CQn) and (CQp> CQn)), the total charge amount is also (PEQp = PEQn) and (PEQp> PEQn) in the peripheral region PER. The breakdown voltage of the pn junction of the cell region CR is always lower than the breakdown voltage of the pn junction of the peripheral region PER.

  That is, if the relationship of (Equation 2) is satisfied, the total charge amount determined by the charge balance of the cell region CR is in the range of (CQp = CQn) and (CQp> CQn) and at the pn junction of the target value or more. The ideal charge balance of the transition region TR and the ideal charge balance of the peripheral region PER can be included in the region where the breakdown voltage is obtained (region of A1 shown in FIG. 3A). That is, in this region (region of A1 shown in FIG. 3A), the total charge amount is in the state of (TQp = TQn) and (TQp> TQn) in the transition region TR, and in the peripheral region PER. The total charge amount is in the state of (PEQp = PEQn) and (PEQp> PEQn), and the breakdown voltage of the pn junction in the cell region CR can always be lower than the breakdown voltage of the pn junction in the transition region TR and the peripheral region PER. .

  FIG. 3B shows the peak of the breakdown voltage (BVdss) of the pn junction in the charge balance of the cell region examined by the present inventors as a comparative example and the peak of the breakdown voltage (BVdss) of the pn junction in the charge balance of the peripheral region. It is a graph which shows charge balance of the proof pressure (BVdss) of pn junction of the semiconductor device at the time of having shifted.

  The breakdown voltage (BVdss) of the pn junction of the cell region CR is also obtained by shifting the breakdown voltage (BVdss) of the pn junction of the charge balance of the cell region CR and the breakdown voltage (BVdss) of the pn junction of the charge balance of the peripheral region PER. The breakdown voltage (BVdss) of the pn junction in the peripheral region PER can be made lower. However, a range (PEQn> PEQp) in which the total charge amount (PEQn) of the n-type column region is larger than the total charge amount (PEQp) of the third p-type column region PC3 in the peripheral region PER (PEQn> PEQp, shown by A3 in FIG. Area) can not be used. Therefore, the process margin at the time of manufacturing the semiconductor device according to the comparative example (region indicated by A2 in FIG. 3B) is the process margin at the time of manufacturing the semiconductor device according to the first embodiment (indicated by A1 in FIG. 3A). Smaller than the region).

  Therefore, the semiconductor device according to the first embodiment has an advantage that the process margin at the time of manufacture can be widened as compared with the semiconductor device according to the comparative example.

  Next, the structures of the p-type column region and the n-type column region in the cell region CR, the transition region TR, and the peripheral region PER will be described in detail.

(2-1) Cell Region In the cell region CR, as shown in FIG. 2, a plurality of first p-type column regions PC1 and a plurality of n-type column regions NC are formed on the epitaxial layer EPI on the main surface of the semiconductor substrate 1S. Are alternately formed. When the p-type impurity concentration of the first p-type column region PC1 is Np1, the width is CRWp, the depth is Dp, and the depth is Tp, the total charge amount (CQp) of the first p-type column region PC1 is
CQp = Np1 × {CRWp × Dp × Tp} (Formula 3)
Is represented by

Further, assuming that the n-type impurity concentration of the n-type column region NC is Nn, the width is CRWn, the depth is Dn, and the depth is Tn, the total charge amount (CQn) of the n-type column region NC is
CQn = Nn × {CRWn × Dn × Tn} (Equation 4)
Is represented by

The width CRWp, depth Dp, and depth Tp of the first p-type column region PC1 are the same as the width CRWn, depth Dn, and depth Tn of the n-type column region NC, respectively, and the p-type impurity concentration of the first p-type column region PC1 (Np1) and the n-type impurity concentration (Nn) of the n-type column region NC are the same. In the power MOSFET according to the first embodiment, the p-type impurity concentration (Np1) of the first p-type column region PC1 and the n-type impurity concentration (Nn) of the n-type column region NC are, for example, 3.0 × 10 ¹⁵ / cm ³ . is there.

  Accordingly, in the cell region CR, the total charge amount (CQp) of the first p-type column region PC1 and the total charge amount (CQn) of the n-type column region NC are the same (CQp = CQn), and charge balance can be achieved. .

(2-2) Transition Region In the transition region TR, as shown in FIG. 2, a plurality of second p-type column regions PC2 are formed apart from each other in the epitaxial layer EPI on the main surface of the semiconductor substrate 1S. . The n-type impurity concentration of the epitaxial layer EPI is lower than the n-type impurity concentration of the n-type column region NC of the cell region CR, for example, 2.4 × 10 ¹⁵ / cm ³ .

When the p-type impurity concentration of the second p-type column region PC2 is Np2, the width is TWp, the depth is Dp, and the depth is Tp, the total charge amount (TQp) of the second p-type column region PC2 is
TQp = Np2 × {TWp × Dp × Tp} (Formula 5)
Is represented by Here, the p-type impurity concentration (Np2) of the second p-type column region PC2 of the transition region TR and the p-type impurity concentration (Np1) of the first p-type column region PC1 of the cell region CR are the same (Np2 = Np1) , And the width (TWp) of the second p-type column region PC2 is smaller than the width (CRWp) of the first p-type column region PC1 of the cell region CR (TWp <CRWp). Thus, the total charge amount (TQp) of the second p-type column region PC2 of the transition region TR is smaller than the total charge amount (CQp) of the first p-type column region PC1 of the cell region CR (TQp <CQp).

Further, when the n-type impurity concentration of the n-type column region made of the epitaxial layer EPI is Nep, the width is TWn, the depth is Dp, and the depth is Tp, the total charge amount (TQn) of the n-type column region made of the epitaxial layer EPI Is
TQn = Nep × {TWn × Dp × Tp} (6)
Is represented by Here, the n-type impurity concentration (Nep) of the epitaxial layer EPI of the transition region TR is lower than the n-type impurity concentration (Nn) of the n-type column region NC of the cell region CR (Nep <Nn). Thereby, even if the width (CRWn) of the n-type column region NC of the cell region CR and the width (TWn) of the n-type column region made of the epitaxial layer EPI of the transition region TR are the same, the epitaxial layer of the transition region TR The total charge amount (TQn) of the n-type column region made of EPI is smaller than the total charge amount (CQn) of the n-type column region NC of the cell region CR (TQn <CQn).

  Therefore, the total charge amount (TQp) of the second p-type column region PC2 of the transition region TR and the total charge amount (TQn) of the n-type column region formed of the epitaxial layer EPI are the total of the first p-type column region PC1 of the cell region CR. The charge amount (CQp) is smaller than the total charge amount (CQn) of the n-type column region NC (TQp <CQp, TQn <CQn). Further, by adjusting the width (TWp) and the pitch of the second p-type column region PC2, in the transition region TR, the total charge amount (TQp) of the second p-type column region PC2 and the n-type column region consisting of the epitaxial layer EPI. The total charge amount (TQn) is the same (TQp = TQn), and charge balance can be achieved.

  In the above description, the p-type impurity concentration of the second p-type column region PC2 of the transition region TR and the p-type impurity concentration of the first p-type column region PC1 of the cell region CR are the same, and the second p-type column of the transition region TR The width (TWp) of the region PC2 was made smaller than the width (CRWp) of the first type p-type column region PC1 of the cell region CR. As a result, the total charge amount (TQp) of the second p-type column region PC2 of the transition region TR is smaller than the total charge amount (CQp) of the first p-type column region PC1 of the cell region CR. However, it is not limited to this.

  For example, the width (TWp) of the second p-type column region PC2 in the transition region TR is the same as the width (CRWp) of the first p-type column region PC1 in the cell region CR, and the p-type of the second p-type column region PC2 in the transition region TR. The impurity concentration may be lower than the p-type impurity concentration of the first p-type column region PC1 of the cell region CR. Thereby, the total charge amount (TQp) of the second p-type column region PC2 in the transition region TR can be made smaller than the total charge amount (CQp) of the first p-type column region PC1 in the cell region CR.

(2-3) Peripheral Region In the peripheral region PER, as shown in FIG. 2, a plurality of third p-type column regions PC3 are formed apart from each other in the epitaxial layer EPI on the main surface of the semiconductor substrate 1S. . The n-type impurity concentration of the epitaxial layer EPI is lower than the n-type impurity concentration of the n-type column region NC of the cell region CR, for example, 2.4 × 10 ¹⁵ / cm ³ .

When the p-type impurity concentration of the third p-type column region PC3 is Np3, the width is PEWp, the depth is Dp, and the depth is Tp, the total charge amount (PEQp) of the third p-type column region PC3 is
PEQp = Np3 × {PEWp × Dp × Tp} (Expression 7)
Is represented by Here, the p-type impurity concentration (Np3) of the third p-type column region PC3 of the peripheral region PER is lower than the p-type impurity concentration (Np2) of the second p-type column region PC2 of the transition region TR (Np3 <Np2). Thereby, even if the width (TWn) of the n-type column region made of the epitaxial layer EPI in the transition region TR and the width (PEWn) of the n-type column region made of the epitaxial layer EPI in the peripheral region PER are the same, the peripheral region The total charge (PEQp) of the third p-type column region PC3 of PER is smaller than the total charge (TQp) of the second p-type column region PC2 of the transition region TR (PEQp <TQp).

Further, when the n-type impurity concentration of the n-type column region made of the epitaxial layer EPI is Nep, the width is PEWn, the depth is Dp, and the depth is Tp, the total charge amount (PEQn) of the n-type column region made of the epitaxial layer EPI Is
PEQn = Nep × {PEWn × Dp × Tp} (Equation 8)
Is represented by Here, the width (PEWn) of the n-type column region made of the epitaxial layer EPI in the peripheral region PER is made smaller than the width (TWn) of the n-type column region made of the epitaxial layer EPI in the transition region TR (PEWn <TWn). . Thereby, the total charge amount (PEQn) of the n-type column region made of the epitaxial layer EPI in the peripheral region PER is smaller than the total charge amount (TQn) of the n-type column region made of the epitaxial layer EPI in the transition region TR ( PEQn <TQn).

  Therefore, the total charge amount (PEQp) of the third p-type column region PC3 in the peripheral region PER and the total charge amount (PEQn) of the n-type column region formed of the epitaxial layer EPI are the total of the second p-type column region PC2 in the transition region TR. The charge amount (TQp) and the total charge amount (TQn) of the n-type column region formed of the epitaxial layer EPI are respectively smaller (PEQp <TQp, PEQn <TQn). Further, by adjusting the p-type impurity concentration (Np3), width (PEWp), and pitch of the third p-type column region PC3, the total charge amount (PEQp) of the third p-type column region PC3 and the epitaxial layer are adjusted in the peripheral region PER. The total charge amount (PEQn) of the n-type column region made of EPI is the same (PEQn = PEQp), and charge balance can be achieved.

  In the above description, the p-type impurity concentration (Np3) of the third p-type column region PC3 of the peripheral region PER is changed to the p-type impurity concentration (Np1) of the first p-type column region PC1 of the cell region CR and the second p of the transition region TR. The concentration is lower than the p-type impurity concentration (Np2) of the E-type column region PC2. Thereby, the total charge amount (PEQp) of the third p-type column region PC3 in the peripheral region PER is compared with the total charge amount (CQp) of the first p-type column region PC1 in the cell region CR and the second type column region PC2 in the transition region TR. Less than the total charge (TQp) of However, it is not limited to this.

  For example, the p-type impurity concentration (Np3) of the third p-type column region PC3 in the peripheral region PER is the same as the p-type impurity concentration (Np2) of the second p-type column region PC2 in the transition region TR, and the third p-type of the peripheral region PER. The width (PEWp) and pitch of the column region PC3 may be smaller than the width (TWp) and pitch of the second p-type column region PC2 of the transition region TR. Thus, the total charge amount (PEQp) of the third p-type column region PC3 in the peripheral region PER is changed to the total charge amount (CQp) of the first p-type column region PC1 in the cell region CR and the second p-type column region PC2 in the transition region TR. Can be smaller than the total charge amount (TQp) of

(3) Summary of Features and Effects In the semiconductor device according to the first embodiment, the n-type impurity concentration (Nn) of the n-type column region NC of the cell region CR is the n-type column region formed of the epitaxial layer EPI of the peripheral region PER. It is characterized in that the concentration is higher than the n-type impurity concentration (Nep) and that charge balance is taken in each of the cell region CR, the transition region TR and the peripheral region PER. Furthermore, as shown in the above (formula 2), the total charge amount (CQp, CQn) of the cell region CR becomes larger than the total charge amount (TQp, TQn) of the transition region TR, and the total charge amount of the transition region TR Each total charge amount is set such that (TQp, TQn) is larger than the total charge amount (PEQp, PEQn) of the peripheral region PER.

  By setting the n-type impurity concentration (Nn) of the n-type column region NC of the cell region CR higher than the n-type impurity concentration (Nep) of the n-type column region formed of the epitaxial layer EPI of the peripheral region PER, Since the breakdown voltage of the pn junction is lower than the breakdown voltage of the pn junction in the peripheral region PER, an avalanche breakdown phenomenon can be caused in the cell region CR. Therefore, before the avalanche breakdown phenomenon occurs in the peripheral region PER which easily exceeds the avalanche resistance of the power MOSFET, the avalanche breakdown phenomenon can be generated in the cell region CR which does not easily exceed the avalanche resistance of the power MOSFET. As a result, even when a voltage exceeding the power supply voltage is applied to the power MOSFET and an avalanche breakdown phenomenon occurs, a situation that leads to the destruction of the power MOSFET can be avoided.

  Further, the cell region CR, the transition region TR, and the peripheral region PER are respectively charge-balanced so that the total charge amount (CQp, CQn) of the cell region CR is larger than the total charge amount (TQp, TQn) of the transition region TR. Further, the total charge amount (TQp, TQn) of the transition region TR is set larger than the total charge amount (PEQp, PEQn) of the peripheral region PER. Thus, in the cell region CR, a region where the breakdown voltage of the pn junction with the total charge amount in the range of (CQp = CQn) and (CQp> CQn) and above the target value can be obtained is a process margin when manufacturing the semiconductor device. It can be done. In this region, the total charge amount is (TQp = TQn) and (TQp> TQn) in the transition region TR, and the total charge amount is also (PEQp = PEQn) and (PEQp> PEQn in the peripheral region PER. And the breakdown voltage of the pn junction in the cell region CR can always be lower than the breakdown voltage of the pn junction in the transition region TR and the peripheral region PER.

  Further, the on-resistance of the power MOSFET can be reduced by increasing the n-type impurity concentration (Nn) of the n-type column region NC of the cell region CR.

  From the above, it is possible to improve the reliability of the semiconductor device including the power MOSFET of the super junction structure according to the first embodiment.

<Method for Manufacturing Semiconductor Device>
An example of a method of manufacturing the semiconductor device (power MOSFET) according to the first embodiment will be described with reference to FIGS. 4 to 18 are cross sectional views showing manufacturing steps of the semiconductor device according to the first embodiment. In the first embodiment, a manufacturing method called a so-called "multi-epitaxial method" will be described in which two-stage epitaxial layers are formed. In addition, a semiconductor device in which the breakdown voltage of the pn junction in the cell region is 600 V to 650 V and the breakdown voltage of the pn junction in the peripheral region is 650 V to 730 V is exemplified. That is, a semiconductor device in which the breakdown voltage of the pn junction in the peripheral region is about 50 V to 80 V higher than the breakdown voltage of the pn junction in the cell region is exemplified. Further, the depths and the depths of the column regions respectively formed in the cell region, the transition region and the peripheral region are the same.

First, as shown in FIG. 4, a semiconductor substrate 1S is prepared in which a first epitaxial layer EPI1 composed of an n-type semiconductor layer is formed on the main surface (surface, upper surface). For example, the semiconductor substrate 1S is formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into single crystal silicon. The n-type impurity concentration of the epitaxial layer EPI1 is, for example, about 2.4 × 10 ¹⁵ / cm ³ , and the thickness of the epitaxial layer EPI1 is, for example, about 22 μm to 25 μm.

  Next, as shown in FIG. 5, a resist film FR1 patterned on the epitaxial layer EPI1 is formed. Resist film FR1 is formed to expose the n-type column formation region of cell region CR and to cover the upper surface of epitaxial layer EPI1 in the other regions including transition region TR and peripheral region PER.

  Then, a plurality of n-type impurities such as phosphorus (P) or arsenic (As) are introduced into the epitaxial layer EPI1 of the cell region CR by ion implantation using the patterned resist film FR1 as a mask. The n-type column regions NC are formed so as to be separated from each other.

Each of the plurality of n-type column regions NC is formed in a substantially columnar shape extending from the lower surface to the upper surface of the epitaxial layer EPI1 by, for example, performing ion implantation with different implantation energy a plurality of times. The n-type impurity concentration in the n-type column region NC is, for example, about 3.0 × 10 ¹⁵ / cm ³ .

  Next, as shown in FIG. 6, after removing the resist film FR1, a patterned resist film FR2 is formed on the epitaxial layer EPI1. Resist film FR2 is formed to expose the first p-type column formation region of cell region CR and the second p-type column formation region of transition region TR, and to cover the upper surface of epitaxial layer EPI1 in other regions including peripheral region PER. Ru.

  Then, a p-type impurity such as boron (B) is introduced into the cell region CR and the epitaxial layer EPI1 in the transition region TR by an ion implantation method using the patterned resist film FR2 as a mask. Then, the plurality of first p-type column regions PC1 are formed so as to be separated from each other, and in the transition region TR, the plurality of second p-type column regions PC2 are formed so as to be separated from each other. In the transition region TR, a partial region of the epitaxial layer EPI1 sandwiched between the second p-type column regions PC2 adjacent to each other becomes an n-type column region.

  Each of the plurality of first p-type column regions PC1 of the cell region CR and the plurality of second p-type column regions PC2 of the transition region TR is, for example, the lower surface of the epitaxial layer EPI1 by performing ion implantation with different implantation energy multiple times. It is formed in a substantially columnar shape ranging from the upper surface to the upper surface.

The p-type impurity concentration, width, and pitch of the first p-type column region PC1 of the cell region CR are set so as to achieve charge balance in the cell region CR. In the semiconductor device according to the first embodiment, a case where the ratio of the width of the first p-type column region PC1 of the cell region CR to the width of the n-type column region NC is 1: 1 is illustrated. In this case, the p of the first p-type column region PC1 is set such that the total charge amount (CQp) of the first p-type column region PC1 and the total charge amount (CQn) of the n-type column region NC are the same (CQp = CQn). Type impurity concentration is set. Therefore, the p-type impurity concentration of the first p-type column region PC1 is the same as the n-type impurity concentration of the n-type column region NC, for example, about 3.0 × 10 ¹⁵ / cm ³ .

  Similarly, the p-type impurity concentration, width, and pitch of the second p-type column region PC2 in the transition region TR are set so that charge balance is achieved in the transition region TR. Furthermore, it is necessary to set the total charge amount (TQp) of the second p-type column region PC2 of the transition region TR smaller than the total charge amount (CQp) of the first p-type column region PC1 of the cell region CR (CQp> TQp) . Further, the total charge amount (TQn) of the n-type column region formed of the epitaxial layer EPI1 of the transition region TR needs to be set smaller than the total charge amount (CQn) of the n-type column region NC of the cell region CR (CQn> TQn).

  Therefore, since the second p-type column region PC2 of the transition region TR and the first p-type column region PC1 of the cell region CR are formed in the same step, the width of the second p-type column region PC2 is equal to that of the first p-type column region PC1. It was smaller than the width. Furthermore, in the transition region TR, since the partial region of the epitaxial layer EPI1 becomes an n-type column region, the total charge amount (TQp) of the second p-type column region PC2 and the total charge amount of the n-type column region composed of the epitaxial layer EPI1 ( The width of the n-type column region (that is, the pitch of the second p-type column region PC2) formed of the epitaxial layer EPI1 was adjusted so that TQn would be the same (TQp = TQn).

  Here, although the width of the second p-type column region PC2 of the transition region TR is smaller than the width of the first p-type column region PC1 of the cell region CR, the present invention is not limited to this. For example, assuming that the width of the second p-type column region PC2 of the transition region TR and the width of the first p-type column region PC1 of the cell region CR are the same, the p-type impurity concentration of the second p-type column region PC2 of the transition region TR is set to the cell region CR. It may be lower than the p-type impurity concentration of the first p-type column region PC1.

  Next, as shown in FIG. 7, after removing the resist film FR2, a patterned resist film FR3 is formed on the epitaxial layer EPI1. The resist film FR3 is formed so as to expose the third p-type column formation region in the peripheral region PER and cover the upper surface of the epitaxial layer EPI1 in other regions including the cell region CR and the transition region TR.

  Then, by introducing a p-type impurity such as boron (B) into the epitaxial layer EPI1 in the peripheral region PER by ion implantation using the patterned resist film FR3 as a mask, a plurality of third p-type column regions are introduced. The PCs 3 are formed to be separated from one another. In the peripheral region PER, a partial region of the epitaxial layer EPI1 sandwiched between the third p-type column regions PC3 adjacent to each other is an n-type column region.

  Each of the plurality of third p-type column regions PC3 in the peripheral region PER is formed in a substantially columnar shape extending from the lower surface to the upper surface of the epitaxial layer EPI1 by, for example, performing ion implantation with different implantation energy a plurality of times.

The p-type impurity concentration, width, and pitch of the third p-type column region PC3 in the peripheral region PER are set so as to achieve charge balance in the peripheral region PER. In the semiconductor device according to the first embodiment, a case where the ratio of the width of the third p-type column region PC3 in the peripheral region PER to the width of the n-type column region formed of the epitaxial layer EPI1 is 1: 1 is illustrated. In this case, the third p-type column so that the total charge amount (PEQp) of the third p-type column region PC3 and the total charge amount (PEQn) of the n-type column region formed of the epitaxial layer EPI1 are the same (PEQp = PEQn). The p-type impurity concentration in the region PC3 is set. Therefore, the p-type impurity concentration of the third p-type column region PC3 is the same as the n-type impurity concentration of the epitaxial layer EPI1, for example, about 2.4 × 10 ¹⁵ / cm ³ .

  Furthermore, the total charge amount (PEQp) of the third column region PC3 in the peripheral region PER needs to be set smaller than the total charge amount (TQp) of the second p-type column region PC2 in the transition region TR (TQp> PEQp). Further, the total charge amount (PEQn) of the n-type column region formed of the epitaxial layer EPI1 in the peripheral region PER needs to be set smaller than the total charge amount (TQn) of the n-type column region formed of the epitaxial layer EPI1 in the transition region TR. Yes (TQn> PEQn).

  Therefore, since each n-type column region of peripheral region PER and transition region TR is formed of the same epitaxial layer EPI1, the width of the n-type column region formed of epitaxial layer EPI1 of peripheral region PER is formed of epitaxial layer EPI1 of transition region TR. It was smaller than the width of the n-type column area. Furthermore, since the third p-type column region PC3 of the peripheral region PER and the second p-type column region PC2 of the transition region TR are formed in different steps, the p-type impurity concentration of the third p-type column region PC3 of the peripheral region PER is The concentration is lower than the p-type impurity concentration of the second p-type column region PC2 of the transition region TR.

  Here, although the p-type impurity concentration of the third p-type column region PC3 in the peripheral region PER is lower than the p-type impurity concentration of the second p-type column region PC2 in the transition region TR, the present invention is not limited thereto. . For example, assuming that the p-type impurity concentration of the third p-type column region PC3 in the peripheral region PER and the p-type impurity concentration of the second p-type column region PC2 in the transition region TR are the same, the width of the third p-type column region PC3 in the peripheral region PER is The width may be smaller than the width of the second p-type column region PC2 of the transition region TR.

Next, as shown in FIG. 8, a second epitaxial layer EPI2 is further formed on the first epitaxial layer EPI1. The impurity concentration of the epitaxial layer EPI2 is, for example, about 2.4 × 10 ¹⁵ / cm ³ , and the thickness of the epitaxial layer EPI2 is, for example, about 22 μm to 25 μm.

Next, as shown in FIG. 9 (similar to the step described with reference to FIG. 5), a resist film FR4 patterned on the epitaxial layer EPI2 is formed, and ion implantation using this resist film FR4 as a mask is performed. An n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the epitaxial layer EPI2 of the cell region CR. Thus, a plurality of n-type column regions NC electrically connected to the plurality of n-type column regions NC formed in the epitaxial layer EPI1 are formed in the epitaxial layer EPI2 so as to be separated from each other. The n-type impurity concentration in the n-type column region NC is, for example, about 3.0 × 10 ¹⁵ / cm ³ .

Next, as shown in FIG. 10 (same as the process described with reference to FIG. 6), after removing the resist film FR4, a resist film FR5 patterned on the epitaxial layer EPI2 is formed, and this resist film FR5 is formed. A p-type impurity such as boron (B) is introduced into the epitaxial layer EPI2 in the cell region CR and the transition region TR by ion implantation using a mask. Thereby, in the cell region CR, a plurality of first p-type column regions PC1 electrically connected to the plurality of first p-type column regions PC1 formed in the epitaxial layer EPI1 are formed in the epitaxial layer EPI2 so as to be separated from each other. . In the transition region TR, a plurality of second p-type column regions PC2 electrically connected to the plurality of second p-type column regions PC2 formed in the epitaxial layer EPI1 are formed so as to be separated from the epitaxial layer EPI2. The p-type impurity concentration of the first p-type column region PC1 and the second p-type column region PC2 is, for example, about 3.0 × 10 ¹⁵ / cm ³ and the charge balance can be maintained in the cell region CR and the transition region TR. The 1p-type column region PC1 and the second p-type column region PC2 are formed.

  As a result, according to the first embodiment, in the cell region CR, a super junction structure in which the first p-type column region PC1 and the n-type column region NC are alternately formed is formed, and in the transition region TR, the second p-type A super junction structure is formed in which column regions PC2 and n-type column regions composed of epitaxial layers EPI1 and EPI2 are alternately formed.

Next, as shown in FIG. 11 (similar to the step described with reference to FIG. 7), after removing the resist film FR5, a resist film FR6 patterned on the epitaxial layer EPI2 is formed, and this resist film FR6 is formed. A p-type impurity such as boron (B) is introduced into the epitaxial layer EPI2 in the peripheral region PER by ion implantation using a mask. Thus, a plurality of third p-type column regions PC3 electrically connected to the plurality of third p-type column regions PC3 formed in the epitaxial layer EPI1 are formed in the peripheral region PER so as to be separated from each other in the epitaxial layer EPI2. . The impurity concentration of the third p-type column region PC3 is, for example, about 2.4 × 10 ¹⁵ / cm ³ , and the ^third p-type column region PC3 is formed to achieve charge balance in the peripheral region PER.

  As a result, according to the first embodiment, in the peripheral region PER, a super junction structure is formed in which the third p-type column region PC3 and the n-type column regions composed of the epitaxial layers EPI1 and EPI2 are alternately formed.

  In the first embodiment, the “multi-epitaxial method” in which the epitaxial layers EPI1 and EPI2 are formed in two layers has been described. However, the present invention is not limited to this. For example, in a product having a source-drain breakdown voltage (BVdss) of 600 V, the epitaxial layer is divided into 6 to 7 layers.

  In the first embodiment, the thickness of each of the epitaxial layers EPI1 and EPI2 is set to 22 μm to 25 μm, but the thickness also depends on the designed cell pitch. In general, when ion implantation is performed with high energy, the ion distribution increases in the x direction (cell pitch), y direction (depth), and z direction (depth), and the width of the mask used in the photolithography technology is reduced. Also, the width of the p-type column region is expanded. When it is desired to reduce the cell pitch in order to reduce the on-resistance, for example, the thickness of each of the epitaxial layers EPI1 and EPI2 is set to about 3 μm to 5 μm, and the energy of ion implantation is decreased accordingly, thereby maintaining a narrow cell pitch. However, in that case, in order to secure a withstand voltage, it is necessary to increase the number of ion implantations by making the epitaxial layer EPI into three or more layers. Furthermore, the total thickness of the three or more multi-layer epitaxial layers EPI needs to be a thickness required to ensure a withstand voltage, for example, about 40 μm to 50 μm in the first embodiment.

  As described above, according to the first embodiment, the super junction structure can be formed in the epitaxial layers EPI1, EPI2 by the “multi-epitaxial method”.

  Next, a process of forming an element portion on the upper surface of the epitaxial layers EPI1, EPI2 having the super junction structure will be described.

  First, as shown in FIG. 12, the upper surface of the epitaxial layer EPI2 is planarized.

  Next, as shown in FIG. 13, a channel region CH is formed in the cell region CR and the transition region TR by photolithography and ion implantation. The channel region CH is a p-type semiconductor region formed by introducing a p-type impurity such as boron (B) into the epitaxial layer EPI2. Subsequently, the gate insulating film GOX is formed on the upper surface of the epitaxial layer EPI2, and the conductor film PF1 is formed on the gate insulating film GOX. The gate insulating film GOX is made of, for example, a silicon oxide film, and is formed by, for example, a thermal oxidation method. However, the gate insulating film GOX is not limited to a silicon oxide film, and may be, for example, a high dielectric constant film having a dielectric constant higher than that of a silicon oxide film represented by a hafnium oxide film. On the other hand, the conductor film PF1 formed on the gate insulating film GOX is made of, for example, a polycrystalline silicon film, and is formed by, for example, a CVD (Chemical Vapor Deposition) method.

  Next, as shown in FIG. 14, the conductor film PF1 is patterned by photolithography and etching. Thus, a plurality of gate electrodes GE are formed in the cell region CR, a gate lead portion GPU is formed in the transition region TR, and a plurality of electrodes (dummy electrodes) FFP are formed in the peripheral region PER. The gate lead part GPU is formed so as to be electrically connected to the plurality of gate electrodes GE.

  Next, a plurality of source regions SR aligned with the gate electrode GE are formed in the cell region CR by photolithography and ion implantation, and a source extraction region SPR is formed in the transition region TR. The source region SR and the source lead region SPR are n-type semiconductor regions formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into the epitaxial layer EPI2. The plurality of source regions SR formed in the cell region CR are electrically connected to the source lead region SPR formed in the transition region TR.

  Next, as shown in FIG. 15, the interlayer insulating film IL covering the plurality of gate electrodes GE, the gate extraction part GPU, and the plurality of electrodes (dummy electrodes) FFP is formed on the epitaxial layer EPI2. The interlayer insulating film IL is made of, for example, a silicon oxide film, and is formed by, for example, a CVD method.

  Next, an opening reaching the source region SR is formed in the interlayer insulating film IL between the adjacent gate electrodes GE in the cell region CR by photolithography and etching, and the gate extraction portion GPU of the transition region TR Form an opening that exposes a portion of the In the transition region TR, the source lead region SPR is exposed by forming an opening in the interlayer insulating film IL.

  Next, a body contact region BC where the bottom reaches the channel region CH is formed in the center of each of the plurality of source regions SR in the cell region CR by photolithography and ion implantation. The body contact region BC is a p-type semiconductor region formed by introducing a p-type impurity such as boron (B) into the epitaxial layer EPI2, and the impurity concentration of the body contact region BC is the channel region CH. It is formed to be higher than the impurity concentration of

  Next, as shown in FIG. 16, a metal is formed on the interlayer insulating film IL including the opening exposing the source region SR, the opening exposing the gate lead portion GPU, and the opening exposing the source lead region SPR. Form a film. This metal film is made of, for example, a laminated film of a titanium tungsten film and an aluminum film, and is formed by, for example, a sputtering method.

  Then, the metal film is patterned by photolithography and etching. Thus, in the cell region CR, the source electrode SE electrically connected to the source region SR and the body contact region BC is formed. In the transition region TR, a gate extraction electrode GPE electrically connected to the gate extraction portion GPU and a source extraction electrode SPE electrically connected to the source extraction region SPR are formed.

  Next, as shown in FIG. 17, the surface protective film PAS is formed to cover the source electrode SE, the gate extraction electrode GPE, and the source extraction electrode SPE. Then, the surface protection film PAS is patterned by photolithography technology and etching technology to protect the partial region of the source electrode SE, the partial region of the gate lead electrode GPE, and the partial region of the source lead electrode SPE. Exposed from membrane PAS. Thus, the area exposed from the surface protective film PAS can function as an external connection area.

  Next, as shown in FIG. 18, the semiconductor substrate 1S is ground from the back surface opposite to the main surface of the semiconductor substrate 1S to make the semiconductor substrate 1S thinner. Then, on the back surface of the semiconductor substrate 1S, a metal film to be the drain electrode DE is formed by a sputtering method or a vapor deposition method. As described above, the semiconductor device having the super junction structure power MOFET according to the first embodiment can be manufactured.

Second Embodiment
In the first embodiment, an example of applying a new technical idea to a power MOSFET having a super junction structure formed by the “multi-epitaxial method” has been described. In the second embodiment, an example in which a new technical idea is applied to a power MOSFET having a super junction structure formed by the “trench fill method” will be described.

<Configuration of semiconductor device>
FIG. 19 is a cross-sectional view showing the configuration of the semiconductor device (power MOSFET) according to the second embodiment. The configuration of the power MOSFET according to the second embodiment shown in FIG. 19 is substantially the same as the configuration of the power MOSFET according to the first embodiment shown in FIG. 2, so differences will be mainly described.

  In the semiconductor device according to the second embodiment, the plurality of first p-type column regions PC1 formed in the cell region CR, the plurality of second p-type column regions PC2 formed in the transition region TR, and the peripheral region PER A plurality of third p-type column regions PC3 are formed by embedding a p-type semiconductor film in a trench. In this respect, the semiconductor device according to the first embodiment in which the first p-type column region PC1, the second p-type column region PC2, the third p-type column region PC3, and the n-type column region NC are formed by ion implantation (see FIG. 2). It is different from. However, the functions themselves of the first p-type column region PC1, the second p-type column region PC2, and the third p-type column region PC3 are the same as those of the semiconductor device according to the first embodiment.

  Also in the semiconductor device according to the second embodiment, the n-type impurity concentration (Nn) of the first n-type column region NC1 of the cell region CR is higher than the n-type impurity concentration (Nep) of the third n-type column region NC3 of the peripheral region PER. And charge balancing in the cell region CR, the transition region TR, and the peripheral region PER. Furthermore, the total charge amount (CQp, CQn) of the cell region CR becomes larger than the total charge amount (TQp, TQn) of the transition region TR, and the total charge amount (TQp, TQn) of the transition region TR becomes the total of the peripheral region PER. The total charge amount is set so as to be larger than the charge amount (PEQp, PEQn).

  That is, as in the first embodiment, the reliability of the semiconductor device including the power MOSFET of the super junction structure according to the second embodiment can be improved.

<Method for Manufacturing Semiconductor Device>
An example of a method of manufacturing a semiconductor device (power MOSFET) according to the second embodiment will be described with reference to FIGS. 20 to 32 are cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment. In the second embodiment, a manufacturing method called a so-called "trench fill method" will be described. In addition, a semiconductor device in which the breakdown voltage of the pn junction in the cell region is 600 V to 650 V and the breakdown voltage of the pn junction in the peripheral region is 700 V to 750 V is exemplified. That is, a semiconductor device is exemplified in which the breakdown voltage of the pn junction in the peripheral region is about 50 V to 150 V higher than the breakdown voltage of the pn junction in the cell region. Further, the depths and the depths of the column regions respectively formed in the cell region, the transition region and the peripheral region are the same.

First, as shown in FIG. 20, a semiconductor substrate 1S is prepared in which a low-concentration epitaxial layer EPIL made of an n-type semiconductor layer is formed on a main surface (surface, upper surface). For example, the semiconductor substrate 1S is formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into single crystal silicon. The n-type impurity concentration of the epitaxial layer EPIL is, for example, about 2.4 × 10 ¹⁵ / cm ³ , and the thickness of the epitaxial layer EPIL is, for example, about 40 μm to 50 μm.

  Next, as shown in FIG. 21, a resist film FR7 patterned on the epitaxial layer EPIL is formed. Resist film FR7 is formed to cover the upper surface of epitaxial layer EPIL in peripheral region PER.

Then, an n-type impurity such as phosphorus (P) is introduced into the cell region CR and the epitaxial layer EPIL of the transition region TR by ion implantation using the patterned resist film FR7 as a mask. Subsequently, annealing is performed to diffuse the n-type impurity introduced into the epitaxial layer EPIL, thereby forming a high concentration epitaxial layer EPIH in the cell region CR and the transition region TR. The n-type impurity concentration of the epitaxial layer EPIH is, for example, about 3.0 × 10 ¹⁵ / cm ³ .

  Next, as shown in FIG. 22, after removing the resist film FR7, a resist film FR8 patterned on the epitaxial layers EPIH and EPIL is formed. Resist film FR8 exposes the second p-type column formation region of transition region TR and the third p-type column formation region of peripheral region PER, and covers the upper surfaces of epitaxial layers EPIH and EPIL in the other regions including cell region CR. It is formed.

  Then, a plurality of trenches (trench) DTP is formed in the epitaxial layer EPIH of the transition region TR and the epitaxial layer EPIL of the peripheral region PER by the etching technique using the patterned resist film FR8 as a mask. The taper angle of the groove DTP is, for example, about 88.0 degrees to 90 degrees.

  At this time, in the transition region TR, the partial region of the epitaxial layer EPIH sandwiched between the adjacent trenches DTP becomes the second n-type column region NC2, and in the peripheral region PER, the epitaxial layer EPIL sandwiched between the adjacent trenches DTP. The partial region is the third n-type column region NC3.

  Next, as shown in FIG. 23, the resist film FR8 is removed. Thereafter, a second p-type column region PC2 made of a p-type semiconductor region is formed in the trench DTP formed in the epitaxial layer EPIH in the transition region TR by, for example, a buried epitaxial growth method, and formed in the epitaxial layer EPIL in the peripheral circuit region PER. A third p-type column region PC3 made of a p-type semiconductor region is formed inside the trench DTP.

The p-type impurity concentration, width, and pitch of the third p-type column region PC3 in the peripheral region PER are set so as to achieve charge balance in the peripheral region PER. The semiconductor device according to the second embodiment exemplifies a case where the ratio of the width of the third p-type column region PC3 in the peripheral region PER to the width of the third n-type column region NC3 is 1: 1. In this case, in the third p-type column region PC3, the total charge amount (PEQp) of the third p-type column region PC3 and the total charge amount (PEQn) of the third n-type column region NC3 are the same (PEQp = PEQn). The p-type impurity concentration is set. Therefore, the p-type impurity concentration of the third p-type column region PC3 is the same as the n-type impurity concentration of the epitaxial layer EPIL constituting the third n-type column region NC3, for example, about 2.4 × 10 ¹⁵ / cm ³ .

Similarly, the p-type impurity concentration, width, and pitch of the second p-type column region PC2 of the transition region TR are set so as to achieve charge balance in the transition region TR. The n-type impurity concentration of the second n-type column region NC2 of the transition region TR is, for example, about 3.0 × 10 ¹⁵ / cm ³ . On the other hand, since the second p-type column region PC2 and the third p-type column region PC3 are formed in the same step, the p-type impurity concentration of the second p-type column region PC2 is, for example, about 2.4 × 10 ¹⁵ / cm ³ . is there. However, by making the width of the second p-type column region PC2 larger than the width of the second n-type column region NC2, for example, the total charge amount (TQp) of the second p-type column region PC2 and the total of the second n-type column region NC2 The charge amount (TQn) can be the same (TQp = TQn).

  Furthermore, the total charge amount (TQp) of the second p-type column region PC2 of the transition region TR needs to be set larger than the total charge amount (PEQp) of the third column region PC3 of the peripheral region PER (TQp> PEQp). In addition, it is necessary to set the total charge (TQn) of the n-type column region formed of the epitaxial layer EPIH of the transition region TR to be larger than the total charge (PEQn) of the n-type column region formed of the epitaxial layer EPIL of the peripheral region PER. Yes (TQn> PEQn).

  However, the n-type impurity concentration of the second n-type column region NC2 of the transition region TR is made higher than the n-type impurity concentration of the third n-type column region NC3 of the peripheral region PER, and the width of the second p-type column region PC2 of the transition region TR Is made larger than the width of the third p-type column region PC3 in the peripheral region PER, the above settings (TQp> PEQp, TQn> PEQn) can be realized.

  As a result, according to the second embodiment, in the transition region TR, a super junction structure in which the second p-type column regions PC2 and the second n-type column regions NC2 are alternately formed is formed, and in the peripheral region PER, the third junction p is formed. A super junction structure is formed in which the mold column regions PC3 and the third n-type column regions NC3 are alternately formed.

  Next, as shown in FIG. 24, a patterned resist film FR9 is formed on the epitaxial layers EPIH and EPIL. The resist film FR9 is formed so as to expose the first p-type column formation region in the cell region CR and cover the upper surfaces of the epitaxial layers EPIH and EPIL in other regions including the transition region TR and the peripheral region PER.

  Then, a plurality of trenches (trench) DC are formed in the epitaxial layer EPIH of the cell region CR by an etching technique using the patterned resist film FR9 as a mask. The taper angle of the groove DC is, for example, about 88.0 degrees to 90 degrees.

  At this time, in the cell region CR, a partial region of the epitaxial layer EPIH sandwiched by the grooves DC adjacent to each other becomes a first n-type column region NC1.

  Next, as shown in FIG. 25, the resist film FR9 is removed.

  Next, as shown in FIG. 26, a first p-type column region PC1 made of a p-type semiconductor region is formed inside the groove DC formed in the epitaxial layer EPIH of the cell region CR by, for example, a buried epitaxial growth method.

  The p-type impurity concentration, width, and pitch of the first p-type column region PC1 of the cell region CR are set so that charge balance is achieved in the cell region CR. In the semiconductor device according to the second embodiment, a case where the ratio of the width of the first p-type column region PC1 of the cell region CR to the width of the first n-type column region NC1 is 1: 1 is illustrated. In this case, the total charge amount (CQp) of the first p-type column region PC1 and the total charge amount (CQn) of the first n-type column region NC1 are the same (CQp = CQn). The p-type impurity concentration is set.

  Further, the total charge amount (CQp) of the first p-type column region PC1 of the cell region CR is larger than the total charge amount (TQp) of the second p-type column region PC2 of the transition region TR (CQp> TQp). The total charge amount (CQn) of the first n-type column region NC1 needs to be set larger than the total charge amount (TQn) of the second n-type column region NC2 of the transition region TR (CQn> TQn).

  Therefore, in the semiconductor device according to the second embodiment, the n-type impurity concentration of the first n-type column region NC1 of the cell region CR is the same as the n-type impurity concentration of the second n-type column region NC2 of the transition region TR. The width of the first n-type column region NC1 in the cell region CR is made larger than the width of the second n-type column region NC2 in the transition region TR. Further, the p-type impurity concentration of the first p-type column region PC1 of the cell region CR is set higher than the p-type impurity concentration of the second p-type column region PC2 of the transition region TR.

  As a result, according to the second embodiment, a super junction structure in which the first p-type column region PC1 and the first n-type column region NC1 are alternately formed is formed in the cell region CR.

  Next, a process of forming an element portion on the upper surface of the epitaxial layers EPIH and EPIL in which the super junction structure is formed will be described.

  First, the upper surfaces of the epitaxial layers EPIH and EPIL are planarized.

  Next, as shown in FIG. 27, a channel region CH is formed in the cell region CR and the transition region TR by photolithography and ion implantation. The channel region CH is a p-type semiconductor region formed by introducing a p-type impurity such as boron (B) into the epitaxial layers EPIH and EPIL. Subsequently, a gate insulating film GOX is formed on the upper surfaces of the epitaxial layers EPIH and EPIL, and a conductor film PF1 is formed on the gate insulating film GOX. The gate insulating film GOX is made of, for example, a silicon oxide film, and is formed by, for example, a thermal oxidation method. However, the gate insulating film GOX is not limited to a silicon oxide film, and may be, for example, a high dielectric constant film having a dielectric constant higher than that of a silicon oxide film represented by a hafnium oxide film. On the other hand, the conductor film PF1 formed on the gate insulating film GOX is made of, for example, a polycrystalline silicon film, and is formed by, for example, the CVD method.

  Next, as shown in FIG. 28, the conductor film PF1 is patterned by photolithography and etching. Thus, a plurality of gate electrodes GE are formed in the cell region CR, a gate lead portion GPU is formed in the transition region TR, and a plurality of electrodes (dummy electrodes) FFP are formed in the peripheral region PER. The gate lead part GPU is formed so as to be electrically connected to the plurality of gate electrodes GE.

  Next, a plurality of source regions SR aligned with the gate electrode GE are formed in the cell region CR by photolithography and ion implantation, and a source extraction region SPR is formed in the transition region TR. Source region SR and source leading region SPR are n-type semiconductor regions formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into epitaxial layers EPIH and EPIL. The plurality of source regions SR formed in the cell region CR are electrically connected to the source lead region SPR formed in the transition region TR.

  Next, as shown in FIG. 29, an interlayer insulating film IL covering the plurality of gate electrodes GE, the gate lead-out portion GPU, and the plurality of electrodes (dummy electrodes) FFP is formed on the epitaxial layers EPIH and EPIL. The interlayer insulating film IL is made of, for example, a silicon oxide film, and is formed by, for example, a CVD method.

  Next, an opening reaching the source region SR is formed in the interlayer insulating film IL between the adjacent gate electrodes GE in the cell region CR by photolithography and etching, and the gate extraction portion GPU of the transition region TR Form an opening that exposes a portion of the In the transition region TR, the source lead region SPR is exposed by forming an opening in the interlayer insulating film IL.

  Next, a body contact region BC where the bottom reaches the channel region CH is formed in the center of each of the plurality of source regions SR in the cell region CR by photolithography and ion implantation. The body contact region BC is, for example, a p-type semiconductor region formed by introducing a p-type impurity such as boron (B) into the epitaxial layers EPIH and EPIL, and the impurity concentration of the body contact region BC is Are formed to be higher than the impurity concentration of the channel region CH.

  Next, as shown in FIG. 30, a metal is formed on the interlayer insulating film IL including the opening that exposes the source region SR, the opening that exposes the gate lead portion GPU, and the opening that exposes the source lead region SPR. Form a film. The metal film is formed of, for example, a laminated film of a titanium tungsten film and an aluminum film, and is formed by, for example, a sputtering method.

  Then, the metal film is patterned by photolithography and etching. Thereby, the source electrode SE electrically connected to the source region SR and the body contact region BC is formed in the cell region CR, and the gate electrically connected to the gate lead part GPU is formed in the transition region TR. A source extraction electrode SPE electrically connected to the extraction electrode GPE and the source extraction region SPR is formed.

  Next, as shown in FIG. 31, the surface protective film PAS is formed to cover the source electrode SE, the gate extraction electrode GPE, and the source extraction electrode SPE. Then, the surface protection film PAS is patterned by photolithography technology and etching technology to protect the partial region of the source electrode SE, the partial region of the gate lead electrode GPE, and the partial region of the source lead electrode SPE. Exposed from membrane PAS. Thereby, the region exposed from the PAS from the surface protective film can function as the external connection region.

  Next, as shown in FIG. 32, the semiconductor substrate 1S is ground from the back surface opposite to the main surface of the semiconductor substrate 1S to make the semiconductor substrate 1S thinner. Then, on the back surface of the semiconductor substrate 1S, a metal film to be the drain electrode DE is formed by a sputtering method or a vapor deposition method. As described above, the semiconductor device having the power MOSFET of the super junction structure according to the second embodiment can be manufactured.

<Advantage of trench fill method>
For example, in the super junction structure, it is effective to narrow the distance between the p-type column region and the n-type column region in order to reduce the on-resistance. This is because it is desirable to increase the n-type impurity concentration in the n-type column region which is the current passage from the viewpoint of reducing the on-resistance. That is, when the n-type impurity concentration in the n-type column region is increased to reduce the on-resistance, the extension of the depletion layer to the n-type column region is reduced, so that the entire n-type column region is depleted. Needs to narrow the width of the n-type column region. Therefore, in consideration of securing the breakdown voltage while increasing the n-type impurity concentration of the n-type column region to reduce the on-resistance in the power MOSFET of the super junction structure, the p-type column region and the n-type column region It is necessary to narrow the interval.

  In this regard, in the "multi-epitaxial method", the p-type column region is formed by ion implantation. For this reason, in consideration of the impurity diffusion effect, the interval between the p-type column region and the n-type column region cannot be sufficiently narrowed. On the other hand, in the “trench fill method”, the p-type column region is formed by a buried epitaxial method in a trench formed in the epitaxial layer. Therefore, in the “trench fill method”, the formation accuracy of the p-type column region is determined by the formation accuracy of the groove. The grooves are then formed by photolithography. At this time, since the accuracy of the photolithography technique is higher than the accuracy of the ion implantation method, the “trench fill method” can form the p-type column region with higher accuracy than the “multi-epitaxial method”. This means that in the “trench fill method”, the interval between the p-type column region and the n-type column region can be made narrower than in the “multi-epitaxial method”. As a result, according to the “trench fill method”, there is an advantage that a power MOSFET having a smaller on-resistance can be manufactured than the “multi-epitaxial method”. That is, the “trench fill method” has an advantage over the “multi-epitaxial method” in that a power MOSFET having a smaller on-resistance can be manufactured while ensuring a withstand voltage.

  Further, by providing a taper angle to the groove formed in the epitaxial layer, it is possible to suppress the on operation of the parasitic npn bipolar transistor. Hereinafter, the reason why the on-operation of the parasitic npn bipolar transistor can be suppressed will be described with reference to FIG.

  FIG. 33 is a graph showing the charge balance of the breakdown voltage (BVdss) of the pn junction, a schematic diagram showing the total charge amount distribution of the pn junction, and a schematic diagram showing the electric field strength of the pn junction. FIG. 33A shows the electric field intensity and the like when the total charge amount (Qp) of the p-type column region and the total charge amount (Qn) of the n-type column region are substantially the same (Qp≈Qn). FIG. 33B shows the electric field strength and the like when the total charge amount (Qp) of the p-type column region is larger than the total charge amount (Qn) of the n-type column region (Qp> Qn). FIG. 33C shows the electric field intensity and the like when the total charge amount (Qp) of the p-type column region is smaller than the total charge amount (Qn) of the n-type column region (Qp <Qn).

  As shown in the charge balance of FIG. 33A, if the total charge amount (Qp) of the p-type column region and the total charge amount (Qn) of the n-type column region are substantially the same (Qp≈Qn) The maximum value of the breakdown voltage (BVdss) of the pn junction can be obtained. Even if the total charge amount (Qp) of the p-type column region and the total charge amount (Qn) of the n-type column region vary by about ± 10% of the total charge amount (Qp) of the p-type column region, The drop in breakdown voltage (BVdss) is slight.

  Further, as shown in the total charge amount distribution and electric field strength of FIG. 33A, the groove in which the p-type column region is formed has a taper angle, and the total charge amount (Qp) of the p-type column region and the n-type When the total charge amount (Qn) of the column region is substantially the same (Qp≈Qn), the electric field strength can be maximized at the intermediate point in the depth direction of the p-type column region and the n-type column region.

  As shown in the charge balance of FIG. 3B, when the total charge amount (Qp) of the p-type column region is larger than the total charge amount (Qn) of the n-type column region (Qp> Qn), the p-type column As the total charge amount (Qp) of the region becomes larger than the total charge amount (Qn) of the n-type column region, the breakdown voltage (BVdss) of the pn junction gradually decreases.

  However, as shown in the total charge amount distribution and electric field strength in FIG. 33B, the groove in which the p-type column region is formed has a taper angle, and the total charge amount (Qp) of the p-type column region is n-type. When it is larger than the total charge amount (Qn) of the column region (Qp> Qn), the electric field strength becomes maximum at a position deeper than the intermediate point in the depth direction of the p-type column region and the n-type column region. That is, when the total charge amount (Qp) of the p-type column region is larger than the total charge amount (Qn) of the n-type column region (Qp> Qn), the position of the maximum electric field strength is the total charge amount of the p-type column region. When (Qp) and the total charge amount (Qn) of the n-type column region are substantially the same (Qp≈Qn), the position is farther from the upper surface of the epitaxial layer than the position of the maximum electric field strength.

  The avalanche breakdown phenomenon occurs near the position of the maximum electric field strength. Therefore, since the position of the maximum electric field strength is away from the upper surface of the epitaxial layer, the current flows to the channel region, but the avalanche current generated here is easily dispersed in the depth direction, and the avalanche current density is reduced. Can be suppressed as an emitter region, a channel region as a base region, and an n-type column region as a collector region.

  On the other hand, as shown in the charge balance of FIG. 33 (c), when the total charge amount (Qp) of the p-type column region is smaller than the total charge amount (Qn) of the n-type column region (Qp <Qn) As the total charge amount (Qp) of the p-type column region becomes smaller than the total charge amount (Qn) of the n-type column region, the breakdown voltage (BVdss) of the pn junction gradually decreases.

  However, as shown in the total charge amount distribution and electric field strength of FIG. 33 (c), the groove in which the p-type column region is formed has a taper angle, and the total charge amount (Qp) of the p-type column region is n-type. When the total charge amount (Qn) in the column region is smaller (Qp <Qn), the electric field strength becomes maximum at a position shallower than the intermediate point in the depth direction of the p-type column region and the n-type column region. That is, when the total charge amount (Qp) of the p-type column region is smaller than the total charge amount (Qn) of the n-type column region (Qp <Qn), the position of the maximum electric field strength is the total charge amount of the p-type column region. When (Qp) and the total charge amount (Qn) of the n-type column region are the same (Qp≈Qn), the position is closer to the upper surface of the epitaxial layer than the position of the maximum electric field strength.

  The avalanche breakdown phenomenon occurs near the position of the maximum electric field strength. Therefore, since the position of the maximum electric field intensity approaches the top surface of the epitaxial layer, the current flows to the channel region while the avalanche current density generated here flows high, so the source region is the emitter region and the channel region is the base region. The parasitic npn bipolar transistor having the n-type column region as the collector region is likely to be turned on.

  From the above, in the “trench fill method”, the groove formed in the epitaxial layer is tapered, and the total charge (Qp) of the p-type column region is the total charge (Qn) of the n-type column region (Qp> Qn), the on-operation of the parasitic npn bipolar transistor can be suppressed.

Third Embodiment
In the third embodiment, a modification of the power MOSFET having a super junction structure formed by the “multi-epitaxial method” described in the first embodiment will be described.

  As described in the second embodiment, in the “trench fill method”, the on-operation of the parasitic npn bipolar transistor can be suppressed by providing a taper angle to the groove formed in the epitaxial layer. In contrast, in the “multi-epitaxial method”, the concentration gradient is provided in the depth direction in the p-type column region or the n-type column region, so that the position of the maximum electric field strength is higher in the epitaxial layer than the intermediate point in the depth direction. It is possible to suppress the on operation of the parasitic npn bipolar transistor away from the top surface.

<Configuration of semiconductor device>
FIG. 34 is a cross-sectional view showing the configuration of the semiconductor device (power MOSFET) according to the third embodiment. The configuration of the power MOSFET according to the third embodiment shown in FIG. 34 is substantially the same as the configuration of the power MOSFET according to the first embodiment shown in FIG. 2, so differences will be mainly described.

  In the semiconductor device according to the third embodiment, a plurality of first p-type column regions PC1 and a plurality of n-type column regions NC formed in the cell region CR and a plurality of second p-type column regions PC2 formed in the transition region TR. The plurality of third p-type column regions PC3 formed in the peripheral region PER are formed by the “multi-epitaxial method”. That is, each of these column regions is formed in a substantially columnar shape extending from the lower surface to the upper surface of the epitaxial layer EPI, for example, by performing ion implantation with different implantation energy a plurality of times.

  In the semiconductor device according to the first embodiment, the impurity concentration of each of the column regions is constant in the depth direction from the upper surface to the lower surface of the epitaxial layer EPI. On the other hand, in the semiconductor device according to the third embodiment, a concentration difference is provided in the impurity concentration of each column region in the depth direction from the upper surface to the lower surface of the epitaxial layer EPI. This concentration difference can be realized, for example, by changing the implantation energy at the same time as ion implantation and adjusting the dose.

  As shown in FIG. 34, in the cell region CR, the n-type impurity concentration of the plurality of n-type column regions NC is gradually increased in the depth direction (y direction) from the upper surface to the lower surface of the epitaxial layer EPI. The p-type impurity concentration of the first p-type column region PC1 is gradually lowered. In the transition region TR, the p-type impurity concentration of the plurality of second p-type column regions PC2 is gradually lowered in the depth direction (y direction) from the upper surface to the lower surface of the epitaxial layer EPI. In the peripheral region PER, the p-type impurity concentration of the plurality of third p-type column regions PC3 is gradually lowered in the depth direction (y direction) from the upper surface to the lower surface of the epitaxial layer EPI.

  FIG. 35 is a schematic diagram showing a total charge amount distribution at a pn junction in the semiconductor device according to the third embodiment, and a schematic diagram showing an electric field strength at the pn junction.

  FIG. 35A is a graph showing the total charge distribution and the electric field strength when the p-type impurity concentration in the p-type column region and the n-type impurity concentration in the n-type column region are uniform in the depth direction.

  In this case, with respect to the depth direction, the total charge amount (Qp) of the p-type column region and the total charge amount (Qn) of the n-type column region are the same in all regions (Qp = Qn). Therefore, the electric field strength is uniform over the entire area in the depth direction. For this reason, the location where the avalanche breakdown phenomenon occurs in the depth direction depends on process variations (for example, distribution of dimensions, impurity concentration, etc.). If the electric field strength becomes maximum near the upper surface of the epitaxial layer, the parasitic npn bipolar transistor may be turned on, and the power MOSFET may be destroyed.

  In FIG. 35B, the n-type impurity concentration in the n-type column region is made uniform in the depth direction, and the p-type impurity concentration in the p-type column region gradually decreases in the depth direction from the upper surface to the lower surface of the epitaxial layer. It is a graph which shows the total charge amount distribution in a case, and an electric field strength.

  In this case, the electric field strength is maximum at a position deeper than the midpoint between the p-type column region and the n-type column region in the depth direction. Thereby, the position of the maximum electric field strength can be further distanced from the upper surface of the epitaxial layer, so that the on operation of the parasitic npn bipolar transistor can be suppressed.

  In FIG. 35C, the p-type impurity concentration in the p-type column region is made uniform in the depth direction, and the n-type impurity concentration in the n-type column region gradually increases in the depth direction from the upper surface to the lower surface of the epitaxial layer. It is a graph which shows the total charge amount distribution in a case, and an electric field strength.

  In this case, the electric field intensity becomes maximum at a position deeper than the intermediate point in the depth direction of the p-type column region and the n-type column region. Thereby, the position of the maximum electric field strength can be further distanced from the upper surface of the epitaxial layer, so that the on operation of the parasitic npn bipolar transistor can be suppressed.

Embodiment 4
In the first embodiment, one of the new technical ideas is that the n-type impurity concentration in the n-type column region of the cell region is made higher than the n-type impurity concentration in the epitaxial layer in the peripheral region. An example applied to a semiconductor device including a power MOSFET has been described. In the fourth embodiment, an example will be described in which the above technical idea is applied to a semiconductor device including an IGBT (insulate gate bipolar transistor).

<Configuration of semiconductor device>
FIG. 36 is a cross-sectional view showing a configuration of a semiconductor device (IGBT) according to the fourth embodiment. Here, using "+" and "-" is a sign conductivity type expressed relative impurity concentrations of the n-type or p-type, for example, "n ^-", "n", "n ^+" It means that the impurity concentration of the n-type impurity is high in the order of

An n ⁺ -type buffer layer BF into which an n-type impurity of silicon is introduced is formed on the main surface (surface, upper surface) of the p ⁺ -type substrate SUB into which a p-type impurity of silicon is introduced.

Furthermore, on the n ⁺ -type buffer layer BF, an n ⁺ -type drift layer DRTC into which an n-type impurity made of silicon is introduced and an n ⁻ -type drift layer DRTP are formed. These n ⁺ type drift layer DRTC and n ⁻ type drift layer DRTP play a role of ensuring a breakdown voltage, and the thickness thereof is, for example, about 5 to 40 μm. Here, an n ⁺ type drift layer DRTC having a relatively high impurity concentration is formed in the cell region CR, and an n ⁻ type drift layer DRTP having a relatively low impurity concentration is formed in the peripheral region PER. . For example, the n-type impurity concentration of the n ⁻ -type drift layer DRTP in the peripheral region PER is about 10% to 20% lower than the n-type impurity concentration of the n ⁺ -type drift layer DRTC in the cell region CR. The impurity concentration is set.

Inside the n ⁺ -type drift layer DRTC in the cell region CR, there is formed a p-type base layer PR having a predetermined depth from the top surface of the n ⁺ -type drift layer DRTC into which a p-type impurity is introduced. Furthermore, inside the p-type base layer PR, an n-type impurity is introduced with a predetermined depth from the upper surface of the n ⁺ -type drift layer DRTC and at a distance from the end of the p-type base layer PR. An n ⁺ -type source layer NR is formed. The n ⁺ -type source layer NR has a predetermined distance from the upper surface of the n ⁺ -type drift layer DRTC inside the p-type base layer PR between the end of the p-type base layer PR and the n ⁺ -type source layer NR. The n ⁺ -type drift layer DRTC is electrically connected through a channel formed in this manner.

Further, a gate insulating film Tox is formed on the p-type base layer PR where a channel between the end of the p-type base layer PR and the n ⁺ -type source layer NR is formed, and a gate is formed on the gate insulating film Tox An electrode GPm is formed.

N the peripheral area PER ^- -type Inside the drift layer Drtp, n ^- -type drift layer plurality of p-type impurity is introduced from the upper surface of Drtp have a predetermined depth p-type field limiting rings (Field Limiting Ring) FLR is formed. The plurality of p-type field limiting rings FLR are formed to surround the cell region CR, and the voltage is fixed. By forming such a plurality of p-type field limiting rings FLR, the electric field is shared by the plurality of p-type field limiting rings FLR, so that the semiconductor device can have a high breakdown voltage.

  Further, although not shown, an n-type guard ring is formed so as to surround a plurality of p-type field limiting rings FLR, and the voltage is fixed. The n-type guard ring has a function of protecting the IGBT element in the semiconductor chip after the semiconductor chip is separated from the semiconductor wafer.

Furthermore, in the cell region CR and the peripheral region PER, an interlayer insulating film ILL is formed so as to cover the elements of the IGBT, the p-type field limiting ring FLR, the n-type guard ring and the like. In the interlayer insulating film ILL, although not shown, openings reaching the n-type ⁺ source layer NR, the p-type base layer PR, the gate electrode GPm, the p-type field limiting ring FLR, and the like are formed. Then, source electrode SPm electrically connected to a part of the surface of n ⁺ type source layer NR and a part of the surface of p type base layer PR is formed, and electrically connected to the back surface of p ⁺ type substrate SUB. The drain electrode DPm is formed.

As described above, in the semiconductor device according to the fourth embodiment, the n type impurity concentration of the n ⁺ type drift layer DRTC in the pn junction (the junction between the p type base layer PR and the n ⁺ type drift layer DRTC) in the cell region CR. Is higher than the n-type impurity concentration of the n ⁻ type drift layer DRTP in the pn junction (the junction between the p type field limiting ring FLR and the n ⁻ type drift layer DRTP) in the peripheral region PER. Thus, the avalanche breakdown voltage of the cell region CR is lower than the avalanche breakdown voltage of the peripheral region PER, so that the avalanche breakdown phenomenon can be generated in the cell region CR. Therefore, before the avalanche breakdown phenomenon occurs in the peripheral region PER that easily exceeds the avalanche resistance of the IGBT, the avalanche breakdown phenomenon can occur in the cell region CR that does not easily exceed the avalanche resistance of the IGBT. As a result, even if a voltage exceeding the power supply voltage is applied to the IGBT and an avalanche breakdown phenomenon occurs, a situation which leads to the destruction of the IGBT can be avoided. Thus, according to the fourth embodiment, the reliability of the semiconductor device including the IGBT can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiments, the novel technical idea has been described by taking the power MOSFET and IGBT as examples of the power semiconductor element, but the novel technical idea described in the present specification is not limited thereto. The present invention can be widely applied to semiconductor devices including other power semiconductors such as diodes.

  The embodiment includes the following modes.

(Supplementary Note 1)
A semiconductor device comprising a semiconductor chip having a cell region and a peripheral region formed outside the cell region, the semiconductor chip comprising:
The semiconductor chip is
(A) semiconductor substrate of first conductivity type,
(B) a buffer layer of a second conductivity type different from the first conductivity type formed on the semiconductor substrate,
(C) a first drift layer of the second conductivity type formed on the buffer layer of the cell region;
(D) a second drift layer of the second conductivity type formed on the buffer layer in the peripheral region,
(E) A base layer of the first conductivity type formed in the first drift layer of the cell region with a first distance from the top surface of the first drift layer,
(F) The second conductive type formed in the base layer at a second distance shorter than the first distance from the top surface of the first drift layer and separated from the end of the base layer Source layer,
(G) a gate insulating film formed on the base layer,
(H) a gate electrode formed on the gate insulating film,
Including
The impurity concentration of the second conductivity type of the second drift layer in the peripheral region is 10% to 20% lower than the impurity concentration of the second conductivity type of the first drift layer in the cell region.

1S Semiconductor substrate BC Body contact region BF n ⁺ type buffer layer CH channel region CHP semiconductor chip CR cell region DC trench (trench)
DE drain electrode DPm drain electrode DRTC n ⁺ type drift layer DRTP n ⁻ type drift layer DTP trench (trench)
EPI, EPI1, EPI2 Epitaxial layer EPIH, EPIL Epitaxial layer FFP electrode (dummy electrode)
FLR p-type field limiting rings FR1 to FR9 Resist film GE Gate electrode GOX Gate insulating film GPE Gate lead electrode GPm Gate electrode GPU Gate lead portion IL, ILL Interlayer insulating film NC n-type column region NC1 1n-type column region NC2 2n Type column region NC3 third n type column region NR n ⁺ type source layer PAS surface protective film PC1 first p type column region PC2 second p type column region PC3 third p type column region PER peripheral region PF1 conductor film PR p type base layer SE source Electrode SPE source extraction electrode SPm source electrode SPR source extraction region SR source region SUB p ⁺ type substrate Tox gate insulating film TR transition region

Claims (3)

A method for manufacturing a semiconductor device having a cell region and a peripheral region formed outside the cell region,
(A) preparing a semiconductor substrate having an epitaxial layer of the first conductivity type formed on the main surface;
(B) introducing an impurity of the first conductivity type into the epitaxial layer of the cell region;
(C) forming a plurality of first trenches in the epitaxial layer of the cell region so as to be separated from each other in a first direction;
(D) After the step (c), the second conductivity type is formed by embedding a first semiconductor film of a second conductivity type different from the first conductivity type in each of the plurality of first trenches in the cell region. Forming the first column regions of the mold spaced apart from one another;
(E) forming a plurality of second grooves in the epitaxial layer of the peripheral region so as to be separated from each other in the first direction;
(F) After the step (e), the second conductivity type second column region is formed by embedding the second conductivity type second semiconductor film in each of the plurality of second grooves in the peripheral region. Forming to be separated from each other,
Including
The impurity concentration of said first conductivity type of the epitaxial layer in the cell area, rather higher than the impurity concentration of said first conductivity type of the epitaxial layer in the peripheral region,
The width in the first direction of the first groove of the cell area and the width in the first direction of the second groove of the peripheral area are the same.
Manufacturing a semiconductor device , wherein the impurity concentration of the first semiconductor film embedded in the first groove of the cell region is higher than the impurity concentration of the second semiconductor film embedded in the second groove of the peripheral region Method. In the method of manufacturing a semiconductor device according to claim 1,
The width in the first direction of the first groove of the cell area is larger than the width in the first direction of the second groove of the peripheral area,
A semiconductor device, wherein the impurity concentration of the first semiconductor film embedded in the first groove of the cell region is the same as the impurity concentration of the second semiconductor film embedded in the second groove of the peripheral region. Manufacturing method. In the method of manufacturing a semiconductor device according to claim 1,
In the step (c), the width in the first direction of the first groove is gradually narrowed in the direction from the upper surface to the lower surface of the epitaxial layer,
In the step (e), the width in the first direction of the second groove is gradually narrowed in the direction from the upper surface to the lower surface of the epitaxial layer.

Images