JP6547265B2 - Imaging device and imaging device - Google Patents

Description

  The present invention relates to an imaging unit and an imaging device.

Conventionally, in a digital pixel sensor chip (Digital Pixel Sensor Chip), a sensor unit including a photodiode, a comparison unit comparing an output signal from the sensor unit with a lamp voltage, and a memory unit recording an output from the comparison unit (For example, refer nonpatent literature 1).
[Prior art document]
[Patent Document]
[Non-Patent Document 1] IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001, A 10000 Frames / s CMOS Digital Pixel Sensor, Stuart Kleinfelder, SukHwan Lim, Xinqiao Liu, and Abbas El Gamal, Fellow, IEEE

  In the above-described digital pixel sensor chip, each pixel has a comparison unit and a memory unit in addition to the sensor unit. Therefore, one pixel is composed of a large number of transistors. Therefore, it has been difficult to provide pixels at high density in a digital pixel sensor chip.

  According to a first aspect of the present invention, an imaging unit having a pixel unit including a plurality of photoelectric conversion units, a signal processing unit processing digital signals output from the imaging unit, and an imaging unit are provided. An imaging unit comprising: a differential comparator that outputs a digital signal by comparing the signal level of an output signal generated according to the amount of charge photoelectrically converted in a pixel unit.

  Note that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a subcombination of these feature groups can also be an invention.

FIG. 6 is a cross-sectional view of a single-lens reflex camera 400. FIG. 2 is a block diagram showing a configuration example of an imaging unit 200. FIG. 2 is a circuit schematic diagram of a pixel unit 11 and a signal processing circuit 22 of an imaging unit 200 in the first embodiment. FIG. 7 is a time chart diagram for explaining the operation of the imaging unit 200. FIG. 2 is a diagram showing an element layout of a pixel unit 11; FIG. 6 is a view showing a positional relationship between the photoelectric conversion unit 31 and the photoelectric conversion unit 33 and the microlens 50 in the pixel unit 11; FIG. 7 is a view showing a modification of the positional relationship between the photoelectric conversion unit 31 and the photoelectric conversion unit 33 and the microlens 50 in the pixel unit 11; FIG. 7 is a circuit schematic diagram of a pixel unit 12 and a signal processing circuit 22 of an imaging unit 300 in a second embodiment. FIG. 18 is a time chart diagram for explaining the operation of the imaging unit 300 in the second embodiment. It is a circuit schematic diagram of pixel part 13 of image pick-up unit 310, and signal processing circuit 22 in a 3rd embodiment.

  Hereinafter, the present invention will be described through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Moreover, not all combinations of features described in the embodiments are essential to the solution of the invention.

  FIG. 1 is a cross-sectional view of a single-lens reflex camera 400. A single-lens reflex camera 400 as an example of an imaging apparatus includes an imaging unit 200, a lens unit 500, and a camera body 600. The lens unit 500 is attached to the camera body 600. The lens unit 500 includes an optical system arranged along the optical axis 410 in its lens barrel, and guides the incident subject light flux to the imaging unit 200 of the camera body 600.

  In the present example, the single-lens reflex camera 400 is described as an example of the imaging device, but the camera body 600 may be regarded as an imaging device. Further, the imaging apparatus is not limited to the lens interchangeable type camera having the mirror unit, but may be a lens interchangeable type camera not having the mirror unit, or a lens integrated type camera regardless of the presence or absence of the mirror unit. Further, in the present example, the direction in which the subject luminous flux travels along the optical axis 410 is taken as a third direction. The directions perpendicular to the third direction and perpendicular to each other are taken as the first direction and the second direction.

  A lens mount 550 is coupled to the camera body 600. The camera body 600 includes a mirror 672 on the third direction side of the body mount 660. The mirror 672 is fixed to the shaft so as to be rotatable between an oblique position provided to be inclined with respect to the subject light flux incident from the lens unit 500 in the third direction and a retracted position for retracting from the subject light flux. .

  When the mirror 672 is in the oblique position, most of the subject light flux incident through the lens unit 500 is reflected by the mirror 672 and guided to the focusing plate 652. The focusing plate 652 is disposed at a position conjugate to the light receiving surface of the imaging unit 200, and visualizes the subject image formed by the optical system of the lens unit 500. An object image formed on the focusing plate 652 is observed from the finder 650 through the pentaprism 654 and the finder optical system 656.

  The focusing plate 652, the pentaprism 654, and the mirror 672 are supported by a mirror box 670 as a structure. The imaging unit 200 is attached to the mirror box 670. When the mirror 672 retracts to the retracted position and the front and rear curtains of the shutter unit 340 are opened, the subject luminous flux transmitted through the lens unit 500 reaches the light receiving surface of the imaging unit 200.

  A body substrate 620 and a rear display unit 634 are sequentially disposed on the opposite side of the imaging unit 200 to the shutter unit 340. A rear display unit 634 in which a liquid crystal panel or the like is adopted is located on the rear of the camera body 600. Electronic circuits such as a CPU 622 and an image processing unit 624 are mounted on the body substrate 620. The output of the imaging unit 200 is delivered to the image processing unit 624.

  FIG. 2 is a block diagram showing a configuration example of the imaging unit 200. As shown in FIG. The imaging unit 200 includes an imaging unit 10 and a signal processing unit 20. The imaging unit 10 may be a chip having the function of the imaging unit 10, and the signal processing unit 20 may be a chip having the function of the signal processing unit 20. A light beam enters the imaging unit 10 from the third direction. At least a part of the imaging unit 10 and the signal processing unit 20 are provided to overlap in the direction of the optical axis 410. In the present example, the entire imaging unit 10 is provided substantially completely on the signal processing unit 20. The imaging unit 10 and the signal processing unit 20 are electrically connected to each other through the bumps 15.

  The imaging unit 10 has a pixel unit 11. The pixel unit 11 has a plurality of photoelectric conversion units arranged two-dimensionally in the first direction and the second direction. Each of the plurality of photoelectric conversion units photoelectrically converts incident light. That is, each of the plurality of photoelectric conversion units generates a charge in accordance with the light amount of the light beam incident from the third direction. Therefore, the pixel unit 11 generates an analog image signal according to the photoelectrically converted charge amount. Furthermore, the pixel unit 11 converts an analog image signal into a digital signal. Thereafter, the pixel unit 11 outputs the converted digital signal to the signal processing circuit 22 of the signal processing unit 20.

  The signal processing unit 20 has a signal processing circuit 22 and a focus detection unit 26. The signal processing circuit 22 processes digital signals. The signal processing circuit 22 includes a latch unit 24. The latch unit 24 has a counter circuit. The latch unit 24 generates a pixel value corresponding to an analog image signal by counting digital signals output from the imaging unit 10 using a counter circuit. The generated pixel value is output from the latch unit 24 to the focus detection unit 26 and the image processing unit 624.

  The focus detection unit 26 detects the focus position of the optical system through which the incident light has passed. Specifically, the focus detection unit 26 detects the image shift amount of the pair of images based on the digital image signal. Further, the focus detection unit 26 performs an operation according to the image shift amount, and calculates a defocus amount which is a deviation of the current imaging surface from the planned imaging surface. In order to adjust the defocus amount, the position of the lens in the lens unit 500 of the single-lens reflex camera 400 is adjusted.

  The image processing unit 624 has an image processing ASIC 625 and a recording unit 626. The image processing ASIC 625 performs various types of image processing using the recording unit 626 as a work space to generate image data. When the image processing ASIC 625 generates image data in the JPEG file format, the image processing ASIC 625 performs compression processing after performing white balance processing, gamma processing, and the like. The generated image data is recorded in the recording unit 626. Further, the back surface display unit 634 displays an image corresponding to the image data recorded in the recording unit 626 for a preset time.

  FIG. 3 is a circuit schematic diagram of the pixel unit 11 and the signal processing circuit 22 of the imaging unit 200 in the first embodiment. In the present example, each transistor is an n-type MOS transistor unless otherwise specified. In the two terminals other than the gate of the n-type MOS transistor, a high potential terminal is referred to as a drain, and a low potential terminal is referred to as a source. On the other hand, in the two terminals other than the gate of the p-type MOS transistor, the high potential terminal is referred to as a source, and the low potential terminal is referred to as a drain.

  First, configurations of the pixel unit 11 and the signal processing circuit 22 will be described. The pixel unit 11 has a plurality of pixel sharing units 48. Although only the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 adjacent in the second direction are shown in FIG. 3, the pixel sharing unit 48 further includes the first direction and the second direction. Multiple are provided. A common voltage VDD is applied to each pixel sharing unit 48.

  One pixel sharing unit 48 includes first to fourth photoelectric conversion units 31-L, 31-R, 33-L and 33-R, and first to fourth transfer transistors 32-L, 32-R, 34. L and 34-R, first and second switching transistors 38-L and 38-R, and a differential comparator 49. In this example, the pixel unit 11 in the imaging unit 10 has a differential comparator 49. That is, the imaging unit 10 and the differential comparator 49 are provided on the same semiconductor chip. As described above, the signal processing circuit 22 has the latch unit 24 and the signal source 25, and the latch unit 24 has a plurality of counter circuits 28.

  A common terminal Tx1_L is connected to the gates of the first transfer transistors 32-L in the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2. Similarly, the common terminal Tx1_R is connected to the gates of the second transfer transistors 32-R in the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2. The common terminal Tx2_R is connected to the gate of the third transfer transistor 34-L, and the common terminal Tx2_L is connected to the gate of the fourth transfer transistor 34-R.

  Furthermore, in the plurality of other pixel sharing units 48 continuous in the second direction, the common terminal Tx1_L is common to the gate of the first transfer transistor 32-L, and the common terminal is common to the gate of the second transfer transistor 32-R. The terminal Tx1_R is connected to the gate of the third transfer transistor 34-L, and the common terminal Tx2_L is connected to the gate of the fourth transfer transistor 34-R, and the terminal Tx2_R is connected to the gate of the fourth transfer transistor 34-R. Note that in a row different from the row in which the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are located, different terminals Tx1_L, Tx1_R, Tx2_L, and Tx2_R are provided.

  In addition, the latch unit 24 includes one set of counter circuits 28 corresponding to the plurality of pixel sharing units 48 continuous in the second direction. In FIG. 3, counter circuits 28-1 to 28-4 forming one set of plural counter circuits 28 are shown. The counter circuit 28-1 is connected to the second output unit 44, and the counter circuit 28-1 is connected to the first output unit 43. Two counter circuits 28 are provided for one pixel sharing unit 48. A plurality of latch units 24 are different from the one set of the plurality of counter circuits 28 corresponding to a row different from the row in which the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are located. The counter circuit 28 of FIG.

  The differential comparator 49 includes a first input unit 41, a second input unit 42, a first output unit 43, and a second output unit 44. The differential comparator 49 has a transistor 35 -L whose gate is the first input 41 and a transistor 35 -R whose gate is the second input 42. The sources of transistors 35 -L and 35 -R are shorted and connected to the drain of transistor 30. The source of the transistor 30 is connected to a constant current source. The constant current source connected to the source of the transistor 30 is a constant current source that defines the current flowing to the differential comparator 49.

  The differential comparator 49 includes p-type transistors 36 -L and 36 -R. The voltage VDD is applied to the sources of the p-type transistors 36 -L and 36 -R. Also, the gates of the p-type transistors 36 -L and 36 -R are shorted together and connected to the drain of the p-type transistor 39. The p-type transistors 36 -L and 36 -R function as loads for the differential comparator 49. A constant current source connected to the p-type transistor 39 and the p-type transistor 39 applies a predetermined constant voltage to the gates of the respective p-type transistors 36 -L and 36 -R. Further, a predetermined voltage is applied between the source and the drain of the p-type transistors 36 -L and 36 -R. This causes p-type transistors 36-L and 36-R to operate in the saturation region. With such a configuration, each p-type transistor 36-L and 36-R functions as a high resistance load.

  The drain of the p-type transistor 36 -L is connected to one of the source and the drain of the transistor 37 and the drain of the transistor 35 -L. Similarly, the drain of the p-type transistor 36-R is connected to the other of the source and the drain of the transistor 37 and the drain of the transistor 35-R.

  One of the source and the drain of the P-type transistor 37 is connected to the first output unit 43. The other of the source and the drain of the P-type transistor 37 is connected to the second output unit 44. By turning on the P-type transistor 37, the first output section 43 and the second output section 44 are electrically conducted. Thereby, the voltage level of the 1st output part 43 and the 2nd output part 44 can be equalized.

  The pixel unit 11 inputs, to one of the first input unit 41 and the second input unit 42, an output signal generated according to the charge amount photoelectrically converted in the photoelectric conversion unit 31 or 33. Further, the pixel unit 11 inputs a signal of a reference level from the DAC 46 to the other of the first input unit 41 and the second input unit 42. The differential comparator 49 of this example compares the reference level with the signal level of the voltage signal input to the first input unit 41 and the second input unit 42, and outputs the first output unit 43 and the second output unit 44. A digital signal corresponding to the comparison result is output from one of them.

  In this example, one DAC 46 is provided for each of the plurality of pixel sharing units 48 continuous in the second direction. That is, in a row different from the row in which the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are located, different DACs 46 are provided. Similarly, one terminal Tx1_L, one terminal Tx1_R, one terminal Tx2_L, and one terminal Tx2_R are provided for each of the plurality of pixel sharing units 48 continuous in the second direction. That is, in a row different from the row in which the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are located, different terminals Tx1_L, Tx1_R, Tx2_L, and Tx2_R are provided. As a modification, only one DAC 46 may be provided. In this case, the output of the DAC 46 is provided row by row using a selector or decoder.

  The counter circuit 28-2 of the latch unit 24 compares the signal level of the first photoelectric conversion unit 31 -L or the third photoelectric conversion unit 33 -L with the reference level input from the DAC 46. A digital signal of 1 is input. Further, the counter circuit 28-1 of the latch unit 24 compares the signal level of the second photoelectric conversion unit 31-R or the fourth photoelectric conversion unit 33-R with the reference level input from the DAC 46. A certain second digital signal is input. When the first digital signal is input from the first output unit 43 to the counter circuit 28-2, the second digital signal may not be used. Conversely, when the second digital signal is input from the second output unit 44 to the counter circuit 28-1, the first digital signal may not be used. That is, the first digital signal and the second digital signal may be switched and input to the latch unit 24.

  In this example, when the voltage value of the signal input to the first input unit 41 is lower than the voltage value of the signal input to the second input unit 42, the first output unit 43 transmits the signal to the counter circuit 28-2. A high voltage signal is output. On the other hand, when the voltage value input to the first input unit 41 is higher than the voltage value input to the second input unit 42, the low voltage signal is output from the first output unit 43 to the counter circuit 28-2. Be done.

  Similarly, when the voltage value input to the second input unit 42 is lower than the voltage value input to the first input unit 41, a high voltage signal is output from the second output unit 44 to the counter circuit 28-1. Be done. On the other hand, when the voltage value input to the second input unit 42 is higher than the voltage value input to the first input unit 41, the second output unit 44 outputs a low voltage signal to the counter circuit 28-1. .

  The signal source 25 supplies a pulse signal of a constant cycle to each counter circuit 28. In this example, the timing at which the magnitude relationship between the voltage value of the first input unit 41 or the second input unit 42 and the voltage value of the reference signal of the ramp waveform of the DAC 46 changes is specified using the pulse signal of the constant cycle. Ru. The fixed period of the pulse signal may be a time width corresponding to the minimum step width of the voltage value in the ramp waveform output by the DAC 46.

  The counter circuit 28-2 is a signal from the timing when the ramp waveform of monotonous increase is input to the second input section 42 to the timing when the voltage value of the second input section 42 becomes equal to or higher than the voltage value of the first input section 41. Count the number of pulses of source 25. The period is referred to as a first count period for convenience. The number of pulses counted in the first count period is treated as a reset level in the photoelectric conversion unit 31 or 33. In addition, the counter circuit 28-2 is a period from the timing when the monotonically decreasing ramp waveform is input to the second input unit 42 to the timing when the voltage value of the second input unit 42 becomes less than or equal to the voltage value of the first input unit 41. Count the number of pulses of the signal source 25 in The period is referred to as a second count period for convenience. The number of pulses counted in the second count period is treated as an output level in the photoelectric conversion unit 31 or 33. The value obtained by subtracting the reset level from the output level is treated as a pixel value in the digital image signal. Since the second count period becomes longer as the amount of charge accumulated in the photoelectric conversion unit 31 or 33 increases, the number of pulses counted in the second count period increases.

  The cathode of the first photoelectric conversion unit 31-L is connected to the source of the first transfer transistor 32-L. The drain of the first transfer transistor 32-L is connected to the first input unit 41. The first transfer transistor 32-L switches whether to connect the first photoelectric conversion unit 31-L to the first input unit 41 or not. The cathode of the second photoelectric conversion unit 31-R is connected to the source of the second transfer transistor 32-R. The drain of the second transfer transistor 32-R is connected to the second input unit 42. The second transfer transistor 32-R switches whether to connect the second photoelectric conversion unit 31-R to the second input unit 42 or not.

  The cathode of the third photoelectric conversion unit 33-L is connected to the source of the third transfer transistor 34-L. The drain of the third transfer transistor 34 -L is connected to the first input unit 41. The third transfer transistor 34 -L switches whether to connect the third photoelectric conversion unit 33 -L to the first input unit 41. The cathode of the fourth photoelectric conversion unit 33-R is connected to the source of the fourth transfer transistor 34-R. The drain of the fourth transfer transistor 34 -R is connected to the second input unit 42. The fourth transfer transistor 34 -R switches whether to connect the fourth photoelectric conversion unit 33 -R to the second input unit 42.

  The DAC 46, which is a digital-to-analog converter, is provided in the imaging unit 200. The drain of the first switching transistor 38 -L and the drain of the second switching transistor 38 -R are both connected to the DAC 46. The gate of the first switching transistor 38-L is connected to the terminal R_L, and the gate of the second switching transistor 38-R is connected to the terminal R_R. The source of the first switching transistor 38 -L is connected to the first input 41, and the source of the second switching transistor 38 -R is connected to the second input 42.

  The DAC 46 sequentially generates a reference level having a ramp waveform and a reset level having a pulse waveform. For example, when resetting the charge stored in the first input unit 41, the DAC 46 generates a reset level signal having a pulse waveform. Then, the terminal R_L outputs a high voltage to turn on the first switching transistor 38-L. Thus, before connecting the first photoelectric conversion unit 31-L to the first input unit 41, the first switching transistor 38-L connects the first input unit 41 and the first transfer transistor 32-L. A reset level signal can be input to the wiring between them. Thereby, the charge accumulated in the first input unit 41 is removed.

  Similarly, when resetting the charge stored in the second input section 42, the DAC 46 generates a reset level signal having a pulse waveform. Then, the terminal R_R outputs a high voltage to turn on the second switching transistor 38-R. Thus, before connecting the second photoelectric conversion unit 31-R to the second input unit 42, the second switching transistor 38-R connects the second input unit 42 and the second transfer transistor 32-R. A reset level signal can be input to the wiring between them. Thereby, the charge accumulated in the second input unit 42 is removed.

  The first switching transistor 38 -L also switches whether to input the reference level of the DAC 46 to the first input unit 41. Similarly, the second switching transistor 38 -R switches whether to input the reference level of the DAC 46 to the second input unit 42. For example, when the reference level of the ramp waveform is input to the first input unit 41, the DAC 46 generates a signal of the ramp waveform. Then, the terminal R_L outputs a high voltage to turn on the first switching transistor 38-L. When the terminal R_L outputs a low voltage, the first switching transistor 38-L is turned off.

  In this example, the latch unit 24 is provided not in the imaging unit 10 but in the signal processing circuit 22 in the signal processing unit 20. Thereby, in the imaging unit 10, the area equivalent to the latch unit 24 can be allocated to the pixel sharing unit 48. In addition, in the pixel sharing unit 48, one differential comparator 49 is provided for the first to fourth photoelectric conversion units 31-L to 33-R. As a result, compared to the conventional example in which one comparison unit is provided for one photodiode, the area occupied by the photoelectric conversion units 31 and 33 in the pixel unit 11 can be increased. Therefore, in the pixel unit 11 having the differential comparator 49, the photoelectric conversion units 31 and 33 can be provided at a higher density than in the conventional case.

  In this example, the constant current source connected to the drain of the p-type transistor 39 and the constant current source connected to the source of the transistor 30 are described as components of the pixel portion 11. However, the constant current source may be provided in the imaging unit 200 and may not necessarily be provided in the pixel unit 11. Alternatively, one constant current source may be provided in one pixel sharing unit 48, and the drain of the p-type transistor 39 and the source of the transistor 30 may be commonly connected.

  Next, the operation of the differential comparator 49 will be described. The differential comparator 49 of this example compares the voltage value of the analog image signal input to the first input unit 41 with the voltage value of the ramp voltage of the DAC 46 input to the second input unit 42. In the present specification, the comparison operation is referred to as a first comparison operation. In the first comparison operation, the differential comparator 49 compares, for example, the signal level of the first photoelectric conversion unit 31-L with the reference level of the ramp waveform. In this case, the pixel unit 11 inputs the output signal of the first photoelectric conversion unit 31 -L to the first input unit 41 and inputs the reference level of the ramp waveform to the second input unit 42.

  In the first comparison operation, an analog image signal is input to the first input unit 41 from any one of the first photoelectric conversion unit 31-L and the third photoelectric conversion unit 33-L. The first transfer transistor 32-L outputs the charge accumulated in the first photoelectric conversion unit 31-L to the first input unit 41. Similarly, the third transfer transistor 34 -L outputs the charge accumulated in the third photoelectric conversion unit 33 -L to the first input unit 41. The first transfer transistor 32-L and the third transfer transistor 34-L can be selectively turned on by selectively setting the terminals Tx1_L and Tx2_L to a high voltage at different timings. Thereby, the first transfer transistor 32-L and the third transfer transistor 34-L have different timings for the charges accumulated in the first photoelectric conversion unit 31-L and the third photoelectric conversion unit 33-L. Output to the first input unit 41. Accordingly, analog image signals are input to the first input unit 41 at different timings from the first photoelectric conversion unit 31 -L and the third photoelectric conversion unit 33 -L.

  In the first comparison operation, a reference signal of a ramp waveform is input from the DAC 46 to the second input unit 42. The voltage value of the ramp waveform reference signal monotonously increases or decreases with time. In the first comparison operation, the DAC 46 of this example inputs a reference signal that monotonously decreases from the high voltage value to the low voltage value to the second input unit 42. In another operation, the DAC 46 inputs a high voltage reference signal to the second input unit 42 for a predetermined time. In yet another operation, the DAC 46 inputs to the second input 42 a reference signal that monotonously decreases from the low voltage value to the high voltage value.

  When the first comparison operation is not performed, the terminal R_L outputs a high voltage to turn on the first switching transistor 38-L, and the DAC 46 outputs a high voltage, thereby the first input unit. 41 can be the high voltage of the DAC 46. As a result, since the charge output to the first input unit 41 can be removed, the charge output to the first input unit 41 is not affected by the previously output charge.

  Further, the differential comparator 49 of this example compares the voltage signal of the analog image signal input to the second input unit 42 with the reference signal of the ramp waveform of the DAC 46 input to the first input unit 41. In the present specification, the comparison operation is referred to as a second comparison operation. For example, in the second comparison operation, the differential comparator 49 compares the signal level of the second photoelectric conversion unit 31-R with the reference level. In this case, the pixel unit 11 inputs the output signal of the second photoelectric conversion unit 31 -R to the second input unit 42 and inputs the reference level to the first input unit 41.

  In the second comparison operation, an analog image signal is input to the second input unit 42 from any one of the second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R. The second transfer transistor 32-R outputs the charge accumulated in the second photoelectric conversion unit 31-R to the second input unit 42. Similarly, the fourth transfer transistor 34 -R outputs the charge stored in the fourth photoelectric conversion unit 33 -R to the second input unit 42. The second transfer transistor 32-R and the fourth transfer transistor 34-R can be selectively turned on by selectively setting the terminals Tx1_R and Tx2_R to a high voltage at different timings. Thereby, the second transfer transistor 32-R and the fourth transfer transistor 34-R have different timings for the charges accumulated in the second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R. Output to the second input unit 42. Accordingly, analog image signals are input to the second input unit 42 at different timings from the second photoelectric conversion unit 31 -R and the fourth photoelectric conversion unit 33 -R.

  In the second comparison operation, a ramp voltage is input from the DAC 46 to the first input unit 41. The voltage signal of the DAC 46 in the second comparison operation is similar to the first comparison operation. When the second comparison operation is not performed, the terminal R_R outputs a high voltage to turn on the second switching transistor 38-R, and the DAC 46 outputs a high voltage, thereby the second input unit. 42 can be the high voltage of the DAC 46. Thereby, the charge output to the second input unit 42 can be removed. Therefore, the charge output to the second input unit 42 is not affected by the charge output previously.

  FIG. 4 is a time chart diagram for explaining the operation of the imaging unit 200. As shown in FIG. The horizontal axis shows time. The vertical axis of each signal indicates a voltage value. Tx1_L and Tx1_R respectively indicate voltage values outputted from the terminals Tx1_L and Tx1_R of FIG. Tx2_L and Tx2_R respectively indicate voltage values outputted from the terminals Tx2_L and Tx2_R of FIG. R_L and R_R respectively indicate voltage values output from the terminals R_L and R_R of FIG. R_c represents the voltage value of the gate of the P-type transistor 37 in FIG. DAC indicates a voltage value output from the DAC 46 in FIG. Further, FIG. 4 shows voltage values of the first input unit 41, the second input unit 42, the first output unit 43, and the second output unit 44 of FIG.

  From time t1 to t9, the charge photoelectrically converted in the first photoelectric conversion unit 31-L is output to the counter circuit 28-2 as a digital signal. The time from time t1 to t9 corresponds to the first comparison operation. From time t9 to t10, the charge photoelectrically converted in the second photoelectric conversion unit 31-R is output to the counter circuit 28-1 as a digital signal. The time from time t9 to time t10 corresponds to the second comparison operation.

  From time t10 to t11, the charge photoelectrically converted in the third photoelectric conversion unit 33-L is output to the counter circuit 28-2. After time t11, the charge photoelectrically converted in the fourth photoelectric conversion unit 33-R is output to the counter circuit 28-1. The operation after time t9 is a repetition of the operation from time t1 to t9, so only the operation from time t1 to t9 will be described below. In addition, since the output of the second output unit 44 is not used by the counter circuit 28-1 from time t1 to t9, it is illustrated as a low voltage. Likewise, the output not used by the counter circuit 28 is illustrated as a low voltage in other periods.

  At time t1, the terminal R_L becomes a high voltage. Also, at time t1, the DAC 46 outputs a reset voltage. As a result, the first switching transistor 38-L is turned on, and the charge of the first input unit 41 is reset. Further, at time t1, R_c becomes a low voltage. As a result, the P-type transistor 37 is turned on, and the first input portion 41 and the second input portion 42 have the same potential. The high voltage of the terminal R_L and the DAC 46 continues until time t2. R_c changes to a high voltage before time t2. From time t1 to t2, the first input unit 41 has a high voltage.

  At time t2, the terminal R_L and the DAC 46 become low voltage. Thereby, the first switching transistor 38-L is turned off. Also, at time t2, the terminal R_R is at high voltage. Thereby, the second switching transistor 38-R is turned on. While the second switching transistor 38-R is on, the potential of the second input unit 42 can follow the potential of the DAC 46 to be a high voltage. The DAC 46 is at low voltage until time t3. In addition, since the reset operation is completed, the terminal R_L becomes a low voltage from t2 to t9, and the first switching transistor 38-L is turned off.

  At time t3, the second switching transistor 38-R is in the on state. Also, the DAC 46 inputs a monotonically increasing ramp voltage. Since the terminal R_R maintains a high voltage, a monotonically increasing ramp voltage is input to the second input unit 42. The maximum value of the ramp voltage output by the DAC 46 is larger than the reset voltage output by the DAC 46 at time t1.

  After time t3 and before time t4, the potential of the first input unit 41 is higher than the reference voltage input to the second input unit 42. Thus, the first output unit 43 outputs a low voltage. However, at time t4, the potential of the first input unit 41 becomes lower than the reference voltage input to the second input unit. Thus, the first output unit 43 outputs a high voltage. It should be noted that the period from t3 when the monotonically increasing ramp waveform is input to the second input portion 42 to t4 when the voltage value of the second input portion 42 becomes equal to or higher than the voltage value of the first input portion 41 is This corresponds to the first count period described in the description of FIG.

  At time t5, the terminal Tx1_L becomes high voltage. Thereby, transfer of charge from the first photoelectric conversion unit 31 -L to the first input unit 41 is started. Between time t5 and time t6, the terminal Tx1_L maintains a high voltage. As a result, the potential of the first input unit 41 is lowered by an amount corresponding to the voltage corresponding to the accumulated charge amount from time t5 to time t6.

  At time t6 to t7, the DAC 46 maintains a high voltage. At time t7, the DAC 46 starts to input a monotonically decreasing ramp voltage. At time t7, the terminal R_R is in the on state. As a result, the second switching transistor 38 -R is turned on, and a monotonically decreasing ramp voltage is input to the second input unit 42.

  At time t8, the potential of the first input unit 41 becomes higher than the reference voltage input to the second input unit 42. Thus, the first output unit 43 outputs a low voltage. A period from t7 when the monotonically decreasing ramp waveform is input to the second input portion 42 to t8 when the voltage value of the second input portion 42 becomes less than or equal to the voltage value of the first input portion 41 is This corresponds to the second count period described in the description of FIG.

  FIG. 5 is a diagram showing an element layout of the pixel unit 11. Similarly to FIG. 3, the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are indicated by dotted lines. The first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 have the same configuration. The first photoelectric conversion unit 31-L and the third photoelectric conversion unit 33-L are provided side by side in the first direction. Similarly, the second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R are provided side by side in the first direction. The first photoelectric conversion unit 31-L and the third photoelectric conversion unit 31-R are provided side by side in a second direction perpendicular to the first direction. Similarly, the third photoelectric conversion unit 33-L and the fourth photoelectric conversion unit 33-R are provided side by side in the second direction.

  In the region of the first photoelectric conversion unit 31-L, a first transfer transistor 32-L is provided in an overlapping manner. In the region of the second photoelectric conversion unit 31-R, a second transfer transistor 32-R is provided in an overlapping manner. Furthermore, a third transfer transistor 34-L is provided in an overlapping manner in the region of the third photoelectric conversion unit 33-L. In addition, in the region of the fourth photoelectric conversion unit 33-R, the fourth transfer transistor 34-R is provided in an overlapping manner.

  The differential comparator 49 is provided between the first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R, and the third photoelectric conversion unit 33-L and the fourth photoelectric conversion unit 33-R. Provided between The differential comparator 49 is shown by a dotted line frame. The first input unit 41 and the second input unit 42 are provided to have long sides parallel to the first direction. The first input portion 41 is adjacent to the first transfer transistor 32-L and the third transfer transistor 34-L in the second direction. Similarly, the second input unit 42 is adjacent to the second transfer transistor 32-R and the fourth transfer transistor 34-R in the second direction.

  According to this configuration, the first input portion 41 can be provided close to the first transfer transistor 32-L and the third transfer transistor 34-L. In addition, the second input unit 42, the second transfer transistor 32-R, and the fourth transfer transistor 34-R can be provided close to each other. Therefore, the wiring length between the input unit and the transfer transistors 32 and 34 can be shortened. Thus, the signal delay between the transfer transistors 32 and 34 and the input, and the noise generated between the transfer transistors 32 and 34 and the input can be reduced.

  FIG. 6 is a view showing the positional relationship between the photoelectric conversion unit 31 and the photoelectric conversion unit 33 and the microlens 50 in the pixel unit 11. The first photoelectric conversion unit 31-L, the second photoelectric conversion unit 31-R, the third photoelectric conversion unit 33-L, and the fourth photoelectric conversion unit 33-R are the same as those in FIG. The photoelectric conversion units 31 and 33 are simply illustrated as squares. The microlens 50 is indicated by a circle. The microlens 50 and the photoelectric conversion unit 31 and the photoelectric conversion unit 33 are provided in the order of the microlens 50 and the photoelectric conversion unit 31 or the photoelectric conversion unit 33 in the third direction. A light flux incident from a subject passes through each of the microlenses 50 and is incident on the photoelectric conversion unit 31 and the photoelectric conversion unit 33.

  FIG. 7 is a view showing a modification of the positional relationship between the photoelectric conversion unit 31 and the photoelectric conversion unit 33 and the microlens 50 in the pixel unit 11. In this example, the first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R or the third photoelectric conversion unit 33-L and the fourth photoelectric conversion are provided corresponding to one microlens 50. It differs from the example of FIG. 6 in that a section 33-R is provided. For example, one microlens 50 is provided commonly to the first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R.

  The first photoelectric conversion unit 31 -L and the second photoelectric conversion unit 33 -L are adjacent in the first direction. The second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R are also adjacent in the first direction. In addition, the first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R are adjacent in the second direction. The third photoelectric conversion unit 33-L and the fourth photoelectric conversion unit 33-R are also adjacent in the second direction.

  The focus detection line 70 includes a plurality of first photoelectric conversion units 31 -L and second photoelectric conversion units 31 -R adjacent in the second direction in the second direction. One image is generated from the charges photoelectrically converted in the plurality of first photoelectric conversion units 31 -L in the focus detection line 70. Also, another image is generated from the charges photoelectrically converted in the plurality of second photoelectric conversion units 31 -R in the focus detection line 70. By comparing the one image with the other image, the image shift amount of the pair of images described above is calculated. Thus, the focus detection line 70 can be used to detect the focus of the optical system.

  FIG. 8 is a circuit schematic diagram of the pixel unit 12 and the signal processing circuit 22 of the imaging unit 300 in the second embodiment. The difference from the first embodiment is the configuration of the pixel sharing unit 58. In addition to the configuration of the pixel sharing unit 48 in the first embodiment, the pixel sharing unit 58 of this example includes a fifth transfer transistor 82 -L and a sixth transfer transistor 82 -R, and a first diode 81-. It further includes an L and a second diode 81-R, a seventh transfer transistor 84-L and an eighth transfer transistor 84-R, and a third diode 83-L and a fourth diode 83-R.

  The fifth transfer transistor 82 -L is provided between the first transfer transistor 32 -L and the first input unit 41. The sixth transfer transistor 82-R is provided between the second transfer transistor 32-R and the second input unit 42. Similarly, the seventh transfer transistor 84 -L is provided between the third transfer transistor 34 -L and the first input portion 41, and the eighth transfer transistor 84 -R is a fourth transfer transistor 34. Provided between R and the second input unit 42;

  The cathode of the first diode 81-L is provided between the drain of the first transfer transistor 32-L and the source of the fifth transfer transistor 82-L. The anode of the first diode 81-L is grounded. The cathode of the second diode 81-R is provided between the drain of the second transfer transistor 32-R and the source of the sixth transfer transistor 82-R. The cathode of the third diode 83 -L is provided between the drain of the third transfer transistor 34 -L and the source of the seventh transfer transistor 84 -L. The cathode of the fourth diode 83-R is provided between the drain of the fourth transfer transistor 34-R and the source of the eighth transfer transistor 84-R. The anodes of the second diode 81 -R, the third diode 83 -L and the fourth diode 83 -R are provided.

  The fifth transfer transistor 82-L switches whether to output the charge transferred from the first transfer transistor 32-L to the first input unit 41 or not. Similarly, the seventh transfer transistor 84 -L switches whether to output the charge transferred from the third transfer transistor 34 -L to the first input unit 41. The sixth transfer transistor 82 -R switches whether to output the charge transferred from the second transfer transistor 32 -R to the second input unit 42. Similarly, the eighth transfer transistor 84 -R switches whether to output the charge transferred from the fourth transfer transistor 34 -R to the second input unit 42.

  The charge transferred from the first transfer transistor 32-L to the cathode of the first diode 81-L is held at the cathode of the first diode 81-L for a predetermined period. By properly adjusting the characteristics of the first diode 81-L, the pn junction interface of the first diode 81-L is completely depleted. As a result, the charge is transferred to the cathode of the first diode 81-L and held there, so that the charge is prevented from flowing to the ground and disappearing. The second diode 81 -R, the third diode 83 -L and the fourth diode 83 -R similarly hold the charge transferred to the cathode.

  FIG. 9 is a time chart diagram for explaining the operation of the imaging unit 300 in the second embodiment. This example is a so-called global shutter method. In the global shutter system, all the first transfer transistors 32-L, the second transfer transistors 32-R, the third transfer transistors 34-L, and the fourth transfer of all the pixel sharing units 58 in the pixel unit 12 The transistor 34-R is simultaneously turned on. Thereby, the charges accumulated in the first photoelectric conversion unit 31-L, the second photoelectric conversion unit 31-R, the third photoelectric conversion unit 33-L, and the fourth photoelectric conversion unit 33-R are simultaneously From the first transfer transistor 32-L, the second transfer transistor 32-R, the third transfer transistor 34-L and the fourth transfer transistor 34-R, the first diode 81-L, the second diode 81 R, transferred to the cathode of the third diode 83 -L and the fourth diode 83 -R, respectively. Thereby, as compared with the rolling shutter method in which charge transfer is performed for each of the plurality of photoelectric conversion units 31 or the plurality of photoelectric conversion units 33 provided continuously in the first direction, Distortion can be improved.

  In this example, the first transfer transistor 32-L and the second transfer transistor 32-R, and the third transfer transistor 34-L and the fourth transfer transistor 34-R simultaneously operate from time t1 to time t2. It is turned on. Note that the first transfer transistor 32-L and the second transfer transistor 32-R, and the third transfer transistor 34-L and the fourth transfer transistor 32-L and the fourth transfer transistor 32-L and the fourth transfer transistor 32-L are also used in the pixel sharing unit 58 other than the pixel sharing unit 58 shown. The transfer transistor 34-R is turned on simultaneously from time t1 to time t2.

  The charge transferred from the first transfer transistor 32-L, the second transfer transistor 32-R, the third transfer transistor 34-L, and the fourth transfer transistor 34-R is temporarily transferred to the first diode 81-. L, the second diode 81-R, the third diode 83-L, and the cathode of the fourth diode 83-R. The subsequent operation is the same as the operation of the first embodiment in FIG. Tx in FIG. 4 corresponds to Ts in FIG. That is, the charges held at the cathodes of the first diode 81 -L, the second diode 81 -R, the third diode 83 -L and the fourth diode 83 -R are transferred to the fifth transfer transistor 82-. L, the sixth transfer transistor 82-R, the seventh transfer transistor 84-L, and the eighth transfer transistor 84-R are sequentially turned on to sequentially transfer data to the first input unit 41 or the second input unit 42. Ru. For example, the fifth transfer transistor 82-L is turned on by setting the terminal Ts1_L to a high voltage, and the charge held at the cathode of the first diode 81-L is output to the first input unit 41.

  In the first and second embodiments, in one differential comparator 49, the outputs of the two photoelectric conversion units 31-L and 33-L are connected to the first input unit 41, and the other two photoelectric conversion units 31 The configuration in which the outputs of -R and 33-R are connected to the second input unit 42 is shown. However, one differential comparator 49 may be further provided with a plurality of photoelectric conversion units. That is, the outputs of the four photoelectric conversion units may be connected to the first input unit 41, and the outputs of the other four photoelectric conversion units may be connected to the second input unit 42. The outputs of the eight photoelectric conversion units may be connected to the first input unit 41, and the outputs of the other eight photoelectric conversion units may be connected to the second input unit 42. The output from each photoelectric conversion unit to the first input unit 41 or the second input unit 42 may be controlled using the terminal Tx common to the gates of each row as in the first embodiment, or the second embodiment As in the embodiment, the control may be performed using the terminal Tx and the terminal Ts common to the gate of each row. By connecting the outputs of eight or more photoelectric conversion units to one differential comparator 49, the number of photoelectric conversion units for one differential comparator 49 is greater than when the outputs of four photoelectric conversion units are connected. To increase. Since a certain occupied area is necessary to configure one differential comparator 49, the ratio of the occupied area of the differential comparator 49 to one photoelectric conversion unit can be reduced by this configuration.

  FIG. 10 is a circuit schematic diagram of the pixel unit 13 and the signal processing circuit 22 of the imaging unit 310 in the third embodiment. The difference from the first embodiment is the configuration of the pixel sharing unit 68. The pixel sharing unit 68 of this example includes a first photoelectric conversion unit 31-L, a first transfer transistor 32-L, a first switching transistor 38-L and a second switching transistor 38-R, and a differential. A comparator 49 is provided. The latch unit 24 has one counter circuit 28 for one pixel sharing unit 68.

  In this example, the signal level of the output signal generated in accordance with the amount of charge photoelectrically converted in the first photoelectric conversion unit 31 -L is input to the first input unit 41. Also, the reference level of the DAC 46 is input to the second input unit 42. Then, the signal level of the output signal and the reference level of the DAC 46 are compared. The operation of comparison is similar to that of the first embodiment. The comparison result is output from the first output unit 43 to the counter circuit 28-2.

  According to the configuration of this example, the latch unit 24 is provided not in the imaging unit 10 but in the signal processing circuit 22 of the signal processing unit 20. Thereby, in the imaging unit 10, the area equivalent to the latch unit 24 can be allocated to the pixel sharing unit 68. As a result, compared to the conventional example in which one differential comparator 49 is provided for one photodiode, the area occupied by the photoelectric conversion units 31 and 33 in the pixel unit 13 can be increased. Therefore, in the pixel unit 13 having the differential comparator 49, the photoelectric conversion units 31 and 33 can be provided at a higher density than in the prior art. In the first embodiment, four photoelectric conversion units 31 and 33 are provided for one differential comparator 49. Therefore, in the first embodiment, the ratio of the area occupied by the differential comparator 49 to one photoelectric conversion unit can be reduced as compared with the third embodiment.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It is apparent to those skilled in the art that various changes or modifications can be added to the above embodiment. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the present invention.

  The execution order of each process such as operations, procedures, steps, and steps in the apparatuses, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly “before”, “preceding” It is to be noted that “it is not explicitly stated as“ etc. ”and can be realized in any order as long as the output of the previous process is not used in the later process. With regard to the flow of operations in the claims, the specification and the drawings, even if it is described using “first,” “next,” etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

Reference Signs List 10 imaging unit, 11 pixel unit, 12 pixel unit, 13 pixel unit, 15 bump, 20 signal processing unit, 22 signal processing circuit, 24 latch unit, 25 signal source, 26 focus detection unit, 28 counter circuit, 30 transistor, 31 Photoelectric conversion unit, 32 transfer transistors, 33 photoelectric conversion units, 34 transfer transistors, 35 transistors, 36 transistors, 37 transistors, 38 switching transistors, 39 transistors, 41 first input unit, 42 second input unit, 43 first output unit , 44 second output unit, 46 DAC, 48 pixel sharing unit, 49 differential comparator, 50 micro lens, 58 pixel sharing unit, 68 pixel sharing unit, 70 focus detection line, 81 diode, 82 transfer transistor, 83 diode, 84 Transfer transistor, 200 imaging unit 300 imaging unit 310 imaging unit 340 shutter unit 410 optical axis 400 single lens reflex camera 500 lens unit 550 lens mount 600 camera body 620 body substrate 622 CPU 624 image processing unit 625 image Processing ASIC, 626 recording unit, 634 rear display unit, 650 finder, 652 focusing plate, 654 pentaprism, 656 finder optical system, 660 body mount, 670 mirror box, 672 mirror

Claims (12)

  A first photoelectric conversion unit and a second photoelectric conversion unit that generate light by photoelectrically converting light;
  A first input unit to which a first signal or a reference signal based on the charge generated by the first photoelectric conversion unit is input, and a second signal or the reference signal based on the charge generated by the second photoelectric conversion unit A comparator having a second input unit to be input, and comparing the first signal or the second signal with the reference signal;
  An imaging device comprising:   When the comparator compares the first signal with the reference signal, the first signal is input to the first input section, and the reference signal is input to the second input section.
  The said 2nd signal is input into the said 2nd input part, and when the said comparator compares the said 2nd signal and the said reference signal, the said reference signal is input into the said 1st input part. Image sensor.   The first signal and the second signal are analog signals,
  The comparator has an output unit that compares the first signal or the second signal with the reference signal and outputs a signal for converting the first signal and the second signal into a digital signal. Item 3. The imaging device according to item 1 or 2. The a 1 rolling feed transistor capable of switching electrical connection between said first photoelectric conversion portion and the first input unit,
A second rolling feed transistor capable of switching electrical connection between the said second photoelectric conversion unit second input unit,
A first SWITCHING transistor capable of switching electrical connection between the generator of the reference signal is generated said first input unit,
A second SWITCHING transistor capable of switching electrical connection between the second input unit and the generating unit,
The imaging device according to any one of claims 1 to 3, further comprising: The generation unit generates a reset signal for resetting at least one of the charges generated by the first photoelectric conversion unit and the second photoelectric conversion unit,
The first SWITCHING transistor, before connecting to the first input portion and said first photoelectric conversion unit, and connecting said generator and said first input unit which generates the reset signal,
Said second SWITCHING transistor, before connecting to the second input unit and said second photoelectric conversion portion, claim connecting the generator and the second input unit which generates the reset signal 4 The imaging device as described in. And wherein the first rolling feed transistor provided between the first input unit, a first storage section for storing said first generated charges in the photoelectric conversion unit,
A fifth rolling feed transistor capable of switching electrical connection between said first input portion and said first storage unit,
And wherein the second rolling feed transistor provided between the second input section, a second storage section for storing the second generated electric charges in the photoelectric conversion unit,
The a 6 rolling feed transistor capable of switching electrical connection between the second input unit and the second storage section,
The imaging device according to claim 4, further comprising: A third photoelectric conversion unit and a fourth photoelectric conversion unit that generate light by photoelectrically converting light ;
The first input unit receives a third signal based on the charge generated by the third photoelectric conversion unit .
The second input unit receives a fourth signal based on the charge generated by the fourth photoelectric conversion unit,
A third rolling feed transistor capable of switching electrical connection between said third photoelectric conversion unit wherein the first input unit,
A fourth rolling feed transistor capable of switching electrical connection between the second input and the fourth photoelectric conversion unit,
The imaging device according to any one of claims 1 to 6, further comprising: Further equipped with a microlens ,
Wherein the first photoelectric conversion unit and the second photoelectric conversion unit image sensor according to any one of claims 1 7 for photoelectrically converting light transmitted through the microlens. Before Kiko comparator, the imaging device according to any one of the 請 Motomeko 1 that provided 8 between the first photoelectric conversion unit and the second photoelectric conversion unit. A signal based on the comparison between the reference signal and the pre-Symbol first signal, any one of the second signal from claim 1, and a signal based on the comparison further comprises a latch portion that is input and the reference signal 9 The imaging element as described in a term. Wherein the comparator and the latch portion, at least a portion in the direction in which light is incident is provided on top, the image pickup device according to claim 10 which is electrically connected by bumps. An imaging device comprising the imaging device according to any one of claims 1 to 11.

Images