JP6545399B2 - INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM - Google Patents

Description

  The present invention relates to an information processing apparatus, an information processing method, and an information processing program.

Patent Document 1 discloses a method for solving the conventional LHP problem. In the method disclosed in Patent Document 1, pCPUs (real CPUs) are preferentially allocated to vCPUs (virtual CPUs) that have acquired lock of the OS. Thus, in the method disclosed in Patent Document 1, the solution of the LHP state is performed to suppress the performance deterioration of GPOS (general-purpose OS). LHP is an abbreviation of Lock Holder Preemption. OS is an abbreviation of Operating System. CPU is an abbreviation of Central Processing Unit.
Further, Non-Patent Document 1 discloses a method for solving the LHP state when a pCPU assigned to a vCPU that has acquired a GPOS lock is assigned as a RTOS (Real-Time OS) vCPU. ing. In Non-Patent Document 1, the LHP problem is solved by causing a vCPU that has acquired a GPOS lock to release a lock by reassigning a pCPU assigned to another vCPU under the GPOS.

Unexamined-Japanese-Patent No. 2006-099182

Hitoshi Mishima, "Resolution of the Lock Holder Preemption Problem with Real-Time Virtual Machine Monitor" 2011 Master's Thesis, 31 January 2012, p. 4 to 23

  However, in the conventional method for solving the LHP problem, the amount of processing required to migrate the vPOS of GPOS, which has passed the pCPU to the vCPU of RTOS, to another pCPU is increased. Therefore, this conventional method has a problem that the performance degradation of GPOS can not be sufficiently improved.

  An object of the present invention is to prevent GPOS performance degradation while maintaining RTOS response performance.

An information processing apparatus according to the present invention is a first execution unit that includes a plurality of CPUs as multiprocessors and executes a first OS using any CPU of the plurality of CPUs as an execution CPU, the execution CPU An information processing apparatus comprising a first execution unit that executes a first OS after acquiring a lock indicating that the second OS is being used to execute the first OS;
A confirmation unit that confirms whether the lock has been acquired for the execution CPU when an interrupt process for executing the second OS occurs;
A selection unit that selects a CPU to which the execution of the second OS is to be transferred from the plurality of CPUs as a transfer destination CPU when the lock is acquired for the execution CPU;
And a second execution unit that causes the transfer destination CPU to execute the second OS.

  An information processing apparatus according to the present invention includes a plurality of CPUs as multiprocessors. The first execution unit executes the first OS using any one of the plurality of CPUs as an execution CPU. The first execution unit executes the first OS after acquiring a lock indicating that the execution CPU is being used to execute the first OS. Further, when an interrupt process for executing the second OS occurs, the confirmation unit confirms whether the lock is acquired for the execution CPU. In addition, when the lock is acquired for the execution CPU, the selection unit selects the CPU to which the execution of the second OS is to be transferred from the plurality of CPUs as the transfer destination CPU. Then, the second execution unit causes the transfer destination CPU to execute the second OS. Therefore, according to the information processing apparatus of the present invention, it is possible to prevent the performance deterioration of the GPOS which is the first OS while maintaining the response performance of the RTOS which is the second OS.

FIG. 2 is a hardware configuration diagram of the information processing apparatus 100 according to the first embodiment. FIG. 2 is a functional configuration diagram of the information processing apparatus 100 according to the first embodiment. FIG. 7 is a flowchart of lock acquisition processing S30 according to the first embodiment. FIG. 8 is a flowchart of lock release processing S40 according to the first embodiment. FIG. 7 is a flowchart of transfer source CPU processing S50 according to the first embodiment. FIG. 7 is a flowchart of confirmation processing S51 according to the first embodiment. FIG. 7 is a flowchart of selection processing S52 according to the first embodiment. FIG. 7 is a flowchart of request transmission processing S53 according to the first embodiment. FIG. 7 is a flowchart of a transfer destination CPU process S60 according to the first embodiment. FIG. 10 is a flowchart of acknowledgment processing S61 according to the first embodiment. FIG. 10 is a flowchart of an execution preparation process S62 according to the first embodiment. 5 is a configuration diagram of a lock table 219a according to Embodiment 2. FIG. FIG. 16 is a flowchart of a selection process S52a according to the second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals. In the description of the embodiment, the description of the same or corresponding parts will be omitted or simplified as appropriate.

Embodiment 1
*** Description of the configuration ***
The hardware configuration of the information processing apparatus 100 according to the present embodiment will be described using FIG. 1.
The information processing apparatus 100 includes a CPU 101, a CPU 102, a CPU 103, and a CPU 104 as a multiprocessor. The CPU 101, the CPU 102, the CPU 103, and the CPU 104 constitute a multiprocessor. In the following, the CPU 101, the CPU 102, the CPU 103, and the CPU 104 may be described as the CPUs 101 to 104.
The multiprocessor mechanism 105 is a mechanism that configures the CPUs 101 to 104 as a multiprocessor.
The memory 106 is an element for storing data accessed by the CPUs 101 to 104.
The device 107 and the device 108 are devices operated by the CPUs 101 to 104.
The interrupt management mechanism 109 generates interrupt processing for the CPUs associated with any combination of the CPUs 101 to 104 according to the interrupt factors generated by the device 107 and the device 108. The interrupt management mechanism 109 for multiprocessors can associate one interrupt cause with a plurality of CPUs. Among the plurality of CPUs associated with the interrupt factor, the CPU that receives the interrupt the earliest processes the interrupt, and the interrupt request to the other CPUs is cancelled.

The functional configuration of the information processing apparatus 100 according to the present embodiment will be described using FIG.
The information processing apparatus 100 is a computer including a plurality of CPUs 201, 202, 203, and 204, which are a plurality of CPUs, as a multiprocessor. The information processing apparatus 100 includes a CPU switch 211, an LHP suppression unit 212, a storage unit 220, a first execution unit 25, and a second execution unit 26 as a functional configuration. The storage unit 220 stores a lock table 219, a CPU number 141, a transfer destination CPU number 142, and an interrupt number 144. The storage unit 220 is realized by a memory.

  In FIG. 2, each of a CPU 201, a CPU 202, a CPU 203 and a CPU 204 corresponds to each of the CPU 101, the CPU 102, the CPU 103 and the CPU 104 in FIG. 1. Hereinafter, the CPU 201, the CPU 202, the CPU 203, and the CPU 204 may be described as the CPUs 201 to 204.

The first execution unit 25 executes the GPOS 205 using any one of a plurality of CPUs as the execution CPU 31. In addition, the first execution unit 25 executes the GPOS 205 after acquiring a lock indicating that the execution CPU 31 is used for the execution of the GPOS 205. That is, the GPOS 205 operates on the CPUs 201 to 204. The GPOS 205 is an example of the first OS 205 x which is a general-purpose OS.
CTX 207, CTX 208, CTX 209, and CTX 210 are contexts of GPOS 205 operating on CPUs 201-204, respectively.
The second execution unit 26 executes the RTOS 206 using any one of a plurality of CPUs. That is, the RTOS 206 operates on the CPUs 201 to 204. The RTOS 206 is an example of a second OS 206x that is a real time OS.

The lock table 219 associates each of a plurality of CPUs with lock information 190 indicating whether a lock has been acquired.
The lock table 219 has a CPU number 191 and a lock counter 192. The lock counter 192 is an example of the lock information 190 indicating whether the lock is acquired for the corresponding CPU. The CPU number 191 is a number assigned to each of a plurality of CPUs. The lock counter 192 is incremented by the first execution unit 25 when the lock for protecting the critical section is acquired for the corresponding CPU. The lock counter 192 is decremented by the first execution unit 25 when the lock is released, ie, unlocked, for the corresponding CPU.

  The CPU switch 211 switches the CPU executing the RTOS 206 to one of the CPUs 201 to 204 based on an instruction of the LHP suppressing unit 212.

The LHP suppressing unit 212 selects a CPU that executes the RTOS 206 when transitioning the RTOS 206 from the idle state to the execution state.
The LHP suppression unit 212 includes a confirmation unit 213, a selection unit 214, a request transmission unit 215, a response unit 28, and an execution preparation unit 218. The response unit 28 includes a request reception unit 216 and a confirmation response unit 217.
The confirmation unit 213 refers to the lock table 219 and confirms the lock counter 192 of its own CPU. The confirmation unit 213 is also referred to as a lock state confirmation unit.
The selection unit 214 selects a CPU to which the execution of the RTOS 206 is to be transferred based on the lock counter 192 for each CPU. The CPU to which the execution of the RTOS 206 is transferred is also referred to as a transfer destination CPU 33. The selection unit 214 is also referred to as a transfer destination CPU selection unit.
The request transmission unit 215 transmits a transfer request 151 requesting transfer of the execution of the RTOS 206 to the transfer destination CPU 33 selected by the selection unit 214.
The confirmation unit 213, the selection unit 214, and the request transmission unit 215 operate in the transfer source CPU 32.

When receiving the transfer request 151 from the request transmission unit 215, the response unit 28 confirms whether the lock is acquired for the transfer destination CPU 33, and transmits a confirmation response to the request transmission unit 215. The request reception unit 216 of the response unit 28 receives the transfer request 151 transmitted from the request transmission unit 215. The confirmation response unit 217 of the response unit 28 refers to the lock table 219, confirms the lock counter 192 of its own CPU, and transmits the result of the confirmation to the request reception unit 216. Then, the request reception unit 216 of the response unit 28 transmits a confirmation response to the request transmission unit 215.
The execution preparation unit 218 prepares to execute the RTOS 206 on its own CPU. The execution preparation unit 218 transmits, to the CPU switch 211, an instruction to switch the CPU executing the RTOS 206 to the transfer destination CPU 33.
The request reception unit 216, the confirmation response unit 217, and the execution preparation unit 218 operate in the transfer destination CPU 33.

The hardware configuration of the information processing apparatus 100 according to the present embodiment will be further described using FIGS. 1 and 2.
As described above, the information processing apparatus 100 is a computer including a plurality of CPUs 201, 202, 203, and 204, which are CPUs, as a multiprocessor.
The CPU is connected to other hardware via signal lines to control these other hardware. The CPU is an IC (Integrated Circuit) that performs arithmetic processing. In the information processing apparatus 100, a plurality of CPUs cooperate and execute programs for realizing the functions of the respective units of the information processing apparatus 100.

  The memory 106 is a storage device that temporarily stores data. Specific examples of the memory 106 are a static random access memory (SRAM) and a dynamic random access memory (DRAM).

  The storage 110 is a storage device for storing data. A specific example of the storage 110 is an HDD (Hard Disk Drive). In addition, the storage 110 is a portable memory such as a SD (Secure Digital) memory card, a CF (Compact Flash), a NAND flash, a flexible disc, an optical disc, a compact disc, a Blu-ray (registered trademark) disc, and a DVD (Digital Versatile Disc). It may be a storage medium.

  The storage 110 stores a program for realizing the function of the information processing apparatus 100. A program for realizing the function of the information processing apparatus 100 is also referred to as an information processing program 620. Further, a method for realizing the function of the information processing apparatus 100 is also referred to as an information processing method 610.

  Information, data, signal values, and variable values indicating the results of processing of each unit of the information processing apparatus 100 are stored in the storage 110 of the information processing apparatus 100, the memory 106, or a register or cache memory in the CPU.

The program for realizing the function of each part of the information processing apparatus 100 may be stored in a portable recording medium. The portable recording medium is specifically a memory card such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a Blu-ray (registered trademark) disk, a DVD (Digital Versatile Disc), or an SD (registered trademark) card.
The information processing program product is a storage medium and a storage device in which the information processing program 620 is recorded.

*** Description of operation ***
The lock acquisition processing S30 according to the present embodiment will be described with reference to FIG. The lock acquisition process S30 is a process in which the first execution unit 25 acquires a lock for protecting a critical section for an execution CPU used to execute the GPOS 205.
In step S301, the first execution unit 25 selects, from the lock table 219, the lock counter 192 of the execution CPU that is its own CPU. In step S302, the first execution unit 25 increments the selected lock counter 192, that is, adds one. In step S303, the first execution unit 25 executes a normal lock acquisition process.

The lock release processing S40 according to the present embodiment will be described with reference to FIG. The lock release process S40 is a process in which the first execution unit 25 releases the lock for the execution CPU used to execute the GPOS 205.
In step S401, the first execution unit 25 executes a normal lock release process. In step S402, the first execution unit 25 selects, from the lock table 219, the lock counter of the execution CPU that is its own CPU. In step S403, the first execution unit 25 decrements the selected lock counter, that is, subtracts one.

  The LHP suppression processing of the LHP suppression unit 212 according to the present embodiment will be described using FIGS. 5 to 11. The LHP suppression process is an operation of the LHP suppression unit 212 when an interrupt process associated with the RTOS 206 occurs. The interrupt process associated with the RTOS 206 is an interrupt process that executes the RTOS 206. The LHP suppression process has a transfer source CPU process S50 and a transfer destination CPU process S60.

<Transfer source CPU processing S50>
The transfer source CPU processing S50 according to the present embodiment will be described using FIG.
Here, the transfer source CPU 32 is an execution CPU that has accepted the interrupt processing.

First, in step S501a, the confirmation unit 213 of the transfer source CPU 32 determines whether the transfer source CPU 32 is executing the RTOS 206 when accepting the interrupt processing. If the transfer source CPU 32 has not executed the RTOS 206, the process proceeds to step S501. If the transfer source CPU 32 is executing the RTOS 206, the process proceeds to step S508.
That is, the RTOS 206 whose second execution unit 26 is the second OS 206x before the confirmation unit 213 of the transfer source CPU 32 confirms that the lock is acquired for the transfer source CPU 32 that is the execution CPU when the interrupt processing occurs. To determine if it is running. If the checking unit 213 determines that the RTOS 206 is being executed, the second executing unit 26 continues the execution of the RTOS 206.

  In step S501, the confirmation unit 213 of the transfer source CPU 32 executes a confirmation process S51 of confirming the lock state of the transfer source CPU 32.

  The confirmation process S51 according to the present embodiment will be described using FIG. In the confirmation process S51, when the interrupt process for executing the RTOS 206 occurs, the confirmation unit 213 confirms whether the lock is acquired for the execution CPU, that is, the own CPU that is the transfer source CPU 32. The confirmation unit 213 refers to the lock information 190 corresponding to the execution CPU using the lock table 219 to confirm whether the lock is acquired for the execution CPU.

  In step S 701, the confirmation unit 213 selects the lock counter of its own CPU from the lock table 219. In step S702, the confirmation unit 213 confirms whether the lock counter is zero or not. If the lock counter is not zero, the confirmation unit 213 proceeds to step S703 and determines that the own CPU has acquired a lock. If the lock counter is zero, the confirmation unit 213 proceeds to step S704 and determines that the own CPU has not acquired the lock. This is the end of the confirmation process S51.

Returning to FIG. 5, the explanation will be continued.
In step S502, the confirmation unit 213 confirms whether or not the own CPU has acquired the lock. If the own CPU has acquired the lock, the selection unit 214 executes selection processing S52 in step S503. If the own CPU does not acquire the lock, it means that the transfer is not necessary. Therefore, in step S508, the second execution unit 26 executes the second execution process S2 for executing the RTOS 206 on the own CPU. .

The selection process S52 according to the present embodiment will be described with reference to FIG.
In the selection process S52, when the lock is acquired for the execution CPU, the selection unit 214 selects the CPU to which the execution of the RTOS 206 is to be transferred from the plurality of CPUs as the transfer destination CPU 33. The selection unit 214 uses the lock table 219 to select a CPU for which the lock has not been acquired among the plurality of CPUs as the transfer destination CPU 33.

In step S 901, the selection unit 214 initializes the CPU number 141 used to reference the lock table 219 to zero. In step S902, the selection unit 214 initializes the transfer destination CPU number 142 storing the transfer destination CPU number to a value obtained by adding 1 to the maximum CPU number which is the maximum value of the CPU numbers installed in the system. .
In step S903, the selection unit 214 confirms whether the CPU number is equal to or different from the own CPU number. If not, the selection unit 214 proceeds to step S 904 and selects the lock counter 192 corresponding to the CPU number 141 from the lock table 219. If the CPU number 141 is equal to the own CPU number, the selection unit 214 proceeds to step S 907.
In step S 905, the selection unit 214 confirms whether the selected lock counter 192 is zero or not. In the case of zero, the selecting unit 214 determines that the lock has not been acquired, and proceeds to step S 906 to set the CPU number 141 in the transfer destination CPU number 142. If it is other than zero, the selection unit 214 proceeds to step S 907.
In step S 907, the selection unit 214 adds 1 to the CPU number 141 in order to refer to the next CPU. In step S 908, the selection unit 214 checks whether the CPU number 141 is less than or greater than the maximum CPU number. If the CPU number 141 is less than or equal to the maximum CPU number, the selection unit 214 returns to step S 903 and continues checking the lock table 219. If the CPU number 141 exceeds the maximum CPU number, the selection unit 214 proceeds to step S 909, and checks whether or not the transfer destination CPU number 142 exceeds the maximum CPU number. If the transfer destination CPU number exceeds the maximum CPU number, the selection unit 214 determines that the transfer destination CPU 33 has not been found, and proceeds to step S 910 to set the own CPU number in the transfer destination CPU number 142. If the transfer destination CPU number is less than or equal to the maximum CPU number, the selection unit 214 ends the process.

Returning to FIG. 5, the explanation will be continued.
In step S504, the selection unit 214 determines whether the transfer destination CPU 33 selected in the selection process S52 is equal to or different from its own CPU. If the transfer destination CPU 33 is equal to its own CPU, it means that no transfer is necessary. Therefore, in step S508, the second execution unit 26 executes the RTOS 206 on its own CPU. When the transfer destination CPU 33 is different from the own CPU, in step S505, the request transmission unit 215 executes the request transmission process S53, and transmits the transfer request 151 requesting the execution of the RTOS 206 to the transfer destination CPU 33.

The request transmission process S53 according to the present embodiment will be described with reference to FIG. In request transmission processing S53, the request transmission unit 215 transmits a transfer request 151 for requesting transfer of the execution of the RTOS 206 to the transfer destination CPU 33 selected by the selection unit 214.
In step S111, the request transmission unit 215 transmits the transfer request 151 to the transfer destination CPU 33 using inter-CPU communication. In step S112, the request transmission unit 215 confirms whether the confirmation response from the transfer destination CPU 33 has been received or not. If not received, the request transmission unit 215 repeats the confirmation as to whether the confirmation response from the transfer destination CPU 33 has been received. When the transfer request is received, the transfer request transmission unit 215 ends the process.

Returning to FIG. 5, the explanation will be continued.
In step S506, the request transmission unit 215 confirms the confirmation response from the transfer destination CPU. If the confirmation response can be transferred, in step S507, the first execution unit 25 executes the first execution process S1 of executing the GPOS 205. If the confirmation response is not transferable, the process returns to step S503, and the selection unit 214 repeats the process from the execution of the selection process S52.
That is, when the request transmission unit 215 receives a confirmation response indicating that the lock has not been acquired for the transfer destination CPU 33 from the response unit 28, the first execution unit 25 continues the execution of the GPOS 205. Further, when the request transmission unit 215 receives from the response unit 28 a confirmation response indicating that the lock is acquired for the transfer destination CPU 33, the selection unit 214 reselects the transfer destination CPU from the plurality of CPUs.
The confirmation response indicating that the lock has not been acquired for the transfer destination CPU 33 means that the confirmation response can be transferred. Further, the confirmation response indicating that the lock is acquired for the transfer destination CPU 33 means that the confirmation response can not be transferred.
This is the end of the description of the transfer source CPU process S50.

<Transfer destination CPU process S60>
The transfer destination CPU process S60 according to the present embodiment will be described with reference to FIG.
In step S601, the request reception unit 216 of the transfer destination CPU 33 receives the transfer request 151 transmitted from the transfer source CPU 32.
In step S602, the confirmation response unit 217 executes confirmation response processing S61.

The confirmation response process S61 according to the present embodiment will be described using FIG.
In the confirmation response process S61, the confirmation response unit 217 confirms whether or not the own CPU as the transfer destination CPU 33 has acquired the lock.
In step S801, the confirmation response unit 217 selects the lock counter 192 of its own CPU from the lock table 219. In step S802, the confirmation response unit 217 confirms whether the lock counter 192 is zero or not.
If the lock counter 192 is not zero, in step S803, the confirmation response unit 217 determines that its own CPU has acquired the lock. Then, in step S804, the confirmation response unit 217 sets the confirmation response as nontransferable.
When the lock counter 192 is zero, in step S805, the confirmation response unit 217 determines that the own CPU has not acquired the lock. Then, in step S806, the confirmation response unit 217 sets the confirmation response to be transferable.
In step S 808, the confirmation response unit 217 transmits a confirmation response to the transfer source CPU 32. The confirmation response unit 217 ends the confirmation response process S61.

Returning to FIG. 9, the description will be continued.
In step S603, the confirmation response unit 217 confirms whether or not the own CPU has acquired the lock. If the own CPU has not acquired the lock, in step S604, the execution preparation unit 218 executes the execution preparation process S62. If the own CPU has acquired the lock, the transfer is not possible, so the first execution unit 25 continues the first execution process S1 of executing the GPOS 205 on the own CPU in step S607. Then, the execution preparation unit 218 ends the transfer destination CPU process S60.

The execution preparation process S62 according to the present embodiment will be described using FIG.
In the execution preparation process S62, the execution preparation unit 218 associates the interrupt process by the interrupt cause associated with the RTOS 206 with the own CPU that is the transfer destination CPU 33.
In step S101, the execution preparation unit 218 initializes an interrupt number 144 for selecting an interrupt cause to zero.
In step S102, the execution preparation unit 218 reads from the interrupt management mechanism 109 the destination CPU associated with the interrupt cause indicated by the interrupt number 144 as the interrupt destination CPU.
In step S103, the execution preparation unit 218 confirms whether or not the transfer source CPU 32 is included in the read out interrupt destination CPU. If not included, the execution preparation unit 218 proceeds to step S107 in order to confirm the next interrupt factor. If it is included, in step S104, the execution preparation unit 218 checks whether the transfer destination CPU 33 includes or does not include the transfer destination CPU 33. If it is included, the execution preparation unit 218 proceeds to step S107 in order to confirm the next interrupt factor. If not included, the execution preparation unit 218 deletes the transfer source CPU 32 from the interrupt destination CPU in step S105. In addition, in step S106, the execution preparation unit 218 adds the transfer destination CPU 33 to the interrupt destination CPU.
In step S107, the execution preparation unit 218 increments the interrupt number 144 in order to select the next interrupt factor.
In step S108, the execution preparation unit 218 confirms whether the interrupt number 144 is less than or greater than the maximum interrupt number. If it is less than or equal to the maximum interrupt number, the execution preparation unit 218 repeats the process from step S102. If the maximum interrupt number is exceeded, the execution preparation unit 218 ends the execution preparation process S62.

Returning to FIG. 9, the description will be continued.
In step S605, the CPU switch 211 switches the CPU executing the RTOS 206 to the transfer destination CPU 33.
In step S606, the second execution unit 26 executes a second execution process S2 for executing the RTOS 206 in the transfer destination CPU 33.

*** Other configuration ***
In the present embodiment, the function of the LHP suppressing unit is realized by software. However, as a modification, some functions of the LHP suppressing unit may be realized by dedicated hardware, and the remaining functions may be realized by software.

The CPU and the storage unit of the information processing apparatus 100 are collectively referred to as “processing circuitry”. That is, the function and storage unit of the LHP suppressing unit of the information processing apparatus 100 are realized by processing circuitry.
Also, "part" may be read as "step" or "procedure" or "treatment". Also, the function of "part" may be realized by firmware.

*** Explanation of the effect of the present embodiment ***
As described above, according to the information processing apparatus 100 according to the present embodiment, the CPU that has not acquired the GPOS lock is selected as the CPU that executes the RTOS, so the occurrence of LHP can be suppressed. Can. Furthermore, according to the information processing apparatus 100 according to the present embodiment, when there is no CPU that has not acquired the GPOS lock, the selection of the CPU that executes the RTOS is immediately ended, and the RTOS execution is started. Can maintain the response performance of RTOS.

  Further, in the information processing apparatus 100 according to the present embodiment, when the interrupt processing associated with the RTOS occurs and the RTOS is transitioned to the execution state, whether the OS operating at the time of receiving the interrupt processing is the RTOS It is determined whether or not. When the OS operating at the time of receiving the interrupt processing is the RTOS, the information processing apparatus 100 executes the RTOS without transferring the CPU, so the response performance of the RTOS can be maintained.

  In addition, in the information processing apparatus 100 according to the present embodiment, when the transfer destination CPU is selected by the selection unit and transfer of the CPU is executed, the transfer destination CPU acquires the lock of GPOS. Re-execute from selection of CPU. Therefore, according to the information processing apparatus 100 according to the present embodiment, it is possible to prevent the performance degradation of the GPOS while maintaining the response performance of the RTOS.

Second Embodiment
In the present embodiment, points different from the first embodiment will be mainly described.
In the present embodiment, the same components as those in the first embodiment may be assigned the same reference numerals and descriptions thereof may be omitted.

  In the present embodiment, the selection processing S52a for selecting the transfer destination CPU 33 is different from the selection processing S52 described in FIG. 7 of the first embodiment. Further, in the present embodiment, the lock table 219a is different from the lock table 219 described in FIG. 2 of the first embodiment.

The configuration of the lock table 219a according to the present embodiment will be described with reference to FIG.
As shown in FIG. 12, in the lock table 219a, each of the plurality of CPUs, the lock information 190, and the priority 193 of each of the plurality of CPUs are associated.

The selection process S52a according to the present embodiment will be described with reference to FIG.
In the selection process S52a, the selection unit 214 uses the lock table 219a to select the CPU with the highest priority 193 as the transfer destination CPU 33 among the CPUs for which the lock has not been acquired.

In step S901a, the selection unit 214 initializes the CPU number 141 used to reference the lock table 219a, the setting CPU number 145, and the setting priority 146 to zero.
The process from step S902 to step S905 is the same as that of FIG. 7 of the first embodiment. In step S 905, the selection unit 214 confirms whether the selected lock counter 192 is zero or not. If it is zero, the selecting unit 214 determines that the lock has not been acquired, and the process advances to step S 905 a. If it is other than zero, the selection unit 214 proceeds to step S 907.

In step S905a, the selection unit 214 compares the setting priority 146 with the priority 193 of the CPU number 141 in the lock table 219a. If the priority 193 is equal to or higher than the setting priority 146, the process advances to step S906a. If the priority 193 is less than the setting priority 146, the process proceeds to step S907.
In step S 906 a, the selection unit 214 sets the CPU number 141 in the transfer destination CPU number 142 and the setting CPU number 145. Further, the selection unit 214 sets the priority 193 of the CPU number 141 in the lock table 219 a as the setting priority 146.
The processing from step S 907 to step S 910 is the same as that in FIG. 7 of the first embodiment.

  As described above, according to the information processing apparatus 100 according to the present embodiment, the priority for each CPU can be set in the lock table, and when there are a plurality of CPUs that have not acquired the lock, based on the priorities. A transfer destination CPU is selected. Therefore, according to the information processing apparatus 100 according to the present embodiment, the transfer destination CPU can be selected more efficiently.

  The first and second embodiments have been described above. In the first and second embodiments, each part of the LHP suppressing unit of the information processing apparatus 100 configures the information processing apparatus 100 as an independent functional block. However, the configuration of the information processing apparatus 100 may be arbitrary as in the above-described embodiment. The functional blocks of the information processing apparatus 100 are arbitrary as long as the functions described in the above-described embodiment can be realized. The information processing apparatus 100 may be configured with these functional blocks in any other combination or arbitrary block configuration.

Although the first and second embodiments have been described, a plurality of parts of these embodiments may be combined and implemented. Alternatively, one portion of these embodiments may be implemented. In addition, these embodiments may be implemented in any combination in whole or in part.
The embodiments described above are essentially preferable examples, and are not intended to limit the scope of the present invention, its applications and applications, and various modifications can be made as necessary. .

  25 first execution unit, 26 second execution unit, 28 response unit, 31 execution CPU, 32 transfer source CPU, 33 transfer destination CPU, 100 information processing apparatus, 101, 102, 103, 104, 201, 202, 203, 204 CPU, 105 multiprocessor mechanism, 106 memory, 107, 108 devices, 109 interrupt management mechanism, 110 storage, 141, 191 CPU number, 142 transfer destination CPU number, 144 interrupt number, 145 setting CPU number, 146 setting priority, 151 Transfer request, 192 lock counter, 190 lock information, 193 priority, 205 GPOS, 205x first OS, 206 RTOS, 206x second OS, 207, 208, 209, 210 CTX, 211 CPU switch, 212 LHP suppressor , 213 Confirmation unit, 214 selection unit, 215 request transmission unit, 216 request reception unit, 217 confirmation response unit, 218 execution preparation unit, 219, 219a lock table, 220 storage unit, 610 information processing method, 620 information processing program, S1 first Execution processing, S2 second execution processing, S30 lock acquisition processing, S40 lock release processing, S50 transfer source CPU processing, S51 confirmation processing, S52, S52a selection processing, S53 request transmission processing, S60 transfer destination CPU processing, S61 acknowledgment processing , S62 Execution preparation processing.

Claims (10)

A first execution unit that includes a plurality of CPUs (Central Processing Units) as a multi-processor, and uses one of the CPUs as an execution CPU to execute a first OS (Operating system), the execution CPUs An information processing apparatus comprising a first execution unit that executes a first OS after acquiring a lock indicating that the second OS is being used to execute the first OS;
A confirmation unit that confirms whether the lock has been acquired for the execution CPU when an interrupt process for executing the second OS occurs;
A selection unit that selects a CPU to which the execution of the second OS is to be transferred from the plurality of CPUs as a transfer destination CPU when the lock is acquired for the execution CPU;
A request transmission unit that transmits a transfer request for requesting the transfer destination CPU selected by the selection unit to transfer the execution of the second OS;
A response unit that, upon receiving the transfer request from the request transmission unit, confirms whether the lock has been acquired for the transfer destination CPU, and transmits a confirmation response to the request transmission unit;
Equipped with
The selection unit is
When the request transmission unit receives, from the response unit, the confirmation response indicating that the lock has been acquired for the transfer destination CPU, a destination to which the execution of the second OS is transferred from the plurality of CPUs Re-selecting the CPU as the transfer destination CPU,
The information processing apparatus further includes:
An information processing apparatus comprising a second execution unit that causes the transfer destination CPU to execute the second OS.   The first execution unit is
  The information according to claim 1, wherein the request transmission unit continues execution of the first OS when receiving the confirmation response indicating that the lock has not been acquired for the transfer destination CPU from the response unit. Processing unit.   A first execution unit that includes a plurality of CPUs (Central Processing Units) as a multi-processor, and uses one of the CPUs as an execution CPU to execute a first OS (Operating system), the execution CPUs An information processing apparatus comprising a first execution unit that executes a first OS after acquiring a lock indicating that the second OS is being used to execute the first OS;
  A confirmation unit that confirms whether the lock has been acquired for the execution CPU when an interrupt process for executing the second OS occurs;
  A selection unit that selects a CPU to which the execution of the second OS is to be transferred from the plurality of CPUs as a transfer destination CPU when the lock is acquired for the execution CPU;
  A second execution unit that causes the transfer destination CPU to execute the second OS;
Equipped with
  The confirmation unit
  When the interrupt process occurs, the second execution unit determines whether the second OS is being executed or not before confirming whether the lock has been acquired for the execution CPU. When it is determined that the OS is being executed, the execution of the second OS by the second execution unit is continued without executing the process of selecting the transfer destination CPU by the selection unit. Information processing apparatus to be. The information processing apparatus is
A lock table in which each of the plurality of CPUs is associated with lock information indicating whether or not the lock is acquired;
The confirmation unit
The information processing according to any one of claims 1 to 3, wherein the lock information corresponding to the execution CPU is referred to using the lock table, and it is confirmed whether the lock is acquired for the execution CPU. apparatus. The selection unit is
The information processing apparatus according to claim 4, wherein a CPU for which the lock has not been acquired among the plurality of CPUs is selected as the transfer destination CPU using the lock table. In the lock table, each of the plurality of CPUs, the lock information, and the priority of each of the plurality of CPUs are associated with each other.
The selection unit is
The information processing apparatus according to claim 5, wherein the CPU having the highest priority among the CPUs for which the lock has not been acquired is selected as the transfer destination CPU using the lock table. A first execution unit that includes a plurality of CPUs (Central Processing Units) as a multi-processor, and uses one of the CPUs as an execution CPU to execute a first OS (Operating system), the execution CPUs An information processing method of an information processing apparatus, comprising: a first execution unit that executes a first OS after acquiring a lock indicating that the first OS is being used to execute the first OS;
The confirmation unit confirms whether the lock has been acquired for the execution CPU when an interrupt process for executing the second OS occurs.
The selection unit selects a CPU to which the execution of the second OS is to be transferred from the plurality of CPUs as a transfer destination CPU when the lock is acquired for the execution CPU,
A request transmission unit transmits a transfer request for requesting transfer of the execution of the second OS to the transfer destination CPU selected by the selection unit;
When the response unit receives the transfer request from the request transmission unit, the response unit confirms whether the lock has been acquired for the transfer destination CPU, and transmits a confirmation response to the request transmission unit.
When the request transmission unit receives the confirmation response indicating that the lock has been acquired for the transfer destination CPU from the response unit, the selection unit receives the confirmation response from the plurality of CPUs. Reselect the CPU to which execution is to be transferred as the transfer destination CPU,
An information processing method for causing a second execution unit to cause the transfer destination CPU to execute the second OS. A first execution unit that includes a plurality of CPUs (Central Processing Units) as a multi-processor, and uses one of the CPUs as an execution CPU to execute a first OS (Operating system), the execution CPUs An information processing program of an information processing apparatus comprising: a first execution unit that executes the first OS after acquiring a lock indicating that the first OS is being used to execute the first OS;
Confirmation processing for confirming whether the lock has been acquired for the execution CPU when an interrupt processing for executing the second OS occurs;
A selection process of selecting a CPU to which the execution of the second OS is to be transferred from the plurality of CPUs as a transfer destination CPU when the lock is acquired for the execution CPU;
Request transmission processing for transmitting a transfer request for requesting transfer of execution of the second OS to the transfer destination CPU selected by the selection processing;
When the transfer request is received, it is confirmed whether the lock has been acquired for the transfer destination CPU, and a response process of transmitting a confirmation response to the request transmission process;
When the confirmation response indicating that the lock has been acquired for the transfer destination CPU is received by the request transmission process, the CPU to which the execution of the second OS is to be transferred is transferred from the plurality of CPUs. A process of reselecting as the transfer destination CPU;
An information processing program that causes the information processing apparatus, which is a computer, to execute a second execution process that causes the transfer destination CPU to execute the second OS.   A first execution unit that includes a plurality of CPUs (Central Processing Units) as a multi-processor, and uses one of the CPUs as an execution CPU to execute a first OS (Operating system), the execution CPUs An information processing method of an information processing apparatus, comprising: a first execution unit that executes a first OS after acquiring a lock indicating that the first OS is being used to execute the first OS;
  The confirmation unit confirms whether the lock has been acquired for the execution CPU when an interrupt process for executing the second OS occurs.
  The selection unit selects a CPU to which the execution of the second OS is to be transferred from the plurality of CPUs as a transfer destination CPU when the lock is acquired for the execution CPU,
  A second execution unit causing the transfer destination CPU to execute the second OS;
  When the interrupt processing occurs, the confirmation unit determines whether the second execution unit is executing the second OS before confirming whether the lock has been acquired for the execution CPU. If it is determined that the second OS is being executed, execution of the second OS by the second execution unit is not performed without executing the process of selecting the transfer destination CPU by the selection unit. Information processing method to be continued.   A first execution unit that includes a plurality of CPUs (Central Processing Units) as a multi-processor, and uses one of the CPUs as an execution CPU to execute a first OS (Operating system), the execution CPUs An information processing program of an information processing apparatus comprising: a first execution unit that executes the first OS after acquiring a lock indicating that the first OS is being used to execute the first OS;
  Confirmation processing for confirming whether the lock has been acquired for the execution CPU when an interrupt processing for executing the second OS occurs;
  A selection process of selecting a CPU to which the execution of the second OS is to be transferred from the plurality of CPUs as a transfer destination CPU when the lock is acquired for the execution CPU;
  A second execution process for causing the transfer destination CPU to execute the second OS;
An information processing program that causes the information processing apparatus that is a computer to execute
  The confirmation process is
  When the interrupt processing occurs, it is determined whether the second OS is being executed or not before the lock for the execution CPU is confirmed to be acquired, and the second OS is being executed. The information processing program for continuing execution of said 2nd OS, without performing processing which chooses said transfer destination CPU, when it is judged.

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