JP2015118493A - Trace device and trace program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a trace device that can suppress increase in CPU load upon output processing of program operation information without adding exclusive hardware, and can record the program operation information without being affected by system down (or an operation situation of a system operation system).SOLUTION: A trace device 1001 incorporating a multicore processor including a plurality of CPUs 101-1 to 101-3 and 201, the trace device 1001 comprises: a system operation system 100 that runs a program using the CPUs 101-1 to 101-3, and collects program operation information indicative of an operation history of the program; and a log control system 200 that operates independently of a system operation system 100 without being affected by an operation situation of the system operation system 100 using the CPU 201, and outputs the program operation information collected by the system operation system 100 to an IO device 1.

Description

  The present invention relates to a tracing device that mounts a multi-core processor and performs tracing (program operation information).

  Conventional program operation information (trace) collection methods include, for example, a method of outputting the date, time, operation content, etc. to a UART (Universal Asynchronous Receiver Transmitter) while the computer system is operating, or outputting the program operation information to a memory. A method of writing to a nonvolatile area and collecting program operation information is used. However, in the method of outputting the program operation information to the UART, a CPU load is generated because the program operation information is output to the UART, which affects the operation timing of the CPU (Central Processing Unit). Depending on the output amount of the program operation information, side effects may occur in the operation of the system. Therefore, it is necessary to operate in consideration of the processing load for outputting the program operation information. Also, the method for outputting the program operation information to the non-volatile area may fall into a state where the collected program operation information cannot be collected, for example, when the system including the OS (operating system) is down or hung up. .

  In order to solve these problems, the following patent documents 1 and 2 are disclosed as conventional techniques. The technique of Patent Document 1 adds dedicated hardware as a technique for collecting program operation information without affecting the operation timing of the CPU, writes the program operation information to the main storage device, and externally uses the dedicated hardware. The program operation information is transferred to the storage device, and the CPU load is reduced by not interposing the CPU. Further, since dedicated hardware is added, it is possible to collect program operation information via the dedicated hardware even when the system is down. The technique of Patent Document 2 monitors the load on each CPU in a computer having a plurality of CPUs, and schedules the tracer to operate on a core with a low CPU load. Thus, a technique has been invented that prevents a specific CPU load from becoming high and reduces the side effects on the system.

JP 2004-54532 A JP 2012-18438 A

  Japanese Patent Application Laid-Open No. 2004-228867 reduces the load on the system by adding dedicated hardware and enables collection of program operation information even when the system is down. However, it is necessary to add dedicated hardware to the computer system. Since dedicated hardware is added to the computer system, there is a problem that the cost and size increase.

  In Patent Document 2, a resource monitoring mechanism and the like are realized by software in an existing computer system, and dedicated hardware is not required. For this reason, the problem of high cost and size expansion does not occur, but when the entire system is down, the program operation information may not be written to the UART or the nonvolatile area. Further, when the resource monitoring mechanism is realized by software, CPU resources for operating them are necessary, and it is necessary to operate so as not to cause side effects on the system.

  An object of the present invention is to provide a trace device capable of suppressing an increase in CPU load in program operation information output processing without adding dedicated hardware and recording program operation information without being affected by a system down. To do.

The tracing device of the present invention
In a trace device equipped with a multi-core processor having a plurality of CPUs (Central Processing Units),
A system operation unit that executes a program using one or more of the CPUs of the multi-core processor and collects program operation information indicating a history of the processing status of the program;
Of the plurality of CPUs of the multi-core processor, one or more CPUs different from the CPU used by the system operation unit are used and are independent of the system operation unit without being affected by the operating status of the system operation unit. And a log control unit that outputs the program operation information collected by the system operation unit to an IO (Input / Output) device.

  According to the present invention, it is possible to provide a tracing device that can suppress an increase in CPU load in the output processing of program operation information without adding dedicated hardware and can record program operation information without being affected by a system down.

1 is a configuration diagram showing a trace device according to Embodiment 1. FIG. FIG. 3 is an explanatory diagram showing an internal configuration of a shared memory of the trace device according to the first embodiment. 5 is a flowchart (system operation system) showing the operation of the trace device according to the first embodiment. 6 is a flowchart (log control system) showing the operation of the trace apparatus according to the first embodiment. FIG. 3 is a sequence diagram of monitoring the operating state of the system operation system of the trace device according to the first embodiment. FIG. 6 is a sequence diagram when the log control system of the trace apparatus detects an abnormality in the system operation system according to the first embodiment. FIG. 3 is a sequence diagram when an abnormality is detected in the system operation system of the trace device according to the first embodiment. FIG. 4 is a configuration diagram showing a trace device according to a second embodiment. FIG. 6 is a configuration diagram showing a trace device according to a third embodiment. 10 is a flowchart showing the operation of the trace device according to the third embodiment. FIG. 6 is a configuration diagram showing a trace device according to a fourth embodiment.

Embodiment 1 FIG.
The trace apparatus 1001 according to the first embodiment will be described with reference to FIGS.
FIG. 1 is a configuration diagram including a hardware configuration and a software configuration of the trace apparatus 1001 according to the first embodiment. A trace apparatus 1001 shown in FIG. 1 includes a system operating system 100 (system operating unit) and a multi-core processor including CPUs 101-1, CPU 101-2, CPU 101-3, and CPU 201, which are four CPUs (Central Processing Units). This is an example of constructing a log control system 200 (log control unit).

(System operation system 100)
The system operation system 100 includes a CPU 101-1 to 101-3, an OS (Operating System) 102, an inter-CPU communication unit 103, an application program 104, an IO (Input / Output) access control unit 105, an abnormality detection processing unit 106, and a program An information writing unit 107 is included. The program information writing unit 107 is realized by the CPU 101-1 or the like executing a process having a program for writing program operation information.
Here, “program operation information” is information (trace) of program operation history.

(Log control system 200)
The log control system 200 includes a CPU 201, an inter-CPU communication unit 203, an IO access control unit 205, an abnormality detection processing unit 206, and a program information reading unit 207.

  The trace device 1001 includes an IO (Input / Output) device 1, a memory 2 (for example, a main storage device), and a communication path 3 that are commonly used by the system operation system 100 and the log control system 200. The system operation system 100 and the log control system 200 described above are realized by each program having the function of “unit”, the OS 102, and the CPUs 101-1 to 101-3 and 201 that execute “each program and the OS 102”. As shown in FIG. 1, in the trace apparatus 1001, the multi-core processor is divided into a plurality of systems (two in FIG. 1), and the system operation system 100 and the log control system 200 are configured. Three CPUs are allocated to the system operation system 100 and one CPU is allocated to the log control system 200. The four CPUs, the CPUs 101-1 to 101-3 and the CPU 201, have the same architecture. These four CPUs are connected by a communication path 3 and are configured to be able to transmit information to each other or to the IO device 1 and the memory 2 that are peripheral hardware connected to the communication path 3.

  The system operation system 100 includes an OS 102. The system operation system 100 includes an inter-CPU communication unit 103, an application program 104, an IO access control unit 105, an abnormality detection processing unit 106, and a program information writing unit 107, and constructs a system operation system. The inter-CPU communication unit 103 to the program information writing unit 107 operate on the OS 102. In addition, the log control system 200 does not include an OS and has a simple configuration. The log control system 200 includes an inter-CPU communication unit 203, an IO access control unit 205, an abnormality detection processing unit 206, and a program information reading unit 207, and constructs a log control system. Assume that either the system operation system 100 or the log control system 200 accesses the IO device 1 shared by the system operation system 100 and the log control system 200. In order to prevent contention of access to the IO device 1 between the system operation system 100 and the log control system 200, the IO access control units 105 and 205 perform exclusive control.

  As shown in FIG. 1, the memory 2 includes a system operation system memory area 21 used by the system operation system 100, a log control system memory area 22 used by the log control system 200, a system operation system 100, and a log control system 200. And shared memory 23 used by both of them.

  The system operation system 100 is a system for operating a normal system. The program information writing unit 107 of the system operation system 100 collects the program operation information including the OS 102 as well as the application program 104 operating on the system operation system 100 and writes the collected program operation information to the shared memory 23.

  The program information reading unit 207 of the log control system 200 reads the program operation information written by the program information writing unit 107 from the shared memory 23 and outputs the read program operation information to the IO device 1.

(Abnormality detection of system operation system 100)
The inter-CPU communication units 103 and 203 and the abnormality detection processing units 106 and 206 monitor the operating state of the system operation system 100 and detect an abnormality in the system operation system 100. When an abnormality of the system operation system 100 is detected, the abnormality detection processing unit 206 of the log control system 200 stops the CPUs 101-1 to 101-3 of the system operation system 100 and is stored in the shared memory 23. Program operation information is output to the IO device 1 by the program information reading unit 207.

  FIG. 2 is a diagram showing a use area of the shared memory 23. As shown in FIG. 2, the shared memory 23 has a memory area divided according to the type of IO device that outputs program operation information. The system operation system 100 writes the program operation information in the shared memory area corresponding to the type of the IO device that outputs the program operation information. FIG. 2 is a diagram when program operation information is output to two IO devices. For example, the output area 231 of the IO device A is an output area to the UART, and the output area 232 of the IO device B is a non-volatile storage such as an HDD (Hard Disk Drive) or an SD memory card (SD Memory Card (SD) Is assigned as an output area to the registered trademark)).

<Activation of Trace Device 1001 and Collection of Program Operation Information>
Next, the operation of the trace device 1001 according to the first embodiment will be described.
FIG. 3 is a flowchart in which the program information writing unit 107 of the system operation system 100 writes the program operation information to the shared memory 23. When a system activation trigger such as power on is detected, the log control system 200 is activated, and then the system operation system 100 is activated. The activated system operation system 100 performs a normal operation, and the program information writing unit 107 writes the operation content to the shared memory 23 as the program operation information (ST1). It is assumed that only the system operating system 100 writes in the area for storing the program operation information in the shared memory 23. The reading is performed only by the program information reading unit 207. Therefore, access contention does not occur, and writing to the shared memory 23 can be performed without determination processing as shown in FIG. In addition, by starting the system operation system 100 after starting the log control system 200, it is possible to acquire program operation information from the time when the system operation system 100 is started. Note that the system operation system 100 and the log control system 200 may be activated in parallel for the purpose of shortening the system activation time.

<Output of program operation information>
FIG. 4 is a flowchart in which the program information reading unit 207 outputs the program operation information stored in the shared memory 23 to the IO device 1. When the output destination IO device 1 is also accessed from the system operating system 100, access contention occurs, and therefore, the exclusive control is performed by the IO access control unit 205 as shown in FIG. This will be described later.

  The program information reading unit 207 of the log control system 200 reads the program operation information written in the shared memory 23 from the area of the shared memory 23 corresponding to the type of the output destination IO device (ST10), and the program operation information exists. (ST11). If there is program operation information to be output to the IO device 1, the IO access control unit 205 determines whether access to the IO device 1 is possible (ST12). When the IO access control unit 205 determines that access is possible, the program information reading unit 207 performs output processing of program operation information to the IO device 1 (ST13). The output processing to the IO device 1 considers the efficiency of the communication path 3 shared with the system operation system 100, and the program information reading unit 207 waits until a certain amount of program operation information is accumulated in the shared memory 23, and every time a certain amount is accumulated. Output to the IO device 1. Data transfer to the IO device 1 may use DMA (Direct Memory Access) in addition to the transfer by the CPU 201 of the log control system 200.

<Abnormality detection>
The abnormality detection processing unit 206 of the log control system 200 has a function of monitoring the operating state of the system operation system 100 and detecting an abnormality of the system operation system 100. A specific detection method is described below.
FIG. 5 is an example of a sequence in which the log control system 200 monitors the operating state of the system operation system 100. Between the CPUs 101-1 to 101-3 via the communication path 3 and the CPU 201, the inter-CPU communication units 103 and 203 and the shared memory 23 are used, and the system operation system 100 periodically stores the shared memory 23. The operation information is updated (ST100). An update notification of operation information is sent to the log control system 200 through communication between the CPU communication units 103 and 203 (ST111). In the log control system 200, a timer (not shown but realized by the CPU 201) is set in advance (ST112), and a timer countdown is performed (ST113). When the log control system 200 receives the update notification of the operation information from the system operation system 100 and receives the update notification, the abnormality detection processing unit 206 checks whether the operation content of the shared memory 23 has been updated to an expected value. (ST114). The abnormality detection processing unit 206 determines that the system operation system 100 is operating normally by being updated to the expected value, resets the timer value (ST115), and performs timer countdown again (ST116). Similarly, the abnormality detection processing unit 206 continues monitoring whether the system operation system is operating normally.

<Abnormality detection of system operation system 100 by log control system 200>
FIG. 6 is an example of a sequence in which the log control system 200 detects a state where the system operation system 100 is not operating normally. The method of monitoring the operating state of the system operation system 100 by the log control system 200 is as shown in FIG. The log control system 200 sets a timer in advance (ST122) and performs a timer countdown (ST123). Although the system operation system 100 has updated the contents of the shared memory 23 (ST120), the system operation system 100 goes down and a state in which the operation information update notification (ST121) cannot be notified occurs. The abnormality detection processing unit 206 of the log control system 200 detects a timer timeout (ST124) because the operation information update notification (ST121) is not notified, and determines that the operation state of the system operation system is abnormal. Then, the operation of the CPU 101 of the system operation system 100 is stopped ST125. Thereafter, the abnormality detection processing unit 206 causes the program information reading unit 207 to forcibly output the program operation information (ST126) and to output the cache information of the system operation system 100 (ST127). The forced output of the program operation information in ST126 and the cache information output of the system operation system 100 in ST127 will be described later.

  Even when the update information of the operation information of the log control system 200 is notified from the system operation system 100, but the operation content of the shared memory 23 is not updated to an expected value, the abnormality detection processing unit 206 also includes the system operation system 100. Is determined to be abnormal.

<Detection of abnormalities in the system operating system>
FIG. 7 shows an example of a sequence when the system operation system 100 detects an abnormality in its own system. The abnormality detection processing unit 106 of the system operation system 100 has a function of detecting an abnormality in its own system operation system. Then, the abnormality detection process ST130 is performed. A specific detection method is described below.
(1) Acquire error detection information of the CPUs 101-1 to 101-3 such as exceptions.
(2) Monitor memory contents using a checksum and detect memory corruption and data write failure.
(3) Monitors whether processing that operates periodically by the application program 104 operates within a certain period, and detects processing delay.
(4) The confirmation data is stored in a specific area of the system operation system memory area 21, and it is monitored whether the area is rewritten to an unexpected value. Detects memory corruption and stack overflow.
(5) With reference to the scheduling information of the OS 102, it is monitored whether the same queue has been in the RUN state for a certain period of time or more after the scheduling queue operation, and whether the periodically operating process has periodically changed to the RUN state.
When an abnormality is detected by any one of the methods (1) to (5), the abnormality detection processing unit 106 of the system operation system 100 performs the log control system 200 via communication between the inter-CPU communication units 103 and 203. An abnormality detection notification is sent to (ST131). When the log control system 200 receives the abnormality detection notification, the abnormality detection processing unit 206 stops the operations of the CPUs 101-1 to 101-3 of the system operation system 100 via the communication path 3 (ST132). Thereafter, the abnormality detection processing unit 206 causes the program information reading unit 207 to forcibly output the program operation information (ST133) and output the cache information of the system operation system 100 (ST134).

<Forced output of program operation information (ST126, ST133)>
The abnormality detection processing unit 206 of the log control system 200 forcibly causes the program information reading unit 207 to output the program operation information written by the program information writing unit 107 of the system operation system 100 to the shared memory 23 to the IO device 1. . When the system operation system 100 is down while the system operation system 100 is using the communication path 3 and the shared IO device 1, the abnormality detection processing unit 206 has the access right of the communication path 3 or the access right of the shared IO device. Is forcibly assigned to the log control system 200 to cause the program information reading unit 207 to output program operation information to the IO device 1.

  By forcibly outputting, it is possible to acquire program operation information immediately before the system operation system 100 goes down. Further, since the output to the IO device 1 is processed by the log control system 200, even if the system operation system 100 goes down, the output process does not stop in the output process to the IO device 1, and program operation information is acquired. Can do. On the other hand, in the conventional technique, when output processing to the IO device 1 is performed in the system operation system, if the system operation system goes down, the output processing is stopped in the output process to the IO device 1, and program operation information is obtained until the end. May not be possible.

<Cache information output of system operation system 100 (ST127, ST134)>
The abnormality detection processing unit 206 of the log control system 200 causes the program information reading unit 207 to acquire the secondary cache information of the CPUs 101-1 to 101-3 of the system operation system 100 and output the information to the IO device 1. As described above, in ST127 and ST134, in addition to the program operation information, the secondary cache information of the CPUs 101-1 to 101-3 in the system operation system 100 in which an abnormality has occurred is accessed from the log control system 200 side, so Collect state.
Further, the abnormality detection processing unit 206 of the log control system 200 acquires the primary cache information of the CPUs 101-1 to 101-3 of the system operation system 100 through the program information reading unit 207.
The abnormality detection processing unit 206 of the log control system 200 activates the stopped CPUs 101-1 to 101-3 again, sends a primary cache read request to the communication path 3, and the CPUs 101-1 to 101-3 hold it. The obtained primary cache information is acquired through the program information reading unit 207, and the state at the time of occurrence of an abnormality is collected. In the log control system 200, after acquiring the primary cache information of the CPUs 101-1 to 101-3, the operations of the CPUs 101-1 to 101-3 are stopped as necessary. The acquisition of the primary cache and secondary cache information of the CPUs 101-1 to 101-3 of the system operation system 100 by the log control system 200 is performed not only when an abnormality occurs in the system operation system 100, but also for trouble investigation and operation details. The abnormality detection processing unit 206 may stop and execute the CPU 101 at a timing when confirmation is desired.

<IO device access control>
Depending on the hardware configuration of the multi-core processor that constructs the trace device 1001, the system operation system 100 and the log control system 200 may access the common IO device 1. Further, in a Soc equipped with a multi-core processor, a common configuration is often used for IO devices. In this case, exclusive control is performed by the IO access control unit 105 of the system operation system 100 and the IO access control unit 205 of the log control system 200 in order to prevent access contention for commonly used IO devices. The IO access control unit 105 and the IO access control unit 205 notify the start and end of access to the commonly used IO device 1 via the communication path 3 by the inter-CPU communication unit 103 and the inter-CPU communication unit 203, respectively. Perform exclusive control. By sharing the access status to the commonly used IO device 1 between the system operation system 100 and the log control system 200 and confirming before accessing the IO device 1, contention can be prevented.

<Shutdown of trace device 1001>
The shutdown of the trace device 1001 terminates the log control system 200 after the system operation system 100 is terminated. The system operation system 100 notifies the log control system 200 of the shutdown using inter-CPU communication. After receiving the shutdown of the system operation system 100, the log control system 200 forcibly outputs the program operation information stored in the shared memory 23 to the IO device 1 and shuts down the log control system 200.

In the above example, the example of the multi-core processor having four CPUs has been described. However, the number of CPUs is not limited to this value, and a multi-core processor having two or more CPUs may be used. That is, the trace apparatus 1001 according to the first embodiment divides the number of CPUs into an arbitrary number in a multi-core processor having two or more CPUs, and constructs the system operation system 100 and the log control system 200. Alternatively, the system operation system 100 and the log control system 200 may be configured by using a part of a plurality of CPUs of a multi-core processor having a plurality of CPUs. For example, in a multi-core processor having five CPUs, three may be used for the system operation system 100 and one may be used for the log control system 200, similarly to the trace device 1001.
In the first embodiment, the case where the OS 102 is mounted on the system operation system 100 has been described. However, the first embodiment can be applied to a system in which the OS 102 is not mounted on the system operation system 100.
Further, since the log control system 200 has a simple configuration, the OS is not installed, but a configuration with a highly robust OS is also possible.
Furthermore, the system operation system 100 can have not only an SMP configuration but also a multi-OS configuration with an AMP configuration and a multi-CPU configuration.

Embodiment 2. FIG.
A trace device 1002 according to the second embodiment will be described with reference to FIG.
FIG. 8 is a configuration diagram of the trace device 1002 according to the second embodiment. In the trace apparatus 1002 of FIG. 8, in the example of constructing a trace apparatus using the multi-core processor shown in the first embodiment, the trace apparatus is constructed using a hypervisor which is one of computer virtualization technologies. The trace device 1002 mounts an OS 202 in the log control system 200 with respect to the trace device 1001, and realizes access control to the IO device 1 and an inter-CPU communication unit via the hypervisor 110. That is, the trace apparatus 1002 further includes the hypervisor 110 to constitute the system operation system 100 and the log control system 200.

  The difference from the first embodiment is that the OS 202 is installed in the log control system 200 as described above, and that the hypervisor 110 is used instead of the inter-CPU communication unit and the IO device access control unit. The method is the same as in the first embodiment. Alternatively, the hypervisor 110 may prioritize the access to the IO device 1 from the system operation system 100 and the log control system 200 and prioritize the IO device access from the system operation system 100. By performing IO device access with priority, it is possible to reduce the influence on the system operation system 100, that is, the waiting time when an IO device access conflict occurs.

Embodiment 3 FIG.
A trace device 1003 according to the third embodiment will be described with reference to FIGS.
FIG. 9 is a configuration diagram of the trace device 1003 according to the third embodiment. FIG. 9 shows an example of constructing a trace device in the multi-core processor shown in the first embodiment, and uses a monitor program 120, which is a program for monitoring and controlling computer input / output, and stores program operation information. In this configuration, the area of the memory 23 is protected. The trace device 1003 in FIG. 9 has a configuration in which the monitor program 120 is installed in the configuration of the first embodiment.
FIG. 10 is an example of a flowchart in which the application program 104 of the system operation system 100 accesses the shared memory 23. The monitor program 120 prevents unauthorized access to the shared memory 23. Only the process (program information writing unit 107) containing the program for writing the program operation information accesses the program operation information area of the shared memory 23. As shown in FIG. 10, the monitor program 120 monitors access to the shared memory 23 and determines whether the process is a process for writing program operation information (ST20). That is, the monitor program 120 determines in ST20 whether or not it is the program information writing unit 107 that writes to the shared memory 23. If the monitor program 120 is a process for writing program operation information (program information writing unit 107), the process for permitting access to the shared memory 23 (ST21) and writing the program operation information (program information writing unit 107) If not, access to the shared memory 23 is prohibited (ST22).

  The monitor program 120 (monitoring program) is a program other than a writing program that monitors writing to the shared memory 23 by using at least one of the CPUs 101-1 to 101-3 and CPU 201 of the multi-core processor. Writing to the shared memory 23 from the program is prohibited.

  For example, a process ID may be used as a method for determining whether or not the process writes program operation information. The monitor program 120 can prevent unnecessary access to the shared memory 23 from a 3rd Party application or a malicious program, thereby improving the robustness of the trace apparatus.

Embodiment 4 FIG.
A tracing device 1004 according to the fourth embodiment will be described with reference to FIG. In the first embodiment, an example in which a trace device is built in a multi-core processor has been shown, but it is also possible to build a log control system in another processor that can access the shared memory 23.
In FIG. 11, the system operation system 100 is constructed on a multi-core processor having four CPUs 101-1 to 101-4. Further, in this example, the log control system 200 is constructed in another processor including a CPU 201 that can access the shared memory 23 via the communication path 3. When the dedicated IO device 4 exists in another processor that constructs the log control system 200, the system operation system 100 and the log control system 200 do not cause access competition to the IO device, and thus the IO access control unit is unnecessary. . This embodiment is the same as the first embodiment except that the log control system 200 is constructed in a separate processor and that an IO access control unit is unnecessary in a hardware configuration that does not cause access competition to the IO device.

The tracing devices 1001 to 1004 according to the first to fourth embodiments described above have the following effects.
(1) The trace devices 1001 to 1004 process output processing to the IO device 1 that requires CPU resources and processing time by a dedicated CPU that is different from the CPU on which the system operates. Therefore, the system side (system operation system 100) can operate without being affected by the output processing load of the program operation information.
(2) The system operation system 100 and the log control system 200 operate in different systems. Therefore, even when the system operation system 100 that is the acquisition target of the program operation information is in a system down state, the program operation information is acquired from the shared memory 2 by the log control system 200 operating in a different system, and the acquired program operation information is It is possible to output to the device 1.
(3) When the log control system 200 monitors the operating state of the system operation system 100 and detects an abnormality in the system operation system 100, the program operation information written in the shared memory 2 is forcibly stored in the IO device 1. Output to. Accordingly, it is possible to prevent a situation in which the program operation information cannot be analyzed because the program operation information is not output.
(4) When an abnormality occurs in the system operation system 100, the CPU of the system operation system 100 is stopped from the log control system 200 to acquire cache information. Therefore, it is possible to analyze the cause immediately before the system operation system 100 that has entered an abnormal state.
(5) Access to the storage area for storing program operation information in the shared memory 23 is performed only by the system operation system 100 and only by the log control system 200. For this reason, the robustness of the trace devices 1001 to 1004 can be enhanced.
(6) Since the trace devices according to the first to fourth embodiments use the existing multi-core technology and realize the trace devices 1001 to 1004, the system size and the number of parts are not affected, and the cost is affected. Nor. Therefore, it can be introduced into an existing system equipped with a multi-core processor, or in a system using SoC (System-on-a-chip) or SiP (System In Package), which is often used in embedded devices in recent years. It can be introduced without changing.

  In the above description of the embodiment, what has been described as “to part” may be “to means”, and may also be “to step”, “to procedure”, and “to process”. . That is, what has been described as “˜unit” may be implemented by software alone, a combination of software and hardware, or a combination of firmware. Firmware and software are stored in a recording medium such as a magnetic disk as a program. The program is read by the CPU and executed by the CPU. That is, the program causes the computer to function as the “to part” described above. Alternatively, the computer executes the procedure and method of “to part” described above.

  Although the tracing device has been described in the above embodiment, it is obvious from the above description that the operation of the tracing device can be grasped as a program for causing a computer to function as a tracing device. Further, it is apparent from the above description that the operation of each “˜unit” of the trace apparatus can be grasped as a trace method.

  As mentioned above, although embodiment was described, you may implement combining 2 or more of these embodiments. Alternatively, one of these embodiments may be partially implemented. Alternatively, two or more of these embodiments may be partially combined. In addition, this invention is not limited to these embodiment, A various deformation | transformation is possible as needed.

  1 IO device, 2 memory, 3 communication path, 21 system operation system memory area, 22 log control system memory area, 23 shared memory, 101-1, 101-2, 101-3, 201 CPU of multi-core processor, 102 operating system , 103, 203 CPU communication unit, 104 application program, 105, 205 IO access control unit, 106, 206 abnormality detection processing unit, 100 system operation system, 200 log control system, 1001, 1002, 1003, 1004 trace device.

Claims (9)

In a trace device equipped with a multi-core processor having a plurality of CPUs (Central Processing Units),
A system operation unit that executes a program using one or more of the CPUs of the plurality of CPUs of the multi-core processor and collects program operation information indicating an operation history of the program;
Of the plurality of CPUs of the multi-core processor, one or more CPUs different from the CPU used by the system operation unit are used and are independent of the system operation unit without being affected by the operating status of the system operation unit. And a log control unit that outputs the program operation information collected by the system operation unit to an IO (Input / Output) device. The trace device further includes a storage device,
The system operating unit is
Write the collected program operation information to the storage device,
The log control unit
2. The trace apparatus according to claim 1, wherein the program operation information written by the system operation unit is read from the storage device, and the read program operation information is output to the IO device. The storage device
The trace apparatus according to claim 2, wherein the system operation unit and the log control unit are shared memories. The area for writing the program operation information in the shared memory is
4. The trace apparatus according to claim 3, wherein only the system operation unit can write. The log control unit
The operating state of the system operation unit is monitored, and if it is determined that an abnormality has occurred in the system operation unit as a result of monitoring, the program operation information existing in the storage device is forcibly output to the IO device. The trace device according to any one of claims 2 to 4, wherein The system operating unit is
When monitoring the operating state of the system operation unit and, as a result of monitoring, determining that an abnormality has occurred in the system operation unit, notify the log control unit of the occurrence of the abnormality,
The log control unit
6. When the occurrence of an abnormality is notified from the system operation unit, the program operation information existing in the storage device is forcibly output to the IO device. Trace device. The log control unit
When the program operation information existing in the storage device is forcibly output to the IO device, the cache information cached in the CPU used by the system operation unit is acquired, and the acquired cache information is stored in the storage device. The trace device according to claim 5, wherein the trace device is stored in the device. The system operating unit is
A program information writing unit for writing the program operation information to the shared memory;
The trace device further comprises:
Write monitoring unit that monitors writing to shared memory and prohibits writing to shared memory without using program information writing unit by using at least one of the plurality of CPUs of the multi-core processor The trace apparatus according to claim 3, further comprising: In the trace device which is a computer equipped with a multi-core processor having a plurality of CPUs (Central Processing Units),
A collection process of executing a program using one or more CPUs of the plurality of CPUs of the multi-core processor and collecting program operation information indicating a history of a processing status of the program;
Of the plurality of CPUs of the multi-core processor, one or more CPUs different from the CPU used for the collection process are used, and the operation is independent of the collection process without being affected by the operation status of the collection process. And a trace program for executing an output process for outputting the program operation information collected by the collection process to an IO (Input / Output) device.

Images