JP5644380B2 - Information processing device - Google Patents

Description

  The present invention relates to an information processing apparatus including a plurality of processing means represented by a multi-core processor.

  Conventionally, information processing apparatuses including a plurality of processing means have been widely used. For example, a multi-core processor in which a plurality of processor cores (CPU cores) are enclosed in one package and each processor core performs processing independently, a multi-processor processing apparatus including a plurality of processors such as CPUs, and the like are known. .

  In this type of information processing apparatus, the plurality of processing units may each execute a unique task. For example, in recent years, in the field of in-vehicle control devices, there has been a movement to integrate the functions of a plurality of control devices into one control device, but in this case, the functions originally possessed by a plurality of control devices are Usually assigned to each processing means. In this way, in an information processing apparatus having a plurality of processing means, each processing means may exhibit an important function, and when an abnormality occurs in any of the processing means, the other processing means It may be necessary to perform alternative processing.

  Patent Document 1 includes abnormality detection means for detecting an abnormality that has occurred in a specific processor, and based on the detection result, a specific processor assigned to a specific processor is assigned to any other processor than the specific processor. A multiprocessor system is described that replaces control. In this system, for example, the core 0 performs processing for vehicle control, and the cores 1 to 3 perform processing for information control. When an abnormality occurs in the core 0, the operating system of the core 1 ( The OS (registered trademark) is switched from the information control OS to the vehicle control OS. At this time, the configuration of the information control OS is changed by rewriting the registry and setting file.

  In addition, in an information processing apparatus including a plurality of processing means, in order to share data among the processing means and to allow each processing means to refer to data input / output to / from an external device, a shared memory is provided. Data is being stored. In the shared memory, various access restrictions are usually performed so that each processing means does not perform unlimited writing or the like.

  Patent Document 2 discloses an access authority information holding unit that holds information related to the access authority of each processor with respect to a predetermined area of the memory, and a memory management unit that manages access to the memory by each processor based on the information related to the access authority. , A multiprocessor system comprising: The access authority information defines the relationship between the address information and the type of access authority (“read”, “write”, “burst transfer”, “code transfer”, “data transfer”, etc.) and the CPU.

JP 2008-305317 A JP 2008-123031 A

  However, the system described in Patent Document 1 does not describe anything in terms of shared memory protection. As described in Patent Document 2, each of the plurality of processing means is often limited with respect to the range (address area and access type) accessible to the shared memory. A request to access the shared memory by the processing means to be performed may be rejected.

  As described above, when an unauthorized access request is made, a system reset may be performed, and as a result, a situation may occur in which the substitute process cannot be performed smoothly.

  The present invention is intended to solve such a problem. When an abnormality occurs in any of a plurality of processing means while realizing memory protection, it is smoothly performed (without causing an error or a system reset). ) A main object is to provide an information processing apparatus capable of performing alternative processing.

In order to achieve the above object, one embodiment of the present invention provides:
An information processing apparatus comprising a plurality of processing means,
A shared memory that is accessed by the plurality of processing means and in which a dedicated area assigned to each processing means is set;
A processing unit other than the processing unit to which the dedicated area of the shared memory is allocated by managing the operation states of the plurality of processing units and referring to the identification information held by each of the plurality of processing units. Management means for managing such that the dedicated area is not used ;
And a hardware unit which holds identification information of said plurality of processing means,
The management means includes
When one of the plurality of processing means is in an abnormal state, the other processing means is instructed to perform a substitute process for the processing means in the abnormal state, and the other processing means is in response to the instruction. When the shared memory is accessed from the processing means, instead of referring to the identification information held in the other processing means, the processing means in the abnormal state held by the hardware means by referring to the identification information, the dedicated region assigned to the processing means becomes the abnormal state, characterized in that it available to the other processing unit.

According to this aspect of the present invention, when one processing unit among a plurality of processing units is in an abnormal state, the management unit performs other processing so as to perform a substitute process for the processing unit in the abnormal state. When the shared memory is accessed from other processing means according to the instruction, instead of referring to the identification information held in the other processing means, the abnormal state held by the hardware means By referring to the identification information of the processing means that has become an abnormal state, the dedicated area allocated to the processing means that has become abnormal can be used for other processing means. When an abnormality occurs in any of the means, the substitute process can be smoothly performed.

In one embodiment of the present invention,
An information processing apparatus comprising a plurality of processing means,
A shared memory that is accessed by the plurality of processing means and in which a dedicated area assigned to each processing means is set;
A processing unit other than the processing unit to which the dedicated area of the shared memory is allocated by managing the operation states of the plurality of processing units and referring to the identification information held by each of the plurality of processing units. Management means for managing such that the dedicated area is not used;
Hardware means holding identification information of the plurality of processing means,
The management means includes
When one of the plurality of processing means is in an abnormal state , the other processing means is instructed to perform a substitute process for the processing means in the abnormal state and held by the hardware means By rewriting the identification information held by the processing means that performs the substitution process using the identification information of the processing means that has become abnormal, the dedicated area assigned to the processing means that has become abnormal , characterized in that it available to the other processing unit.

In one embodiment of the present invention,
An information processing apparatus comprising a plurality of processing means,
A shared memory that is accessed by the plurality of processing means and in which a dedicated area assigned to each processing means is set;
A processing unit other than the processing unit to which the dedicated area of the shared memory is allocated by managing the operation states of the plurality of processing units and referring to the identification information held by each of the plurality of processing units. Management means for managing such that the dedicated area is not used;
Hardware means holding identification information of the plurality of processing means,
The management means includes
When one of the plurality of processing means is in an abnormal state , the other processing means is instructed to perform alternative processing of the processing means in the abnormal state, and identification information held by itself Instead, by instructing the processing means that performs the alternative processing to output the identification information of the processing means in the abnormal state held by the hardware means, the processing means in the abnormal state is instructed. an exclusive area allocated, characterized in that it available to the other processing unit.

In one embodiment of the present invention,
The instruction to perform the alternative process may be given to a processing unit in an idle state.

In one embodiment of the present invention,
For example, the hardware means downloads the identification information of the plurality of processing means by downloading the identification information of the plurality of processing means from a ROM (Read Only Memory) or an EEPROM (Electrically Erasable and Programmable Read Only Memory). It is a register to hold.

In one embodiment of the present invention,
The management means is, for example, RTOS (Real-Time Operating System).

In one embodiment of the present invention,
The plurality of processing means are processor cores,
It may be configured as a multi-core processor.

  According to the present invention, it is possible to provide an information processing apparatus capable of smoothly performing substitution processing when an abnormality occurs in any of a plurality of processing units while realizing memory protection.

1 is a system configuration example of an information processing apparatus 1 according to a first embodiment of the present invention. It is a figure which shows the order of information transmission when the alternative process is instruct | indicated in the information processing apparatus 1 which concerns on 1st Example. It is a figure which shows the order of information transmission when the alternative process is instruct | indicated in the information processing apparatus 2 which concerns on 2nd Example. It is an example of a system configuration | structure of the information processing apparatus 3 which concerns on 3rd Example of this invention. It is a figure which shows the order of information transmission when the alternative process is instruct | indicated in the information processing apparatus 3 which concerns on 3rd Example.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

  Hereinafter, an information processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. The information processing apparatus according to each embodiment of the present invention is configured as a multi-core processor in which a plurality of processor cores (CPU cores; hereinafter omitted) are enclosed in one package, or a multi-processor processing apparatus including a plurality of processors such as CPUs. However, in the following description, it is assumed to be configured as a multi-core processor.

<First embodiment>
[Configuration, basic functions]
FIG. 1 is a system configuration example of an information processing apparatus 1 according to a first embodiment of the present invention. The information processing apparatus 1 includes processor cores 10 # 1 and 10 # 2, an identification ID holding register 20, an RTOS (Real-time operating system) 30, and a shared memory 40 as main components. These components are communicably connected by a bus (which may be a serial line) 50, for example. There is no particular limitation on the number of processor cores, but in the present embodiment, the number is two.

  The processor cores 10 # 1, 10 # 2 fetch an instruction sequence stored in a program memory (not shown) and temporarily store it, a program counter indicating the address of the fetched instruction sequence, and an instruction buffer. It has an instruction decoder that decodes (decodes) an instruction sequence, an arithmetic unit for executing an instruction decoded by the instruction decoder, a dedicated register for storing an operation result by the arithmetic unit, a primary cache memory, etc. Executes processing related to a specific task.

  The processor cores 10 # 1 and 10 # 2 have internal registers 12 # 1 and 12 # 2 that hold their identification IDs and the like, respectively.

  The identification ID holding register 20 holds identification IDs and the like of the processor cores 10 # 1 and 10 # 2.

  The identification IDs held by these registers are downloaded from a ROM (Read Only Memory) 15 or an EEPROM (Electrically Erasable and Programmable Read Only Memory) or the like when the information processing apparatus 1 is started or recovered. Although a register is suitable from the viewpoint of processing speed, a nonvolatile memory, other hardware means, or the like may be used instead of the register.

  The RTOS 30 is executed by any one of the processor cores 10 # 1, 10 # 2, or other processor cores. The RTOS 30 is a real-time operating system such as OSEK, ITRON, or the like. The RTOS 30 realizes the functions of a normal operating system and manages the operating states of the processor cores 10 # 1 and 10 # 2.

  The shared memory 40 is, for example, a RAM (Random Access Memory). In the shared memory 40, dedicated areas 40 # 1 and 40 # 2 that can be used by the processor cores 10 # 1 and 10 # 2 are set.

  Exclusive control for the dedicated area in the shared memory 40 is performed by the RTOS 30. When an access request from one of the processor cores to the shared memory 40 is made, the RTOS 30 refers to the identification ID held in the internal register 12 # 1 or 12 # 2 included in the requesting processor core, and accesses the identification ID and access. The addresses of the shared memory 40 included in the request are compared. If a processor core other than the processor core to which the dedicated area is assigned makes an access request to the dedicated area, it is rejected and error processing is executed. Thus, the processor cores other than the processor core to which the dedicated area is allocated are managed so as not to use the dedicated area (realization of memory protection).

[Alternative processing]
When one of the processor cores 10 # 1 and 10 # 2 that manage the operation state becomes an abnormal state, the RTOS 30 according to the first embodiment performs an alternative process for the processor core that has become the abnormal state. Instruct other processor cores to The instruction of the substitute process is not performed unconditionally, and the substitute process may not be instructed in consideration of the importance and urgency of the instruction executed by each processor core.

  Further, when three or more processor cores are provided, it is preferable that the function of the RTOS 30 is set in advance so that an alternative process is instructed to a processor core having a process margin such as an idle state.

  The RTOS 30 according to the first embodiment, when instructing an alternative process, replaces the identification ID held by the internal register 12 # 1 or 12 # 2 with the identification ID held by the identification ID holding register 20. Among these, the identification information of the processor core in an abnormal state is referred to.

  As a result, the processor core that performs the substitution process can use the dedicated area of the shared memory 40 that is allocated to the processor core that is in an abnormal state.

  FIG. 2 is a diagram illustrating the order of information transmission when an alternative process is instructed in the information processing apparatus 1 according to the first embodiment. In this figure, it is assumed that the processor core 10 # 2 is in an abnormal state. Further, illustration of the ROM 15 is omitted.

  (1) First, an interrupt signal indicating an abnormal state is transmitted from the processor core 10 # 2 to the RTOS 30. Instead of this, the RTOS 30 may perform polling or the like to detect an abnormality in the processor core 10 # 2.

  (2) Next, the RTOS 30 transmits an alternative instruction to the processor core 10 # 1.

  (3) Thereafter, an access request to the shared memory 40 is made from the processor core 10 # 1.

  (4) Since the RTOS 30 does not refer to the internal register 12 # 1 of the processor core 10 # 1, but refers to the identification ID of the processor core # 2 among the identification IDs held by the identification ID holding register 20, (5 ) Allow the processor core 10 # 1 to use the dedicated area for the processor core # 2.

  According to the information processing apparatus 1 of the present embodiment described above, when the RTOS 30 instructs an alternative process, the identification ID holding register 20 replaces the identification ID held by the internal register 12 # 1 or 12 # 2. Since the identification information of the processor core in an abnormal state is referred to among the stored identification IDs, memory protection is achieved, and when an abnormality occurs in any of the plurality of processor cores, an error or error Alternative processing can be performed without causing a system reset;

  In addition, since the information held in the register or the like is not changed and the substitute processing is realized through the processing of the RTOS 30, when the processor core in an abnormal state is restored, it can be quickly restored to the original state. it can. That is, recovery can be performed smoothly.

<Second embodiment>
[Configuration and basic functions] are the same as those in the first embodiment, and therefore, the same reference numerals are given to the respective constituent elements and the description thereof is omitted.

[Alternative processing]
As in the first embodiment, the RTOS 30 according to the second embodiment is in an abnormal state when any of the processor cores 10 # 1 and 10 # 2 managing the operation state is in an abnormal state. The other processor core is instructed to perform the processor core replacement process. The instruction of the substitute process is not performed unconditionally, and the substitute process may not be instructed in consideration of the importance and urgency of the instruction executed by each processor core.

  In addition, when the RTOS 30 according to the second embodiment instructs the substitute processing, the contents of the internal register of the processor core that instructs the substitute processing of the internal register 12 # 1 or 12 # 2 are set as an abnormal state. A process of rewriting the identification ID of the processor core that has become is executed. The identification ID of the processor core in an abnormal state is acquired from the identification ID holding register 20. Here, the “rewrite” process includes a process of instructing the processor core to “rewrite”.

  As a result, the processor core that performs the substitution process can use the dedicated area of the shared memory 40 that is allocated to the processor core that is in an abnormal state.

  FIG. 3 is a diagram illustrating the order of information transmission when an alternative process is instructed in the information processing apparatus 2 according to the second embodiment. In this figure, it is assumed that the processor core 10 # 2 is in an abnormal state. Further, illustration of the ROM 15 is omitted.

  (1) First, an interrupt signal indicating an abnormal state is transmitted from the processor core 10 # 2 to the RTOS 30. Instead of this, the RTOS 30 may perform polling or the like to detect an abnormality in the processor core 10 # 2.

  (2) Next, the RTOS 30 transmits an alternative instruction to the processor core 10 # 1. (3) At this time, the RTOS 30 rewrites (or rewrites) the contents of the internal register 12 # 1 of the processor core 10 # 1 to the identification ID of the processor core 10 # 2.

  (4) Thereafter, an access request to the shared memory 40 is made from the processor core 10 # 1.

  (5) The RTOS 30 refers to the internal register 12 # 1 of the processor core 10 # 1, reads the identification ID of the processor core # 2, and (6) the dedicated area for the processor core # 2 by the processor core 10 # 1. Allow use.

  According to the information processing apparatus 2 of the present embodiment described above, when the RTOS 30 instructs the substitution process, the contents of the internal register of the processor core that designates the substitution process are set to the identification ID of the processor core that is in an abnormal state. Therefore, the replacement process can be smoothly performed when an abnormality occurs in any of the plurality of processor cores while realizing memory protection.

<Third embodiment>
[Configuration, basic functions]
FIG. 4 is a system configuration example of the information processing apparatus 3 according to the third embodiment of the present invention. Since the information processing apparatus 3 according to the present embodiment is different from the first and second embodiments only in the information transmission path, the same reference numerals are given to the respective components, and the description thereof is omitted. In this embodiment, the identification ID holding register is subdivided, the register holding only the identification ID of the processor core 10 # 2 is connected to 10 # 1, and only the identification ID of the processor core 10 # 1 is held. It is also possible for the registered register to be connected to 10 # 2.

[Alternative processing]
As in the first embodiment, the RTOS 30 according to the third embodiment is in an abnormal state when any of the processor cores 10 # 1 and 10 # 2 managing the operation state is in an abnormal state. The other processor core is instructed to perform the processor core replacement process. The instruction of the substitute process is not performed unconditionally, and the substitute process may not be instructed in consideration of the importance and urgency of the instruction executed by each processor core.

  In addition, when the RTOS 30 according to the third embodiment instructs the substitution process, the abnormality held in the identification ID holding register 20 in place of the identification ID held by itself for the processor core performing the substitution process. Instructs to output the identification ID of the processor core in the state.

  As a result, the processor core that performs the substitution process can use the dedicated area of the shared memory 40 that is allocated to the processor core that is in an abnormal state.

  FIG. 5 is a diagram illustrating the order of information transmission when an alternative process is instructed in the information processing apparatus 3 according to the third embodiment. In this figure, it is assumed that the processor core 10 # 2 is in an abnormal state. Further, illustration of the ROM 15 is omitted.

  (1) First, an interrupt signal indicating an abnormal state is transmitted from the processor core 10 # 2 to the RTOS 30. Instead of this, the RTOS 30 may perform polling or the like to detect an abnormality in the processor core 10 # 2.

  (2) Next, the RTOS 30 transmits an alternative instruction to the processor core 10 # 1. (3) At this time, the RTOS 30 replaces the processor core 10 # 1 with the identification ID of the processor core 10 # 2 held by the identification ID holding register 20 instead of the identification ID held by the internal register 12 # 1. Is output.

  (4) The processor core 10 # 1 reads the identification ID of the processor core 10 # 2 from the identification ID holding register 20, and (5) the processor core 10 # 10 outputs an access request to the shared memory 40 to the RTOS 30. An access request is output together with the identification ID of # 2.

  (6) Since the RTOS 30 is an access request input together with the identification ID of the processor core 10 # 2, the RTOS 30 permits the processor core 10 # 1 to use a dedicated area for the processor core # 2.

  According to the information processing apparatus 3 of the present embodiment described above, when the RTOS 30 instructs the substitution process, the identification ID holding register 20 is used instead of the identification ID held by itself for the processor core performing the substitution process. In order to instruct to output the identification ID of the processor core that has been held in an abnormal state, it is possible to perform replacement processing smoothly when an abnormality occurs in any of the plurality of processor cores while realizing memory protection. Can be done.

  In the information processing apparatus 3 of the third embodiment, it is necessary that the program executed by each processor core has a function of switching the identification ID in accordance with an instruction from the RTOS 30. For this reason, it is necessary to include in advance a sequence of instructions for switching the identification ID in accordance with an instruction from the RTOS 30 in a program executed by each processor core.

  On the other hand, in the case of the first embodiment and the second embodiment, there is an advantage that the present invention can be realized only by correcting the function of the RTOS 30 without the need for the additional function of the program as described above.

  The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

1, 2, 3 Information processing apparatus 10 # 1, 10 # 2 Processor core 12 # 1, 12 # 2 Internal register 15 ROM
20 Identification ID holding register 30 RTOS
40 shared memory 40 # 1, 40 # 2 dedicated area 50 bus

Claims (7)

An information processing apparatus comprising a plurality of processing means,
A shared memory that is accessed by the plurality of processing means and in which a dedicated area assigned to each processing means is set;
A processing unit other than the processing unit to which the dedicated area of the shared memory is allocated by managing the operation states of the plurality of processing units and referring to the identification information held by each of the plurality of processing units. Management means for managing such that the dedicated area is not used ;
And a hardware unit which holds identification information of said plurality of processing means,
The management means includes
When one of the plurality of processing means is in an abnormal state, the other processing means is instructed to perform a substitute process for the processing means in the abnormal state, and the other processing means is in response to the instruction. When the shared memory is accessed from the processing means, instead of referring to the identification information held in the other processing means, the processing means in the abnormal state held by the hardware means by referring to the identification information, the dedicated region assigned to the processing unit in an abnormal state, the information processing apparatus, characterized in that available to the other processing unit. An information processing apparatus comprising a plurality of processing means,
A shared memory that is accessed by the plurality of processing means and in which a dedicated area assigned to each processing means is set;
A processing unit other than the processing unit to which the dedicated area of the shared memory is allocated by managing the operation states of the plurality of processing units and referring to the identification information held by each of the plurality of processing units. Management means for managing such that the dedicated area is not used;
Hardware means holding identification information of the plurality of processing means,
The management means includes
When one of the plurality of processing means is in an abnormal state , the other processing means is instructed to perform a substitute process for the processing means in the abnormal state and held by the hardware means By rewriting the identification information held by the processing means that performs the substitution process using the identification information of the processing means that has become abnormal, the dedicated area assigned to the processing means that has become abnormal An information processing apparatus which can be used for the other processing means. An information processing apparatus comprising a plurality of processing means,
A shared memory that is accessed by the plurality of processing means and in which a dedicated area assigned to each processing means is set;
A processing unit other than the processing unit to which the dedicated area of the shared memory is allocated by managing the operation states of the plurality of processing units and referring to the identification information held by each of the plurality of processing units. Management means for managing such that the dedicated area is not used;
Hardware means holding identification information of the plurality of processing means,
The management means includes
When one of the plurality of processing means is in an abnormal state , the other processing means is instructed to perform alternative processing of the processing means in the abnormal state, and identification information held by itself Instead, by instructing the processing means that performs the alternative processing to output the identification information of the processing means in the abnormal state held by the hardware means, the processing means in the abnormal state is instructed. An information processing apparatus characterized in that the allocated dedicated area can be used for the other processing means. The information processing apparatus according to any one of claims 1 to 3 ,
The alternative process instruction for performing the an information processing apparatus, characterized in that it is made to processing means adapted idle. The information processing apparatus according to any one of claims 1 to 4 ,
The hardware means holds the identification information of the plurality of processing means by downloading the identification information of the plurality of processing means from a ROM (Read Only Memory) or an EEPROM (Electrically Erasable and Programmable Read Only Memory). An information processing apparatus characterized by being a register. An information processing apparatus according to any one of claims 1 to 5 ,
It said management means, information processing apparatus, characterized in that the RTOS (Real-Time Operating System) . The plurality of processing means are processor cores,
Configured as a multi-core processor, the information processing apparatus according to any one of claims 1 to 6.

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