JP6542961B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to an object, a method, or a method of manufacturing. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, the present invention relates to, for example, a semiconductor device, a display device, a light emitting device, a power storage device, a driving method thereof, or a manufacturing method thereof. In particular, the present invention relates to, for example, a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor. In particular, the present invention relates to, for example, a semiconductor device having a transistor and a method for manufacturing the same.

A transistor used in many flat panel displays represented by a liquid crystal display device and a light emitting display device is formed of a silicon semiconductor such as amorphous silicon, single crystal silicon or polycrystalline silicon formed on a glass substrate. . In addition, transistors using the silicon semiconductor are also used in integrated circuits (ICs) and the like.

In recent years, in place of silicon semiconductors, a technique using a metal oxide exhibiting semiconductor characteristics for a transistor has attracted attention. Note that in this specification, a metal oxide exhibiting semiconductor characteristics is referred to as an oxide semiconductor.

For example, a technology is disclosed in which a transistor including zinc oxide or an In—Ga—Zn-based oxide is manufactured as an oxide semiconductor and the transistor is used as a switching element of a pixel of a display device (Patent Document 1) And Patent Document 2).

Unexamined-Japanese-Patent No. 2007-123861 JP 2007-96055 A

In a transistor including an oxide semiconductor film, a large amount of defects included in the oxide semiconductor film leads to a defect in the electrical characteristics of the transistor and a change over time or a stress test (for example, a BT (Bias-Temperature) stress test) ), Which causes the increase of the fluctuation of the electrical characteristics of the transistor, typically the threshold voltage.

In addition, when the amount of impurities contained in the oxide semiconductor film, typically, impurities such as silicon and carbon which are constituent elements of the insulating film is large as well as defects, electric characteristics of the transistor become unnecessary.

Thus, an object of one embodiment of the present invention is to reduce defects in an oxide semiconductor film in a semiconductor device or the like using an oxide semiconductor film. Alternatively, an object of one embodiment of the present invention is to reduce the impurity concentration of an oxide semiconductor film in a semiconductor device or the like using an oxide semiconductor film. Alternatively, an object of one embodiment of the present invention is to improve electrical characteristics in a semiconductor device or the like using an oxide semiconductor film. Another object of one embodiment of the present invention is to improve the reliability of a semiconductor device or the like using an oxide semiconductor film. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or the like with low off current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or the like with low power consumption. Alternatively, an object of one embodiment of the present invention is to provide a display device and the like which can reduce eye fatigue. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or the like using a transparent semiconductor film. Alternatively, an object of one embodiment of the present invention is to provide a novel semiconductor device or the like. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device or the like having excellent characteristics. Note that the descriptions of these objects do not disturb the existence of other objects. Note that in one embodiment of the present invention, it is not necessary to solve all of these problems. In addition, problems other than these are naturally apparent from the description of the specification, drawings, claims and the like, and it is possible to extract the problems other than these from the description of the specification, drawings, claims and the like. It is.

In one embodiment of the present invention, a gate electrode and a gate insulating film are formed over a substrate, a multilayer film including an oxide semiconductor film and an oxide film is formed over the gate insulating film, and 300 ° C. to 400 ° C., preferably After performing the first heat treatment at 320 ° C. to 370 ° C., a pair of electrodes in contact with the multilayer film is formed, and a first oxide insulating film is formed over the multilayer film and the pair of electrodes. A second oxide insulating film is formed over the first oxide insulating film, and a second heat treatment is performed at 300 ° C to 400 ° C, preferably 320 ° C to 370 ° C; is there.

Note that the substrate placed in the evacuated processing chamber is maintained at 180 ° C. to 400 ° C., the source gas is introduced into the processing chamber, the pressure in the processing chamber is 100 Pa to 250 Pa, and the substrate is provided in the processing chamber. By supplying high frequency power to the electrode, the first oxide insulating film can be formed.

The substrate placed in the evacuated processing chamber is maintained at 180 ° C. to 280 ° C., the source gas is introduced into the processing chamber, the pressure in the processing chamber is set to 100 Pa to 250 Pa, and the substrate is installed in the processing chamber. by supplying a high frequency power of 0.17 W / cm ² or more 0.5 W / cm ² or less to the electrode, it is possible to form the second oxide insulating film.

In addition, as the first oxide insulating film and the second oxide insulating film, a silicon oxide film or a silicon oxynitride film is formed using a deposition gas containing silicon and an oxidizing gas as a source gas.

  Note that the oxide semiconductor film preferably contains In or Ga.

Further, the energy level of the lower end of the conduction band of the oxide film is closer to the vacuum level than the energy level of the lower end of the conduction band of the oxide semiconductor film. Furthermore, the difference between the energy level at the lower end of the conduction band of the oxide film and the energy level at the lower end of the conduction band of the oxide semiconductor film is 0.05 eV or more.
It is preferable that it is V or less. Note that since the energy difference between the vacuum level and the lower end of the conduction band is also called electron affinity, the electron affinity of the oxide film is smaller than the electron affinity of the oxide semiconductor film, and the difference is 0.05 eV or more and 2 eV or less preferable.

According to one embodiment of the present invention, in a semiconductor device using an oxide semiconductor film, defects in the oxide semiconductor film can be reduced. Alternatively, in one embodiment of the present invention, impurities in the oxide semiconductor film can be reduced in a semiconductor device or the like using the oxide semiconductor film. Alternatively, according to one embodiment of the present invention, electrical characteristics can be improved in a semiconductor device using an oxide semiconductor film. Alternatively, according to one embodiment of the present invention, reliability can be improved in a semiconductor device using an oxide semiconductor film. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like with low off current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a display device or the like capable of reducing eye fatigue can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like using a transparent semiconductor film can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device or the like can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like with excellent characteristics can be provided.

7A and 7B are a top view and a cross-sectional view illustrating one embodiment of a transistor. FIG. 7 is a cross-sectional view illustrating one embodiment of a method for manufacturing a transistor. It is a figure explaining the band structure of a transistor. FIG. 5 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 5 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 5 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 5 is a cross-sectional view illustrating one embodiment of a transistor. 7A and 7B are a top view and a cross-sectional view illustrating one embodiment of a transistor. 7A and 7B are a top view and a cross-sectional view illustrating one embodiment of a transistor. FIG. 7 is a cross-sectional view illustrating one embodiment of a method for manufacturing a transistor. FIG. 5 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 5 is a cross-sectional view illustrating one embodiment of a transistor. 7A and 7B are a top view and a cross-sectional view illustrating one embodiment of a transistor. 7A and 7B are a top view and a cross-sectional view illustrating one embodiment of a transistor. 1A and 1B are a block diagram and a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 5 is a top view illustrating one embodiment of a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 5 is a top view illustrating one embodiment of a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 5 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. It is a figure which shows the micro electron beam diffraction pattern of an oxide semiconductor. It is a figure which shows the micro electron beam diffraction pattern of an oxide semiconductor. It is a figure explaining the touch sensor concerning an embodiment. It is a figure explaining the example of composition of the touch panel and electronic equipment concerning an embodiment. It is a figure explaining a pixel provided with a touch sensor concerning an embodiment. It is a figure explaining operation of a touch sensor concerning an embodiment, and a pixel. It is a block diagram which shows the structural example of a liquid crystal display device. 5 is a timing chart illustrating an example of a method of driving a liquid crystal display device. FIG. 5 illustrates an electronic device using a semiconductor device which is an embodiment of the present invention. FIG. 5 illustrates an electronic device using a semiconductor device which is an embodiment of the present invention. It is a figure which shows the Vg-Id characteristic of a transistor. FIG. 16 is a diagram showing variation amounts of threshold voltage and shift value of a transistor after BT stress test and light BT stress test. It is a figure explaining the definition of a threshold voltage and a shift value. It is a figure which shows the threshold value of the transistor after an optical BT stress test and an optical BT stress test. It is a figure which shows the Vg-Id characteristic of the transistor before and behind BT stress test.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit of the present invention and the scope thereof. Therefore, the present invention should not be construed as being limited to the description of the embodiments and examples given below. In the embodiments and examples described below, the same reference numerals or the same hatch patterns are used in common in different drawings for the same portions or portions having similar functions, and the repetitive description thereof is omitted. Do.

In each of the drawings described in this specification, the size of each component, the thickness of the film, or the region is
May be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.

Further, the terms first, second, third and the like used in the present specification are given to avoid confusion of components, and are not limited numerically. Therefore, for example, "first" can be appropriately replaced with "second" or "third" and the like.

In addition, the functions of "source" and "drain" may be switched when the direction of current changes in circuit operation. Therefore, in the present specification, the terms "source" and "drain" can be used interchangeably.

In addition, voltage refers to a potential difference between two points, and potential refers to electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, in general, the potential difference between a potential at a certain point and a reference potential (for example, ground potential) is simply referred to as a potential or a voltage, and the potential and the voltage are often used as synonyms. Therefore, unless otherwise specified in the present specification, the potential may be read as a voltage, or the voltage may be read as a potential.

In this specification, in the case where the etching step is performed after the photolithography step, the mask formed in the photolithography step is removed.

Embodiment 1
In this embodiment mode, a semiconductor device which is one embodiment of the present invention and a manufacturing method thereof are described with reference to drawings.

In a transistor including an oxide semiconductor film, oxygen vacancies are examples of defects leading to defects in the electrical characteristics of the transistor. For example, in a transistor including an oxide semiconductor film in which oxygen vacancies are contained in the film, the threshold voltage is likely to change in the negative direction, and thus, the transistor tends to be normally on. This is because charge is generated due to oxygen vacancies contained in the oxide semiconductor film to reduce resistance. When the transistor has normally-on characteristics, various problems occur such as an operation failure is likely to occur during operation, or power consumption during non-operation is increased. In addition, there is a problem in that the amount of change in the electrical characteristics of the transistor, typically the threshold voltage, is increased due to aging or a stress test.

One of the causes of oxygen deficiency is damage that occurs in the manufacturing process of the transistor.
For example, when an insulating film, a conductive film, or the like is formed over the oxide semiconductor film by a plasma CVD method or a sputtering method, the oxide semiconductor film may be damaged depending on the formation conditions.

In addition to oxygen vacancies, impurities such as silicon and carbon, which are constituent elements of the insulating film, and water also cause defects in electrical characteristics of the transistor. Therefore, when the impurity is mixed into the oxide semiconductor film, the resistance of the oxide semiconductor film is lowered, and electrical characteristics of the transistor, which is typically a threshold voltage, are measured by a change over time or a stress test. There is a problem that the amount of fluctuation increases.

Therefore, in this embodiment, in a semiconductor device including a transistor including an oxide semiconductor film, it is an object to reduce oxygen vacancies in an oxide semiconductor film including a channel region and impurity concentration of the oxide semiconductor film. I assume.

On the other hand, the display devices sold in the market tend to become larger with a screen size of 60 inches or more diagonally, and further, development is performed taking into consideration the screen size of 120 inches diagonally or more There is. For this reason, in the glass substrate used for a display apparatus, the area enlargement of 8th generation or more is advanced. However, when using a large area substrate, high temperature processing, eg 450
Because the heating process is performed at a temperature of at least ° C., the heating apparatus becomes large and expensive, and the production cost increases. In addition, when the high temperature treatment is performed, the warpage or shrink of the substrate occurs, and the yield is reduced.

Therefore, it is an object of the present embodiment to manufacture a semiconductor device using heat treatment with a small number of heat treatment steps and a temperature at which a large-area substrate can be used.

1A to 1C illustrate a top view and a cross-sectional view of the transistor 50 included in the semiconductor device. The transistor 50 shown in FIG. 1 is a channel etch type transistor. 1A is a top view of the transistor 50, and FIG. 1B is a dashed-dotted line A- in FIG. 1A.
FIG. 1 (C) is a cross-sectional view taken along the alternate long and short dash line C-D in FIG. 1 (A). Note that in FIG. 1A, the substrate 11, part of components of the transistor 50 (eg, the gate insulating film 17), the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film for the sake of clarity. 25 etc. are omitted.

The transistor 50 illustrated in FIGS. 1B and 1C includes a gate electrode 15 provided over the substrate 11. In addition, a gate insulating film 17 formed on the substrate 11 and the gate electrode 15
And a multilayer film 20 overlapping with the gate electrode 15 via the gate insulating film 17 and a pair of electrodes 21 and 22 in contact with the multilayer film 20. In addition, the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 are formed on the gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 and 22.
A protective film 26 is formed.

In the transistor 50 described in this embodiment, the multilayer film 20 includes the oxide semiconductor film 18 and the oxide film 19. Further, part of the oxide semiconductor film 18 functions as a channel region. Further, the oxide insulating film 23 is formed to be in contact with the multilayer film 20, and the oxide insulating film 24 is formed to be in contact with the oxide insulating film 23. That is, the oxide film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23.

The oxide semiconductor film 18 is typically an In-Ga oxide film, an In-Zn oxide film, or In
-M-Zn oxide film (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf
).

Note that when the oxide semiconductor film 18 is an In-M-Zn oxide film, the atomic ratio of In to M is preferably 25 at, where the sum of In and M is 100 atomic%.
greater than or equal to M, less than 75 atomic% in M, and more preferably 34 at
c% or more, M is less than 66 atomic%.

The oxide semiconductor film 18 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. Thus, the off-state current of the transistor 50 can be reduced by using an oxide semiconductor with a wide energy gap.

The thickness of the oxide semiconductor film 18 is 3 nm to 200 nm, preferably 3 nm to 10 nm.
The thickness is 0 nm or less, more preferably 3 nm or more and 50 nm or less.

The oxide film 19 is typically an In-Ga oxide, an In-Zn oxide, or In-M-Zn.
Is an oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and the energy of the lower end of the conduction band is closer to the vacuum level than the oxide semiconductor film 18, and typically The difference between the energy at the lower end of the conduction band of the oxide film 19 and the energy at the lower end of the conduction band of the oxide semiconductor film 18 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0. 15
It is eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the oxide film 19 and the electron affinity of the oxide semiconductor film 18 is 0.
05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2e
It is V or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

As the oxide film 19, Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf can be used.
By having an atomic ratio higher than n, the following effects may be obtained. (1) Oxide film 1
Increase the energy gap of 9. (2) The electron affinity of the oxide film 19 is reduced.
(3) Shield impurities from the outside. (4) The insulating property is higher than that of the oxide semiconductor film 18. (5) Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf is a metal element having a strong bonding force with oxygen, and therefore Al, Ti, Ga, Y, Zr, La, Ce, Nd or By having Hf in an atomic ratio higher than In, oxygen deficiency is less likely to occur.

When the oxide film 19 is an In-M-Zn oxide film, the sum of In and M is 100 ato
The atom number ratio of In to M is preferably 50 atomic% of In, assuming that it is mic%
Less than, M is 50 atomic% or more, more preferably, In is less than 25 atomic%, and M is 75 atomic% or more.

In addition, the oxide semiconductor film 18 and the oxide film 19 are In-M-Zn oxide films (M is Al,
In the case of Ti, Ga, Y, Zr, La, Ce, Nd or Hf, M (Al, Ti, Ga, Y, Zr, La, contained in the oxide film 19 in comparison with the oxide semiconductor film 18 Ce, Nd,
Or an atom number ratio of Hf) is large, and typically, it is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more higher than the atoms contained in the oxide semiconductor film 18 It is a number ratio.

In addition, the oxide semiconductor film 18 and the oxide film 19 are In-M-Zn oxide films (M is Al,
In the case of Ti, Ga, Y, Zr, La, Ce, Nd or Hf), the oxide film 19 is made of In: M
: Zn = x ₁ : y ₁ : z ₁ [atomic ratio], and the oxide semiconductor film 18 is made of In: M: Zn = x ₂ :
Assuming that y ₂ : z ₂ [atomic number ratio], y ₁ / x ₁ is larger than y ₂ / x ₂ , preferably
y ₁ / x ₁ is 1.5 times or more than y ₂ / x ₂ . More preferably, y ₁ / x ₁ is y
_It is more than 2 times larger than ₂ / x ₂ , more preferably, y ₁ / x ₁ is more than 3 times larger than y ₂ / x ₂ . At this time, it is preferable that y ₂ be x ₂ or more in the oxide semiconductor film because stable electric characteristics can be given to the transistor including the oxide semiconductor film. Where y
_{When 2} is three or more times as large as x ₂ , the field-effect mobility of a transistor including the oxide semiconductor film is reduced, so y ₂ is preferably less than three times as large as x ₂ .

For example, an In—Ga—Zn oxide having an atomic ratio of In: Ga: Zn = 1: 1: 1 or 3: 1: 2 can be used as the oxide semiconductor film 18. Also, as the oxide film 19, I
n: Ga: Zn = Zn = 1: 3: 2, 1: 3: 4, 1: 6: 2, 1: 6: 4, 1: 6: 1
An In-Ga-Zn oxide having an atomic ratio of 0 or 1: 9: 6 can be used. Note that the atomic ratio of the oxide semiconductor film 18 and the oxide film 19 includes a variation of plus or minus 20% of the atomic ratio of the metal element contained in the sputtering target as an error.

As the oxide semiconductor film 18 and the oxide film 19, an oxide semiconductor film with low carrier density is used. For example, the oxide semiconductor film 18 and the oxide film 19 have a carrier density of 1 × 10
¹⁷ pieces / cm ³ or less, preferably 1 × 10 ¹⁵ pieces / cm ³ or less, more preferably 1 × 1
0 ¹³ / cm ³ or less, more preferably 1 × ^{10 11} atoms / cm ³ using the following oxide semiconductor film.

Note that the composition is not limited to those described above, and a composition having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, and the like) of the required transistor. In addition, in order to obtain semiconductor characteristics of a required transistor, the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the oxide semiconductor film 18 are made appropriate. Is preferred.

The oxide film 19 is an oxide semiconductor film 18 when an oxide insulating film 24 to be formed later is formed.
It also functions as a damage alleviation film.

The thickness of the oxide film 19 is 3 nm to 100 nm, preferably 3 nm to 50 nm.

Note that by using an oxide semiconductor film having a low impurity concentration and a low density of defect states as the oxide semiconductor film 18, a transistor having further excellent electrical characteristics can be preferably manufactured. Here, the fact that the impurity concentration is low and the density of defect states is low (the amount of oxygen deficiency is small) is called high purity intrinsic or substantially high purity intrinsic.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may be able to reduce the carrier density because the number of carriers is small. Thus, in the transistor in which a channel region is formed in the oxide semiconductor film, the threshold voltage may be negative (also referred to as normally on) in some cases.

In addition, since the high purity intrinsic or the substantially high purity intrinsic oxide semiconductor film has a low density of defect states, the density of trap states may also be low.

In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a very small off-state current, a device with a channel width of 1 × 10 ⁶ μm and a channel length L of 10 μm, When the voltage between drain electrodes (drain voltage) is in the range of 1 V to 10 V, it is possible to obtain the characteristic that the off current is less than the measurement limit of the semiconductor parameter analyzer, that is, less than 1 × 10 ⁻¹³ A.

Thus, a transistor in which a channel region is formed in the oxide semiconductor film might be a transistor with high reliability, which has less variation in electrical characteristics. Note that the charge trapped in the trap states of the oxide semiconductor film may take a long time to disappear and may behave like fixed charge. Therefore, the transistor whose channel region is formed in the oxide semiconductor film with high trap state density may have unstable electrical characteristics. The impurities include hydrogen, nitrogen, alkali metals or alkaline earth metals.

Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to form water,
An oxygen vacancy is formed in the lattice from which oxygen is released (or the portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons that are carriers may be generated. In addition, when a part of hydrogen bonds to oxygen which is bonded to a metal atom, an electron which is a carrier may be generated. Thus, a transistor including an oxide semiconductor which contains hydrogen is likely to be normally on.

Therefore, it is preferable that hydrogen be reduced as much as possible in the oxide semiconductor film 18. Specifically, secondary ion mass spectrometry (SIMS: Secon) is performed on the oxide semiconductor film 18.
The hydrogen concentration obtained by dary ion mass spectrometry is
5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³
Or less, 5 × 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁸ atoms / cm
³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, still more preferably 1 × 1
0 ¹⁶ atoms / cm ³ or less.

When the oxide semiconductor film 18 contains silicon or carbon, which is one of the group 14 elements, the amount of oxygen vacancies in the oxide semiconductor film 18 is increased to be n-type. Therefore, the concentration of silicon or carbon in the oxide semiconductor film 18, or the concentration of silicon or carbon in the vicinity of the interface between the oxide film 19 and the oxide semiconductor film 18 (the concentration obtained by secondary ion mass spectrometry)
And 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³
It is assumed that

Further, in the oxide semiconductor film 18, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. Make it When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, which may increase the off-state current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film 18.

In addition, when nitrogen is contained in the oxide semiconductor film 18, electrons which are carriers are generated, carrier density is increased, and n-type is easily formed. As a result, a transistor including an oxide semiconductor which contains nitrogen is likely to be normally on. Therefore, in the oxide semiconductor film, nitrogen is preferably reduced as much as possible. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is preferably 5 × 10 ¹⁸ atoms / cm ³ or less. .

The oxide semiconductor film 18 and the oxide film 19 may have, for example, a non-single-crystal structure. The non-single crystal structure is, for example, a CAAC-OS (C Axis Aligned Crys described later).
talline Oxide Semiconductor), polycrystalline structure, microcrystalline structure described later, or amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect states, and CAAC-OS has the lowest density of defect states.

The oxide semiconductor film 18 and the oxide film 19 may have, for example, an amorphous structure. The oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystalline component. Alternatively, the oxide film having an amorphous structure has, for example, a completely amorphous structure and no crystal part.

Note that the oxide semiconductor film 18 and the oxide film 19 have two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. It may be a mixed membrane. The mixed film may have, for example, two or more regions of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. In addition, the mixed film may have, for example, a stacked structure of two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. May have.

Here, the oxide film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23. Thus, even if trap states are formed between the oxide film 19 and the oxide insulating film 23 due to impurities and defects, there is a gap between the trap states and the oxide semiconductor film 18. As a result, electrons flowing through the oxide semiconductor film 18 are not easily captured by the trap states, which can increase the on-state current of the transistor and can increase the field-effect mobility. In addition, when an electron is trapped in the trap level, the electron becomes a negative fixed charge. As a result, the threshold voltage of the transistor fluctuates. However, since there is a gap between the oxide semiconductor film 18 and the trap level, trapping of electrons in the trap level can be reduced and fluctuation in threshold voltage can be reduced.

Further, since the oxide film 19 can shield impurities from the outside, the amount of impurities moving from the outside to the oxide semiconductor film 18 can be reduced. Also, oxide film 1
9 is difficult to form oxygen deficiency. For these reasons, the impurity concentration and the oxygen deficiency amount in the oxide semiconductor film 18 can be reduced.

In the transistor 50 described in this embodiment, the oxide insulating film 23 is formed in contact with the multilayer film 20, and the oxide insulating film 24 in contact with the oxide insulating film 23 is formed.

The oxide insulating film 23 is an oxide insulating film which transmits oxygen. Note that the oxide insulating film 23 also functions as a film for alleviating damage to the multilayer film 20 when the oxide insulating film 24 to be formed later is formed.

As the oxide insulating film 23, a silicon oxide film, a silicon oxynitride film, or the like with a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm, can be used. Note that in this specification, a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen as its composition, and a silicon nitride oxide film has a nitrogen content more than oxygen as its composition Refers to a membrane with many

The oxide insulating film 23 preferably has a small amount of defects. Typically, the spin density of a signal appearing at g = 2.001 derived from dangling bonds of silicon is 3 × 10 ¹⁷ by ESR measurement. It is preferable that it is spins / cm < ³ > or less. This is because if the density of defects included in the oxide insulating film 23 is high, oxygen is bonded to the defects, and the oxide insulating film 2
This is because the amount of oxygen permeation in 3 decreases.

In addition, it is preferable that the amount of defects at the interface between the oxide insulating film 23 and the multilayer film 20 be small, and typically, spin of a signal appearing at g = 1.93 derived from defects of the multilayer film 20 by ESR measurement. The density is preferably 1 × 10 ¹⁷ spins / cm ³ or less, and more preferably the detection lower limit or less.

Note that in the oxide insulating film 23, all oxygen that has entered the oxide insulating film 23 from the outside does not move to the outside of the oxide insulating film 23, and some oxygen remains in the oxide insulating film 23. Further, oxygen enters the oxide insulating film 23 and oxygen contained in the oxide insulating film 23 is the oxide insulating film 23.
The movement of oxygen may occur in the oxide insulating film 23 by moving to the outside of the

When an oxide insulating film which transmits oxygen is formed as the oxide insulating film 23, the oxide insulating film 23 is formed.
Oxygen released from the oxide insulating film 24 which is provided thereover can be transferred to the oxide semiconductor film 18 through the oxide insulating film 23.

An oxide insulating film 24 is formed in contact with the oxide insulating film 23. Oxide insulating film 2
4 is formed using an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition. In the oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition, part of oxygen is released by heating. The oxide insulating film containing oxygen at a higher proportion than the stoichiometric composition has a desorption amount of oxygen of 1.0 × 10 ¹⁸ atoms in terms of oxygen atoms in TDS analysis.
It is an oxide insulating film which has a density of at least ³ cm ³ , preferably at least 3.0 × 10 ²⁰ atoms / cm ³ .

The oxide insulating film 24 has a thickness of 30 nm to 500 nm, preferably 50 nm.
A silicon oxide film, a silicon oxynitride film, or the like with a thickness of 400 nm or less can be used.

The oxide insulating film 24 preferably has a small amount of defects, and typically, the spin density of a signal appearing at g = 2.001 derived from dangling bonds of silicon is 1.5 × by ESR measurement. Less than 10 ¹⁸ spins / cm ³ and further 1 × 10 ¹⁸ spins / cm
It is preferable that it is ³ or less. Note that since the oxide insulating film 24 is separated from the multilayer film 20 as compared to the oxide insulating film 23, the defect density may be higher than that of the oxide insulating film 23.

  Hereinafter, details of another configuration of the transistor 50 will be described.

The material of the substrate 11 and the like are not particularly limited, but at least the heat resistance needs to be sufficient to withstand the subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 11. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SO
It is also possible to apply an I substrate or the like, and a substrate provided with semiconductor elements on these substrates may be used as the substrate 11. When a glass substrate is used as the substrate 11, the sixth
Generation (1500 mm × 1850 mm), Seventh Generation (1870 mm × 2200 mm), Eighth
Generation (2200 mm × 2400 mm), 9th Generation (2400 mm × 2800 mm), 1st
A large-sized display device can be manufactured by using a large-area substrate such as 0 generation (2950 mm × 3400 mm).

Alternatively, a flexible substrate may be used as the substrate 11 and the transistor 50 may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 11 and the transistor 50. The peeling layer can be used to separate from the substrate 11 and reprint it on another substrate after the semiconductor device is partially or completely completed thereon. At this time, the transistor 50 can be transferred to a substrate having low heat resistance or a flexible substrate.

The gate electrode 15 is formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described metal element, or an alloy combining the above-described metal elements, or the like. can do. In addition, a metal element selected from any one or more of manganese and zirconium may be used. The gate electrode 15 may have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a titanium nitride film Layer structure, two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film,
There is a titanium film, a three-layer structure in which an aluminum film is laminated on the titanium film, and a titanium film is formed thereon. Alternatively, an alloy film or nitride film in which one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined with aluminum may be used.

The gate electrode 15 may be made of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Also,
A stacked structure of the above-described light-transmitting conductive material and the above-described metal element can also be employed.

In addition, an In—Ga—Zn-based oxynitride film, an In—Sn-based oxynitride film, an In—Ga-based oxynitride film, an In—Zn-based oxynitride film, between the gate electrode 15 and the gate insulating film 17. Film,
A Sn-based oxynitride film, an In-based oxynitride film, a metal nitride film (InN, ZnN or the like) or the like may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, which is larger than the electron affinity of the oxide semiconductor, and thus shift the threshold voltage of the transistor including the oxide semiconductor to a positive value. Thus, a switching element having a so-called normally-off characteristic can be realized. For example, in the case of using an In-Ga-Zn-based oxynitride film, an In-Ga-Zn-based oxynitride film having a nitrogen concentration at least higher than that of the oxide semiconductor film 18, specifically, 7 atomic% or more is used.

The gate insulating film 17 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn based metal oxide, silicon nitride, etc. Set up.

Further, as the gate insulating film 17, hafnium silicate (HfSiO _x ), hafnium silicate to which nitrogen is added (HfSi _x O _y N _z ), hafnium aluminate to which nitrogen is added (HfAl _x O _y N _z ), hafnium oxide , Yttrium oxide and other high-
The gate leakage of the transistor can be reduced by using the k material.

The thickness of the gate insulating film 17 is preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, and more preferably 50 nm to 250 nm.

The pair of electrodes 21 and 22 is a single layer of a single metal composed of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten as a conductive material, or an alloy containing this as a main component Used as a structure or a laminated structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a tungsten film, copper-magnesium
A two-layer structure in which a copper film is laminated on an aluminum alloy film, a titanium film or a titanium nitride film, an aluminum film or a copper film is laminated on the titanium film or titanium nitride film, and a titanium film or nitride is further formed thereon. A three-layer structure for forming a titanium film, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon There is a three-layer structure etc. Note that a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

Further, by providing a nitride insulating film 25 having a blocking effect of oxygen, hydrogen, water, an alkali metal, an alkaline earth metal or the like on the oxide insulating film 24, diffusion of oxygen from the multilayer film 20 to the outside In addition, it is possible to prevent entry of hydrogen, water and the like from the outside into the multilayer film 20. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that instead of a nitride insulating film having a blocking effect of oxygen, hydrogen, water, an alkali metal, an alkaline earth metal or the like, an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided. Examples of the oxide insulating film having a blocking effect such as oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, hafnium oxide nitride, and the like.

  Next, a method for manufacturing the transistor 50 illustrated in FIG. 1 will be described with reference to FIG.

As shown in FIG. 2A, the gate electrode 15 is formed on the substrate 11, and the gate insulating film 17 is formed on the gate electrode 15.

  Here, a glass substrate is used as the substrate 11.

The formation method of the gate electrode 15 is shown below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like, and a mask is formed over the conductive film by a photolithography step. Next, part of the conductive film is etched using the mask to form the gate electrode 15. After this, the mask is removed.

The gate electrode 15 may be formed by an electrolytic plating method, a printing method, an inkjet method or the like instead of the above forming method.

Here, a tungsten film with a thickness of 100 nm is formed by a sputtering method. Next, a mask is formed by a photolithography step, and the tungsten film is dry etched using the mask to form the gate electrode 15.

  The gate insulating film 17 is formed by a sputtering method, a CVD method, an evaporation method, or the like.

In the case where a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film is formed as the gate insulating film 17, it is preferable to use a deposition gas containing silicon and an oxidizing gas as a source gas. Typical examples of deposition gases containing silicon include silane, disilane,
There are trisilane, fluorinated silane and the like. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

When a gallium oxide film is formed as the gate insulating film 17, MOCVD (Meta) is
(1) It can be formed using an Organic Chemical Vapor Deposition) method.

Next, as illustrated in FIG. 2B, the oxide semiconductor film 18 and the oxide film 19 are formed over the gate insulating film 17.

The method for forming the oxide semiconductor film 18 and the oxide film 19 will be described below. An oxide semiconductor film to be the oxide semiconductor film 18 and an oxide film to be the oxide film 19 are continuously formed over the gate insulating film 17. Next, a mask is formed over the oxide film by a photolithography step, and then the oxide semiconductor film and the oxide film are partially etched using the mask, as illustrated in FIG. 2B. On the gate insulating film 17 and the gate electrode 15
A multilayer film 20 including the oxide semiconductor film 18 and the oxide film 19 which are separated into elements so as to overlap with a part of After this, the mask is removed.

The oxide semiconductor film to be the oxide semiconductor film 18 and the oxide film to be the oxide film 19 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, or the like.

In the case of forming the oxide semiconductor film and the oxide film by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as appropriate as a power supply device for generating plasma.

As a sputtering gas, a mixed gas of a rare gas (typically, argon), an oxygen gas, a rare gas, and oxygen is appropriately used. In the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

Further, the target may be appropriately selected in accordance with the composition of the oxide semiconductor film and the oxide film to be formed.

The oxide semiconductor film 18 and the oxide film 19 do not merely stack the respective films, but a continuous junction (here, in particular, a structure in which the energy at the lower end of the conduction band continuously changes between the respective films) is formed. Make as. That is, a layered structure is employed in which there is no defect level such as a trap center or a recombination center for the oxide semiconductor film 18 or an impurity that forms a barrier that inhibits the flow of carriers at the interface of each film. . Temporarily, stacked oxide semiconductor film 1
If impurities are mixed between the oxide film 8 and the oxide film 19, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface and annihilated.

In order to form a continuous junction, it is necessary to use the multi-chamber type film forming apparatus (sputtering apparatus) provided with a load lock chamber to continuously stack the respective films without exposure to the atmosphere. Each chamber in the sputtering apparatus is evacuated at a high vacuum (1 × 10 ⁻⁷ Pa to 5 ° C.) using an adsorption-type evacuation pump such as a cryopump in order to remove water and the like that become impurities to the oxide semiconductor film as much as possible. It is preferable to set it to about ^10-4 Pa). Alternatively, it is preferable that a turbo molecular pump and a cold trap be combined to prevent backflow of a gas, particularly a gas containing carbon or hydrogen, from the exhaust system into the chamber.

In order to obtain a high purity intrinsic or substantially high purity intrinsic oxide semiconductor film, it is necessary to not only highly evacuate the chamber but also to purify the sputtering gas. The oxygen gas or argon gas used as the sputtering gas has a dew point of −40 ° C. or less, preferably −80 ° C. or less,
By using a gas which is preferably highly purified to -100 ° C or lower, more preferably -120 ° C or lower, moisture and the like can be prevented as much as possible from being taken into the oxide semiconductor film.

Here, a 35 nm-thick In—Ga is formed as an oxide semiconductor film by a sputtering method.
After forming a -Zn oxide film (In: Ga: Zn = 1: 1: 1), a 20 nm-thick In-Ga-Zn oxide film (In: Ga: Zn =) is formed as an oxide film by a sputtering method. 1:
Form 3: 2). Next, a mask is formed over the oxide film, and a part of each of the oxide semiconductor film and the oxide film is selectively etched to form the oxide semiconductor film 18 and the oxide film 19.
To form a multilayer film 20.

After this, the first heat treatment is performed. By the first heat treatment, hydrogen, water, and the like contained in the oxide semiconductor film 18 can be released, so that the concentration of hydrogen and the concentration of water contained in the oxide semiconductor film can be reduced. The temperature of the heat treatment is typically 300 ° C to 400 ° C, preferably 320 ° C to 370 ° C.

An electric furnace, an RTA apparatus, or the like can be used for the first heat treatment. By using the RTA apparatus, heat treatment can be performed at a temperature higher than the strain point of the substrate for only a short time. Therefore, the heat treatment time can be shortened.

The first heat treatment is performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (argon, helium, etc.) It is good. Note that it is preferable that the nitrogen, oxygen, ultra dry air, or a rare gas do not contain hydrogen, water, and the like. Alternatively, after heat treatment in a nitrogen or rare gas atmosphere, heating may be performed in an oxygen or ultradry air atmosphere. As a result, hydrogen, water, and the like contained in the oxide semiconductor film can be released, and oxygen can be supplied to the oxide semiconductor film. As a result, the amount of oxygen vacancies contained in the oxide semiconductor film can be reduced.

  Next, as shown in FIG. 2C, the pair of electrodes 21 and 22 are formed.

The formation method of a pair of electrodes 21 and 22 is shown below. At first, sputtering method, CVD
A conductive film is formed by a method, an evaporation method, or the like. Next, a mask is formed over the conductive film by a photolithography step. Next, the conductive film is etched using the mask to form the pair of electrodes 21 and 2.
Form 2 After this, the mask is removed.

Here, a 50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film are sequentially stacked by a sputtering method. Next, a mask is formed over the titanium film by a photolithography step, and the tungsten film, the aluminum film, and the titanium film are dry etched using the mask to form a pair of electrodes 21 and 22.

Next, as illustrated in FIG. 2D, the oxide insulating film 23 is formed over the multilayer film 20 and the pair of electrodes 21 and 22. Next, the oxide insulating film 24 is formed over the oxide insulating film 23.

Note that after the oxide insulating film 23 is formed, the oxide insulating film 2 is continuously exposed without exposure to the air.
It is preferred to form four. After the oxide insulating film 23 is formed, oxidation is performed by continuously forming the oxide insulating film 24 by adjusting one or more of the flow rate of the source gas, the pressure, the high frequency power, and the substrate temperature without opening to the atmosphere. While being able to reduce the impurity concentration derived from the atmospheric component of the interface between the product insulating film 23 and the oxide insulating film 24, it is possible to move the oxygen contained in the oxide insulating film 24 to the oxide semiconductor film 18. The amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced.

As the oxide insulating film 23, the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is maintained at 180.degree. C. to 400.degree. C., more preferably 200.degree. C. to 370.degree. The pressure in the processing chamber is 20 Pa or more and 250 Pa or less,
More preferably, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film 23 under the condition of 100 Pa to 250 Pa and under conditions where high frequency power is supplied to an electrode provided in the processing chamber.

As a source gas of the oxide insulating film 23, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Typical examples of deposition gases containing silicon include silane, disilane,
There are trisilane, fluorinated silane and the like. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

By using the above conditions, an oxide insulating film which transmits oxygen can be formed as the oxide insulating film 23. In addition, by providing the oxide film 19 and the oxide insulating film 23, damage to the oxide semiconductor film 18 can be reduced in a step of forming the oxide insulating film 24 which is to be formed later.

Note that the oxide insulating film 23 is 180 ° C. to 400 ° C., preferably 300 ° C. to 400 ° C., more preferably 320 ° C. to 370 ° C. for a substrate placed in a processing chamber evacuated of a plasma CVD apparatus. A silicon oxide film is used as the oxide insulating film 23 under the conditions of maintaining the pressure in the processing chamber at 100 Pa to 250 Pa by introducing the source gas into the processing chamber and supplying high-frequency power to the electrode provided in the processing chamber. Alternatively, a silicon oxynitride film can be formed.

Under the film forming conditions, by setting the substrate temperature to the above temperature, the bonding force of silicon and oxygen becomes strong. As a result, oxygen is transmitted as the oxide insulating film 23, and a dense and hard oxide insulating film, typically, an etching rate for a 0.5 wt% hydrofluoric acid at 25 ° C. is 10 nm / min or less Preferably, a silicon oxide film or a silicon oxynitride film which is 8 nm / min or less can be formed.

Furthermore, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, the content of water contained in the oxide insulating film 23 is reduced, so that the variation in the electrical characteristics of the transistor 50 can be reduced and the threshold voltage can be reduced. Fluctuations can be suppressed. Also, the pressure in the processing chamber is 1
When the oxide insulating film 23 is formed, the damage to the multilayer film 20 including the oxide semiconductor film 18 can be reduced by setting the pressure in the range of 00 Pa to 250 Pa, and the oxide semiconductor film 18 can be included. The amount of oxygen deficiency can be reduced. In particular, by increasing the film formation temperature of the oxide insulating film 23 or the oxide insulating film 24 to be formed later, typically at a temperature higher than 220 ° C., one of oxygen contained in the oxide semiconductor film 18 can be obtained. The part is detached and oxygen deficiency is likely to be formed. In addition, when film formation conditions for reducing the amount of defects in the oxide insulating film 24 to be formed later are used to improve the reliability of the transistor, the amount of oxygen released can be easily reduced. As a result of these, it may be difficult to reduce oxygen vacancies in the oxide semiconductor film 18. However, by setting the pressure in the treatment chamber to 100 Pa to 250 Pa and reducing damage to the oxide semiconductor film 18 when the oxide insulating film 23 is formed, even a small amount of oxygen released from the oxide insulating film 24 can be obtained. Oxygen vacancies in the oxide semiconductor film 18 can be reduced.

Note that the amount of oxidizing gas relative to the deposition gas containing silicon is 100 times or more.
The hydrogen content in the oxide insulating film 23 can be reduced. As a result, the amount of hydrogen mixed in the oxide semiconductor film 18 can be reduced, so that negative shift of the threshold voltage of the transistor can be suppressed.

Here, as the oxide insulating film 23, silane with a flow rate of 30 sccm and a flow rate of 4000 sc are used.
A plasma CVD method using a dinitrogen monoxide as the source gas, a pressure in the processing chamber of 200 Pa, a substrate temperature of 220 ° C., and a high frequency power of 150 W supplied to a parallel plate electrode using a 27.12 MHz high frequency power supply A silicon oxynitride film with a thickness of 50 nm is formed. Under the conditions, a silicon oxynitride film through which oxygen can be transmitted can be formed.

As the oxide insulating film 24, the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is maintained at 180.degree. C. to 280.degree. C., more preferably 200.degree. C. to 240.degree. The pressure in the processing chamber is 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less.
. 17W / cm ² or more 0.5 W / cm ² or less, more preferably under the conditions for supplying high-frequency power of 0.25 W / cm ² or more 0.35 W / cm ² or less, a silicon oxide film or a silicon oxynitride film .

As a source gas of the oxide insulating film 24, a deposition gas containing silicon and an oxidizing gas are preferably used. Typical examples of deposition gases containing silicon include silane, disilane,
There are trisilane, fluorinated silane and the like. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

By supplying the high frequency power of the above power density in the processing chamber under the above pressure as the film forming condition of the oxide insulating film 24, the decomposition efficiency of the source gas in the plasma is enhanced, oxygen radicals are increased, and the source gas is oxidized. As a result, the oxygen content in the oxide insulating film 24 becomes larger than the stoichiometric composition. However, when the substrate temperature is the above temperature, since the bonding force between silicon and oxygen is weak, part of oxygen in the film is released by heat treatment in a later step. As a result,
An oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition and from which part of oxygen is released by heating can be formed. Further, the oxide insulating film 23 is provided on the multilayer film 20. Therefore, in the step of forming the oxide insulating film 24, the oxide insulating film 23 becomes a protective film of the multilayer film 20. In addition, the oxide film 19 serves as a protective film of the oxide semiconductor film 18. As a result of these, the oxide insulating film 24 can be formed using high frequency power with high power density while reducing damage to the oxide semiconductor film 18.

Note that the amount of defects in the oxide insulating film 24 can be reduced by increasing the flow rate of the deposition gas containing silicon to the oxidizing gas under the film formation conditions of the oxide insulating film 24. Typically, ESR measurement shows that g = 2.0 derived from dangling bonds of silicon
The spin density of the signal appearing at 01 is less than 6 × 10 ¹⁷ spins / cm ³ , preferably 3 ×
An oxide insulating film with a small amount of defects, which is 10 ¹⁷ spins / cm ³ or less, preferably 1.5 × 10 ¹⁷ spins / cm ³ or less, can be formed. As a result, the reliability of the transistor can be improved.

Here, as the oxide insulating film 24, silane with a flow rate of 200 sccm and a flow rate of 4000 s
The pressure of the processing chamber is 200 Pa and the substrate temperature is 220 ° C.
Then, a silicon oxynitride film with a thickness of 400 nm is formed by a plasma CVD method in which a parallel plate electrode is supplied with high frequency power of 1500 W using a 27.12 MHz high frequency power supply. The plasma CVD apparatus is a parallel plate type plasma CVD having an electrode area of 6000 cm ²
It is a device, and 0.25 W when supplied power is converted to power per unit area (power density)
It is / cm ² .

Next, heat treatment is performed. The temperature of the heat treatment is typically 300 ° C to 400 ° C, preferably 320 ° C to 370 ° C.

For the heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature higher than the strain point of the substrate for only a short time. Therefore, the heat treatment time can be shortened.

The heat treatment is carried out using nitrogen, oxygen, ultra-dry air (water content is 20 ppm or less, preferably 1 p
pm or less, preferably 10 ppb or less of air) or a rare gas (argon, helium, etc.)
You can do it under the atmosphere of Note that it is preferable that the nitrogen, oxygen, ultra dry air, or a rare gas do not contain hydrogen, water, and the like.

By the heat treatment, part of oxygen contained in the oxide insulating film 24 can be moved to the oxide semiconductor film 18, and the amount of oxygen vacancies contained in the oxide semiconductor film 18 can be reduced.

In the case where the oxide insulating film 23 and the oxide insulating film 24 contain water, hydrogen, or the like, the nitride insulating film 25 having a function of blocking water, hydrogen, or the like is formed later, and heat treatment is performed. Water, hydrogen, and the like contained in the material insulating film 23 and the oxide insulating film 24 move to the oxide semiconductor film 18 and a defect is generated in the oxide semiconductor film 18. However, water, hydrogen, and the like contained in the oxide insulating film 23 and the oxide insulating film 24 can be released by the heating, and variations in the electrical characteristics of the transistor 50 can be reduced and the threshold voltage can be reduced. Fluctuations can be suppressed.

Note that by forming the oxide insulating film 24 over the oxide insulating film 23 while heating, oxygen is transferred to the oxide semiconductor film 18 and oxygen vacancies contained in the oxide semiconductor film 18 are reduced. Since it is possible, the heat treatment may not be performed.

  Here, heat treatment is performed at 350 ° C. for one hour in a nitrogen and oxygen atmosphere.

Further, when forming the pair of electrodes 21 and 22, the multilayer film 20 is formed by etching the conductive film.
Is damaged, the back channel of the multilayer film 20 (in the multilayer film 20, the gate electrode 15
The oxygen deficiency occurs on the side opposite to the side opposite to the side opposite to the side. However, by applying an oxide insulating film containing oxygen at a higher proportion than the stoichiometric composition to the oxide insulating film 24, oxygen vacancies generated on the back channel side due to heat treatment can be repaired. it can. Thus, defects included in the multilayer film 20 can be reduced, and thus the reliability of the transistor 50 can be improved.

  Next, a nitride insulating film 25 is formed by sputtering, CVD or the like.

Note that in the case where the nitride insulating film 25 is formed by plasma CVD, the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is set at 300 ° C. to 400 ° C., more preferably 320 ° C. to 370 ° C. This is preferable because a dense nitride insulating film can be formed.

When a silicon nitride film is formed as the nitride insulating film 25 by a plasma CVD method, it is preferable to use a deposition gas containing silicon, nitrogen, and ammonia as a source gas. By using a small amount of ammonia as the source gas as compared to nitrogen, the ammonia is dissociated in the plasma to generate active species. The active species cleaves the bond of silicon and hydrogen contained in the deposition gas containing silicon and the triple bond of nitrogen. As a result, bonding between silicon and nitrogen is promoted, bonding between silicon and hydrogen is reduced, defects are reduced, and a dense silicon nitride film can be formed. On the other hand, in the source gas, when the amount of ammonia to nitrogen is large, decomposition of the silicon-containing deposition gas and nitrogen does not proceed, and silicon and hydrogen bonds remain to increase defects, and rough silicon nitride A film is formed. For these reasons, in the source gas, the flow ratio of nitrogen to ammonia is preferably 5 or more and 50 or less, and more preferably 10 or more and 50 or less.

Here, in the processing chamber of the plasma CVD apparatus, silane at a flow rate of 50 sccm, a flow rate of 5000
A nitrogen of sccm and a flow rate of 100 sccm of ammonia are used as source gases, the pressure in the processing chamber is 100 Pa, the substrate temperature is 350 ° C., and the frequency is 1000 using a 27.12 MHz high frequency power supply.
A 50-nm-thick silicon nitride film is formed by plasma CVD in which high-frequency power of W is supplied to parallel plate electrodes. In the plasma CVD apparatus is a plasma CVD apparatus of a parallel plate type electrode area is 6000 cm ^2, is converted to electric power supplied per unit area (power ^{density) 1.7 × 10 -1 W / cm} 2 It is.

Through the above steps, the protective film 26 including the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 can be formed.

Next, heat treatment may be performed. The temperature of the heat treatment is typically 300 ° C. or higher.
The temperature is 0 ° C. or less, preferably 320 ° C. or more and 370 ° C. or less.

  Through the above steps, the transistor 50 can be manufactured.

In this embodiment, the first heat treatment and the second heat treatment are performed in the manufacturing process of the transistor; however, the oxide semiconductor film is included in the oxide semiconductor film by forming a multilayer film including the oxide semiconductor film. It is possible to reduce the impurity concentration and to prevent the trapping of carriers at defect levels. As a result, even when the temperature of each heat treatment is set to 400 ° C. or lower, a transistor in which the amount of fluctuation in threshold voltage is equal to that of a transistor heat-treated at a high temperature can be manufactured. As a result, the cost of the semiconductor device can be reduced.

Further, by forming an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition by overlapping with the oxide semiconductor film functioning as a channel region, the oxygen in the oxide insulating film is oxidized. It can be moved to the object semiconductor film. As a result, the content of oxygen vacancies in the oxide semiconductor film can be reduced.

In particular, an oxide insulating film which transmits oxygen is formed between the oxide semiconductor film which functions as channel formation and the oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition. In forming an oxide insulating film containing oxygen at a higher proportion than the stoichiometric composition,
Damage to the oxide semiconductor film can be suppressed. As a result, the amount of oxygen vacancies contained in the oxide semiconductor film can be reduced.

Then, an oxide film is formed over the oxide semiconductor film, whereby the oxide semiconductor film is damaged when the oxide insulating film contains oxygen at a higher proportion than the stoichiometric composition. Entry can be further suppressed. In addition, by formation of an oxide film, entry of an insulating film to be formed over the oxide semiconductor film, for example, a constituent element of the oxide insulating film, can be suppressed.

As described above, in a semiconductor device using an oxide semiconductor film, a semiconductor device with a reduced amount of defects can be obtained. In addition, a semiconductor device using the oxide semiconductor film and having improved electrical characteristics can be obtained.

<Band structure of transistor>
Next, the band structure of the multilayer film 20 will be described with reference to FIG.

Here, as an example, an In—Ga—Zn oxide having an energy gap of 3.15 eV is used as the oxide semiconductor film 18, and an energy gap of 3.5 e is used as the oxide film 19.
An In—Ga—Zn oxide which is V is used. The energy gap can be measured using a spectroscopic ellipsometer (UT-300 manufactured by HORIBA JOBIN YVON).

The energy difference between the vacuum level and the top of the valence band (also referred to as ionization potential) of the oxide semiconductor film 18 and the oxide film 19 is 8 eV and 8.2 eV, respectively. The energy difference between the vacuum level and the top of the valence band can be determined by ultraviolet photoelectron spectroscopy (UPS: Ultravio).
let Photoelectron Spectroscopy device (PHI V)
It can measure using ersaProbe).

Therefore, the energy difference between the vacuum level and the bottom of the conduction band (also referred to as electron affinity) of the oxide semiconductor film 18 and the oxide film 19 is 4.85 eV and 4.7 eV, respectively.

FIG. 3A schematically shows a part of the band structure of the multilayer film 20. Here, the case where a silicon oxide film is provided in contact with the multilayer film 20 will be described. EcI1 shown in FIG. 3A indicates the energy at the lower end of the conduction band of the silicon oxide film, EcS1 indicates the energy at the lower end of the conduction band of the oxide semiconductor film 18, and EcS2 indicates the energy at the lower end of the conduction band of the oxide film 19. The energy is indicated, and EcI2 is the energy at the lower end of the conduction band of the silicon oxide film. Also, EcI1
Corresponds to the gate insulating film 17 in FIG. 1B, and EcI2 corresponds to the oxide insulating film 23 in FIG. 1B.

As shown in FIG. 3A, in the oxide semiconductor film 18 and the oxide film 19, the energy at the lower end of the conduction band changes gently without any barrier. In other words, it can be said that it changes continuously. This is because the multilayer film 20 contains an element in common with the oxide semiconductor film 18, and a mixed layer is formed by the mutual movement of oxygen between the oxide semiconductor film 18 and the oxide film 19. It can be said that there is.

As shown in FIG. 3A, the oxide semiconductor film 18 of the multilayer film 20 becomes a well.
In the transistor using 0, it is understood that a channel region is formed in the oxide semiconductor film 18. In the multilayer film 20, the energy at the lower end of the conduction band changes continuously.
It can be said that the oxide semiconductor film 18 and the oxide film 19 are in continuous contact with each other.

Note that as shown in FIG. 3A, in the vicinity of the interface between the oxide film 19 and the oxide insulating film 23, although the trap level due to the impurity or the defect may be formed, the oxide film 19 is formed. With the provision, the oxide semiconductor film 18 and the trap level can be separated. However, when the energy difference between EcS1 and EcS2 is small, electrons in the oxide semiconductor film 18 may reach the trap level beyond the energy difference. By trapping electrons in the trap level, a negative charge is generated at the interface with the insulating film, resulting in a negative fixed charge, and the threshold voltage of the transistor is shifted in the positive direction. Therefore, it is preferable to set the energy difference between EcS1 and EcS2 to 0.1 eV or more, preferably 0.15 eV or more, because fluctuation in threshold voltage of the transistor is reduced and stable electrical characteristics can be obtained.

Further, FIG. 3B schematically shows a part of the band structure of the multilayer film 20, and is a modified example of the band structure shown in FIG. Here, the case where a silicon oxide film is provided in contact with the multilayer film 20 will be described. Note that EcI1 shown in FIG. 3B indicates the energy of the lower end of the conduction band of the silicon oxide film, EcS1 indicates the energy of the lower end of the conduction band of the oxide semiconductor film 18, E
cI2 represents the energy at the lower end of the conduction band of the silicon oxide film. In addition, EcI1 is shown in FIG.
EcI2 corresponds to the oxide insulating film 23 in FIG. 1B.

In the transistor shown in FIG. 1B, the multilayer film 20 is formed when the pair of electrodes 21 and 22 are formed.
In other words, the oxide film 19 may be etched. Meanwhile, the oxide semiconductor film 1
A mixed layer of the oxide semiconductor film 18 and the oxide film 19 may be formed on the upper surface of the oxide film 19 when the oxide film 19 is formed.

For example, the oxide semiconductor film 18 may be formed of In—Ga: Zn = 1: 1: 1 [atomic ratio].
Ga—Zn oxide or In—Ga—Z of In: Ga: Zn = 3: 1: 2 [atomic ratio]
It is an oxide semiconductor film formed using n oxide as a sputtering target, and the oxide film 19 is an In—Ga—Zn oxide of In: Ga: Zn = 1: 3: 2 [atomic number ratio]. Or an oxide film formed using an In—Ga—Zn oxide with an atomic ratio of In: Ga: Zn = 1: 6: 4 as a sputtering target, the oxide semiconductor film 18 is more preferable than the oxide semiconductor film 18 Since the content of Ga in the oxide film 19 is high, a mixed layer containing more Ga than the GaO x layer or the oxide semiconductor film 18 can be formed on the top surface of the oxide semiconductor film 18.

Therefore, even when the oxide film 19 is etched, the energy at the lower end of the conduction band on the EcI2 side of EcS1 becomes high, and may have a band structure as shown in FIG. 3 (B).

In the case of the band structure shown in FIG. 3B, when observing the cross section of the channel region,
The multilayer film 20 may be observed apparently with only the oxide semiconductor film 18. However, since a mixed layer containing a larger amount of Ga than the oxide semiconductor film 18 is substantially formed over the oxide semiconductor film 18, the mixed layer can be regarded as a 1.5 layer. . In addition, when this mixed layer measures the element contained in the multilayer film 20 by EDX analysis etc., for example,
This can be confirmed by analyzing the composition above the oxide semiconductor film 18. For example, it can be confirmed that the composition above the oxide semiconductor film 18 has a content of Ga larger than the composition in the oxide semiconductor film 18.

<Modification 1, base insulating film>
In the transistor 50 described in this embodiment, a base insulating film can be provided between the substrate 11 and the gate electrode 15 as needed. Examples of the material of the base insulating film include silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, and the like. Note that by using silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide or the like as the material of the base insulating film, impurities from the substrate 11, typically an alkali metal, can be used.
Diffusion of water, hydrogen or the like to the multilayer film 20 can be suppressed.

  The base insulating film can be formed by a sputtering method, a CVD method, or the like.

<Modified example 2, gate insulating film>
In the transistor 50 described in this embodiment, the gate insulating film 17 can have a stacked-layer structure as needed. Here, the configuration of the gate insulating film 17 will be described with reference to FIG.

As shown in FIG. 5A, the gate insulating film 17 can have a stacked structure in which a nitride insulating film 17a and an oxide insulating film 17b are sequentially stacked from the gate electrode 15 side. By providing the nitride insulating film 17a on the side of the gate electrode 15, transfer of impurities from the gate electrode 15, typically hydrogen, nitrogen, an alkali metal, an alkaline earth metal or the like to the multilayer film 20 is prevented. be able to.

Further, by providing the oxide insulating film 17 b on the multilayer film 20 side, it is possible to reduce the density of defect states at the interface between the gate insulating film 17 and the multilayer film 20. As a result, a transistor with less deterioration in electrical characteristics can be obtained. When the oxide insulating film 17 b is formed using an oxide insulating film containing oxygen in excess of oxygen satisfying the stoichiometric composition, as in the case of the oxide insulating film 24, the gate insulating film 17 and the multilayer film are formed. It is further preferable because the density of defect states at the 20 interface can be further reduced.

As shown in FIG. 5B, the gate insulating film 17 is formed of a nitride insulating film 17c with few defects.
A layered structure in which the nitride insulating film 17 d having a high hydrogen blocking property and the oxide insulating film 17 b are sequentially stacked from the gate electrode 15 side can be obtained. By providing the nitride insulating film 17 c with few defects as the gate insulating film 17, the withstand voltage of the gate insulating film 17 can be improved. Further, by providing the nitride insulating film 17 d having a high hydrogen blocking property, the hydrogen from the gate electrode 15 and the nitride insulating film 17 c can be prevented from moving to the multilayer film 20.

An example of a method for manufacturing the nitride insulating films 17c and 17d illustrated in FIG. 5B will be described below. First, a silicon nitride film with few defects is formed as the nitride insulating film 17c by plasma CVD using a mixed gas of silane, nitrogen, and ammonia as a source gas. Next, the source gas is switched to a mixed gas of silane and nitrogen, and a second silicon nitride film having a low hydrogen concentration and capable of blocking hydrogen is formed as the nitride insulating film 17 d. By such a formation method, it is possible to form the gate insulating film 17 in which a nitride insulating film having few defects and having a hydrogen blocking property is stacked.

As shown in FIG. 5C, the gate insulating film 17 includes a nitride insulating film 17e having a high impurity blocking property, a nitride insulating film 17c with few defects, and a nitride insulating film 17d having a high hydrogen blocking property. The oxide insulating film 17 b can have a stacked structure in which the oxide insulating film 17 b is stacked in order from the gate electrode 15 side. By providing the nitride insulating film 17 e having a high blocking property of impurities as the gate insulating film 17, impurities from the gate electrode 15, typically, hydrogen, nitrogen,
It is possible to prevent an alkali metal, an alkaline earth metal or the like from migrating to the multilayer film 20.

An example of a method for manufacturing the nitride insulating films 17e, 17c, and 17d illustrated in FIG. 5C will be described below. First, a silicon nitride film having high blocking property of impurities is formed as the nitride insulating film 17 e by plasma CVD using a mixed gas of silane, nitrogen, and ammonia as a source gas. Next, by increasing the flow rate of ammonia, a silicon nitride film with few defects is formed as the nitride insulating film 17c. Next, the source gas is switched to a mixed gas of silane and nitrogen, and a second silicon nitride film having a low hydrogen concentration and capable of blocking hydrogen is formed as the nitride insulating film 17 d. A gate insulating film 17 in which a nitride insulating film having few defects and having a blocking property of impurities is stacked by such a formation method.
Can be formed.

<Modification 3 Regarding a Pair of Electrodes>
As the pair of electrodes 21 and 22 provided in the transistor 50 described in this embodiment, a conductive material which easily combines with oxygen, such as tungsten, titanium, aluminum, copper, molybdenum, chromium, or tantalum alone or an alloy, is preferably used . As a result, the multilayer film 20
The oxygen contained therein and the conductive material contained in the pair of electrodes 21 and 22 are combined to form an oxygen deficient region in the multilayer film 20. In addition, part of the constituent elements of the conductive material forming the pair of electrodes 21 and 22 may be mixed into the multilayer film 20. As a result of these, as shown in FIG.
b is formed. The low resistance regions 20 a and 20 b are in contact with the pair of electrodes 21 and 22 and are formed between the gate insulating film 17 and the pair of electrodes 21 and 22. The low resistance regions 20a and 20b have high conductivity, so that the contact resistance between the multilayer film 20 and the pair of electrodes 21 and 22 can be reduced, and the on current of the transistor can be increased.

Alternatively, the pair of electrodes 21 and 22 may have a stacked structure of a conductive material which is easily bonded to oxygen and a conductive material which is not easily bonded to oxygen, such as titanium nitride, tantalum nitride, or ruthenium. With such a stacked structure, oxidation of the pair of electrodes 21 and 22 can be prevented at the interface between the pair of electrodes 21 and 22 and the oxide insulating film 23. It is possible to suppress the increase in resistance.

<Modified Example 4, Multilayer Film>
In the method for manufacturing the transistor 50 described in this embodiment, a compound generated by a reaction of the oxide semiconductor film 18 and / or a compound generated by a reaction of the oxide film 19 can be provided on the side surface of the multilayer film. Here, description will be made with reference to FIG. 7 which is an enlarged view of the vicinity of the multilayer film 20 of the transistor 50 of FIG. 1B.

For example, as shown in FIG. 7A, the compound 19 c generated by the reaction of the oxide film 19 can be provided on the back channel side of the multilayer film 20. Compound 19c is a pair of electrodes 21
, 22 and then form TMAH (Tetramethylammonium Hydro
The oxide film 19 can be formed by exposing the oxide film 19 to an alkaline solution such as a solution, or an acidic solution such as phosphoric acid, nitric acid, hydrofluoric acid, hydrochloric acid, hydrochloric acid, sulfuric acid, acetic acid, and oxalic acid.

Note that in this step, part of the oxide film 19 is etched and reacted with the alkaline solution and the acidic solution, and a reactant remains. In the case where the oxide film 19 is formed of In—Ga oxide or In—M—Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), Since In (indium oxide) contained in the oxide film 19 is preferentially removed, the G
Compound 19c with a high proportion of a or M is formed.

Compound 19c having a higher proportion of Ga or M compared to In is M, Al, Ti, Ga
, Y, Zr, La, Ce, Nd or Hf at a higher atomic ratio than In. For this reason,
Since it is possible to shield impurities from the outside, the amount of impurities moving from the outside to the oxide semiconductor film 18 can be reduced. As a result, a transistor with less variation in threshold voltage can be manufactured.

In addition, it is possible to remove the etching residue between the pair of electrodes 21 and 22 by the treatment. As a result, it is possible to suppress the generation of the leak current flowing between the pair of electrodes 21 and 22.

Further, as shown in FIG. 7B, the compound 19d can be provided on the side surface of the multilayer film 20. The compound 19 d can be formed into a multilayer film 20 by using TMAH (Tetramethyla).
It can be formed by wet etching using an alkaline solution such as a solution of mmonium hydroxide or the like, or an acidic solution such as phosphoric acid, nitric acid, hydrofluoric acid, hydrochloric acid, hydrochloric acid, sulfuric acid, acetic acid, oxalic acid and the like. Alternatively, the compound 19 d can be formed by dry etching using boron trichloride gas and chlorine gas as an etching gas. Alternatively, after forming the multilayer film 20, the oxide film 19 is exposed to the above-mentioned solution.
Compound 19d can be formed.

The compound 19d has a higher proportion of Ga or M compared to In, as with the compound 19c.
Therefore, since the compound 19d can shield impurities from the outside, the amount of impurities moving from the outside to the oxide semiconductor film 18 can be reduced. As a result, a transistor with less variation in threshold voltage can be manufactured.

<Modification 5 Regarding Multilayer Film>
In the manufacturing method of the transistor 50 described in this embodiment, after the pair of electrodes 21 and 22 are formed, the multilayer film 20 is exposed to plasma generated in an oxygen atmosphere to form oxygen in the oxide semiconductor film 18 and the oxide film 19. Can be supplied. As an oxidizing atmosphere, there is an atmosphere of oxygen, ozone, dinitrogen monoxide, nitrogen dioxide and the like. Furthermore, in the plasma processing, the substrate 1
It is preferable to expose the multilayer film 20 to plasma generated with no bias applied to one side. As a result, oxygen can be supplied without damaging the multilayer film 20, and the amount of oxygen deficiency contained in the multilayer film 20 can be reduced. Further, impurities remaining on the surface of the multilayer film 20, for example, halogen such as fluorine and chlorine can be removed by the etching process.

<Modification 6, Regarding Protective Film>
In the transistor 50 shown in this embodiment, as shown in FIG.
A protective film 26 a over which the oxide insulating film 24 and the nitride insulating film 25 are stacked can be provided. Since the transistor illustrated in FIG. 8 includes the oxide film 19 over the oxide semiconductor film 18, the oxide film 19 functions as a protective film when the oxide insulating film 24 is formed. As a result, when the oxide insulating film 24 is formed, the oxide semiconductor film 18 is not exposed to plasma, and plasma damage caused when the oxide insulating film 24 is formed by plasma CVD using relatively high power is reduced. it can.

Further, oxygen contained in the oxide insulating film 24 can be directly moved to the multilayer film 20, so that the amount of oxygen supplied to the oxide semiconductor film 18 can be increased. As a result, the amount of oxygen vacancies in the oxide semiconductor film 18 can be further reduced.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Second Embodiment
In this embodiment, a semiconductor device including a transistor capable of further reducing the amount of defects in the oxide semiconductor film as compared to Embodiment 1 will be described with reference to the drawings. The transistor described in this embodiment is different from that in Embodiment 1 in that an oxide film is provided between the gate insulating film and the oxide semiconductor film.

FIG. 9 illustrates a top view and a cross-sectional view of the transistor 60 included in the semiconductor device. Figure 9 (A)
9B is a cross-sectional view taken along dashed-dotted line A-B in FIG. 9A, and FIG. 9C is a dashed-dotted line C in FIG. 9A. It is sectional drawing between -D. Note that FIG.
In (A), the substrate 11, part of components of the transistor 60 (for example, the gate insulating film 17), the oxide insulating film 23, the oxide insulating film 24, the nitride insulating film 25, and the like are omitted for clarity. doing.

The transistor 60 shown in FIG. 9 has a gate electrode 15 provided on the substrate 11. In addition, a gate insulating film 17 formed on the substrate 11 and the gate electrode 15, and a gate insulating film 17
A multilayer film 34 overlapping the gate electrode 15, and a pair of electrodes 21 in contact with the multilayer film 34,
And 22. In addition, over the gate insulating film 17, the multilayer film 34, and the pair of electrodes 21 and 22, a protective film 2 including the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25.
6 are formed.

In the transistor 60 described in this embodiment, the multilayer film 34 includes the oxide film 31, the oxide semiconductor film 32, and the oxide film 33. In addition, the oxide semiconductor film 32 functions as a channel region.

Further, the gate insulating film 17 and the oxide film 31 are in contact with each other. That is, the oxide film 31 is provided between the gate insulating film 17 and the oxide semiconductor film 18.

Further, the multilayer film 34 and the oxide insulating film 23 are in contact with each other. In addition, the oxide insulating film 23 and the oxide insulating film 24 are in contact with each other. That is, the oxide film 33 is provided between the oxide semiconductor film 18 and the oxide insulating film 23.

For the oxide film 31 and the oxide film 33, materials and formation methods similar to those of the oxide film 19 described in Embodiment 1 can be used as appropriate.

The oxide film 31 preferably has a thickness smaller than that of the oxide semiconductor film 32. By setting the thickness of the oxide film 31 to greater than or equal to 1 nm and less than or equal to 5 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, variation in threshold voltage of the transistor can be reduced.

When the oxide films 31 and 33 are In-M-Zn oxides, the sum of In and M is 1
When the atomic ratio of In and M is taken as 00 atomic%, preferably, the atomic ratio of In and M is 50 at.
Less than atomic%, M is 50 atomic% or more, more preferably, In is 25 atoms
Less than ic%, M is 75 atomic% or more.

The oxide semiconductor film 32 can be formed using a material and a formation method similar to those of the oxide semiconductor film 18 described in Embodiment 1 as appropriate.

Here, as the oxide film 31, a 30 nm thick In—Ga film is formed by sputtering.
A Zn oxide film (In: Ga: Zn = 1: 6: 4) is formed. In addition, the oxide semiconductor film 3
An In—Ga—Zn oxide film (In: Ga: Zn = 1: 1: 1) with a thickness of 10 nm is formed. Further, an In-Ga-Zn oxide film (In: 10 nm thick) is formed as the oxide film 33.
Ga: Zn = 1: 3: 2) is formed.

In the transistor described in this embodiment, an oxide insulating film 23 which transmits oxygen to the back channel (the surface opposite to the surface facing the gate electrode 15 in the multilayer film 34) side of the multilayer film 34 is used.
, And the oxide insulating film 24 which contains oxygen at a higher proportion than the stoichiometric composition. Therefore, oxygen contained in the oxide insulating film 24 containing oxygen at a higher proportion than that in the stoichiometric composition is transferred to the oxide semiconductor film 32 contained in the multilayer film 34, and is transferred to the oxide semiconductor film 32. The amount of oxygen deficiency included can be reduced.

Further, the multilayer film 34 is damaged by the etching for forming the pair of electrodes 21 and 22, and oxygen deficiency occurs on the back channel side of the multilayer film 34, but more oxygen than the stoichiometric composition is generated. The oxygen vacancies can be repaired by oxygen contained in the oxide insulating film 24. Thus, the reliability of the transistor 60 can be improved.

From the above, the chemical quantity can be determined via the oxide film 31, the oxide semiconductor film 32, and the multilayer film 34 including the oxide film 33, and the oxide insulating film 23 that transmits oxygen provided on the multilayer film 34. It is possible to reduce oxygen vacancies in the multilayer film 34 by having the oxide insulating film 24 containing oxygen more than oxygen that satisfies the theoretical composition. Further, the oxide film 31 is provided between the gate insulating film 17 and the oxide semiconductor film 32, and the oxide film 33 is provided between the oxide semiconductor film 32 and the oxide insulating film 23. Therefore, the concentration of silicon or carbon in the vicinity of the interface between the oxide film 31 and the oxide semiconductor film 32, the concentration of silicon or carbon in the oxide semiconductor film 32, or the concentration of the oxide film 33 and the oxide semiconductor film 32 The concentration of silicon or carbon in the vicinity of the interface can be reduced. As a result, in the multilayer film 34, the absorption coefficient derived by constant photocurrent measurement is less than 1 × 10 ⁻³ / cm, preferably 1 × 10 ⁻⁴ / c.
It is less than m and there are very few localized levels.

The transistor 60 having such a structure can improve the electrical characteristics of the transistor because the number of defects in the oxide semiconductor film 32 is extremely small. Typically, increase in on current and mobility of the field effect mobility can be achieved. An improvement is possible. In addition, the variation amount of the threshold voltage in the BT stress test and the light BT stress test which are an example of the stress test is small, and the reliability is high.

Third Embodiment
In this embodiment, a semiconductor device including a transistor capable of increasing the on-state current of the transistor while further reducing the amount of defects in the oxide semiconductor film as compared to Embodiments 1 and 2 is shown in FIG. Explain with reference to. The transistor described in this embodiment is different from that in Embodiment 1 in that an oxide film is provided between the pair of electrodes 21 and 22 and the oxide insulating film 23. Although the present embodiment will be described using Embodiment 1, it can be applied to Embodiment 2 as appropriate.

FIG. 10 illustrates a top view and a cross-sectional view of the transistor 70 included in the semiconductor device. A top view of the transistor 70 is shown in FIG. In FIG. 10A, a cross-sectional view taken along dashed-dotted line A-B is shown in FIG. 10B, and a cross-sectional view taken along dashed-dotted line C-D is shown in FIG. 10A, for the sake of clarity, the substrate 11, part of components of the transistor 70 (eg, the gate insulating film 17), the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 etc. are omitted.

The transistor 70 is different from the transistor 50 in that the pair of electrodes 21 and 22 is surrounded by the oxide semiconductor film 18 a and the oxide film 19 a. Specifically, the transistor 70 includes an oxide semiconductor film 18 a provided over the gate insulating film 17 and an oxide semiconductor film 18.
a, a pair of electrodes 21 and 22, an oxide semiconductor film 18a and a pair of electrodes 21,
And 22 an oxide film 19a.

The transistor 70 has a lower contact resistance between the oxide semiconductor film 18a and the pair of electrodes 21 and 22 than the transistor 60 because the pair of electrodes 21 and 22 is in contact with the oxide semiconductor film 18a. It is a transistor whose on-state current is improved more than 60.

Further, in the transistor 70, since the pair of electrodes 21 and 22 is in contact with the oxide semiconductor film 18a, the oxide film can be formed without increasing the contact resistance between the oxide semiconductor film 18a and the pair of electrodes 21 and 22. 19a can be thickened. In this manner, trap levels generated due to plasma damage when forming the protective film 26 or mixing of constituent elements of the protective film 26 are formed in the vicinity of the interface between the oxide semiconductor film 18 a and the oxide film 19 a. Can be suppressed.
That is, the transistor 65 can achieve both the improvement of the on current and the reduction of the fluctuation amount of the threshold voltage.

A method for manufacturing the transistor 70 is described with reference to FIG. First, as in FIG. 2A, the gate electrode 15 and the gate insulating film 17 are formed on the substrate 11 (see FIG. 11A).

Next, the oxide semiconductor film 28 to be the oxide semiconductor film 18 a is formed later, and then the pair of electrodes 21 and 22 is formed. Next, an oxide film 29 to be the oxide film 19a later is formed (see FIG.
See FIG. 11 (B). ).

The oxide semiconductor film 28 can be formed using a material and a formation method similar to those of the oxide semiconductor film 18 described in Embodiment 1 as appropriate. Further, the pair of electrodes 21 and 22 can be formed in the same manner as in FIG. Note that the pair of electrodes 21 and 22 is formed over the oxide semiconductor film 28. For the oxide film 29, the same material and formation method as those of the oxide film 19 described in Embodiment 1 can be used as appropriate.

Next, a part of each of the oxide semiconductor film 28 and the oxide film 29 is simultaneously etched to form a multilayer film 20 including the oxide semiconductor film 18 a and the oxide film 19 a (FIG. 11 (C
See). ). Note that the etching can be performed by using a mask after a mask is formed over the oxide film to be the oxide film 29 by a photolithography step. In addition, since the oxide semiconductor film 28 and the oxide film 29 are etched simultaneously, the oxide semiconductor film 18 a
The end portions of the oxide film 19a substantially coincide with each other.

Next, a protective film 26 is formed so as to cover the gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 and 22. The protective film 26 can be formed in the same manner as in the first embodiment.
In the method for manufacturing the transistor 70, heat treatment can be performed with reference to Embodiment 1 as appropriate.

In addition, since a defect such as an oxygen vacancy may be generated in the oxide semiconductor film 18 a by etching for forming the pair of electrodes 21 and 22 and the carrier density may increase, the oxidation before forming the oxide film 29 is It is preferable to supply the oxygen to the oxide semiconductor film 18a by exposing the substance semiconductor film 18a to plasma generated in an oxygen atmosphere. Thus, in the transistor 70, formation of trap states in the vicinity of the interface between the oxide semiconductor film 18a and the oxide film 19a can be suppressed, and the amount of fluctuation in threshold voltage can be reduced. it can. Alternatively, in the transistor 70, a leak current flowing in the vicinity of the side surface of the oxide semiconductor film 18a in the multilayer film 20 can be reduced, and an increase in off current can be suppressed.

Further, the multilayer film 20 is damaged by the etching for forming the pair of electrodes 21 and 22 and oxygen deficiency occurs on the back channel side of the multilayer film 20, but a part of oxygen contained in the oxide insulating film 24 is oxidized. It is possible to move the oxide semiconductor film 18a to reduce the amount of oxygen vacancies contained in the oxide semiconductor film 18a. Thereby, the reliability of the transistor 70 can be improved.

<Modification 1>
In the transistor 70 described in this embodiment, the multilayer film 20 and the pair of electrodes 21 and 22 are provided.
The laminated structure of can be changed as appropriate. For example, a transistor as shown in FIG. 12 can be used as a modification.

The transistor illustrated in FIG. 12 is different from the transistor 60 in that the oxide semiconductor film 18 b and the oxide film 19 b are formed in different steps. That is, an end portion of the oxide semiconductor film 18 b is covered with the pair of electrodes 21 and 22 and is different from the end portion not in contact with the oxide film 19 b.

In the transistor illustrated in FIG. 12, the contact resistance between the multilayer film 20 and the pair of electrodes 21 and 22 is low because the pair of electrodes 21 and 22 and the oxide semiconductor film 18 b are in direct contact as compared to the transistor 50. This is a transistor whose on current is improved more than that of the transistor 50.

Further, in the transistor illustrated in FIG. 12, since the pair of electrodes 21 and 22 are in direct contact with the oxide semiconductor film 18b, oxidation is performed without increasing the contact resistance between the multilayer film 20 and the pair of electrodes 21 and 22. The object film 19b can be thickened. By doing this, the trap level generated by plasma damage when forming the protective film 26 or the mixing of the constituent elements of the protective film 26 occurs in the vicinity of the interface between the oxide semiconductor film 18 b and the oxide film 19 b. It can be suppressed to be formed. That is, both the improvement of the on current and the reduction of the fluctuation of the threshold voltage can be achieved.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Embodiment 4
In this embodiment, a transistor having a different structure from those in Embodiments 1 to 3 will be described with reference to FIGS. The transistor 80 described in this embodiment has a plurality of gate electrodes which are opposed to each other through an oxide semiconductor film.

The transistor 80 shown in FIG. 13 has a gate electrode 15 provided on the substrate 11.
Further, a gate insulating film 17 formed on the substrate 11 and the gate electrode 15, and a gate insulating film 1
7, the multilayer film 20 overlapping with the gate electrode 15, and a pair of electrodes 21 in contact with the multilayer film 20.
, 22 and. Note that the multilayer film 20 includes the oxide semiconductor film 18 and the oxide film 19. Further, over the gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 and 22, a protective film 26 including the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 is formed. Ru. In addition, a gate electrode 61 overlapping with the multilayer film 20 via the protective film 26 is provided.

The gate electrode 61 can be formed in the same manner as the gate electrode 15 described in the first embodiment.

The transistor 70 described in the present embodiment has a gate electrode 15 facing to the other through the multilayer film 20.
And a gate electrode 61. By applying different potentials to the gate electrode 15 and the gate electrode 61, the threshold voltage of the transistor 70 can be controlled.

In addition, by including the multilayer film 20 including the oxide semiconductor film 18 with a reduced amount of oxygen vacancies, electrical characteristics of the transistor can be improved. In addition, the transistor has a small amount of fluctuation in threshold voltage and high reliability.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments and examples.

Fifth Embodiment
In this embodiment, a transistor having a structure different from that in Embodiments 1 to 4 is described with reference to FIG.

In this embodiment, a semiconductor device including a transistor capable of further reducing the amount of defects in the oxide semiconductor film as compared to Embodiments 1 to 4 will be described with reference to the drawings. In the transistor described in this embodiment, the back channel side of the multilayer film 20 is covered with a protective film as compared with Embodiments 1 to 4, and the etching process is performed to form a pair of electrodes. It differs in that it is not exposed to the resulting plasma.

FIG. 14 illustrates a top view and a cross-sectional view of the transistor 90 included in the semiconductor device. Figure 14 (
A) is a top view of the transistor 90, and FIG. 14 (B) is a dashed-dotted line A- of FIG. 14 (A).
FIG. 14C is a cross-sectional view taken along line B-B. FIG. 14C is a cross-sectional view taken along alternate long and short dash line C-D in FIG. 14A, for the sake of clarity, the substrate 11, part of the components of the transistor 90 (eg, the gate insulating film 17), the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 etc. are omitted.

The transistor 90 shown in FIG. 14 has a gate electrode 15 provided on the substrate 11.
Further, a gate insulating film 17 formed on the substrate 11 and the gate electrode 15, and a gate insulating film 1
A multi-layered film 20 overlapping with the gate electrode 15 is provided through 7. A protective film 26 formed of the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 is formed on the gate insulating film 17 and the multilayer film 20, and is formed on the protective film 26. A pair of electrodes 21 b and 22 b connected to the multilayer film 20 at the opening 26 is provided.

  Next, a method for manufacturing the transistor 90 is described.

As in the first embodiment, the gate electrode 15 is formed on the substrate 11, and the gate insulating film 17 is formed on the substrate 11 and the gate electrode 15. Next, the multilayer film 20 is formed on the gate insulating film 17. After that, first heat treatment is performed to release impurities contained in the oxide semiconductor film.

Next, as in the first embodiment, an oxide insulating film 23 is formed on the gate insulating film 17 and the multilayer film 20.
The oxide insulating film 24 and the nitride insulating film 25 are formed. Note that after the oxide insulating film 24 is formed, second heat treatment is performed to supply part of oxygen contained in the oxide insulating film 24 to the oxide semiconductor film 18.

Next, each of the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 is partially etched to form an opening that exposes a portion of the multilayer film 20. Thereafter, a pair of electrodes 21 b and 22 b in contact with the multilayer film 20 are formed in the same manner as in the first embodiment.

In the present embodiment, when etching the pair of electrodes 21 b and 22 b, the multilayer film 20 is
Since the protective film 26 is covered with the protective film 26, the multilayer film 20, particularly the back channel region of the multilayer film 20, is not damaged by the etching for forming the pair of electrodes 21b and 22b. Further, the oxide insulating film 24 is formed using an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition. Therefore, a part of oxygen contained in the oxide insulating film 24 is added to the oxide semiconductor film 1
The oxygen vacancy amount contained in the oxide semiconductor film 18 can be reduced.

Through the above steps, defects included in the multilayer film 20 can be reduced, and the reliability of the transistor 90 can be improved.

Sixth Embodiment
In this embodiment, a transistor having a different structure from those in Embodiments 1 to 5 will be described with reference to FIGS.

In this embodiment, a semiconductor device including a transistor capable of further reducing the amount of defects in the oxide semiconductor film as compared to Embodiments 1 to 4 will be described with reference to the drawings. As in the fifth embodiment, the transistor described in the present embodiment is a multilayer film 2.
This embodiment is different from the first to fourth embodiments in that the back channel side of 0 is covered with a protective film and is not exposed to plasma generated in the etching process for forming a pair of electrodes.

FIG. 15 illustrates a top view and a cross-sectional view of the transistor 100 included in the semiconductor device. Figure 15.
The transistor 100 shown in FIG. 1 is a channel protective transistor. FIG. 15A is a top view of the transistor 100, FIG. 15B is a cross-sectional view taken along dashed-dotted line A-B in FIG. 15A, and FIG. ) Is a cross-sectional view taken along the alternate long and short dash line C-D. Note that in FIG. 15A, some components of the substrate 11 and the transistor 100 (for the sake of clarity,
For example, the gate insulating film 17 etc. is omitted.

The transistor 100 shown in FIG. 15 has a gate electrode 15 provided on a substrate 11. The gate insulating film 17 is formed on the substrate 11 and the gate electrode 15, and the multilayer film 20 overlapping the gate electrode 15 with the gate insulating film 17 interposed therebetween. Also, gate insulating film 17
And the multilayer insulating film 20, the oxide insulating film 23a, the oxide insulating film 24a, and the nitride insulating film 25.
and a pair of electrodes 21c and 22bc formed on the gate insulating film 17, the multilayer film 20, and the protective film 26a.

  Next, a method for manufacturing the transistor 100 is described.

As in the first embodiment, the gate electrode 15 is formed on the substrate 11, and the gate insulating film 17 is formed on the substrate 11 and the gate electrode 15. Next, the multilayer film 20 is formed on the gate insulating film 17. After that, first heat treatment is performed to release impurities contained in the oxide semiconductor film.

Next, as in the first embodiment, the oxide insulating film 2 is formed on the gate insulating film 17 and the multilayer film 20.
Third, the oxide insulating film 24 and the nitride insulating film 25 are formed. Note that after the oxide insulating film 24 is formed, second heat treatment is performed to supply part of oxygen contained in the oxide insulating film 24 to the oxide semiconductor film 18.

Next, the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 are partially etched to form the oxide insulating film 23a, the oxide insulating film 24a, and the nitride insulating film 25a. To form a protective film 26a.

Next, a pair of electrodes 21c and 22c in contact with the multilayer film 20 are formed in the same manner as in the first embodiment.

In the present embodiment, when etching the pair of electrodes 21c and 22c, the multilayer film 20 is
Is covered by the protective film 26a, the multilayer film 20 is not damaged by the etching for forming the pair of electrodes 21c and 22c. Further, the oxide insulating film 24 a is formed using an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition. Therefore, part of oxygen contained in the oxide insulating film 24a is moved to the oxide semiconductor film 18, and the oxide semiconductor film 1 is formed.
The amount of oxygen deficiency contained in No. 8 can be reduced.

In FIG. 15, the nitride insulating film 25a is formed as the protective film 26c.
A stacked structure of the oxide insulating film 23a and the oxide insulating film 24a may be employed. In this case, it is preferable to form the nitride insulating film 25a after forming the pair of electrodes 21c and 22c. As a result, it is possible to prevent the entry of hydrogen, water and the like from the outside into the multilayer film 20.

Through the above steps, defects included in the multilayer film 20 can be reduced, and the reliability of the transistor 100 can be improved.

Seventh Embodiment
Although various films such as the metal film, the oxide semiconductor film, the inorganic insulating film, and the like disclosed in the above embodiments can be formed by a sputtering method or a plasma CVD (Chemical Vapor Deposition) method, other methods, for example, thermal You may form by CVD method. MOCVD (Metal Organic Chemical Va) as an example of a thermal CVD method
por Deposition) method or ALD (Atomic Layer Deposi)
You may use the

The thermal CVD method has an advantage that no defect is generated due to plasma damage because the film formation method does not use plasma.

In the thermal CVD method, the source gas and the oxidizing agent may be simultaneously sent into the chamber, and the inside of the chamber may be at atmospheric pressure or under reduced pressure, and reaction may be performed near the substrate or on the substrate to deposit on the substrate. .

In the ALD method, the inside of the chamber may be at atmospheric pressure or under reduced pressure, a source gas for reaction may be sequentially introduced into the chamber, and film formation may be performed by repeating the order of gas introduction. For example, each switching valve (also referred to as a high-speed valve) is switched to supply two or more types of source gases in sequence to the chamber, and multiple source gases are not mixed simultaneously with the first source gas simultaneously or later. Introduce an active gas (such as argon or nitrogen),
Introduce a second source gas. When an inert gas is introduced at the same time, the inert gas may be a carrier gas, and the inert gas may be introduced at the same time as the introduction of the second source gas. Further, instead of introducing the inert gas, the second source gas may be introduced after the first source gas is discharged by vacuum evacuation. The first source gas is adsorbed on the surface of the substrate to form a first layer, and reacts with the second source gas introduced later to stack the second layer on the first layer. Thin film is formed. A thin film having excellent step coverage can be formed by repeating the process several times while controlling the gas introduction order until the desired thickness is obtained. Since the thickness of the thin film can be adjusted by repeating the gas introduction sequence, precise film thickness adjustment is possible.
It is suitable for fabricating a fine FET.

The thermal CVD method such as the MOCVD method or the ALD method can form various films such as the metal film, the oxide semiconductor film, the inorganic insulating film, and the like disclosed in the embodiments described above, for example, I
When an nGaZnO film is formed, trimethylindium, trimethylgallium and dimethylzinc are used. The chemical formula of trimethylindium is In (CH ₃ ) ₃ . The chemical formula of trimethylgallium is Ga (CH ₃ ) ₃ . Moreover, the chemical formula of dimethyl zinc is Zn (CH ₃ ) ₂ . Further, the present invention is not limited to these combinations, and triethylgallium (chemical formula Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethyl zinc (chemical formula Zn (C ₂ H ₅ )) can be used instead of dimethylzinc. ₂ ) can also be used.

For example, in the case of forming a hafnium oxide film by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide solution, typically tetrakisdimethylamide hafnium (TDAH)) is vaporized Two kinds of gases, a source gas and ozone (O3) as an oxidant, are used. The chemical formula of tetrakisdimethylamidohafnium is Hf [N (CH ₃ ) ₂ ] ₄ . Further, as another material liquid, there is tetrakis (ethylmethylamide) hafnium or the like.

For example, in the case of forming an aluminum oxide film by a film forming apparatus using ALD, a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA)) and H ₂ as an oxidizing agent Two kinds of gas of O are used. The chemical formula of trimethylaluminum is Al (CH ₃ ) ₃ . Also, as other material liquid, Tris (
Dimethylamide) aluminum, triisobutyl aluminum, aluminum tris (2
, 2,6,6- tetramethyl-3,5-heptanedionate) and the like.

For example, in the case of forming a silicon oxide film by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on a formation surface, chlorine contained in an adsorbate is removed, and oxidizing gas (O
_2. Supply radicals of dinitrogen monoxide) to react with the adsorbate.

For example, in the case of forming a tungsten film by a film forming apparatus using ALD, WF ₆
Gas and B ₂ H ₆ gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF
_{6) A} gas and an H ₂ gas are simultaneously introduced to form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, an oxide semiconductor film, for example, In—Ga—Zn— can be formed by a deposition apparatus using ALD.
In the case of forming an O film, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form In film.
A -O layer is formed, and then a Ga (CH ₃ ) ₃ gas and an O ₃ gas are simultaneously introduced to form a GaO layer, and then a Zn (CH ₃ ) ₂ and an O ₃ gas are simultaneously introduced to form a ZnO layer Form
The order of these layers is not limited to this example. In addition, these gases are mixed to form In-Ga-.
A mixed compound layer such as an O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed. In place of the O ₃ gas, an H ₂ O gas obtained by bubbling with an inert gas such as Ar may be used, but it is more preferable to use an O ₃ gas not containing H. Further, instead of the In (CH ₃ ) ₃ gas, an In (C ₂ H ₅ ) ₃ gas may be used. Also, instead of using Ga (CH ₃ ) ₃ gas,
Ga (C ₂ H ₅ ) ₃ gas may be used. Also, instead of using In (CH ₃ ) ₃ gas,
C ₂ H ₅ ) ₃ gas may be used. Alternatively, Zn (CH ₃ ) ₂ gas may be used.

Eighth Embodiment
In this embodiment, a semiconductor device which is an embodiment of the present invention will be described with reference to the drawings. Note that in this embodiment, a semiconductor device which is an embodiment of the present invention will be described by using a display device as an example.

FIG. 16A illustrates an example of a semiconductor device. In the semiconductor device illustrated in FIG. 16A, the pixel portion 101, the scan line driver circuit 104, and the signal line driver circuit 106 are arranged in parallel or substantially in parallel, and the scan line driver circuit 104 has a potential of It has m scanning lines 107 to be controlled, and n signal lines 109 which are disposed in parallel or substantially in parallel and whose potential is controlled by the signal line driving circuit 106. Further, the pixel portion 101 has a plurality of pixels 301 arranged in a matrix. In addition, along the scanning line 107, each has a capacitive line 115 disposed in parallel or substantially in parallel. The capacitive lines 115 may be disposed parallel or substantially parallel to each other along the signal line 109. The scan line driver circuit 104 and the signal line driver circuit 106 may be collectively referred to as a driver circuit portion.

Each scanning line 107 is electrically connected to n pixels 301 arranged in any one of the pixels 301 arranged in m rows and n columns in the pixel portion 101. Also, each signal line 109
Are the m pixels 30 arranged in any column among the pixels 301 arranged in m rows and n columns.
Connected to 1 electrically. m and n are both integers of 1 or more. In addition, each capacitance line 115
Of the pixels 301 arranged in m rows and n columns, n pixels 30 arranged in any row
It is electrically connected with 1. When the capacitive lines 115 are disposed parallel or substantially parallel to each other along the signal line 109, the capacitive line 115 is disposed in any one of the pixels 301 disposed in m rows and n columns. Electrically connected to the m pixels 301.

16B and 16C illustrate a circuit configuration which can be used for the pixel 301 of the display device illustrated in FIG.

The pixel 301 illustrated in FIG. 16B includes a liquid crystal element 132, a transistor 131_1, and a capacitor 133_1.

The potential of one of the pair of electrodes of the liquid crystal element 132 is appropriately set in accordance with the specification of the pixel 301. The alignment state of the liquid crystal element 132 is set by the data to be written. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 132 included in each of the plurality of pixels 301. Alternatively, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 132 for each pixel 301 in each row.

For example, as a method of driving a display provided with the liquid crystal element 132, a TN mode, an STN mode, a VA mode, an ASM (Axially Symmetric Aligned M) can be used.
icro-cell mode, OCB (Optically Compensated)
Birefringence) mode, FLC (Ferroelectric Liqu)
id Crystal) mode, AFLC (AntiFerroelectric Li
quid crystal mode, MVA mode, PVA (patterned Ve
rtical alignment) mode, IPS mode, FFS mode, or TB
A (Transverse Bend Alignment) mode or the like may be used. Further, as a method of driving the display device, in addition to the above-described driving method, ECB (Electri
cally Controlled Birefringence) mode, PDLC (
Polymer Dispersed Liquid Crystal) mode, PNL
There are C (Polymer Network Liquid Crystal) mode, guest host mode, etc. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

Alternatively, the liquid crystal element may be formed of a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. A liquid crystal exhibiting a blue phase has a short response speed of 1 msec or less and is optically isotropic, so alignment processing is unnecessary and the viewing angle dependency is small.

In the pixel 301 in the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 131_1 is electrically connected to the signal line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 132 . In addition, the gate electrode of the transistor 131_1 is connected to the scanning line G.
It is electrically connected to L_m. The transistor 131_1 has a function of controlling writing of data of a data signal by being turned on or off.

One of the pair of electrodes of the capacitor 133_1 is a wiring to which a potential is supplied (hereinafter referred to as a capacitor line CL).
And the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 132. Note that the value of the potential of the capacitor line CL is appropriately set in accordance with the specification of the pixel 301. The capacitor 133_1 has a function as a storage capacitor for storing written data.

For example, in the display device including the pixel 301 in FIG. 16B, the scan line driver circuit 104 sequentially selects the pixels 301 in each row, turns on the transistor 131_1, and writes data signal data.

The pixel 301 to which data is written is brought into the holding state as the transistor 131_1 is turned off. Images can be displayed by sequentially performing this on a row-by-row basis.

The pixel 301 illustrated in FIG. 16C includes a transistor 131_2 and a capacitor 133.
_2, a transistor 134, and a light emitting element 135.

One of the source electrode and the drain electrode of the transistor 131_2 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n) to which a data signal is supplied. Further, the gate electrode of the transistor 131_2 is electrically connected to a wiring (hereinafter, referred to as a scan line GL_m) to which a gate signal is supplied.

The transistor 131_2 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitor 133_2 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 131_2. Be done.

The capacitor 133_2 has a function as a storage capacitor for storing written data.

One of the source electrode and the drain electrode of the transistor 134 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 134 is a transistor 131 _
It is electrically connected to the other of the two source electrodes and drain electrode.

One of the anode and the cathode of the light emitting element 135 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 134.

As the light emitting element 135, for example, an organic electroluminescent element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 135 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

Note that the high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and the low power supply potential VSS is applied to the other.

In the display device including the pixel 301 in FIG. 16C, the pixels 301 in each row are sequentially selected by the scan line driver circuit 104, and the transistor 131_2 is turned on to write data signal data.

The pixel 301 to which data is written is brought into the holding state as the transistor 131_2 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 134 is controlled in accordance with the potential of the written data signal, and the light emitting element 135 emits light with luminance according to the amount of current flowing. Images can be displayed by sequentially performing this on a row-by-row basis.

Note that in this specification and the like, a display element, a display device which is a device having a display element, a light emitting element, and a light emitting device which is a device having a light emitting element have various modes or have various elements. Can do. As an example of a display element, a display device, a light emitting element or a light emitting device, an EL (electroluminescent) element (EL element including organic and inorganic substances, organic EL element, inorganic EL element), LED (white LED, red LED, green LED) , Blue LED
Etc.), transistors (transistors that emit light according to current), electron-emitting devices, liquid crystal devices, electron ink, electrophoresis devices, grating light valves (GLV), plasma displays (PDPs), MEMS (micro-electro-mechanical-systems) ), Digital Micro Mirror Device (DMD), DMS (Digital Micro Shutter), M
IRASOL (registered trademark), IMOD (interference modulation) device, piezoelectric ceramic display, carbon nanotube, etc., by the electromagnetic action,
Some have display media in which the contrast, brightness, reflectance, transmittance, etc. change. EL
An example of a display device using an element is an EL display. As an example of a display device using an electron emission element, a field emission display (FED) or S
ED system flat display (SED: Surface-conduction Ele)
ctron-emitter Display) and the like. Examples of a display device using a liquid crystal element include a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct view liquid crystal display, projection liquid crystal display) and the like. Examples of a display device using an electronic ink or an electrophoretic element include electronic paper.

An example of an EL element is an element having an anode, a cathode, and an EL layer sandwiched between the anode and the cathode. As an example of the EL layer, one using light emission (fluorescence) from singlet excitons, one using light emission (phosphorescence) from triplet excitons, light emission from singlet excitons
Including those using fluorescence) and those using light emission (phosphorescence) from triplet excitons,
One formed by organic matter, one formed by inorganic matter, one including those formed by organic matter and one formed by inorganic matter, one including material of high molecular weight material, one including low molecular weight material Or one containing a high molecular weight material and a low molecular weight material. However, the present invention is not limited to this, and various EL elements can be used.

As an example of the liquid crystal element, there is an element which controls transmission or non-transmission of light by an optical modulation action of liquid crystal. The element can be constructed by a pair of electrodes and a liquid crystal layer. The optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including an electric field in the lateral direction, an electric field in the longitudinal direction, or an electric field in the oblique direction). Specifically, as an example of the liquid crystal element, nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (
PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type polymer liquid crystal, banana type liquid crystal and the like.

Next, a specific example of a liquid crystal display device using a liquid crystal element for the pixel 301 will be described.
Here, a top view of the pixel 301 illustrated in FIG. 16B is illustrated in FIG. Note that in FIG. 17, the counter electrode and the liquid crystal element are omitted.

In FIG. 17, the conductive film 304 c functioning as a scanning line has a direction (generally perpendicular to the signal line)
It is extended and provided in the horizontal direction in the figure). The conductive film 310 d functioning as a signal line is provided so as to extend in a direction (vertical direction in the drawing) substantially orthogonal to the scanning line. The conductive film 310 f functioning as a capacitor line is provided so as to extend in a direction parallel to the signal line. Note that the conductive film 304c functioning as a scan line is electrically connected to the scan line driver circuit 104 (see FIG. 16A) and functions as a conductive film 310d functioning as a signal line and a capacitor line. The conductive film 310 f is electrically connected to the signal line driver circuit 106 (see FIG. 16A).

The transistor 103 is provided in a region where a scan line and a signal line intersect. The transistor 103 includes a conductive film 304c functioning as a gate electrode, a gate insulating film (not shown in FIG. 17), a multilayer film 308b in which a channel region formed over the gate insulating film is formed, a source electrode and a drain electrode. It is constituted by conductive films 310d and 310e which function. Note that the conductive film 304 c also functions as a scan line, and a region overlapping with the multilayer film 308 b functions as a gate electrode of the transistor 103. The conductive film 310 d also functions as a signal line, and a region overlapping with the multilayer film 308 b functions as a source electrode or a drain electrode of the transistor 103. Further, in FIG. 17, the scanning line is positioned such that its end is outside the end of the multilayer film 308b in the top surface shape. For this reason, the scanning line functions as a light shielding film that shields light from a light source such as a backlight. As a result, light is not irradiated to the multilayer film 308 b included in the transistor, and fluctuation in electrical characteristics of the transistor can be suppressed.

The conductive film 310 e is electrically connected to the light-transmitting conductive film 316 b which functions as a pixel electrode in the opening 362 c.

The capacitor 105 is connected to the conductive film 310 f functioning as a capacitor line in the opening 362. The capacitor 105 also functions as a pixel electrode and a light-transmitting conductive film 308 c formed over the gate insulating film, a dielectric film formed of a nitride insulating film provided over the transistor 103, and a capacitor electrode. The light-emitting conductive film 316 c is formed. That is, the capacitor 105 has a light transmitting property.

As described above, since the capacitor 105 has translucency, the capacitor 105 can be formed large (in a large area) in the pixel 301. Therefore, it is possible to increase the aperture ratio to 50% or more, preferably 55% or more, preferably 60% or more, and obtain a semiconductor device having an increased charge capacity. For example, in a semiconductor device with high resolution, for example, a liquid crystal display device, the area of a pixel is reduced and the area of a capacitor is also reduced. Therefore, in a semiconductor device with high resolution, the charge capacity stored in the capacitor is reduced. However, since the capacitor 105 described in this embodiment has translucency, by providing the capacitor in a pixel, the aperture ratio can be increased while obtaining sufficient charge capacity in each pixel. Typically, it can be suitably used for a high resolution semiconductor device having a pixel density of 200 ppi or more, and further 300 ppi or more.

The pixel 301 shown in FIG. 17 has a shape in which the side parallel to the conductive film 304c functioning as a scanning line is longer than the side parallel to the conductive film 310d functioning as a signal line, and as a capacitor line A conductive film 310 f functioning is provided so as to extend in a direction parallel to the conductive film 310 d functioning as a signal line. As a result, the area of the conductive film 310 f occupied in the pixel 301 can be reduced, so that the aperture ratio can be increased. In addition, since the conductive film 310f functioning as a capacitor line is in direct contact with the light-transmitting conductive film 308c without using a connection electrode, the aperture ratio can be further increased.

In one embodiment of the present invention, the aperture ratio can be increased even in a high-resolution display device, so that light from a light source such as a backlight can be efficiently used, and power consumption of the display device can be reduced. be able to.

Next, FIG. 18 shows a cross-sectional view taken along alternate long and short dash line C-D in FIG. Note that in FIG. 18, a cross-sectional view of a drive circuit portion (a top view is omitted) including the scan line drive circuit 104 and the signal line drive circuit 106 is shown by A-B. In this embodiment mode, a vertical electric field liquid crystal display device is described.

In the liquid crystal display device described in this embodiment, a liquid crystal element 322 is sandwiched between a pair of substrates (a substrate 302 and a substrate 342).

The liquid crystal element 322 includes a light-transmitting conductive film 316 b above the substrate 302, films controlling alignment (hereinafter referred to as alignment films 318 and 352), a liquid crystal layer 320, and a conductive film 350.
Have. Note that the light-transmitting conductive film 316 b functions as one electrode of the liquid crystal element 322, and the conductive film 350 functions as the other electrode of the liquid crystal element 322.

Thus, the liquid crystal display device refers to a device having a liquid crystal element. The liquid crystal display device includes a drive circuit and the like for driving a plurality of pixels. In addition, the liquid crystal display device includes a control circuit, a power supply circuit, a signal generation circuit, a backlight module, and the like disposed on another substrate,
It is also called a liquid crystal module.

In the driver circuit portion, a conductive film 304a functioning as a gate electrode, an insulating film 305 and an insulating film 306 functioning as a gate insulating film, a multilayer film 308a where a channel region is formed, a conductive film 310a functioning as a source electrode and a drain electrode, The transistor 102 is constituted by 310b. The multilayer film 308 a is provided on the gate insulating film.

In the pixel portion, a conductive film 304c functioning as a gate electrode, an insulating film 305 and an insulating film 306 functioning as a gate insulating film, a multilayer film 308b in which a channel region formed over the gate insulating film is formed, a source electrode and a drain electrode Conductive film 310 d functioning as
The transistor 103 is composed of 0e. The multilayer film 308 b is provided on the gate insulating film. Insulating films 312 and 314 are provided as protective films over the conductive films 310 d and 310 e.

In addition, the light-transmitting conductive film 316 b which functions as a pixel electrode is connected to the conductive film 310 e in the opening portion provided in the insulating films 312 and 314.

In addition, the capacitor 105 is formed of the light-transmitting conductive film 308 c functioning as one electrode, the insulating film 314 functioning as a dielectric film, and the light-transmitting conductive film 316 b functioning as the other electrode. The light-transmitting conductive film 308 c is provided over the gate insulating film.

In the drive circuit portion, conductive film 30 formed simultaneously with conductive films 304a and 304c.
Conductive film 31 formed simultaneously with conductive films 310a, 310b, 310d, and 310e.
0c means the light-transmitting conductive film 31 formed simultaneously with the light-transmitting conductive film 316b.
Connected by 6a.

The conductive film 304 b and the light-transmitting conductive film 316 a include the insulating film 306 and the insulating film 312.
Connect at the opening provided in. In addition, the conductive film 310 c and the conductive film 3 having translucency
16 a is connected at an opening provided in the insulating film 312 and the insulating film 314.

  Here, components of the display device shown in FIG. 18 will be described below.

Conductive films 304 a, 304 b, and 304 c are formed over the substrate 302. Conductive film 3
04a has a function as a gate electrode of the transistor in the drive circuit portion. The conductive film 304 c is formed in the pixel portion 101 and functions as a gate electrode of a transistor in the pixel portion. The conductive film 304 b is formed in the scan line driver circuit 104 and is connected to the conductive film 310 c.

  For the substrate 302, the material of the substrate 11 described in Embodiment 1 can be used as appropriate.

For the conductive films 304a, 304b, and 304c, the material and the manufacturing method of the gate electrode 15 described in Embodiment 1 can be used as appropriate.

An insulating film 305 and an insulating film 306 are formed over the substrate 302 and the conductive films 304a, 304c, and 304b. The insulating film 305 and the insulating film 306 have a function as a gate insulating film of the transistor in the driver circuit portion and a gate insulating film of the transistor in the pixel portion 101.

The insulating film 305 is preferably formed using the nitride insulating film described in the gate insulating film 17 described in Embodiment 1. The insulating film 306 is preferably formed using the oxide insulating film described in the gate insulating film 17 described in Embodiment 1.

Over the insulating film 306, multilayer films 308a and 308b and a light-transmitting conductive film 308c are formed. The multilayer film 308 a is formed at a position overlapping with the conductive film 304 a and functions as a channel region of a transistor in the driver circuit portion. In addition, the multilayer film 308 b is a conductive film 30.
It is formed at a position overlapping with 4c and functions as a channel region of the transistor in the pixel portion.
The light-transmitting conductive film 308 c functions as one electrode of the capacitor 105.

For the multilayer films 308a and 308b and the light-transmitting conductive film 308c, the materials and manufacturing method of the multilayer film 20 described in Embodiment 1 and the multilayer film 34 described in Embodiment 3 can be used as appropriate.

The light-transmitting conductive film 308c is a multilayer film similar to the multilayer films 308a and 308b,
And, it is characterized in that it contains impurities. An impurity is hydrogen. Note that boron, phosphorus, tin, antimony, a rare gas element, an alkali metal, an alkaline earth metal or the like may be contained as an impurity instead of hydrogen.

The multilayer films 308a and 308b and the light-transmitting conductive film 308c are both formed over the gate insulating film, but have different impurity concentrations. Specifically, the impurity concentration of the light-transmitting conductive film 308c is higher than that of the multilayer films 308a and 308b. For example, the multilayer film 308a, 3
The hydrogen concentration contained in 08b is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 1.
0 ¹⁸ atoms / cm ^{3 or} less, preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, still more preferably 1 × 10 ¹⁶ atos
The hydrogen concentration in the light-transmitting conductive film 308c which is ms / cm ³ or less is 8 × 1.
It is 0 ¹⁹ atoms / cm ³ or more, preferably 1 × 10 ²⁰ atoms / cm ³ or more, more preferably 5 × 10 ²⁰ atoms / cm ³ or more. In addition, the multilayer film 308a, 308
The concentration of hydrogen contained in the light-transmitting conductive film 308c is twice as compared to that in b, preferably 1
0 times or more.

The light-transmitting conductive film 308c has lower resistivity than the multilayer films 308a and 308b. The resistivity of the light-transmitting conductive film 308c is 1 × the resistivity of the multilayer films 308a and 308b.
10 ⁻⁸ times or more and 1 × 10 ⁻¹ times or less is preferable, and typically 1 × 10 ⁻³ Ωc
m or more and 1 × 10 ⁴ Ωcm or less, more preferably, a resistivity of 1 × 10 ⁻³ Ωcm or more 1 ×
It should be less than 10 ⁻¹ Ωcm.

The multilayer films 308 a and 308 b are in contact with a film formed of a material that can improve interface characteristics with the multilayer film, such as the insulating film 306 and the insulating film 312.
The transistor 08 b functions as a semiconductor, and the transistor having the multilayer films 308 a and 308 b has excellent electrical characteristics.

On the other hand, the light-transmitting conductive film 308c is in contact with the insulating film 314 in the opening 362 (see FIG. 21A). The insulating film 314 is a film formed of a material that prevents external impurities such as water, alkali metals, alkaline earth metals and the like from diffusing into the multilayer film, and further contains hydrogen. Therefore, when hydrogen in the insulating film 314 diffuses into a multilayer formed simultaneously with the multilayers 308a and 308b, hydrogen combines with oxygen in the oxide semiconductor film included in the multilayer to generate electrons as carriers. Ru. As a result, the oxide semiconductor film included in the multilayer film has high conductivity and functions as a conductor. That is, it can be said that the oxide semiconductor film has high conductivity. Here, a conductive film 308c having a light-transmitting property is formed of a metal oxide whose conductivity is enhanced by containing the same material as the multilayer films 308a and 308b as its main component and having a hydrogen concentration higher than that of the multilayer films 308a and 308b. It is called.

However, one aspect of the embodiment of the present invention is not limited to this, and the conductive film 30 having translucency
In some cases, 8 c may not be in contact with the insulating film 314.

Further, one embodiment of the present invention is not limited thereto, and a light-transmitting conductive film 308 is provided.
In some cases, c may be formed in a separate step from the multilayer film 308a or 308b. In that case, the light-transmitting conductive film 308c is formed of the multilayer films 308a and 308b.
It may have different materials. For example, the light-transmitting conductive film 308c may be formed using indium tin oxide (hereinafter, referred to as ITO), indium zinc oxide, or the like.

In the semiconductor device described in this embodiment, an electrode which is one of capacitor elements is formed at the same time as a multilayer film of a transistor. In addition, a light-transmitting conductive film which functions as a pixel electrode is used as the other electrode of the capacitor. Therefore, in order to form a capacitor, a step of newly forming a conductive film is unnecessary, and the number of steps of manufacturing a semiconductor device can be reduced. In addition, the capacitor element is light-transmitting because the pair of electrodes is formed of a light-transmitting conductive film. As a result, the aperture ratio of the pixel can be increased while increasing the area occupied by the capacitive element.

For the conductive films 310 a, 310 b, 310 c, 310 d, and 310 e, the materials and manufacturing method of the pair of electrodes 21 and 22 described in Embodiment 1 can be used as appropriate.

An insulating film 312 and an insulating film 3 are formed over the insulating film 306, the multilayer films 308a and 308b, the light-transmitting conductive film 308c, and the conductive films 310a, 310b, 310c, 310d, and 310e.
14 is formed. The insulating film 312 is preferably formed using a material capable of improving interface characteristics with the multilayer film, similarly to the insulating film 306, and at least the same material and fabrication as the oxide insulating film 24 described in Embodiment 1. Methods can be used as appropriate. Alternatively, as described in Embodiment 1, the oxide insulating film 23 and the oxide insulating film may be stacked.

Like the insulating film 305, the insulating film 314 is preferably made of a material that prevents external impurities such as water, an alkali metal, an alkaline earth metal and the like from diffusing into the multilayer film. The material and manufacturing method of the nitride insulating film 25 shown in FIG.

In addition, light-transmitting conductive films 316 a and 316 b are formed over the insulating film 314. The light-transmitting conductive film 316a is electrically connected to the conductive film 304b in the opening 364a (see FIG. 21C), and the conductive film 310c in the opening 364b (see FIG. 21C). Electrically connected. That is, it functions as a connection electrode which connects the conductive film 304 b and the conductive film 310 c. The light-transmitting conductive film 316 b is formed in the opening 364 c (FIG.
C) See. And electrically connected to the conductive film 310e, and has a function as a pixel electrode of a pixel. The light-transmitting conductive film 316 b can function as one of the pair of electrodes of the capacitor.

In order to form a connection structure in which the conductive film 304 b and the conductive film 310 c are in direct contact, the conductive film 3
Before forming 10c, it is necessary to perform patterning to form an opening in the insulating film 305 and the insulating film 306 and to form a mask, but the connection structure in FIG. 18 does not require the photomask. . However, as shown in FIG. 18, the conductive film 316a having translucency
By connecting the conductive film 304 b and the conductive film 310 c, the conductive film 304 b and the conductive film 310 can be obtained.
There is no need to make a connection where c is in direct contact, and one photomask can be reduced. That is, the number of manufacturing steps of the semiconductor device can be reduced.

As the light-transmitting conductive films 316a and 316b, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium A light-transmitting conductive material such as zinc oxide or indium tin oxide to which silicon oxide is added can be used.

In addition, on the substrate 342, a film having color (hereinafter, referred to as a color film 346) is formed. The colored film 346 has a function as a color filter. Also, colored film 346
A light shielding film 344 adjacent to the light shielding film 344 is formed on the substrate 342. The light shielding film 344 functions as a black matrix. The colored film 346 is not necessarily provided. For example, the colored film 346 may not be provided depending on whether the display device is black and white.

The colored film 346 may be a colored film that transmits light of a specific wavelength band, for example,
Red (R) color filter that transmits light in the red wavelength band, green (G) color filter that transmits light in the green wavelength band, blue (B) color filter that transmits light in the blue wavelength band Etc. can be used.

As the light shielding film 344, a metal film, an organic insulating film containing a black pigment, or the like may be used as long as it has a function of shielding light in a specific wavelength range.

In addition, an insulating film 348 is formed over the colored film 346. The insulating film 348 has a function as a planarization layer or a function of suppressing diffusion of an impurity which can be contained in the colored film 346 to the liquid crystal element side.

In addition, a conductive film 350 is formed over the insulating film 348. The conductive film 350 has a function as the other of the pair of electrodes of the liquid crystal element in the pixel portion. Note that an insulating film having a function as an alignment film may be separately formed over the light-transmitting conductive films 316 a and 316 b and the conductive film 350.

In addition, the liquid crystal layer 3 is provided between the light-transmitting conductive films 316 a and 316 b and the conductive film 350.
20 are formed. The liquid crystal layer 320 is formed of a substrate 3 using a sealing material (not shown).
It is sealed between the O. 02 and the substrate 342. Note that the sealing material preferably has a structure in contact with an inorganic material in order to suppress entry of moisture and the like from the outside.

In addition, the liquid crystal layer 320 is formed between the light-transmitting conductive films 316 a and 316 b and the conductive film 350.
A spacer may be provided to maintain the thickness (also referred to as a cell gap).

A method for manufacturing an element portion provided over a substrate 302 shown in the semiconductor device shown in FIG.
This will be described using FIG. 19 to FIG.

  First, the substrate 302 is prepared. Here, a glass substrate is used as the substrate 302.

Next, a conductive film is formed over the substrate 302, and the conductive film is processed into a desired region to form conductive films 304a, 304b, and 304c. Note that the conductive films 304a, 304b, 304
The formation of c can be formed by forming a mask by the first patterning in a desired area and etching an area not covered by the mask. (Refer to FIG. 19 (A))
.

The conductive films 304a, 304b, and 304c can be typically formed by an evaporation method, a CVD method, a sputtering method, a spin coating method, or the like.

Next, the insulating film 305 is formed over the substrate 302 and the conductive films 304a, 304b, and 304c, and the insulating film 306 is formed over the insulating film 305 (see FIG. 19A).

The insulating film 305 and the insulating film 306 can be formed by a sputtering method, a CVD method, or the like. Note that it is preferable to form the insulating film 305 and the insulating film 306 continuously in vacuum, because the mixing of impurities can be suppressed.

  Next, a multilayer film 307 is formed over the insulating film 306 (see FIG. 19B).

The multilayer film 307 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, or the like.

Next, the multilayer film 307 is processed into a desired region to form island-shaped multilayer films 308a and 308b.
, 308d. The multilayer films 308a, 308b, and 308d can be formed by forming a mask by second patterning in a desired region and etching a region not covered by the mask. As etching, dry etching, wet etching, or a combination of both can be used (FIG. 19).
(C)).

Next, a first heat treatment is performed. The first heat treatment uses the same conditions as the first heat treatment described in Embodiment 1. Through the first heat treatment, the multilayer films 308a, 308b, and 308d are formed.
The crystallinity of the oxide semiconductor used for the
Impurities such as hydrogen and water can be removed from 8b and 308d. Note that the first heating step may be performed before the oxide semiconductor is etched.

Next, a conductive film 309 is formed over the insulating film 306 and the multilayer films 308a, 308b, and 308d (see FIG. 20A).

  The conductive film 309 can be formed by, for example, a sputtering method.

Next, the conductive film 309 is processed into a desired region, whereby the conductive films 310a, 310b, and 31 can be obtained.
Form 0c, 310d, 310e. Note that the conductive films 310a, 310b, 310c, 3
The formation of 10d and 310e can be performed by forming a mask by third patterning in a desired area and etching an area not covered by the mask (FIG. 2).
0 (B)).

Next, the insulating film 306, the multilayer films 308 a, 308 b, and 308 d, and the conductive films 310 a and 3.
An insulating film 311 is formed to cover the tops of 10b, 310c, 310d and 310e (FIG. 2).
0 (C)).

The insulating film 311 can be stacked under the same conditions as the oxide insulating film 23 and the oxide insulating film 24 described in Embodiment 1.

Next, the insulating film 311 is processed into a desired region, whereby the insulating film 312 and the opening 362 are formed.
Form Note that the insulating film 311 and the opening 362 can be formed by forming a mask by fourth patterning in a desired region and etching a region which is not covered by the mask. (See FIG. 21 (A)).

The opening 362 is formed so that the surface of the multilayer film 308 d is exposed. Opening 36
For example, a dry etching method can be used as a formation method of 2. However, the method for forming the opening 362 is not limited to this, and a wet etching method or a combination of a dry etching method and a wet etching method may be used.

After that, a second heat treatment is performed to partially oxidize oxygen contained in the insulating film 311 to the multilayer film 30.
Oxygen is transferred to the oxide semiconductor film included in 8a and 308b, and the multilayer films 308a and 308b are formed.
The amount of oxygen vacancies in the oxide semiconductor film contained in

Next, the insulating film 313 is formed over the insulating film 312 and the multilayer film 308d (see FIG. 21B).

As the insulating film 313, impurities from the outside, for example, oxygen, hydrogen, water, alkali metal,
It is preferable to use a material that prevents the alkaline earth metal or the like from diffusing into the multilayer film, and further preferably to contain hydrogen, typically using an inorganic insulating material containing nitrogen, such as a nitride insulating film. Can. The insulating film 313 can be formed using, for example, a CVD method.

The insulating film 314 is a film formed of a material that prevents external impurities such as water, alkali metals, alkaline earth metals and the like from diffusing into the multilayer film, and further contains hydrogen. Therefore, when hydrogen in the insulating film 314 diffuses into the multilayer film 308d, hydrogen bonds with oxygen in the oxide semiconductor film included in the multilayer film 308d, and electrons which are carriers are generated. As a result,
The oxide semiconductor film included in the multilayer film 308 d has high conductivity and becomes a light-transmitting conductive film 308 c.

The silicon nitride film is preferably formed at a high temperature in order to enhance the blocking property, for example, a substrate temperature of 100 ° C. or more and a strain point of the substrate or less, more preferably 300 ° C. or more.
It is preferable to form a film by heating at a temperature of 00 ° C. or less. In the case of forming a film at a high temperature, oxygen may be desorbed from the oxide semiconductor used as the multilayer films 308a and 308b, which may cause a phenomenon in which the carrier concentration is increased.

Next, the insulating film 313 is processed into a desired region, whereby the insulating film 314 and the opening 364 are formed.
a, 364b, 364c are formed. Note that the insulating film 314 and the openings 364 a and 364
b and 364c can be formed by forming a mask by fifth patterning in a desired region and etching a region not covered by the mask (see FIG. 21C).

The opening 364 a is formed so that the surface of the conductive film 304 b is exposed. The opening 364 b is formed to expose the conductive film 310 c. Also, the opening 364c is
The conductive film 310 e is formed to be exposed.

In addition, as a method of forming the openings 364a, 364b, and 364c, for example, a dry etching method can be used. However, the method for forming the openings 364a, 364b, and 364c is not limited to this, and a wet etching method or a combination of a dry etching method and a wet etching method may be used.

Next, the conductive film 31 is formed on the insulating film 314 so as to cover the openings 364a, 364b, and 364c.
5 are formed (see FIG. 22A).

  The conductive film 315 can be formed by, for example, a sputtering method.

Next, the conductive film 315 is processed into a desired region, whereby the light-transmitting conductive film 316 a,
Form 316b. Note that the light-transmitting conductive films 316 a and 316 b can be formed by forming a mask by sixth patterning in a desired region and etching a region not covered by the mask (see FIG. See FIG. 22 (B)).

Through the above steps, a pixel portion having a transistor and a driver circuit portion can be formed over the substrate 302. Note that in the manufacturing process described in this embodiment, the transistors and the capacitor can be formed at the same time using the first to sixth patterning, that is, six masks.

Note that, in this embodiment mode, hydrogen contained in the insulating film 314 is diffused into the multilayer film 308d to increase the conductivity of the oxide semiconductor film included in the multilayer film 308d.
8b is covered with a mask, and an impurity such as hydrogen, boron, phosphorus, tin, antimony, a rare gas element, an alkali metal, an alkaline earth metal or the like is added to the multilayer film 308d;
The conductivity of the oxide semiconductor film included in 8 d may be increased. As a method of adding hydrogen, boron, phosphorus, tin, antimony, a rare gas element or the like to the multilayer film 308d, there are an ion doping method, an ion implantation method, and the like. On the other hand, as a method of adding an alkali metal, an alkaline earth metal or the like to the multilayer film 308d, there is a method of exposing a solution containing the impurity to the multilayer film 308d.

Next, a structure formed on the substrate 342 provided to face the substrate 302 will be described below.

First, the substrate 342 is prepared. As the substrate 342, a material shown in the substrate 302 can be used. Next, a light shielding film 344 and a colored film 346 are formed over the substrate 342 (FIG.
See A).

The light shielding film 344 and the colored film 346 can be formed by a printing method, an ink jet method, or the like using various materials.
The film is formed at a desired position by an etching method using a photolithography technique.

Next, an insulating film 348 is formed over the light shielding film 344 and the colored film 346 (see FIG. 23B).

As the insulating film 348, an organic insulating film such as an acrylic resin, an epoxy resin, or a polyimide can be used, for example. By forming the insulating film 348, for example, the colored film 346 is formed.
It is possible to suppress diffusion of impurities and the like contained therein to the liquid crystal layer 320 side. However, the insulating film 348 is not necessarily provided, and the insulating film 348 may not be formed.

Next, a conductive film 350 is formed over the insulating film 348 (see FIG. 23C). Conductive film 350
As the above, the material shown in the conductive film 315 can be used.

  Through the above steps, a structure formed over the substrate 342 can be formed.

Next, the insulating film 31 formed on the substrate 302 and the substrate 342, more specifically on the substrate 302
4. Translucent conductive films 316 a and 316 b and a conductive film 35 formed on the substrate 342
An alignment film 318 and an alignment film 352 are formed on 0, respectively. Alignment film 318, alignment film 352
Can be formed using a rubbing method, an optical alignment method, or the like. After that, the liquid crystal layer 320 is formed between the substrate 302 and the substrate 342. As a method for forming the liquid crystal layer 320, a dispenser method (dropping method) or an injection method in which liquid crystal is injected using capillary action after bonding the substrate 302 and the substrate 342 can be used.

  Through the above steps, the display device illustrated in FIG. 18 can be manufactured.

Note that this embodiment can be combined as appropriate with any of the other embodiments shown in this specification.

<Modification 1>

A modified example of a liquid crystal display device using a liquid crystal element for the pixel 301 will be described. Here, a top view of the pixel 301 illustrated in FIG. 16B is illustrated in FIG. Note that in FIG. 24, the counter electrode and the liquid crystal element are omitted. The description of the same configuration as that of the seventh embodiment will be omitted.

<Structure of Semiconductor Device>
In FIG. 24, an opening 374c is provided inside the opening 372c, which is different from the pixel 301 shown in FIG. Moreover, the point that an opening 372 is provided instead of the opening 364 differs from the pixel shown in FIG. The conductive film 310 e is electrically connected to the light-transmitting conductive film 316 b which functions as a pixel electrode in the opening 372 c and the opening 374 c.

Next, FIG. 25 shows a cross-sectional view taken along alternate long and short dash line C-D in FIG. In FIG. 25, a cross-sectional view of a drive circuit portion (a top view is omitted) is shown in A-B.

As shown in FIG. 25, over the conductive film 304 a, an opening 372 a (see FIG. 26A) provided in the insulating film 306 and the insulating film 312 and an opening 374 provided in the insulating film 314.
a (see FIG. 26C). The opening 374a (see FIG. 26C) is located inside the opening 372a (see FIG. 26A). In the opening 374a (see FIG. 26C), the conductive film 304a and the light-transmitting conductive film 316a are connected.

Further, an opening 372 b provided in the insulating film 312 is formed over the conductive film 310 c (see FIG.
)reference. And an opening 374 b (see FIG. 26C) provided in the insulating film 314. The opening 374b (see FIG. 26C) is the opening 372b (see FIG. 26A).
Located inside). In the opening 374b (see FIG. 26C), the conductive film 310c
And the light-transmitting conductive film 316a are connected.

Further, an opening 372 c provided in the insulating film 312 is formed over the conductive film 310 e (see FIG.
)reference. And an opening 374c (see FIG. 26C) provided in the insulating film 314. The opening 374c (see FIG. 26C) has an opening 372c (see FIG. 26A).
Located inside). In the opening 374c (see FIG. 26C), the conductive film 310e
And the light-transmitting conductive film 316 b are connected.

In addition, an opening 372 provided in the insulating film 312 is provided over the light-transmitting conductive film 308 c.
(See FIG. 26A). The light-transmitting conductive film 308 is formed in the opening 372.
c is in contact with the insulating film 314.

A connection portion of the conductive film 304b and the light-transmitting conductive film 316a, a connection portion of the conductive film 310c and the light-transmitting conductive film 316a, a conductive film 310e, and the light-transmitting conductive film 316b
The connection portions are respectively covered with the insulating film 305 and / or the insulating film 314. Insulating film 3
The insulating film 314 and the insulating film 314 are formed of an insulating film formed of a material that prevents external impurities such as water, alkali metals, alkaline earth metals and the like from diffusing into the multilayer film. In addition, the side surfaces of the openings 372 a, 372 b, 372 c, and 372 (see FIG. 26A) are the insulating film 305.
And / or covered with an insulating film 314. Since a multilayer film is provided inside the insulating film 305 and the insulating film 314, impurities from the outside, for example, water, an alkali metal, an alkaline earth metal or the like, are transmitted through the conductive film 304b, the conductive films 310c and 310e, and the Light conductive film 30
It is possible to prevent diffusion to the multilayer film included in the transistor from the connection portion of 8c, 316a, and 316b. Therefore, fluctuation of the electrical characteristics of the transistor can be prevented, and the reliability of the semiconductor device can be improved.

<Method for manufacturing semiconductor device>
Regarding a method for manufacturing an element portion provided over a substrate 302 shown in the semiconductor device shown in FIG.
This will be described using FIG. 19, FIG. 20, FIG. 26, and FIG.

19 and 20, conductive films 304a, 304b, and 304c functioning as a gate electrode, an insulating film 305 functioning as a gate insulating film, and an insulating film 306, over the substrate 302, as in the seventh embodiment. Multilayer films 308a, 308b, 308d, and conductive films 310a, 3
10b, 310c, 310d, and 310e and the insulating film 311 are formed. Note that in the process, the first to third patterning steps are performed to form the conductive films 304 a and 3 b, respectively.
04b, 304c, multilayer films 308a, 308b, 308d, conductive films 310a, 310b,
310c, 310d, 310e are formed.

Next, as illustrated in FIG. 26A, the insulating film 311 is processed into desired regions, whereby the insulating film 312 and the openings 372, 372b, and 372c are formed. Furthermore, the opening 372a is formed by processing the insulating film 306 which is part of the gate insulating film into a desired region. Note that in the formation of the insulating film 305, the insulating film 312, and the openings 372, 372a, 372b, and 372c, a mask is formed in a desired region by the fourth patterning, and a region not covered with the mask is etched. Can be formed by Opening 372, 372a
As a method of forming the portions 372 b and 372 c, the method of forming the opening 362 described in Embodiment 7 can be used as appropriate.

By forming at least the opening 372 a in the etching step, the etching amount can be reduced in the etching step using a mask formed in the fifth patterning performed later.

  After that, the second heat treatment is performed as in the seventh embodiment.

Next, the insulating film 305, the conductive films 310c and 310e, the insulating film 312, and the multilayer film 308d
An insulating film 313 is formed thereover (see FIG. 26B).

Next, as in the seventh embodiment, the insulating film 313 is processed into a desired region to form the insulating film 3.
14 and openings 374a, 374b, 374c. Note that the insulating film 314 and the openings 374a, 374b, and 374c can be formed by forming a mask by fifth patterning in a desired region and etching a region which is not covered by the mask (see FIG. See FIG. 26 (C)).

Next, as in Embodiment 7, a conductive film 315 is formed over the insulating film 314 so as to cover the openings 374a, 374b, and 374c (see FIG. 27A).

Next, the conductive film 315 is processed into a desired region, whereby the light-transmitting conductive film 316 a,
Form 316b. Note that the light-transmitting conductive films 316 a and 316 b can be formed by forming a mask by sixth patterning in a desired region and etching a region not covered by the mask (see FIG. See FIG. 27 (B)).

Through the above steps, a pixel portion having a transistor and a driver circuit portion can be formed over the substrate 302. Note that in the manufacturing process described in this embodiment, the transistors and the capacitor can be formed at the same time using the first to sixth patterning, that is, six masks.

In the case where the opening 372 a is not formed in FIG. 26A, the insulating film 305, the insulating film 306, the insulating film 312, and the insulating film 31 are formed in the etching process illustrated in FIG.
4 must be etched, and the amount of etching will increase compared to the other openings. As a result, variations occur in the etching step, and in some regions,
The opening 374a is not formed, and the light-transmitting conductive film 316a and the conductive film 3 which are formed later are formed.
A contact failure of 04b occurs. However, in the present embodiment, since the opening 372a and the opening 374a are formed by two etching steps, etching defects are unlikely to occur in the step of forming the opening. As a result, the yield of the semiconductor device can be improved. Although the opening 372a is used here, the same effects can be obtained in the openings 374b and 374c.

<Modification 2>
A modified example of a liquid crystal display device using a liquid crystal element for the pixel 301 will be described. In the liquid crystal display device illustrated in FIGS. 18 and 25, the light-transmitting conductive film 308 is in contact with the insulating film 314 but can be in contact with the insulating film 305. In this case, since it is not necessary to provide the opening 362 as shown in FIG. 21, it is possible to reduce the level difference on the surface of the light-transmitting conductive films 316a and 316b. Therefore, it is possible to reduce the alignment disorder of the liquid crystal material contained in the liquid crystal layer 320. In addition, a semiconductor device with high contrast can be manufactured.

Such a structure is shown in FIG. 19B in which the insulating film 30 is formed before the multilayer film 307 is formed.
6 may be selectively etched to expose a part of the insulating film 305.

<Modification 3>
Here, modifications of the semiconductor device described in Embodiment 1 will be described with reference to FIGS. 28 to 30. FIG. In FIG. 28, A-B shows a cross-sectional view of the drive circuit portion, and C-D shows a cross-sectional view of the pixel portion.

The semiconductor device shown in FIG. 28 is different from the semiconductor device shown in Embodiment 1 in that a channel protective transistor is used.

In the driver circuit portion, a conductive film 304a functioning as a gate electrode, an insulating film 305 and an insulating film 306 functioning as a gate insulating film, a multilayer film 308a where a channel region is formed, a conductive film 310a functioning as a source electrode and a drain electrode, The transistor 102 is constituted by 310b. An insulating film 312 functioning as a channel protective film is provided between the multilayer film 308 a and the conductive films 310 a and 310 b. In addition, the conductive films 310a, 310b, and 310c.
Over the insulating film 314 is provided as a protective film.

In the pixel portion, a conductive film 304c functioning as a gate electrode, an insulating film 305 and an insulating film 306 functioning as a gate insulating film, a multilayer film 308b in which a channel region formed over the gate insulating film is formed, a source electrode and a drain electrode Conductive film 310 d functioning as
The transistor 103 is composed of 0e. Multilayer film 308b and conductive films 310d and 310e
An insulating film 312 functioning as a channel protective film is provided between the In addition, the conductive film 310
An insulating film 314 is provided as a protective film over the light-transmitting conductive film 308c and the conductive films d and 310e.

In addition, the light-transmitting conductive film 316 b functioning as a pixel electrode is connected to the conductive film 310 e in the opening portion provided in the insulating film 314.

In addition, the capacitor 105 is formed of the light-transmitting conductive film 308 c functioning as one electrode, the insulating film 314 functioning as a dielectric film, and the light-transmitting conductive film 316 b functioning as the other electrode.

In the drive circuit portion, conductive film 30 formed simultaneously with conductive films 304a and 304c.
Conductive film 31 formed simultaneously with conductive films 310a, 310b, 310d, and 310e.
0c means the light-transmitting conductive film 31 formed simultaneously with the light-transmitting conductive film 316b.
Connected by 6a.

In this modification, when the conductive films 310a, 310b, 310d, and 310e are etched, the multilayer films 308a and 308b are covered with the insulating film 312, so the conductive film 310a,
The multilayer film 308 a 308 is formed by etching to form 310 b 310 d 310 e.
b does not get damaged. Further, the insulating film 312 is formed using an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition. Therefore, part of oxygen contained in the insulating film 312 can be moved to the multilayer films 308a and 308b, and the amount of oxygen vacancies contained in the multilayer films 308a and 308b can be reduced.

Regarding a method for manufacturing an element portion provided over a substrate 302 shown in the semiconductor device shown in FIG.
This will be described using FIG. 19, FIG. 29, and FIG.

Similarly to the seventh embodiment, conductive films 304a, 304b, and 304c functioning as a gate electrode, insulating films 305 and 306 functioning as a gate insulating film, and a multilayer film 308a are formed over the substrate 302 through the process of FIG. , 308b, 308d. Note that in the process, the first patterning and the second patterning are performed to form the conductive films 304 a and 3 b, respectively.
04b and 304c, and the multilayer films 308a, 308b and 308d are formed.

  Next, as shown in FIG. 29A, the insulating film 311 is formed as in the seventh embodiment.

  After that, the second heat treatment is performed as in the seventh embodiment.

Next, as shown in FIG. 29B, the insulating film 311 is processed into a desired region to form the insulating film 312 over the multilayer films 308a and 308b. In the case where the insulating film 306 is formed using the same material as the insulating film 312 in this step, part of the insulating film 306 is etched and only a region covered with the multilayer films 308 a and 308 b remains. Note that the insulating film 306 and the insulating film 312 can be formed by forming a mask by third patterning in a desired region and etching a region which is not covered by the mask.

Next, after a conductive film is formed over the insulating film 305, the insulating film 306, and the multilayer films 308a and 308b, the conductive films 310a, 310b, 310c, and 310d are subjected to the steps similar to the seventh embodiment.
310e are formed (see FIG. 29C). Note that the conductive films 310a, 310b, and 310
The formation of c, 310 d, and 310 e can be performed by forming a mask by fourth patterning in a desired area and etching an area not covered by the mask.

Next, the insulating film 305, the insulating film 312, the multilayer film 308d, and the conductive films 310a, 310b, 3
The insulating film 313 is formed over the 10c, 310d, and 310e (see FIG. 30A).

Next, as in the seventh embodiment, the insulating film 313 is processed into a desired region to form the insulating film 3.
14 and the openings 384a, 384b, 384c. Note that the insulating film 314 and the openings 384a, 384b, and 384c can be formed by forming a mask by fifth patterning in a desired region and etching a region which is not covered with the mask (see FIG. See FIG. 30 (B)).

Next, as in the seventh embodiment, a conductive film is formed over the insulating film 314 so as to cover the openings 384a, 384b, and 384c, and then the conductive film is processed into a desired region to achieve light transmittance. The conductive films 316a and 316b are formed (see FIG. 30C). Note that the light-transmitting conductive films 316 a and 316 b can be formed by forming a mask by sixth patterning in a desired region and etching a region not covered by the mask.

Through the above steps, a pixel portion having a transistor and a driver circuit portion can be formed over the substrate 302. Note that in the manufacturing process described in this embodiment, the transistors and the capacitor can be formed at the same time using the first to sixth patterning, that is, six masks.

<Modification 4>
In this embodiment mode and the modification example, the light-transmitting conductive film 308 c and the light-transmitting conductive film 316 b are used as a pair of electrodes included in the capacitor 105, but instead, as shown in FIG. As shown, between the insulating film 312 and the insulating film 314, a conductive film 31 having translucency
7 is formed, the light-transmitting conductive film 316 c is formed over the insulating film 314, the light-transmitting conductive film 317 and the light-transmitting conductive film 316 c are formed as a pair of electrodes for forming the capacitor element 105. It can be used as

Furthermore, an organic insulating film such as an acrylic resin, an epoxy resin, or a polyimide may be provided over the insulating film 312. Since the organic insulating film such as an acrylic resin has high flatness, it is possible to reduce the level difference on the surface of the light-transmitting conductive film 316a. Therefore, it is possible to reduce the alignment disorder of the liquid crystal material contained in the liquid crystal layer 320. In addition, a semiconductor device with high contrast can be manufactured.

<Modification 5>
In this embodiment mode and the modification example, the light-transmitting conductive film 308 c and the light-transmitting conductive film 316 b are used as the pair of electrodes included in the capacitor.
Conductive films formed simultaneously with 04b and 304c, conductive films 310a, 310b, 310c, 3
It is possible to appropriately select two or more of the conductive film formed simultaneously with 10d and 310e, the light-transmitting conductive film 308c, and the light-transmitting conductive film 316b.

(Embodiment 9)
In this embodiment, one mode applicable to the multilayer film 20 and the multilayer film 34 in the transistor included in the semiconductor device described in the above embodiment will be described. Note that although an oxide semiconductor film included in a multilayer film is described here as an example, an oxide film can have a similar structure.

The oxide semiconductor film is a single crystal oxide semiconductor (hereinafter referred to as a single crystal oxide semiconductor).
An oxide semiconductor having a polycrystalline structure (hereinafter referred to as a polycrystalline oxide semiconductor), an oxide semiconductor having a microcrystalline structure (hereinafter referred to as a microcrystalline oxide semiconductor), and an oxide semiconductor having an amorphous structure (hereinafter referred to as an amorphous semiconductor) , Or an amorphous oxide semiconductor). The oxide semiconductor film may be formed using a CAAC-OS. The oxide semiconductor film may be formed using an amorphous oxide semiconductor and an oxide semiconductor having crystal grains. The single crystal oxide semiconductor, the CAAC-OS, the polycrystalline oxide semiconductor, the microcrystalline oxide semiconductor, and the amorphous oxide semiconductor are described below.

<Single-crystal oxide semiconductor>
The single crystal oxide semiconductor has low impurity concentration and low density of defect states (small amount of oxygen vacancies), for example, so that carrier density can be reduced. Therefore, a transistor in which a single crystal oxide semiconductor is used for a channel region may rarely have normally-on electrical characteristics. In addition, since the single crystal oxide semiconductor has a low density of defect states, the density of trap states may also be low. Therefore, a transistor in which a single crystal oxide semiconductor is used for a channel region may be a transistor with high reliability, which has less variation in electrical characteristics.

<CAAC-OS>
The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts fit inside a cube whose one side is less than 100 nm. Therefore, CAAC-
The crystal part included in the OS film is also included in the case where one side is smaller than 10 nm, smaller than 5 nm, or smaller than 3 nm. The CAAC-OS film is characterized in that the density of defect states is lower than that of a microcrystalline oxide semiconductor film. Hereinafter, the CAAC-OS film is described in detail.

The CAAC-OS is, for example, a transmission electron microscope (TEM: Transmission)
In some cases, a crystal part can be confirmed by an observation image by an electron microscope. The crystal part contained in the CAAC-OS is, for example, an observation image by TEM,
In many cases, the size fits in a cube with a side of 100 nm. In addition, CAAC-OS is
In some cases, the boundary between the crystal part and the crystal part can not be clearly confirmed by the observation image by the TEM. In addition, CAAC-OS is an observation image by TEM and grain boundaries (also referred to as grain boundaries).
May not be clearly identified. Since, for example, the CAAC-OS does not have clear grain boundaries, impurities are less likely to segregate. In addition, since the CAAC-OS does not have clear grain boundaries, for example, the density of defect states is unlikely to be high. In addition, for example, the CAAC-OS is
Since there is no clear grain boundary, the decrease in electron mobility is small.

For example, the CAAC-OS has a plurality of crystal parts, and in some of the plurality of crystal parts, the c-axis may be aligned in a direction parallel to the normal vector of the formation surface or the normal vector of the surface.
Therefore, CAAC-OS has, for example, X-ray diffraction (XRD: X-Ray Diffrac
analysis by out-of-plane method using an
There may be a peak where θ is around 31 °. In the CAAC-OS, for example, spots (bright spots) may be observed in an electron diffraction pattern. In particular, the beam diameter is 1
An electron beam diffraction pattern obtained using an electron beam of 0 nmφ or less or 5 nmφ or less is called a very fine electron beam diffraction pattern. In addition, in the CAAC-OS, for example, the directions of the a-axis and the b-axis may not be uniform between different crystal parts. The CAAC-OS may be, for example, c-axis oriented, and the a-axis or / and the b-axis may not be aligned with the macro.

FIG. 31 is an example of a nanobeam electron diffraction pattern of a sample including a CAAC-OS. Here, the sample is cut in a direction perpendicular to the formation surface of the CAAC-OS, and sliced so as to have a thickness of about 40 nm. Here, an electron beam with a beam diameter of 1 nmφ is made to enter from a direction perpendicular to the cut surface of the sample. It can be seen from FIG. 31 that a spot is observed in the very fine electron diffraction pattern of the CAAC-OS.

For example, the crystal parts included in the CAAC-OS are aligned so that the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS or the normal vector of the surface, and from the direction perpendicular to the ab plane The metal atoms are arranged in a triangular shape or a hexagonal shape, and the metal atoms are arranged in a layer, or the metal atoms and the oxygen atoms are arranged in a layer, as viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In the present specification, the term “perpendicular” also includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. Moreover, when it describes only as parallel, it shall also contain the range of -10 degrees or more and 10 degrees or less, preferably -5 degrees or more and 5 degrees or less.

Since the c-axis of the crystal part included in CAAC-OS is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS or the normal vector of the surface, the shape of the CAAC-OS (
Depending on the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may face in different directions. In addition, the crystal part is formed when a film is formed or when a crystallization process such as a heat treatment is performed after the film formation. Therefore, the c-axis of the crystal part is aligned in a direction parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS is formed.

The CAAC-OS can be formed, for example, by reducing the impurity concentration. Here, the impurity is an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and a transition metal element. In particular, an element such as silicon has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor. Therefore, in the case where the element deprives the oxide semiconductor of oxygen, the atomic arrangement of the oxide semiconductor may be disturbed to lower crystallinity. Further, since heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), the atomic arrangement of the oxide semiconductor may be disturbed to lower the crystallinity of the oxide semiconductor. Therefore,
The CAAC-OS is an oxide semiconductor with low impurity concentration. Further, an impurity contained in the oxide semiconductor may be a carrier generation source.

In the CAAC-OS, distribution of crystal parts is not necessarily uniform. For example, CAA
In the case of crystal growth from the surface side of the oxide semiconductor in the formation process of C-OS, the proportion of the crystal part in the vicinity of the surface may be higher than that in the vicinity of the formation surface. Also, CAAC
When an impurity is mixed into -OS, the crystallinity of the crystal part in the impurity mixed region may be lowered.

Alternatively, the CAAC-OS can be formed, for example, by reducing the density of defect states. In an oxide semiconductor, for example, oxygen vacancies increase the density of defect states. Oxygen deficiency can be a carrier trap or a carrier generation source by capturing hydrogen. In order to form a CAAC-OS, for example, it is important not to cause oxygen deficiency in an oxide semiconductor. Thus, the CAAC-OS is an oxide semiconductor with a low density of defect states. Alternatively, the CAAC-OS is an oxide semiconductor with a low amount of oxygen vacancies.

Constant photocurrent measurement method (CPM: Constant Photo) in CAAC-OS
The absorption coefficient derived by the current method) is less than 1 × 10 ⁻³ / cm, preferably less than 1 × 10 ⁻⁴ / cm, more preferably less than 5 × 10 ⁻⁵ / cm. The absorption coefficient has a positive correlation with energy (converted to the wavelength) corresponding to the localized level derived from the oxygen deficiency and the contamination of impurities, and thus the number of defect levels in the CAAC-OS is extremely low.

In addition, the absorption coefficient according to the defect level can be calculated from the following equation by removing the absorption coefficient portion called the Arback tail caused by the tail of the band from the curve of the absorption coefficient obtained by the CPM measurement. In addition, an Arback tail means a field which has a fixed slope in a curve of an absorption coefficient obtained by CPM measurement, and the slope is called Arback energy.

Here, α (E) represents the absorption coefficient at each energy, and α _u represents the absorption coefficient by the Arback tail.

In addition, a transistor using a high-purity intrinsic or a substantially high-purity intrinsic CAAC-OS has less variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

<Method for manufacturing CAAC-OS>
The c-axis of the crystal part included in the CAAC-OS is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS or the normal vector of the surface, so the shape of the CAAC-OS (cross-sectional shape of the formation surface Or depending on the cross-sectional shape of the surface, they may turn in different directions. Note that
The direction of the c-axis of the crystal part is a direction parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS is formed. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

  There are three methods for forming a CAAC-OS.

In the first method, the oxide semiconductor film is formed at a deposition temperature of 100 ° C. to 450 ° C., whereby the c-axis of the crystal part included in the oxide semiconductor film is a normal vector of the formation surface or This is a method of forming crystal parts aligned in a direction parallel to the surface normal vector. In the present specification, the film formation temperature is preferably 100 ° C. or more and 400 ° C. or less.

In the second method, after the oxide semiconductor film is formed to have a small thickness, heat treatment is performed at a temperature higher than or equal to 200 ° C. and lower than or equal to 700 ° C. to form the c-axis of the crystal part in the oxide semiconductor film. This is a method of forming a crystal part aligned in a direction parallel to the surface normal vector or the surface normal vector. In the present specification, the heating temperature is preferably 200 ° C. or more and 400 ° C. or less.

The third method is to form the first oxide semiconductor film with a thin thickness, and
The c-axis of the crystal part included in the oxide semiconductor film corresponds to the normal vector of the formation surface or the method of the surface by heat treatment at a temperature of at most 20 ° C. and further deposition of a second oxide semiconductor film. This is a method of forming crystal parts aligned in a direction parallel to the line vector. In the present specification, the heating temperature is preferably 200 ° C. or more and 400 ° C. or less.

  Here, a method for forming a CAAC-OS using the first method is described.

<Target, and Method for Producing Target>
For example, the CAAC-OS is formed by a sputtering method using a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, the crystal region included in the sputtering target is cleaved from the a-b plane, and separated as flat-plate-like or pellet-like sputtering particles having a plane parallel to the a-b plane. is there. In this case, the flat-plate-like or pellet-like sputtering particles reach the formation surface while maintaining the crystalline state, whereby a CAAC-OS can be formed.

  In addition, in order to form a CAAC-OS, it is preferable to apply the following conditions.

By reducing the mixing of impurities at the time of film formation, it is possible to suppress that the crystal state is broken by the impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) in the film formation chamber may be reduced. Further, the concentration of impurities in the deposition gas may be reduced. Specifically, a deposition gas whose dew point is -80.degree. C. or less, preferably -100.degree. C. or less, more preferably -100.degree. C. or less is used.

Further, by raising the heating temperature (for example, the substrate heating temperature) of the formation surface at the time of film formation, migration of the sputtering particles occurs after reaching the formation surface. Specifically, the film formation is performed with the temperature of the formation surface set to 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C.
When flat-plate-like sputtering particles reach the formation surface by raising the temperature of the formation surface at the time of film formation, migration occurs on the formation surface, and the flat surface of the sputtering particles adheres to the formation surface Do. In addition, although it changes also with kinds of oxide, the diameter (circle equivalent diameter) of the surface parallel to an ab surface becomes 1 nm-30 nm, or 1 nm-10 nm or less about sputtered particle. The flat-plate-like sputtered particles may have a hexagonal columnar shape in which the hexagonal surface is a surface parallel to the a-b surface. In that case, the direction perpendicular to the plane of the hexagon is the c-axis direction.

Note that plasma damage at the time of film formation can be reduced by sputtering a sputtering target using cations of oxygen. Therefore, when ions collide with the surface of the sputtering target, it is possible to suppress the reduction in crystallinity of the sputtering target or the amorphization.

In addition, by sputtering a sputtering target using cations of oxygen or argon, when flat-plate-like sputtered particles have a hexagonal column shape, positive charge can be charged at the corners of the hexagonal surface. By having a positive charge at the corner of the hexagonal surface, the positive charges can repel each other in one sputtering particle, and a flat shape can be maintained.

In order for the corners in the plane of the flat sputtering particle to have a positive charge, direct current (
It is preferred to use a DC power supply. Note that a high frequency (RF) power supply or an alternating current (AC) power supply can also be used. However, it is difficult to apply an RF power supply to a sputtering apparatus capable of forming a film on a large area substrate. In addition, it is considered that a DC power supply is preferable to an AC power supply from the viewpoint described below.

When using an AC power supply, adjacent targets repeat the cathode potential and the anode potential. When the flat-plate-like sputtered particles are positively charged, the flat-plate-like shape can be maintained by repelling each other. However, when an AC power supply is used, a time during which an electric field is not applied instantaneously occurs, so that the charges charged on the flat-plate-like sputtered particles may disappear and the structure of the sputtered particles may be broken. Therefore, it is understood that using a DC power supply is preferable to using an AC power supply.

Further, it is preferable to reduce plasma damage at the time of film formation by increasing the proportion of oxygen in the film formation gas and optimizing the power. The proportion of oxygen in the deposition gas is 30% by volume or more, preferably 100.
Volume%

An In-Ga-Zn-O compound target is shown below as an example of the sputtering target.

In-G, which is polycrystalline by mixing InO _X powder, GaO _Y powder, and ZnO _Z powder in a predetermined number of moles, heat treatment at a temperature of 1000 ° C. or more and 1500 ° C. or less after pressure treatment
It is used as an a-Zn-O compound target. Note that the pressure treatment may be performed while cooling (or cooling) or may be performed while heating. Note that X, Y and Z are arbitrary positive numbers. Here, the predetermined molar ratio is, for example, InO _X powder, GaO _Y powder, and ZnO _Z powder: 2: 2: 1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4 : 2: 3, 3: 1: 2, 1
: 3: 2, 1: 6, or 1: 9: 6. The type of powder and the molar ratio to be mixed may be changed as appropriate depending on the sputtering target to be produced.

By using the sputtering target by the above method, an oxide semiconductor film with uniform thickness and uniform crystal orientation can be formed.

<Polycrystalline oxide semiconductor>
An oxide semiconductor having a polycrystal is called a polycrystalline oxide semiconductor. A polycrystalline oxide semiconductor includes a plurality of crystal grains.

In a polycrystalline oxide semiconductor, for example, crystal grains may be confirmed in an observation image by TEM. For example, crystal grains contained in the polycrystalline oxide semiconductor often have a particle size of 2 nm to 300 nm, 3 nm to 100 nm, or 5 nm to 50 nm in an observation image by TEM. In addition, in the case of a polycrystalline oxide semiconductor, for example, the boundary between the crystal grain and the crystal grain may be sometimes confirmed in an observation image by a TEM. In addition, in the case of a polycrystalline oxide semiconductor, for example, a grain boundary may be confirmed in an observation image by TEM.

The polycrystalline oxide semiconductor may have, for example, a plurality of crystal grains, and the orientation may be different in the plurality of crystal grains. In addition, for polycrystalline oxide semiconductor, for example, using an XRD apparatus,
When analysis by the out-of-plane method is performed, a peak at 2θ of around 31 ° indicating orientation or a peak indicating multiple orientations may appear. In addition, polycrystalline oxide semiconductors are
For example, spots may be observed in an electron diffraction pattern.

A polycrystalline oxide semiconductor, for example, may have high electron mobility because it has high crystallinity. Thus, a transistor in which a polycrystalline oxide semiconductor is used for a channel region has high field-effect mobility. However, in the polycrystalline oxide semiconductor, impurities may segregate at grain boundaries. In addition, grain boundaries of the polycrystalline oxide semiconductor become defect states. A grain boundary in a polycrystalline oxide semiconductor may be a carrier generation source or a trap level. Therefore, a transistor using a polycrystalline oxide semiconductor in a channel region is compared to a transistor using a CAAC-OS in a channel region. Thus, the transistor may have a large variation in electrical characteristics and low reliability.

The polycrystalline oxide semiconductor can be formed by heat treatment at a high temperature or laser light treatment.

<Microcrystalline oxide semiconductor>
For example, in a microcrystalline oxide semiconductor film, in some cases, a crystal part can not be clearly confirmed in an observation image by TEM. The crystal part included in the microcrystalline oxide semiconductor film is 1 nm to 10 nm.
The size is often 0 nm or less, or 1 nm or more and 10 nm or less. In particular, nanocrystals which are microcrystals of 1 nm to 10 nm, or 1 nm to 3 nm (nc: nano
An oxide semiconductor film having a crystal), an nc-OS (nanocrystalli)
It is called ne oxide semiconductor) film. In addition, in the case of an nc-OS film, for example, an observation image by TEM may not clearly confirm the grain boundaries.

The nc-OS film has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, in the nc-OS film, regularity is not observed in crystal orientation between different crystal parts. Therefore, no orientation can be seen in the entire film. Therefore, the nc-OS film may not be distinguished from the amorphous oxide semiconductor film depending on the analysis method. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus using an X-ray having a diameter larger than that of a crystal part, a peak indicating a crystal plane is not detected in analysis by the out-of-plane method. In addition, when electron diffraction (also referred to as limited field electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of a crystal part is performed on the nc-OS film, diffraction like halo pattern is performed. A pattern is observed. While nc
When electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter (for example, 1 nm or more and 30 nm or less) close to the size of the crystal part or smaller than the crystal part is performed on the -OS film, spots are observed. Be done. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed in a ring shape (in a ring shape). Also, nc-
When nanobeam electron diffraction is performed on the OS film, a plurality of spots may be observed in the ring-shaped region.

FIG. 32 shows an example in which nanobeam electron diffraction is performed on a sample having an nc-OS film while changing measurement points. Here, the sample is cut in the direction perpendicular to the formation surface of the nc-OS film,
It is sliced to have a thickness of 10 nm or less. Further, here, an electron beam with a probe diameter of 1 nmφ is made incident from a direction perpendicular to the cut surface of the sample. According to FIG. 32, when nanobeam electron diffraction is performed on a sample having an nc-OS film, a diffraction pattern indicating a crystal plane can be obtained.
It was found that no orientation to a crystal plane in a specific direction was observed.

The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. However, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, nc-
The OS film has a higher density of defect states than the CAAC-OS film.

Therefore, the carrier density of the nc-OS film may be higher than that of the CAAC-OS film. In the case of an oxide semiconductor film with high carrier density, electron mobility may be high. Thus, a transistor using an nc-OS film may have high field-effect mobility. In addition, since the nc-OS film has a higher density of defect states than the CAAC-OS film, carrier traps may be increased. Therefore, a transistor using an nc-OS film is
As compared with a transistor using an OS film, the transistor has large variations in electrical characteristics and low reliability. However, since the nc-OS film can be formed even if it contains a relatively large amount of impurities, it can be more easily formed than the CAAC-OS film, and may be suitably used depending on the application. Therefore, a semiconductor device having a transistor using an nc-OS film can be manufactured with high productivity in some cases.

<Amorphous oxide semiconductor>
An amorphous oxide semiconductor has, for example, disordered atomic arrangement and no crystal part. Alternatively, an amorphous oxide semiconductor has an amorphous state such as quartz, for example, and regularity in atomic arrangement is not observed.

In the case of an amorphous oxide semiconductor, for example, a crystal part may not be confirmed in an observation image by TEM.

When an amorphous oxide semiconductor is analyzed by an out-of-plane method using an XRD apparatus, a peak indicating orientation may not be detected. In addition, an amorphous oxide semiconductor film is
For example, a halo pattern may be observed in an electron diffraction pattern. In addition, in the case of an amorphous oxide semiconductor film, for example, a spot can not be observed with a very fine electron diffraction pattern,
Halo patterns may be observed.

An amorphous oxide semiconductor can be formed, for example, by containing an impurity such as hydrogen at a high concentration. Thus, an amorphous oxide semiconductor is, for example, an oxide semiconductor containing an impurity at a high concentration.

When the oxide semiconductor contains impurities at a high concentration, defect states such as oxygen vacancies may be formed in the oxide semiconductor. Therefore, an amorphous oxide semiconductor with a high impurity concentration has a high density of defect states. In addition, since an amorphous oxide semiconductor has low crystallinity, CAAC-OS or nc-OS
The density of defect states is higher than that of

Therefore, the carrier density of the amorphous oxide semiconductor may be higher than that of nc-OS. Therefore, a transistor in which an amorphous oxide semiconductor is used for a channel region may have normally-on electrical characteristics. Therefore, it may be suitably used for a transistor for which normally-on electrical characteristics are required. Since the amorphous oxide semiconductor has a high density of defect states, the trap state density may also be high. Therefore, in the case where a transistor including an amorphous oxide semiconductor in a channel region has large variation in electrical characteristics and low reliability as compared to a transistor including a CAAC-OS or nc-OS in the channel region. There is. However, an amorphous oxide semiconductor can be formed by a film formation method in which a relatively large amount of impurities is contained, which can be easily formed and can be suitably used depending on the application. For example, an amorphous oxide semiconductor is formed by a film formation method such as spin coating method, sol-gel method, immersion method, spray method, screen printing method, contact printing method, inkjet printing method, roll coating method, mist CVD method, etc. You may
Accordingly, a semiconductor device including a transistor in which an amorphous oxide semiconductor is used for a channel region can be manufactured with high productivity.

Note that the density of the oxide semiconductor increases, for example, when the number of defects is small. Further, in the oxide semiconductor, for example, when the crystallinity of hydrogen or the like is high, the density is high. Further, in the oxide semiconductor, for example, when the concentration of impurities such as hydrogen is low, the density is high. For example, a single crystal oxide semiconductor is
The density may be higher than AC-OS. In addition, for example, the CAAC-OS may have a higher density than the microcrystalline oxide semiconductor. In addition, for example, a polycrystalline oxide semiconductor may have a higher density than a microcrystalline oxide semiconductor. In addition, for example, a microcrystalline oxide semiconductor may have a higher density than an amorphous oxide semiconductor.

Tenth Embodiment
In this embodiment, a human interface to which the semiconductor device of one embodiment of the present invention can be applied will be described. In particular, a configuration example of a sensor (hereinafter, referred to as a touch sensor) capable of detecting proximity or contact of a detection target will be described.

As a touch sensor, various methods such as an electrostatic capacitance method, a resistive film method, a surface elasticity method, an infrared method, and an optical method can be used.

Representative examples of the capacitive touch sensor include a surface capacitive type and a projected capacitive type. Also, as the projected capacitive type, there are a self-capacitive type, a mutual capacitive type, and the like mainly from the difference in driving method. Here, it is preferable to use the mutual capacitance method because it is possible to simultaneously detect multiple points (also referred to as multipoint detection (multitouch)).

Here, the touch sensor will be described in detail, but in addition to that, the camera (including an infrared camera) or the like detects an operation (gesture) of a detected object (for example, a finger or a hand) or a viewpoint movement of a user Sensors that can be used can also be used as human interfaces.

<Example of sensor detection method>
FIGS. 33A and 33B are a schematic view showing a configuration of a mutual capacitive touch sensor and a schematic view of an input / output waveform. The touch sensor includes a pair of electrodes, and a capacitance is formed between them. An input voltage is input to one of the pair of electrodes. In addition, a detection circuit that detects a current flowing to the other electrode (or a potential of the other electrode) is provided.

For example, as shown in FIG. 33A, when a rectangular wave is used as the waveform of the input voltage, a waveform having a sharp peak is detected as the output current waveform.

Further, as shown in FIG. 33 (B), when the to-be-detected body having conductivity approaches or comes in contact with the capacitance, the capacitance value between the electrodes decreases, and the output current value accordingly decreases.

As described above, by detecting a change in capacitance using a change in output current (or potential) with respect to an input voltage, proximity or contact of a detection subject can be detected.

<Example of configuration of touch sensor>
FIG. 33C illustrates a configuration example of a touch sensor including a plurality of capacitors arranged in a matrix.

The touch sensor includes a plurality of wirings extending in the X direction (horizontal direction in the drawing) and a plurality of wirings intersecting in the plurality of wirings and extending in the Y direction (vertical direction in the drawing). A capacitance is formed between two crossing wires.

Further, either the input voltage or the common potential (including the ground potential and the reference potential) is input to the wiring extending in the X direction. In addition, a detection circuit (for example, a source meter, a sense amplifier, or the like) is electrically connected to the wiring extending in the Y direction, and a current (or a potential) flowing in the wiring can be detected.

The touch sensor scans the plurality of wires extending in the X direction so that the input voltage is sequentially input, and detects a change in current (or potential) flowing in the wires extending in the Y direction.
This enables two-dimensional sensing of a detection subject.

<Example of configuration of touch panel>
Hereinafter, a configuration example of a touch panel including a display portion having a plurality of pixels and a touch sensor, and an example of incorporating the touch panel into an electronic device will be described.

  FIG. 34A is a schematic cross-sectional view of an electronic device provided with a touch panel.

The electronic device 3530 includes a housing 3531 and at least the touch panel 3 in the housing 3531.
532, a battery 3533, and a control unit 3534. Further, the touch panel 3532 is electrically connected to the control unit 3534 through the wiring 3535. The control unit 3534 controls the display of an image on the display unit and the sensing operation of the touch sensor. In addition, the battery 3533 is electrically connected to the control unit 3534 through the wiring 3536, and can supply power to the control unit 3534.

The touch panel 3532 is provided such that the display surface side is exposed to the outside of the housing 3531. An image can be displayed on the exposed surface of the touch panel 3532 and at the same time, an object to be touched or approached can be detected.

  34 (B) to (E) show configuration examples of the touch panel.

A touch panel 3532 illustrated in FIG. 34B includes a first substrate 3541 and a second substrate 354.
A display panel 3540 including a display portion 3542 between three, a third substrate 3545 including a touch sensor 3544, and a protective substrate 3546 are provided.

As the display panel 3540, a liquid crystal element, organic EL (Electro Lumines)
c) various display devices such as a display device to which an element is applied and electronic paper can be applied. Note that the touch panel 3532 may additionally include a backlight, a polarizing plate, and the like in accordance with the structure of the display panel 3540.

It is preferable that at least the surface has an increased mechanical strength because the object to be detected is in contact with or in proximity to one surface of the protective substrate 3546. For example, a reinforced glass which has been physically or chemically treated by an ion exchange method, an air cooling method, or the like and has a compressive stress applied to its surface can be used as the protective substrate 3546. Alternatively, a flexible substrate such as plastic whose surface is coated can be used. Note that a protective film or an optical film may be provided over the protective substrate 3546.

The touch sensor 3544 is provided on at least one surface of the third substrate 3545. Alternatively, the pair of electrodes that form the touch sensor 3544 may be formed on both surfaces of the third substrate 3545. In addition, a flexible film may be used as the third substrate 3545 in order to make the touch panel thinner. In addition, the touch sensor 3544 may be held between a pair of substrates (including a film).

FIG. 34B shows a structure in which the protective substrate 3546 and the third substrate provided with the touch sensor 3544 are bonded by the adhesive layer 3547, but these may not necessarily be bonded. Further, the third substrate 3545 and the display panel 3540 may be bonded to each other by an adhesive layer.

The touch panel 3532 illustrated in FIG. 34B is provided with a display panel and a substrate provided with a touch sensor independently. The touch panel having such a configuration can also be called an external touch panel. With such a configuration, the display panel and the substrate including the touch sensor can be separately manufactured, and by overlapping them, the function of the touch sensor can be added to the display panel, so a special manufacturing process is required. The touch panel can be easily manufactured without

In the touch panel 3532 illustrated in FIG. 34C, the touch sensor 3544 is a second substrate 35.
43 is provided on the surface of the protective substrate 3546 side. The touch panel having such a configuration can also be called an on-cell touch panel. With such a configuration, the number of required substrates can be reduced, so that the thickness and weight of the touch panel can be reduced.

In the touch panel 3532 illustrated in FIG. 34D, the touch sensor 3544 is a protective substrate 354.
It is provided on one side of six. With such a configuration, the display panel and the touch sensor can be separately manufactured, so that the touch panel can be easily manufactured. Furthermore, since the number of required substrates can be reduced, thinning and weight reduction of the touch panel can be realized.

In the touch panel 3532 illustrated in FIG. 34E, the touch sensor 3544 is a display panel 35.
It is provided on the inside of 40 pairs of substrates. A touch panel having such a configuration can also be called an in-cell touch panel. With such a configuration, the number of required substrates can be reduced, so that the thickness and weight of the touch panel can be reduced. Such a touch panel can be realized, for example, by forming a circuit functioning as a touch sensor over the first substrate 3541 or the second substrate 3543 with a transistor, a wiring, an electrode, or the like included in the display portion 3542. In the case of using an optical touch sensor, a photoelectric conversion element may be provided.

<Configuration example of in-cell touch panel>
Hereinafter, a configuration example of a touch panel in which a touch sensor is incorporated in a display portion having a plurality of pixels will be described. Here, an example in which a liquid crystal element is applied as a display element provided in a pixel is described.

FIG. 35A is an equivalent circuit diagram of part of a pixel circuit provided in the display portion of the touch panel exemplified in this configuration example.

One pixel includes at least a transistor 3503 and a liquid crystal element 3504. In addition, a wiring 3501 is provided to the gate of the transistor 3503, and a wiring 35 is provided to one of the source and the drain.
Each 02 is electrically connected.

The pixel circuit includes a plurality of wirings extending in the X direction (eg, the wirings 3510_1 and 3510).
2) and a plurality of wirings (for example, wirings 3511) extending in the Y direction, which are provided to intersect with each other, and a capacitance is formed therebetween.

Further, among the plurality of pixels provided in the pixel circuit, one of the electrodes of the liquid crystal element provided in each of the plurality of adjacent pixels is electrically connected to form one block. The blocks are classified into two types: island-like blocks (eg, block 3515_1, block 3515_2) and linear blocks (eg, block 3516) extending in the Y direction. Although only a part of the pixel circuit is shown in FIG. 35, actually, these two types of blocks are repeatedly arranged in the X direction and the Y direction.

The wire 3510_1 (or 3510_2) extending in the X direction is an island block 351.
It is electrically connected to 5_1 (or block 3515_2). Although not shown, X
Directionally extending wires 3510_1 electrically connect a plurality of island-shaped blocks 3515_1 discontinuously arranged along the X-direction through the line-shaped blocks. In addition, a wire 3511 extending in the Y direction is electrically connected to the linear block 3516.

FIG. 35B is an equivalent circuit diagram showing a connection configuration of a plurality of wirings 3510 extending in the X direction and a plurality of wirings 3511 extending in the Y direction. An input voltage or a common potential can be input to each of the wirings 3510 extending in the X direction. Also, the wiring 3 extending in the Y direction
A ground potential can be input to each of the electrodes 511, or the wiring 3511 can be electrically connected to a detection circuit.

<Operation example of touch panel>
The operation of the touch panel described above will be described below with reference to FIG.

As shown in FIG. 36A, one frame period is divided into a write period and a detection period. The writing period is a period in which image data is written to pixels, and the wirings 3510 (also referred to as gate lines) are sequentially selected. On the other hand, a detection period is a period in which sensing is performed by a touch sensor, and wirings 3510 extending in the X direction are sequentially selected and an input voltage is input.

FIG. 36B is an equivalent circuit diagram in the writing period. In the writing period, the common potential is input to both the wiring 3510 extending in the X direction and the wiring 3511 extending in the Y direction.

FIG. 36C is an equivalent circuit diagram at a certain point in the detection period. In the detection period, each of the wirings 3511 extending in the Y direction is electrically connected to the detection circuit. Further, among the wirings 3510 extending in the X direction, an input voltage is input to a selected one, and a common potential is input to the other ones.

As described above, it is preferable to independently provide an image writing period and a period in which sensing by a touch sensor is performed. As a result, it is possible to suppress the decrease in the sensitivity of the touch sensor due to the noise at the time of writing the pixel.

(Embodiment 11)
In this embodiment mode, a driving method for reducing power consumption of a display device is described.
By the driving method of this embodiment, power consumption of a display device in which an oxide semiconductor transistor is applied to a pixel can be further reduced. Hereinafter, reduction in power consumption of a liquid crystal display device which is an example of a display device will be described with reference to FIGS. 37 and 38. FIG.

FIG. 37 is a block diagram showing a configuration example of the liquid crystal display device of the present embodiment. As shown in FIG. 37, the liquid crystal display device 500 includes a liquid crystal panel 501 as a display module, and further includes a control circuit 510 and a counter circuit 520.

The liquid crystal display device 500 receives an image signal (Video) that is digital data, and a synchronization signal (SYNC) for controlling rewriting of the screen of the liquid crystal panel 501. The synchronization signals include, for example, a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a reference clock signal (CLK).

The liquid crystal panel 501 includes a display unit 530, a scanning line drive circuit 540, and a data line drive circuit 5.
It has 50. The display unit 530 includes a plurality of pixels 531. The pixels 531 in the same row are connected to the scan line drive circuit 540 by a common scan line 541, and the pixels 531 in the same column are connected to the data line drive circuit 550 by a common data line 551.

The liquid crystal panel 501 has a common voltage (Vcom) and a high power supply voltage (power supply voltage).
And a low power supply voltage (VSS). The common voltage (Vcom) is displayed on the display unit 5
The 30 pixels 531 are supplied.

The data line drive circuit 550 processes the input image signal, generates a data signal, and outputs the data signal to the data line 551. The scan line driving circuit 540 outputs a scan signal for selecting the pixel 531 to which a data signal is written to the scan line 541.

The pixel 531 includes a switching element whose electrical connection to the data line 551 is controlled by a scan signal. When the switching element is turned on, a data signal is written from the data line 551 to the pixel 531.

  The electrode to which Vcom is applied corresponds to the common electrode.

Control circuit 510 is a circuit that controls the entire liquid crystal display device 500, and is a liquid crystal display device 50.
And a circuit that generates a control signal of a circuit that constitutes 0.

Control circuit 510 includes a control signal generation circuit that generates control signals for scan line drive circuit 540 and data line drive circuit 550 from the synchronization signal (SYNC). Start pulse (GSP), clock signal (GCLK) and the like are provided as control signals for scan line drive circuit 540, and start pulse (SSP) and clock signal (SC) are provided as control signals for data line drive circuit 550.
LK) etc. For example, control circuit 510 generates, as clock signals (GCLK, SCLK), a plurality of clock signals having the same cycle and shifted in phase.

Control circuit 510 also receives an image signal (Vide) input from the outside of liquid crystal display device 500.
Control the output to the data line drive circuit 550 of o).

Data line drive circuit 550 is a digital / analog conversion circuit (hereinafter referred to as D / A conversion circuit 55).
Call it 2 ). The DA conversion circuit 552 converts the image signal into an analog signal and generates a data signal.

When an image signal input to the liquid crystal display device 500 is an analog signal, the control circuit 510 converts the signal into a digital signal and outputs the digital signal to the liquid crystal panel 501.

The image signal is image data for each frame. The control circuit 510 has a function of performing image processing on an image signal and controlling output of the image signal to the data line driving circuit 550 based on information obtained by the processing. Therefore, the control circuit 510 includes a motion detection unit 511 that detects a motion from image data for each frame. When it is determined in the motion detection unit 511 that there is no motion, the control circuit 510 stops the output of the image signal to the data line drive circuit 550, and restarts the output of the image signal when it determines that there is a motion.

The image processing for motion detection performed by the motion detection unit 511 is not particularly limited. For example, as a motion detection method, for example, there is a method of obtaining difference data from image data between two consecutive frames. The presence or absence of motion can be determined from the obtained difference data. There is also a method of detecting a motion vector.

In addition, the liquid crystal display device 500 can be provided with an image signal correction circuit that corrects an input image signal. For example, the image signal is corrected such that a voltage higher than the voltage corresponding to the gradation of the image signal is written to the pixel 531. By performing such correction, the response time of the liquid crystal element can be shortened. A method of correcting the image signal and driving the control circuit 510 in this manner is called overdrive driving. Further, in the case of performing double-speed driving for driving the liquid crystal display device 500 at an integral multiple of the frame frequency of the image signal, the control circuit 510 creates image data for interpolating between two frames, or black between two frames. Image data for display may be generated.

Hereinafter, using a timing chart shown in FIG. 38, an image having motion like a moving image,
The operation of the liquid crystal display device 500 for displaying an image without motion like a still image will be described.
In FIG. 38, the vertical synchronization signal (Vsync) and the data line 5 from the data line drive circuit 550 are shown.
51 shows a signal waveform of the data signal (Vdata) output to 51.

FIG. 38 is a timing chart of the liquid crystal display device 500 during the 3 m frame period. Here, it is assumed that there is a motion in the image data of the first k frame period and the j frame period of the end, and there is no motion in the image data of the other frame periods. Note that k and j are each 1
It is an integer greater than or equal to m-2.

In the first k frame periods, the motion detection unit 511 determines that the image data of each frame has a motion. Control circuit 510 outputs a data signal (Vdata) to data line 551 based on the determination result of motion detection unit 511.

Then, the motion detection unit 511 performs image processing for motion detection, and when it is determined that there is no motion in the image data of the (k + 1) th frame, the control circuit 510 determines the k + 1th frame based on the determination result of the motion detection unit 511. During the period, the image signal (Vid to the data line drive circuit 550
Stop the output of eo). Thus, the output of the data signal (Vdata) from the data line drive circuit 550 to the data line 551 is stopped. Further, in order to stop the rewriting of the display portion 530, the supply of control signals (start pulse signal, clock signal and the like) to the scan line drive circuit 540 and the data line drive circuit 550 is stopped. Then, in control circuit 510, motion detection unit 51
1 stop the output of the image signal to the data line drive circuit 550 and the output of the control signal to the scan line drive circuit 540 and the data line drive circuit 550 until the determination result that the image data has motion is obtained. , The rewriting of the display unit 530 is stopped.

In this specification, “do not supply a signal to the liquid crystal panel” refers to applying a voltage different from a predetermined voltage for operating the circuit to the wiring supplying the signal, or electrically connecting the wiring It refers to being in a floating state.

When the rewriting of the display portion 530 is stopped, an electric field in the same direction is continuously applied to the liquid crystal element, and there is a possibility that the liquid crystal of the liquid crystal element is deteriorated. When such a problem becomes apparent,
Regardless of the determination result of the motion detection unit 511, a signal is supplied from the control circuit 510 to the scanning line drive circuit 540 and the data line drive circuit 550 at a predetermined timing, and a data signal whose polarity is inverted is written to the data line 551. The direction of the electric field applied to the liquid crystal element may be reversed.

The polarity of the data signal input to the data line 551 is determined based on Vcom.
Its polarity is positive if the voltage of the data signal is higher than Vcom and negative if it is lower.

Specifically, as shown in FIG. 38, in the (m + 1) th frame period, control circuit 510 outputs a control signal to scan line drive circuit 540 and data line drive circuit 550, and an image signal to data line drive circuit 550. Output Video. The data line drive circuit 550 outputs to the data line 551 a data signal (Vdata) whose polarity is inverted with respect to the data signal (Vdata) output to the data line 551 in the kth frame period. Therefore, the data signal (Vdata) whose polarity is inverted is written to the data line 551 in the (m + 1) th frame period and the (2m + 1) th frame period in which no motion is detected in image data. Since rewriting of the display portion 530 is performed intermittently during a period in which there is no change in image data, deterioration of the liquid crystal element can be prevented while power consumption due to the rewriting is reduced.

Then, when the motion detection unit 511 determines that there is a motion in the image data of the (2m + 1) th and subsequent frames, the control circuit 510 controls the scanning line drive circuit 540 and the data line drive circuit 550.
Are controlled, and the display unit 530 is rewritten.

As described above, according to the driving method of FIG. 38, the polarity of the data signal (Vdata) is inverted every m frame periods regardless of the presence or absence of movement of the image data (Video). On the other hand, with regard to the rewriting of the display unit 530, the display unit 530 is rewritten for each frame during the display period of the image including the motion, and the display unit 530 is displayed for every m frames during the display period of the image without motion.
Will be rewritten. As a result, power consumption associated with rewriting of the display portion can be reduced. Therefore, the increase in power consumption due to the increase in driving frequency and the number of pixels can be suppressed.

As described above, in the liquid crystal display device 500, deterioration of the liquid crystal is suppressed to maintain the display quality by making the driving method of the liquid crystal display device different between the mode for displaying a moving image and the mode for displaying a still image. It also becomes possible to provide a power saving liquid crystal display device.

In addition, in the case of displaying a still image, when pixels are rewritten for each frame, human eyes may feel that the pixel rewriting is flickering, which causes fatigue. The liquid crystal display device according to the present embodiment is effective for alleviating tired eyes because the frequency of pixel rewriting is low in the still image display period.

Therefore, by using a liquid crystal panel in which a backplane is formed of oxide semiconductor transistors, it is possible to provide a high-definition, low-power, medium- and small-sized display liquid crystal display device that is very suitable for portable electronic devices. .

In order to prevent deterioration of the liquid crystal, the interval of polarity inversion of the data signal (here, the m frame period) is 2 seconds or less, preferably 1 second or less.

In addition, although motion detection of image data is performed by the motion detection unit 511 of the control circuit 510, it is not necessary to perform motion detection only by the motion detection unit 511. Liquid crystal display device 500 with data on movement
May be input to the control circuit 510 from the outside.

Further, the condition for determining that there is no movement in the image data is not based on the image data between two consecutive frames, and the number of frames necessary for the determination can be appropriately determined according to the usage pattern of the liquid crystal display device 500. . For example, the rewriting of the display unit 530 may be stopped when there is no movement in the image data of consecutive m frames.

Although a liquid crystal display device is used as a display device in this embodiment, the driving method of this embodiment can be used for another display device such as a light emitting display device.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 12)
The semiconductor device which is one embodiment of the present invention can be applied to various electronic devices (including game machines). As the electronic device, a television set (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, A sound reproduction apparatus, a game machine (pachinko machine, slot machine, etc.), a game case can be mentioned. An example of these electronic devices is shown in FIG.

FIG. 39A shows a table 9000 having a display portion. In the table 9000, a display portion 9003 is incorporated in a housing 9001, and an image can be displayed by the display portion 9003. Note that a structure in which the housing 9001 is supported by four leg portions 9002 is shown. In addition, a power supply cord 9005 for supplying power is included in a housing 9001.

The semiconductor device described in any of the above embodiments can be used for the display portion 9003. Therefore, the display quality of the display portion 9003 can be increased.

The display unit 9003 has a touch input function, and the display unit 9003 of the table 9000
By touching the display button 9004 displayed on the screen with a finger or the like, screen operations and information can be input, and communication with other home appliances is possible or control is possible.
It is good also as a control device which controls other household appliances by screen operation. For example, with the use of a semiconductor device having an image sensor function, the display portion 9003 can have a touch input function.

In addition, with the hinge provided in the housing 9001, the screen of the display portion 9003 can be erected perpendicularly to the floor, and can also be used as a television set. In a small room
If a television with a large screen is installed, the free space will be narrowed, but if the display unit is built in the table, the room space can be used effectively.

FIG. 39B illustrates a television set 9100. FIG. Television equipment 9100
The display portion 9103 is incorporated in the housing 9101 and can display an image by the display portion 9103. Note that a structure in which the housing 9101 is supported by a stand 9105 is shown here.

The television set 9100 can be operated by an operation switch of the housing 9101 or a separate remote controller 9110. Channels and volume can be controlled with an operation key 9109 of the remote controller 9110, and a video displayed on the display portion 9103 can be manipulated. In addition, the remote control 9110 may be provided with a display portion 9107 for displaying information output from the remote control 9110.

A television set 9100 illustrated in FIG. 39B includes a receiver, a modem, and the like.
The television device 9100 can receive a general television broadcast by a receiver.
Furthermore, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication can be performed by connecting to a wired or wireless communication network via a modem. Is also possible.

The semiconductor device described in any of the above embodiments can be used for the display portions 9103 and 9107. Therefore, the display quality of the television set can be improved.

FIG. 39C illustrates a computer 9200 which includes a main body 9201, a housing 9202, a display portion 9, and the like.
203, keyboard 9204, external connection port 9205, pointing device 920
6 and so on.

The semiconductor device described in any of the above embodiments can be used for the display portion 9203. Therefore, the display quality of the computer 9200 can be improved.

The display portion 9203 has a touch input function, and the display portion 92 of the computer 9200.
By touching display button 9004 displayed on 03 with a finger or the like, screen operations and information can be input, and communication with other home appliances is possible or control is possible. It is good also as a control device which controls other household appliances by screen operation.

FIGS. 40A and 40B illustrate a foldable tablet terminal. Figure 40 (A
Is open, and the tablet terminal includes the housing 9630, the display portion 9631a, the display portion 9631b, the display mode switching switch 9034, the power switch 9035, the power saving mode switching switch 9036, the clasp 9033, and the operation switch 9038. And.

The semiconductor device described in any of the above embodiments includes the display portion 9631 a and the display portion 9631 b.
It can be used for Therefore, the display quality of the tablet terminal can be improved.

A portion of the display portion 9631 a can be a touch panel area 9632 a, and data can be input by touching the displayed operation key 9638. Display unit 96
31a shows, as an example, a configuration in which a half area has a display-only function and the other half area has a touch panel function, but the present invention is not limited to this structure. Display unit 96
The entire area 31a may have a touch panel function. For example, the display unit 9
The entire surface of the screen 631 a can be displayed as a keyboard button to form a touch panel, and the display portion 9631 b can be used as a display screen.

Further, in the display portion 9631 b, as in the display portion 9631 a, part of the display portion 9631 b can be used as a region 9632 b of the touch panel. In addition, by touching the position where the keyboard display switching button 9639 on the touch panel is displayed with a finger or a stylus, a keyboard button can be displayed on the display portion 9631 b.

Further, touch input can be performed simultaneously on the touch panel region 9632 a and the touch panel region 9632 b.

Further, the display mode switching switch 9034 can switch the display orientation such as vertical display or horizontal display, and can select switching between black and white display and color display. The power saving mode switching switch 9036 can optimize the display brightness in accordance with the amount of external light at the time of use detected by the light sensor incorporated in the tablet type terminal. The tablet type terminal may incorporate not only an optical sensor but also other detection devices such as a sensor for detecting inclination of a gyro, an acceleration sensor or the like.

Further, FIG. 40A shows an example in which the display areas of the display portion 9631 b and the display portion 9631 a are the same, but the present invention is not particularly limited, and one size may be different from the other size. It may be different. For example, a display panel in which one can perform higher definition display than the other may be used.

The tablet terminal is closed in FIG. 40B and the housing 9630 and the solar battery 9 are illustrated in FIG.
633, the charge and discharge control circuit 9634 is included. Note that in FIG. 40 (B), the charge and discharge control circuit 96
As an example of 34, a configuration including a battery 9635 and a DCDC converter 9636 is shown.

Note that since the tablet terminal can be folded in half, the housing 9630 can be closed when not in use. Therefore, the display portion 9631 a and the display portion 9631 b can be protected.
It is excellent in durability, and can provide a tablet type terminal excellent in reliability also from the viewpoint of long-term use.

In addition to this, the tablet-type terminals illustrated in FIGS. 40A and 40B have a function of displaying various information (still images, moving images, text images, and the like), a calendar, a date, time, and the like. A function of displaying on the display portion, a touch input function of performing touch input operation or editing of information displayed on the display portion, a function of controlling processing by various software (programs), and the like can be provided.

Electric power can be supplied to the touch panel, the display portion, the video signal processing portion, or the like by the solar battery 9633 mounted on the surface of the tablet terminal. Note that the solar cell 9633 can be provided on one side or both sides of the housing 9630 and is preferable because charging of the battery 9635 can be efficiently performed. When a lithium ion battery is used as the battery 9635, advantages such as downsizing can be achieved.

In addition, the structure and operation of the charge and discharge control circuit 9634 illustrated in FIG.
C) and a block diagram will be described. In FIG. 40C, a solar cell 9633 and a battery 9 are illustrated.
635, DC-DC converter 9636, converter 9637, switches SW1 to SW3
, The display portion 9631, the battery 9635, the DCDC converter 963
6, the converter 9637, and the switches SW1 to SW3 correspond to the charge / discharge control circuit 9634 shown in FIG.

First, an example of the operation in the case where power is generated by the solar cell 9633 by external light will be described. The power generated by the solar cell is set to a voltage for charging the battery 9635.
The CDC converter 9636 boosts or lowers the voltage. When the power from the solar cell 9633 is used to operate the display portion 9631, the switch SW 1 is turned on, and the converter 9637 boosts or steps down the voltage required for the display portion 9631. In addition, when display on the display portion 9631 is not performed, the switch SW1 may be turned off and the switch SW2 may be turned on to charge the battery 9635.

Although the solar cell 9633 is illustrated as an example of the power generation means, it is not particularly limited, and the battery 9635 is charged by another power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). It may be For example, a non-contact power transmission module that transmits and receives power wirelessly (without contact) to charge the battery, or another charging unit may be combined.

Note that the structure and the like described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

In this embodiment, Vg-Id characteristics of a transistor and measurement results of a light BT stress test will be described.

First, a manufacturing process of a transistor included in Sample 1 is described. This embodiment will be described with reference to FIG.

First, as shown in FIG. 2A, a glass substrate was used as the substrate 11, and the gate electrode 15 was formed on the substrate 11.

A tungsten film with a thickness of 100 nm was formed by a sputtering method, a mask was formed on the tungsten film by a photolithography step, and part of the tungsten film was etched using the mask to form a gate electrode 15.

  Next, a gate insulating film 17 (corresponding to GI in FIG. 41) was formed on the gate electrode 15.

As the gate insulating film 17, a 50 nm-thick first silicon nitride film, a 300 nm-thick second silicon nitride film, a 50 nm-thick third silicon nitride film, and a 50 nm-thick silicon oxynitride film are stacked. It formed.

The first silicon nitride film supplies silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 100 sccm as source gases into the processing chamber of the plasma CVD apparatus, and controls the pressure in the processing chamber to 100 Pa, 27.12 MHz Power supply of 2000 W using a high frequency power supply of

Next, under the conditions of the source gas of the first silicon nitride film, the ammonia flow rate is 2000
It changed to sccm and formed the 2nd silicon nitride film.

Next, silane at a flow rate of 200 sccm and nitrogen at a flow rate of 5000 sccm are supplied as source gases to the processing chamber of the plasma CVD apparatus, and the pressure in the processing chamber is controlled to 100 Pa, 27.1.
A power of 2000 W was supplied using a 2 MHz high frequency power supply to form a third silicon nitride film.

Next, silane at a flow rate of 20 sccm and dinitrogen monoxide at a flow rate of 3000 sccm are supplied as source gases to the processing chamber of the plasma CVD apparatus, and the pressure in the processing chamber is controlled to 40 Pa.
A power of 100 W was supplied using a 12 MHz high frequency power supply to form a silicon oxynitride film.

Note that the substrate temperature was set to 350 ° C. in the film formation step of the first to third silicon nitride films and the silicon oxynitride film.

  Next, a multilayer film 20 overlapping the gate electrode 15 was formed via the gate insulating film 17.

Here, an oxide semiconductor film (corresponding to S2 in FIG. 41) with a thickness of 35 nm is formed over the gate insulating film 17 by sputtering, and then an oxide film with a thickness of 20 nm (FIG. 4).
1 (corresponding to S3). Next, a mask was formed over the oxide film by a photolithography step, and part of the oxide semiconductor film and the oxide film were etched using the mask to form the oxide semiconductor film 18 and the oxide film 19. Thereafter, a first heat treatment was performed to form a multilayer film 20.

In the oxide semiconductor film (S2), the sputtering target is In: Ga: Zn = 1: 1:
A target of 1 (atomic ratio), argon flow rate 100 sccm and flow rate 100 scc
m oxygen was supplied as a sputtering gas into the processing chamber of the sputtering apparatus, the pressure in the processing chamber was controlled to 0.6 Pa, and 5 kW of DC power was supplied. Note that the substrate temperature at the time of forming the oxide semiconductor film was 200 ° C.

The oxide film (S3) uses a sputtering target as a target of In: Ga: Zn = 1: 3: 2 (atomic number ratio), and Ar and 20 sc at 180 sccm as a sputtering gas.
Oxygen of cm was supplied into the processing chamber of the sputtering apparatus, the pressure in the processing chamber was controlled to 0.6 Pa, and 5 kW of DC power was supplied. Note that the substrate temperature at the time of forming the oxide film was 200.degree.

In the first heat treatment, heat treatment was performed at 350 ° C. for one hour in a nitrogen atmosphere, and then heat treatment was performed at 350 ° C. for one hour in a nitrogen and oxygen atmosphere.

  The structure obtained through the steps up to here can be referred to FIG.

Next, after a part of the gate insulating film 17 was etched to expose the gate electrode (not shown), as shown in FIG. 2C, a pair of electrodes 21 and 22 in contact with the multilayer film 20 were formed. .

Here, a conductive film is formed over the gate insulating film 17 and the multilayer film 20. As the conductive film,
An aluminum film having a thickness of 400 nm was formed on a tungsten film having a thickness of 50 nm, and a titanium film having a thickness of 100 nm was formed on the aluminum film. Next, a mask was formed over the conductive film by a photolithography step, and part of the conductive film was wet etched using the mask to form a pair of electrodes 21 and 22. Thereafter, the surface of the multilayer film 20 was washed with a phosphoric acid aqueous solution prepared by diluting 85% phosphoric acid 100 times.

Next, the substrate is moved to a reduced pressure processing chamber and heated at 220 ° C., and then a 150 W high frequency power is supplied to the upper electrode provided in the processing chamber using a 27.12 MHz high frequency power source to The multilayer film 20 was exposed to oxygen plasma generated in a nitrogen atmosphere.

Next, a protective film 26 was formed on the multilayer film 20 and the pair of electrodes 21 and 22 (see FIG. 2D). Here, as the protective film 26, the oxide insulating film 23 (corresponding to P1 in FIG. 41), the oxide insulating film 24 (corresponding to P2 in FIG. 41), and the nitride insulating film 25 are formed.

First, after the plasma treatment, the oxide insulating film 23 and the oxide insulating film 24 were continuously formed without exposure to the air. A 50 nm-thick silicon oxynitride film was formed as the oxide insulating film 23, and a 400 nm-thick silicon oxynitride film was formed as the oxide insulating film 24.

The oxide insulating film 23 is a plasma in which silane having a flow rate of 30 sccm and dinitrogen monoxide having a flow rate of 4000 sccm are used as source gases, the pressure in the processing chamber is 200 Pa, the substrate temperature is 220 ° C., and 150 W high frequency power is supplied to the parallel plate electrode. It formed by CVD method.

The oxide insulating film 24 uses silane with a flow rate of 200 sccm and dinitrogen monoxide at a flow rate of 4000 sccm as source gases, the pressure in the processing chamber is 200 Pa, the substrate temperature is 220 ° C., and 1500
It formed by the plasma CVD method which supplied the high frequency electric power of W to the parallel plate electrode. Under the conditions, a silicon oxynitride film which contains oxygen at a higher proportion than the stoichiometric composition and from which part of oxygen is released by heating can be formed.

Next, a second heat treatment is performed to form the oxide insulating film 23 and the oxide insulating film 24 from water, nitrogen,
Hydrogen and the like were released, and part of oxygen contained in the oxide insulating film 24 was supplied to the multilayer film 20. Here, heat treatment was performed at 350 ° C. for one hour in a nitrogen and oxygen atmosphere.

Next, a nitride insulating film 25 was formed on the oxide insulating film 24. Here, nitride insulating film 2
A silicon nitride film having a thickness of 100 nm was formed as 5.

The nitride insulating film 25 uses silane at a flow rate of 50 sccm, nitrogen at a flow rate of 5000 sccm, and ammonia at a flow rate of 100 sccm as source gases, the pressure in the processing chamber is 100 Pa, the substrate temperature is 350 ° C., and high-frequency power of 1000 W is a parallel plate electrode. It formed by the supplied plasma CVD method.

Next, although not shown, part of the protective film 26 is etched to form an opening that exposes part of the pair of electrodes 21 and 22.

Next, a planarizing film was formed on the nitride insulating film 25 (not shown). Here, after the composition was applied on the nitride insulating film 25, exposure and development were performed to form a planarized film having an opening for exposing a part of the pair of electrodes. In addition, the 1.5-micrometer-thick acrylic resin was formed as a planarizing film. After this, heat treatment was performed. The heat treatment was performed at a temperature of 250 ° C. for 1 hour in an atmosphere containing nitrogen.

Next, a conductive film connected to part of the pair of electrodes was formed (not shown). Here, ITO including silicon oxide with a thickness of 100 nm was formed by a sputtering method. After that, heat treatment was performed at 250 ° C. for 1 hour in a nitrogen atmosphere.

  Through the above steps, Sample 1 having a transistor was manufactured.

In the transistor of sample 1, the multilayer film 20 has a three-layer structure, and the gate insulating film 17
An oxide film (corresponding to S1 in FIG. 41) having a thickness of 5 nm is formed between the first and the oxide semiconductor films 18 under the same conditions as the oxide film 19, and the oxide film 19 (FIG. A sample having a transistor manufactured to have a thickness of 15 nm (corresponding to S3) is referred to as a sample 2.

In the transistor of sample 1, the multilayer film 20 has a three-layer structure, and the gate insulating film 17
A sample including a transistor manufactured using an oxide film (corresponding to S1 in FIG. 41) with a thickness of 10 nm between the oxide semiconductor film 18 and the oxide semiconductor film 18 using the same conditions as the oxide film 19 is a sample 3.

In the transistor of Sample 1, instead of the multilayer film 20, only the oxide semiconductor film 18 is formed, the heating temperature is set to 450 ° C. in the first heat treatment, and the pressure is set under the film formation conditions of the oxide insulating film 23. A sample including a transistor manufactured at 40 Pa and a flow rate of silane at 160 sccm under the film formation conditions of the oxide insulating film 24 is referred to as a comparative sample 1.

Further, in the transistor of Sample 1, only the oxide semiconductor film 18 is formed instead of the multilayer film 20, and a sample including a transistor manufactured at a heating temperature of 350 ° C. in the first heat treatment is set as Comparative Sample 2.

Note that the transistor included in each sample has a channel length (L) of 6 μm, a channel width (W
) Is 50 μm.

Next, V as the initial characteristics of the transistors included in Samples 1 to 3 and Comparative Sample 1
The g-Id characteristics were measured. Here, the substrate temperature is 25 ° C., the source-drain potential difference (hereinafter referred to as drain voltage) is 1 V and 10 V, and the source-gate electrode potential difference (hereinafter referred to as gate voltage) is -15 V to +15 V Characteristics of the current (hereinafter referred to as drain current) flowing between the source and the drain when changing to
The characteristics were measured.

FIG. 41 shows Vg-Id characteristics of transistors included in each sample. In each graph shown in FIG. 41, the horizontal axis represents gate voltage Vg, the left vertical axis represents drain current Id, and the right vertical axis represents field effect mobility. The horizontal axis is shown as -15V to 15V. The solid line represents the Vg-Id characteristics when the drain voltage Vd is 1 V and 10 V, and the broken line represents the field effect mobility with respect to the gate voltage when the drain voltage Vd is 10 V. Note that
The field effect mobility is the result in the saturated region of each sample.

  In each sample, twenty transistors having the same structure were fabricated in the substrate.

From FIG. 41, it can be seen that good switching characteristics are obtained in Samples 1 to 3 and Comparative Sample 1 respectively.

Next, BT stress tests and light BT stress tests of Samples 1 to 3 and Comparative Sample 1 were performed. The BT stress test is a type of accelerated test and can evaluate in a short time the change in characteristics of the transistor (that is, the change with time) caused by long-term use. Examining the amount of fluctuation of the characteristics of the transistor before and after the BT stress test is an important index for examining the reliability.

  First, a gate BT stress test and an optical gate BT stress test were performed.

Here, a measurement method of the gate BT stress test will be described. First, the Vg-Id characteristics in the initial characteristics of the transistor are measured as described above.

Next, the substrate temperature is maintained at an arbitrary temperature (hereinafter referred to as stress temperature), and a pair of electrodes functioning as a source and a drain of the transistor are set to the same potential, and a pair of electrodes functioning as a source and drain electrode A potential different from that applied to the gate electrode is applied for a fixed time (hereinafter referred to as a stress time). Next, the substrate temperature is appropriately set, and the electrical characteristics of the transistor are measured. As a result, the difference between the threshold voltage and the shift value in the electrical characteristics before and after the gate BT stress test can be obtained as a variation.

Note that a stress test that applies a negative voltage to the gate electrode is called a negative gate BT stress test (Dark-GBT), and a stress test that applies a positive voltage is a positive gate BT
It is called a stress test (Dark + GBT). In addition, a light negative gate BT stress test (Photo-GBT) is applied to apply a negative voltage to the gate electrode while irradiating light.
And light plus gate BT stress test (Pho) stress test to apply positive voltage
to + GBT).

Here, as the gate BT stress condition, the stress temperature is 60 ° C., and the stress time is 3 hours.
600 seconds, -30 V or +30 V for the gate electrode, 0 for the source and drain electrodes
V was applied. The electric field strength applied to the gate insulating film at this time was 0.66 MV / cm.

Further, under the same conditions as the above-mentioned BT stress test, a transistor was irradiated with 10000 lx of white LED light to conduct a light gate BT stress test. In addition, the measurement temperature of the Vg-Id characteristic of the transistor after BT stress test was 60 degreeC.

The difference between the threshold voltage of the initial characteristics of the transistors included in Samples 1 to 3 and Comparative Sample 1 and the threshold voltage after BT stress test (that is, variation amount of threshold voltage (ΔVth))
The difference between the shift values (ie, the shift amount (ΔShift)) is shown in FIG. In FIG. 42 (A), plus gate BT stress test (Dark + GBT), minus gate BT stress test (Dark-GBT), light plus gate BT stress test (P
The variation of hoto + GBT) and light negative gate BT stress test (Photo-GBT) is shown.

Next, the stress temperature was changed to conduct a stress test. Here, under the conditions of the gate BT stress test, the gate BT stress test was performed with a stress temperature of 125 ° C. Note that the measurement temperature of the Vg-Id characteristics of the transistor after the gate BT stress test is 4
It was 0 ° C.

The variation (ΔVth) of the threshold voltage and the variation (ΔShift) of the shift value contained in Samples 1 to 3 and Comparative Sample 1 are shown in FIG. In FIG. 42B, a plus gate BT stress test (Dark + GBT), a minus gate BT stress test (D)
ark-GBT) shows each variation amount.

Here, the threshold voltage and the shift value in the present specification will be described with reference to FIG.

In the present specification, the threshold voltage (Vth) has a horizontal axis representing the gate voltage (Vg [V]),
The tangent line 614 and the Vg axis (i.e., Id) obtained by extrapolating the tangent line 614 of the maximum slope Id ^1/2 in a curve 612 plotted with the square root of the drain current (Id ^1/2 [A]) as the vertical axis ^1/2 is defined by the gate voltage at the intersection with 0A) (see FIG. 43A). Note that
In the present specification, the threshold voltage is calculated by setting the drain voltage Vd to 10V. Further, in the present specification, the threshold voltage (Vth) is an average value of Vth of each of 20 transistors included in each sample.

Further, in the present specification, the shift value (Shift) has a maximum slope in a curve 616 in which the gate voltage (Vg [V]) is plotted on the horizontal axis and the logarithm of the drain current (Id [A]) is plotted on the vertical axis. It is defined by the gate voltage at the intersection with the straight line Id = 1.0 × 10 ⁻¹² [A] when the tangent 618 of a certain Id is extrapolated (see FIG. 43B). In the present specification, the shift value is calculated by setting the drain voltage Vd to 10V. Further, in the present specification, the shift value is an average value of the shift values of the 20 transistors included in each sample.

From FIG. 42 (A), in comparison with Comparative Sample 1, Samples 1 to 3 have negative gate BT.
It can be seen that the stress test (Dark-GBT) fluctuation is small. In addition, it can be seen that the light negative gate BT stress test (Photo-GBT) fluctuation amount is small.

In addition, it can be seen that the amount of fluctuation of the sample 2 is smaller in each stress test as compared with the sample 1 and the sample 3. From this, it is understood that the amount of fluctuation of the threshold voltage and the shift value can be reduced by forming the multilayer film into three layers and reducing the thickness of the first oxide film.

From FIG. 42 (B), in comparison with Comparative Sample 1, Samples 1 to 3 have negative gate BT.
It can be seen that the stress test (Dark-GBT) fluctuation is small.

From the above, in the heat treatment for desorbing impurities from the oxide semiconductor film and the multilayer film, the oxide film in contact with the oxide semiconductor film is provided even when the heating temperature is lowered to 450 ° C. to 350 ° C. It can be seen that the amount of fluctuation of the transistor characteristics can be reduced.

Next, in sample 1 and sample 2 and comparative sample 1 and comparative sample 2, plus gate B
T stress test (Dark + GBT) was performed. Here, the stress temperature is 60 ° C. or 125 ° C., and the stress time is 100 seconds, 500 seconds, 1500 seconds, respectively.
The amount of fluctuation of the threshold voltage was measured as 2000 seconds and 3600 seconds. FIG. 44 shows the variation of the threshold voltage at each stress time and the approximate curve obtained from each variation. The horizontal axis represents stress time, and the vertical axis represents variation (ΔVth) of the threshold voltage. Also, FIG. 44 (A) shows the measurement result when the stress temperature is 60 ° C., and FIG. 44 (B) shows the stress temperature 125
It is a measurement result at the time of ° C.

From FIG. 44, it can be seen that the variation amount of the threshold voltage of the sample 1 and the sample 2 is smaller than that of the comparative sample 2. From this, in heat treatment of the multilayer film or the oxide semiconductor film, even if the temperature is lowered to 450 ° C. to 350 ° C., an oxide in contact with the oxide semiconductor film is provided, that is, a multilayer film is formed; It has been found that the fluctuation amount of can be reduced.

Also, it can be seen that the variation amount of the transistor characteristics of the sample 1 and the sample 2 is slightly larger than that of the comparative sample 1, but is equivalent to that of the comparative sample 1.

Next, the plus gate BT stress test (Dark + GBT) was performed on Sample 1 and Sample 2 and Comparative Sample 2. Here, the stress temperature was 125 ° C., and the stress time was 3600 seconds, and the variation of the threshold voltage was measured. Note that the measurement temperature of the Vg-Id characteristics of the transistor after the gate BT stress test was 40.degree.

In addition, a negative source BT stress test (Dark-SBT) was performed on Sample 1 and Sample 2 and Comparative Sample 2. The source BT stress test is a type of accelerated test similar to the gate BT stress test, and can evaluate in a short time the change in characteristics of the transistor (that is, the change with time) caused by long-term use.

Here, a measurement method of the source BT stress test will be described. First, the Vg-Id characteristics in the initial characteristics of the transistor are measured as described above.

Next, the substrate temperature is kept constant, the gate electrode and the drain electrode of the transistor are set to the same potential, and a potential different from that of the gate electrode and the drain electrode is applied to the source electrode in a pulsed manner. Next, the substrate temperature is set as in the measurement of the electrical characteristics, and the electrical characteristics of the transistor are measured. As a result, it is possible to observe the variation of the electrical characteristics before and after the source BT stress test.

Here, as source BT stress conditions, the stress temperature is 125 ° C., the stress time is 3600 seconds, the pulse frequency is 60 Hz (period is 16.7 ms), the application time is 0.
Pulsed -30 V was applied to the source electrode at 6% (100 μs). In addition, 0 V was applied to the gate electrode and the drain electrode. The measurement temperature of the Vg-Id characteristics of the transistor after the source BT stress test was set to 40.degree.

Vg− in initial characteristics of transistors included in sample 1 and sample 2 and comparative sample 2
Id characteristics and Vg-Id characteristics of the transistor after the stress test are shown in FIG. In FIG. 45, the upper part shows the measurement result of the plus gate BT stress test (Dark + GBT), and the lower part shows the measurement result of the minus source BT stress test (Dark-SBT). A thin solid line indicates the Vg-Id characteristic in the initial characteristics of the transistor, and a thick solid line indicates the Vg-Id characteristic of the transistor after the stress test. In addition, it is Vg-Id characteristic in case the drain voltage Vd is 1V and 10V, respectively. A thin broken line indicates the field effect mobility in the initial characteristics of the transistor, and a thick broken line indicates the field effect mobility in the transistor after the stress test. In addition, the field effect mobility with respect to gate voltage when drain voltage Vd is 10 V is shown, respectively.

As compared with Comparative Sample 2, in Sample 1 and Sample 2, both the plus gate BT stress test (Dark + GBT) and the negative source BT stress test (Dark-SBT) reduce the amount of fluctuation in threshold voltage after the stress test. Know that Further, in the plus gate BT stress test (Dark + GBT), in the comparative sample 2, the on current is decreased after the stress test, but in the sample 1 and the sample 2, no decrease in on current is observed. From the above, when the heat treatment temperature for desorbing the impurities from the oxide semiconductor film and the multilayer film is a relatively low temperature of 350 ° C., a multilayer film including an oxide film in contact with the oxide semiconductor film can be obtained. It has been found that the amount of fluctuation of the electrical characteristics of the transistor can be reduced.

Claims (2)

Forming a gate electrode and a gate insulating film on the substrate;
An oxide semiconductor film is formed on the gate insulating film,
An oxide film is formed over the oxide semiconductor film,
The oxide semiconductor film and the oxide film have In, Ga, and Zn, respectively.
The atomic ratio of Ga to In of the oxide film is larger than the atomic ratio of Ga to In of the oxide semiconductor film,
After the oxide film is formed, first heat treatment is performed at 300 ° C. to 400 ° C.,
After the first heat treatment, a pair of electrodes in contact with the oxide film is formed;
An oxide insulating film is formed on the pair of electrodes,
The oxide insulating film is in contact with the oxide film between the pair of electrodes,
After the oxide insulating film is formed, a second heat treatment is performed at 300 ° C to 400 ° C. Forming a gate electrode and a gate insulating film on the substrate;
An oxide semiconductor film is formed on the gate insulating film,
An oxide film is formed over the oxide semiconductor film,
The oxide semiconductor film and the oxide film have In, Ga, and Zn, respectively.
The atomic ratio of Ga to In of the oxide film is larger than the atomic ratio of Ga to In of the oxide semiconductor film,
After the oxide film is formed, first heat treatment is performed at 300 ° C. to 400 ° C.,
After the first heat treatment, a pair of electrodes in contact with the oxide film is formed;
The temperature of the substrate is 180 ° C. or more and 280 ° C. or less, the pressure in the processing chamber is 100 Pa or more and 250 Pa or less, and an oxide insulating film is formed over the pair of electrodes by plasma CVD.
The oxide insulating film is in contact with the oxide film between the pair of electrodes,
After the oxide insulating film is formed, second heat treatment is performed at 300 ° C to 400 ° C,
After the second heat treatment, a temperature of the substrate is set to 300 ° C. to 400 ° C., and a nitride insulating film is formed over the oxide insulating film by a plasma CVD method.