JP2019165253A - Semiconductor device manufacturing method - Google Patents

Abstract

To reduce defects of an oxide semiconductor film in a semiconductor device using the oxide semiconductor film; improve electrical characteristics in a semiconductor device using an oxide semiconductor film; and improve reliability in a semiconductor device using an oxide semiconductor film.SOLUTION: A semiconductor device manufacturing method comprises the steps of: forming a gate electrode and a gate insulation film on a substrate; forming, on the gate insulation film, a multilayer film having an oxide semiconductor film and an oxide film; performing a first heat treatment at a temperature within a range not less than 300°C and not more than 400°C to form a pair of electrodes which contact the multilayer film; forming a first oxide insulation film on the multilayer film and the pair of electrodes; forming a second oxide insulation film on the first oxide insulation film; and performing a second heat treatment at a temperature within a range not less than 300°C and not more than 400°C.SELECTED DRAWING: Figure 1

Description

The present invention relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, a driving method thereof, or a manufacturing method thereof. In particular, the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor, for example. In particular, the present invention relates to a semiconductor device including a transistor and a manufacturing method thereof, for example.

Transistors used in many flat panel displays typified by liquid crystal display devices and light-emitting display devices are composed of silicon semiconductors such as amorphous silicon, single crystal silicon, or polycrystalline silicon formed on a glass substrate. . In addition, a transistor including the silicon semiconductor is used for an integrated circuit (IC) or the like.

In recent years, a technique using a metal oxide exhibiting semiconductor characteristics for a transistor instead of a silicon semiconductor has attracted attention. Note that in this specification, a metal oxide exhibiting semiconductor characteristics is referred to as an oxide semiconductor.

For example, a technique is disclosed in which a transistor using zinc oxide or an In—Ga—Zn-based oxide as an oxide semiconductor is manufactured, and the transistor is used for a switching element of a pixel of a display device or the like (Patent Document 1). And Patent Document 2).

JP 2007-123861 A JP 2007-96055 A

In a transistor including an oxide semiconductor film, a large amount of defects included in the oxide semiconductor film leads to poor electrical characteristics of the transistor and changes with time and stress tests (for example, a BT (Bias-Temperature) stress test). ), The electrical characteristics of the transistor, typically the amount of fluctuation of the threshold voltage increases.

Further, not only defects but also impurities contained in the oxide semiconductor film, typically impurities such as silicon and carbon which are constituent elements of the insulating film, cause unnecessary electrical characteristics of the transistor.

Thus, an object of one embodiment of the present invention is to reduce defects in an oxide semiconductor film in a semiconductor device or the like including the oxide semiconductor film. Another object of one embodiment of the present invention is to reduce the impurity concentration of an oxide semiconductor film in a semiconductor device or the like including the oxide semiconductor film. Another object of one embodiment of the present invention is to improve electrical characteristics of a semiconductor device or the like including an oxide semiconductor film. Another object of one embodiment of the present invention is to improve reliability in a semiconductor device or the like including an oxide semiconductor film. Another object of one embodiment of the present invention is to provide a semiconductor device or the like with low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like with low power consumption. Another object of one embodiment of the present invention is to provide a display device or the like that can reduce eye fatigue. Another object of one embodiment of the present invention is to provide a semiconductor device or the like using a transparent semiconductor film. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having excellent characteristics. Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

In one embodiment of the present invention, a gate electrode and a gate insulating film are formed over a substrate, a multilayer film including an oxide semiconductor film and an oxide film is formed over the gate insulating film, and is preferably 300 ° C. to 400 ° C., preferably After performing the first heat treatment at 320 ° C. to 370 ° C., a pair of electrodes in contact with the multilayer film is formed, and a first oxide insulating film is formed over the multilayer film and the pair of electrodes. A method for manufacturing a semiconductor device, in which a second oxide insulating film is formed over the first oxide insulating film and subjected to second heat treatment at 300 ° C. to 400 ° C., preferably 320 ° C. to 370 ° C. is there.

Note that the substrate placed in the evacuated processing chamber is held at 180 ° C. or higher and 400 ° C. or lower, and a source gas is introduced into the processing chamber so that the pressure in the processing chamber is 100 Pa or higher and 250 Pa or lower. By supplying high-frequency power to the electrode, the first oxide insulating film can be formed.

In addition, the substrate placed in the evacuated processing chamber is held at 180 ° C. or higher and 280 ° C. or lower, and a raw material gas is introduced into the processing chamber so that the pressure in the processing chamber is 100 Pa or higher and 250 Pa or lower. by supplying a high frequency power of 0.17 W / cm ² or more 0.5 W / cm ² or less to the electrode, it is possible to form the second oxide insulating film.

As the first oxide insulating film and the second oxide insulating film, a silicon oxide film or a silicon oxynitride film is formed using a deposition gas containing silicon and an oxidizing gas as a source gas.

  Note that the oxide semiconductor film preferably contains In or Ga.

In addition, the energy level at the lower end of the conduction band of the oxide film is closer to the vacuum level than the energy level at the lower end of the conduction band of the oxide semiconductor film. Further, the difference between the energy level at the lower end of the conduction band of the oxide film and the energy level at the lower end of the conduction band of the oxide semiconductor film is 0.05 eV or more and 2e.
V or less is preferable. Note that since the energy difference between the vacuum level and the conduction band bottom is also referred to as electron affinity, the electron affinity of the oxide film is smaller than the electron affinity of the oxide semiconductor film, and the difference is 0.05 eV or more and 2 eV or less. preferable.

According to one embodiment of the present invention, defects in an oxide semiconductor film can be reduced in a semiconductor device including an oxide semiconductor film. Alternatively, according to one embodiment of the present invention, impurities in an oxide semiconductor film can be reduced in a semiconductor device or the like including an oxide semiconductor film. Alternatively, according to one embodiment of the present invention, electrical characteristics of a semiconductor device including an oxide semiconductor film can be improved. Alternatively, according to one embodiment of the present invention, reliability of a semiconductor device including an oxide semiconductor film can be improved. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a display device or the like that can reduce eye fatigue can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like using a transparent semiconductor film can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device or the like can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like having excellent characteristics can be provided.

10A to 10C are a top view and cross-sectional views illustrating one embodiment of a transistor. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a transistor. It is a figure explaining the band structure of a transistor. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 10 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 10 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 10 is a cross-sectional view illustrating one embodiment of a transistor. 10A to 10C are a top view and cross-sectional views illustrating one embodiment of a transistor. 10A to 10C are a top view and cross-sectional views illustrating one embodiment of a transistor. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a transistor. FIG. 10 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 10 is a cross-sectional view illustrating one embodiment of a transistor. 10A to 10C are a top view and cross-sectional views illustrating one embodiment of a transistor. 10A to 10C are a top view and cross-sectional views illustrating one embodiment of a transistor. 10A and 10B are a block diagram and a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 10 is a top view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a top view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. It is a figure which shows the micro electron beam diffraction pattern of an oxide semiconductor. It is a figure which shows the micro electron beam diffraction pattern of an oxide semiconductor. It is a figure explaining the touch sensor which concerns on embodiment. It is a figure explaining the structural example of the touchscreen and electronic device which concern on embodiment. It is a figure explaining a pixel provided with a touch sensor concerning an embodiment. It is a figure explaining operation | movement of the touch sensor and pixel which concern on embodiment. It is a block diagram which shows the structural example of a liquid crystal display device. 3 is a timing chart illustrating an example of a method for driving a liquid crystal display device. FIG. 10 illustrates an electronic device including a semiconductor device that is one embodiment of the present invention. FIG. 10 illustrates an electronic device including a semiconductor device that is one embodiment of the present invention. It is a figure which shows the Vg-Id characteristic of a transistor. It is a figure which shows the fluctuation amount of the threshold voltage and shift value of a transistor after a BT stress test and an optical BT stress test. It is a figure explaining the definition of a threshold voltage and a shift value. It is a figure which shows the threshold value of the transistor after an optical BT stress test and an optical BT stress test. It is a figure which shows the Vg-Id characteristic of the transistor before and after a BT stress test.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments and examples below. In the following embodiments and examples, the same portions or portions having similar functions are denoted by the same reference numerals or the same hatch patterns in different drawings, and description thereof is not repeated. To do.

Note that in each drawing described in this specification, the size of each component, the thickness of a film, or a region is
May be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.

Further, the terms such as first, second, and third used in this specification are given for avoiding confusion between components, and are not limited numerically. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.

Further, the functions of “source” and “drain” may be interchanged when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

Further, the voltage refers to a potential difference between two points, and the potential refers to electrostatic energy (electric potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, generally, a potential difference between a potential at a certain point and a reference potential (for example, ground potential) is simply referred to as a potential or a voltage, and the potential and the voltage are often used as synonyms. Therefore, in this specification, unless otherwise specified, the potential may be read as a voltage, or the voltage may be read as a potential.

In this specification, in the case where an etching step is performed after a photolithography step, the mask formed in the photolithography step is removed.

(Embodiment 1)
In this embodiment, a semiconductor device which is one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

In a transistor including an oxide semiconductor film, oxygen vacancies are examples of defects that lead to poor electrical characteristics of the transistor. For example, in a transistor including an oxide semiconductor film in which oxygen vacancies are included in the film, the threshold voltage is likely to fluctuate in the negative direction, which tends to be normally on. This is because electric charges are generated due to oxygen vacancies in the oxide semiconductor film and resistance is reduced. When the transistor has a normally-on characteristic, various problems such as an operation failure easily occurring during operation or a high power consumption during non-operation occur. In addition, there is a problem that the electrical characteristics of the transistor, typically the amount of variation in the threshold voltage, increases due to a change with time and a stress test.

One of the causes of oxygen vacancies is damage that occurs in a transistor manufacturing process.
For example, when an insulating film, a conductive film, or the like is formed over the oxide semiconductor film by a plasma CVD method or a sputtering method, the oxide semiconductor film may be damaged depending on the formation conditions.

In addition to oxygen vacancies, impurities such as silicon and carbon, which are constituent elements of the insulating film, and water also cause defects in the electrical characteristics of the transistor. For this reason, when the impurities are mixed into the oxide semiconductor film, the resistance of the oxide semiconductor film is reduced, and the electrical characteristics of the transistor, typically the threshold voltage, is reduced by aging and stress tests. There is a problem that the amount of fluctuation increases.

Therefore, in this embodiment, in a semiconductor device including a transistor including an oxide semiconductor film, it is an object to reduce oxygen vacancies in the oxide semiconductor film including a channel region and the impurity concentration of the oxide semiconductor film. And

On the other hand, display devices sold in the market tend to increase in screen size to a diagonal of 60 inches or more, and are further developed with a view to screen sizes of a diagonal of 120 inches or more. Yes. For this reason, in the glass substrate used for a display apparatus, the area increase of the 8th generation or more is progressing. However, when using large area substrates, high temperature processing, for example 450
Since the heat treatment is performed at a temperature higher than 0 ° C., the heating apparatus becomes large and expensive, and the production cost increases. Further, when the high temperature treatment is performed, the substrate is warped and shrinks, and the yield is reduced.

Thus, in this embodiment, it is an object to manufacture a semiconductor device using a small number of heat treatment steps and heat treatment at a temperature that is possible even with a large-area substrate.

1A to 1C are a top view and cross-sectional views of a transistor 50 included in a semiconductor device. A transistor 50 illustrated in FIG. 1 is a channel-etched transistor. 1A is a top view of the transistor 50, and FIG. 1B is a dashed-dotted line A− in FIG.
FIG. 1C is a cross-sectional view taken along one-dot chain line CD in FIG. 1A. Note that in FIG. 1A, for the sake of clarity, part of the components of the substrate 11, the transistor 50 (for example, the gate insulating film 17), the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film are illustrated. 25 etc. are omitted.

A transistor 50 illustrated in FIGS. 1B and 1C includes a gate electrode 15 provided over a substrate 11. Further, the gate insulating film 17 formed on the substrate 11 and the gate electrode 15.
And a multilayer film 20 that overlaps the gate electrode 15 with the gate insulating film 17 interposed therebetween, and a pair of electrodes 21 and 22 in contact with the multilayer film 20. Further, the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 are provided over the gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 and 22.
Is formed.

In the transistor 50 described in this embodiment, the multilayer film 20 includes the oxide semiconductor film 18 and the oxide film 19. In addition, part of the oxide semiconductor film 18 functions as a channel region. An oxide insulating film 23 is formed so as to be in contact with the multilayer film 20, and an oxide insulating film 24 is formed so as to be in contact with the oxide insulating film 23. That is, the oxide film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23.

The oxide semiconductor film 18 is typically an In—Ga oxide film, an In—Zn oxide film, or In
-M-Zn oxide film (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf
)

Note that when the oxide semiconductor film 18 is an In-M-Zn oxide film and the sum of In and M is 100 atomic%, the atomic ratio of In and M is preferably 25 at.
omic% or more, M is less than 75 atomic%, more preferably In is 34 atomic%.
c% or more and M is less than 66 atomic%.

The oxide semiconductor film 18 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, the off-state current of the transistor 50 can be reduced by using an oxide semiconductor with a wide energy gap.

The thickness of the oxide semiconductor film 18 is 3 nm to 200 nm, preferably 3 nm to 10 nm.
0 nm or less, more preferably 3 nm or more and 50 nm or less.

The oxide film 19 typically includes an In—Ga oxide, an In—Zn oxide, and an In—M—Zn.
It is an oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), and the energy at the lower end of the conduction band is closer to the vacuum level than the oxide semiconductor film 18. The difference between the energy at the lower end of the conduction band of the oxide film 19 and the energy at the lower end of the conduction band of the oxide semiconductor film 18 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0. 15
eV or more, 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the oxide film 19 and the electron affinity of the oxide semiconductor film 18 is 0.
05eV or more, 0.07eV or more, 0.1eV or more, or 0.15eV or more, and 2e
V or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

As the oxide film 19, Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf is used as I.
By having an atomic ratio higher than n, the following effects may be obtained. (1) Oxide film 1
Increase the 9 energy gap. (2) The electron affinity of the oxide film 19 is reduced.
(3) Shield impurities from the outside. (4) Compared with the oxide semiconductor film 18, the insulating property is increased. (5) Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf is a metal element having a strong binding force with oxygen, so Al, Ti, Ga, Y, Zr, La, Ce, Nd or By having Hf at a higher atomic ratio than In, oxygen vacancies are less likely to occur.

When the oxide film 19 is an In-M-Zn oxide film, the sum of In and M is 100 at
When the atomic ratio of In and M is preferably mic%, In is preferably 50 atomic% of In.
Or less, M is 50 atomic% or more, and more preferably, In is less than 25 atomic% and M is 75 atomic% or more.

In addition, the oxide semiconductor film 18 and the oxide film 19 are In-M-Zn oxide films (M is Al,
In the case of Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), compared with the oxide semiconductor film 18, M (Al, Ti, Ga, Y, Zr, La, Ce, Nd,
Alternatively, the atomic ratio of Hf) is large and is typically 1.5 times or more, preferably 2 times or more, more preferably 3 times or more higher than the above atoms contained in the oxide semiconductor film 18. Number ratio.

In addition, the oxide semiconductor film 18 and the oxide film 19 are In-M-Zn oxide films (M is Al,
In the case of Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), the oxide film 19 is formed of In: M.
: Zn = x ₁ : y ₁ : z ₁ [atomic number ratio], the oxide semiconductor film 18 is changed to In: M: Zn = x ₂ :
y ₂ : z ₂ [atomic ratio], y ₁ / x ₁ is larger than y ₂ / x ₂ ,
y ₁ / x ₁ is 1.5 times or more than y ₂ / x ₂ . More preferably, y ₁ / x ₁ is y
₂ / _{x 2} increases more than twice, and more _preferably, y 1 / _{x 1} is three or more times greater than _y 2 / _{x 2.} At this time, it is preferable that y ₂ in the oxide semiconductor film be x ₂ or more because stable electrical characteristics can be imparted to a transistor including the oxide semiconductor film. However, y
If ₂ is greater than or equal to three times the x _2, the field-effect mobility of the transistor including the oxide semiconductor film is lowered, y ₂ is smaller than three times x ₂ preferred.

For example, an In—Ga—Zn oxide with an atomic ratio of In: Ga: Zn = 1: 1: 1 or 3: 1: 2 can be used as the oxide semiconductor film 18. Further, as the oxide film 19, I
n: Ga: Zn = Zn = 1: 3: 2, 1: 3: 4, 1: 6: 2, 1: 6: 4, 1: 6: 1
An In—Ga—Zn oxide with an atomic ratio of 0 or 1: 9: 6 can be used. Note that the atomic ratio of the oxide semiconductor film 18 and the oxide film 19 includes a variation of plus or minus 20% of the atomic ratio of the metal element contained in the sputtering target as an error.

As the oxide semiconductor film 18 and the oxide film 19, oxide semiconductor films with low carrier density are used. For example, the oxide semiconductor film 18 and the oxide film 19 have a carrier density of 1 × 10.
¹⁷ pieces / cm ³ or less, preferably 1 × 10 ¹⁵ pieces / cm ³ or less, more preferably 1 × 1
An oxide semiconductor film having 0 ¹³ pieces / cm ³ or less, more preferably 1 × 10 ¹¹ pieces / cm ³ or less is used.

Note that the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of the transistor. In addition, in order to obtain the required semiconductor characteristics of the transistor, the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the oxide semiconductor film 18 are appropriate. It is preferable.

The oxide film 19 is formed when the oxide insulating film 24 to be formed later is formed.
Also functions as a damage mitigating film.

The thickness of the oxide film 19 is 3 nm to 100 nm, preferably 3 nm to 50 nm.

Note that it is preferable to use an oxide semiconductor film with a low impurity concentration and a low density of defect states as the oxide semiconductor film 18 because a transistor having more excellent electric characteristics can be manufactured. Here, low impurity concentration and low density of defect states (small amount of oxygen vacancies) are called high purity intrinsic or substantially high purity intrinsic.

An oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic has few carrier generation sources, and thus may have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may have few electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative.

In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states.

Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely small off-state current, a channel width of 1 × 10 ⁶ μm, and a channel length L of 10 μm. When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, it is possible to obtain a characteristic that the off-current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ⁻¹³ A or less.

Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has a small variation in electrical characteristics and may be a highly reliable transistor. Note that the charge trapped in the trap level of the oxide semiconductor film takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film with a high trap state density may have unstable electrical characteristics. Examples of impurities include hydrogen, nitrogen, alkali metals, and alkaline earth metals.

Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to become water,
Oxygen vacancies are formed in the lattice from which oxygen is released (or the portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In some cases, a part of hydrogen is bonded to oxygen bonded to a metal atom, so that an electron serving as a carrier is generated. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on.

For this reason, it is preferable that the oxide semiconductor film 18 has hydrogen reduced as much as possible. Specifically, in the oxide semiconductor film 18, secondary ion mass spectrometry (SIMS: Secon) is used.
hydrogen concentration obtained by the (dary Ion Mass Spectrometry)
5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³
5 × 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁸ atoms / cm
³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, further preferably 1 × 1
0 ¹⁶ atoms / cm ³ or less.

If the oxide semiconductor film 18 contains silicon or carbon, which is one of Group 14 elements, the amount of oxygen vacancies in the oxide semiconductor film 18 increases and becomes n-type. Therefore, the concentration of silicon or carbon in the oxide semiconductor film 18 or the concentration of silicon or carbon in the vicinity of the interface between the oxide film 19 and the oxide semiconductor film 18 (concentration obtained by secondary ion mass spectrometry)
2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³
The following.

In the oxide semiconductor film 18, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. To. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film 18.

In addition, when nitrogen is contained in the oxide semiconductor film 18, electrons as carriers are generated, the carrier density is increased, and the oxide semiconductor film 18 is likely to be n-type. As a result, a transistor including an oxide semiconductor containing nitrogen is likely to be normally on. Therefore, it is preferable that nitrogen be reduced as much as possible in the oxide semiconductor film. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is preferably 5 × 10 ¹⁸ atoms / cm ³ or less. .

Further, the oxide semiconductor film 18 and the oxide film 19 may have a non-single crystal structure, for example. The non-single crystal structure is, for example, a CAAC-OS (C Axis Aligned Crys) described later.
talline oxide semiconductor), a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

The oxide semiconductor film 18 and the oxide film 19 may have an amorphous structure, for example. An oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystal component. Alternatively, an amorphous oxide film has, for example, a completely amorphous structure and does not have a crystal part.

Note that the oxide semiconductor film 18 and the oxide film 19 each include two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. A mixed film may be used. For example, the mixed film may include two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. For example, the mixed film has a stacked structure of two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. May have.

Here, the oxide film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23. Therefore, even if a trap level is formed between the oxide film 19 and the oxide insulating film 23 due to impurities and defects, there is a gap between the trap level and the oxide semiconductor film 18. As a result, electrons flowing through the oxide semiconductor film 18 are not easily captured by the trap level, the on-state current of the transistor can be increased, and field-effect mobility can be increased. In addition, when an electron is trapped at the trap level, the electron becomes a negative fixed charge. As a result, the threshold voltage of the transistor fluctuates. However, since there is a gap between the oxide semiconductor film 18 and the trap level, trapping of electrons at the trap level can be reduced, and variation in threshold voltage can be reduced.

In addition, since the oxide film 19 can shield impurities from the outside, the amount of impurities moving from the outside to the oxide semiconductor film 18 can be reduced. The oxide film 1
9 is difficult to form oxygen deficiency. Therefore, the impurity concentration and the amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced.

In the transistor 50 described in this embodiment, the oxide insulating film 23 is formed so as to be in contact with the multilayer film 20, and the oxide insulating film 24 is formed in contact with the oxide insulating film 23.

The oxide insulating film 23 is an oxide insulating film that transmits oxygen. Note that the oxide insulating film 23 also functions as a damage reducing film for the multilayer film 20 when the oxide insulating film 24 to be formed later is formed.

As the oxide insulating film 23, a silicon oxide film, a silicon oxynitride film, or the like having a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm can be used. Note that in this specification, a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen as a composition, and a silicon nitride oxide film includes a nitrogen content as compared to oxygen as a composition. Refers to membranes with a lot of

The oxide insulating film 23 preferably has a small amount of defects. Typically, the ESR measurement indicates that the spin density of a signal appearing at g = 2.001 derived from dangling bonds in silicon is 3 × 10 ^17. It is preferable that the spins / cm ³ or less. This is because when the defect density included in the oxide insulating film 23 is large, oxygen is bonded to the defect, and the oxide insulating film 2
This is because the permeation amount of oxygen in 3 is reduced.

Further, it is preferable that the amount of defects at the interface between the oxide insulating film 23 and the multilayer film 20 is small. Typically, the spin of a signal appearing at g = 1.93 derived from the defects of the multilayer film 20 is determined by ESR measurement. It is preferable that the density is 1 × 10 ¹⁷ spins / cm ³ or less, and more preferably the detection lower limit or less.

Note that in the oxide insulating film 23, all of the oxygen that has entered the oxide insulating film 23 from the outside does not move to the outside of the oxide insulating film 23, and some oxygen remains in the oxide insulating film 23. In addition, oxygen enters the oxide insulating film 23 and oxygen contained in the oxide insulating film 23 converts the oxide insulating film 23 into oxygen.
In some cases, oxygen moves in the oxide insulating film 23 by moving to the outside.

When an oxide insulating film that transmits oxygen is formed as the oxide insulating film 23, the oxide insulating film 23
Oxygen released from the oxide insulating film 24 provided above can be moved to the oxide semiconductor film 18 through the oxide insulating film 23.

An oxide insulating film 24 is formed so as to be in contact with the oxide insulating film 23. Oxide insulating film 2
4 is formed using an oxide insulating film containing oxygen in excess of the stoichiometric composition. Part of oxygen is released by heating from the oxide insulating film containing oxygen in excess of that in the stoichiometric composition. An oxide insulating film containing oxygen in excess of the stoichiometric composition has an oxygen desorption amount of 1.0 × 10 ¹⁸ atoms in terms of oxygen atoms in TDS analysis.
/ Cm ³ or higher, preferably 3.0 × 10 ²⁰ atoms / cm ³ or higher.

The oxide insulating film 24 has a thickness of 30 nm to 500 nm, preferably 50 nm.
A silicon oxide film, a silicon oxynitride film, or the like with a thickness of 400 nm or less can be used.

The oxide insulating film 24 preferably has a small amount of defects. Typically, the ESR measurement indicates that the spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is 1.5 ×. Less than 10 ¹⁸ spins / cm ^{3 or even} 1 × 10 ¹⁸ spins / cm
It is preferable that it is ³ or less. Note that the oxide insulating film 24 is farther from the multilayer film 20 than the oxide insulating film 23, and thus may have a higher defect density than the oxide insulating film 23.

  Hereinafter, details of another configuration of the transistor 50 will be described.

Although there is no big restriction | limiting in the material etc. of the board | substrate 11, it is necessary to have the heat resistance of the grade which can endure at least heat processing after that. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 11. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SO
An I substrate or the like can also be applied, and a substrate in which a semiconductor element is provided over these substrates may be used as the substrate 11. When a glass substrate is used as the substrate 11, the sixth
Generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm), 8th
Generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm), 1st
A large display device can be manufactured by using a large-area substrate of generation 0 (2950 mm × 3400 mm) or the like.

Alternatively, a flexible substrate may be used as the substrate 11, and the transistor 50 may be formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 11 and the transistor 50. The separation layer can be used to separate the semiconductor device from the substrate 11 and transfer it to another substrate after part or all of the semiconductor device is completed thereon. At that time, the transistor 50 can be transferred to a substrate having poor heat resistance or a flexible substrate.

The gate electrode 15 is formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy including the above-described metal element, or an alloy combining the above-described metal elements. can do. Alternatively, a metal element selected from one or more of manganese and zirconium may be used. Further, the gate electrode 15 may have a single layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a titanium nitride film Layer structure, two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film,
There are a titanium film and a three-layer structure in which an aluminum film is laminated on the titanium film and a titanium film is further formed thereon. Alternatively, an alloy film or a nitride film in which aluminum is combined with one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

The gate electrode 15 includes indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Also,
A stacked structure of the light-transmitting conductive material and the metal element can also be used.

Further, an In—Ga—Zn-based oxynitride film, an In—Sn-based oxynitride film, an In—Ga-based oxynitride film, an In—Zn-based oxynitride film is provided between the gate electrode 15 and the gate insulating film 17. Material film,
An Sn-based oxynitride film, an In-based oxynitride film, a metal nitride film (InN, ZnN, or the like) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and have a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of a transistor using the oxide semiconductor is shifted to plus. Thus, a switching element having a so-called normally-off characteristic can be realized. For example, in the case of using an In—Ga—Zn-based oxynitride film, an In—Ga—Zn-based oxynitride film having a nitrogen concentration higher than that of the oxide semiconductor film 18, specifically, 7 atomic% or more is used.

For the gate insulating film 17, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn metal oxide, silicon nitride, or the like may be used. Provided.

Further, as the gate insulating film 17, hafnium silicate (HfSiO _x ), hafnium silicate added with nitrogen (HfSi _x O _y N _z ), hafnium aluminate added with nitrogen (HfAl _x O _y N _z ), hafnium oxide High-, such as yttrium oxide
The gate leakage of the transistor can be reduced by using the k material.

The thickness of the gate insulating film 17 may be 5 nm to 400 nm, more preferably 10 nm to 300 nm, and more preferably 50 nm to 250 nm.

The pair of electrodes 21 and 22 is a single layer of a single metal made of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component, as a conductive material. Used as a structure or a laminated structure. For example, a single layer structure of an aluminum film containing silicon, a two layer structure in which a titanium film is stacked on an aluminum film, a two layer structure in which a titanium film is stacked on a tungsten film, copper-magnesium-
A two-layer structure in which a copper film is laminated on an aluminum alloy film, a titanium film or a titanium nitride film, an aluminum film or a copper film laminated on the titanium film or the titanium nitride film, and a titanium film or a nitridation thereon A three-layer structure for forming a titanium film, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film stacked on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon. There are three-layer structures. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

Further, by providing a nitride insulating film 25 having a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like on the oxide insulating film 24, diffusion of oxygen from the multilayer film 20 to the outside. Intrusion of hydrogen, water, etc. into the multilayer film 20 from the outside can be prevented. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film having a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. Examples of the oxide insulating film having a blocking effect of oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

  Next, a method for manufacturing the transistor 50 illustrated in FIGS. 1A to 1C is described with reference to FIGS.

As shown in FIG. 2A, the gate electrode 15 is formed over the substrate 11, and the gate insulating film 17 is formed over the gate electrode 15.

  Here, a glass substrate is used as the substrate 11.

A method for forming the gate electrode 15 will be described below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like, and a mask is formed over the conductive film by a photolithography process. Next, part of the conductive film is etched using the mask to form the gate electrode 15. Thereafter, the mask is removed.

Note that the gate electrode 15 may be formed by an electrolytic plating method, a printing method, an ink jet method or the like instead of the above forming method.

Here, a tungsten film with a thickness of 100 nm is formed by a sputtering method. Next, a mask is formed by a photolithography process, and the tungsten film is dry-etched using the mask to form the gate electrode 15.

  The gate insulating film 17 is formed by a sputtering method, a CVD method, a vapor deposition method, or the like.

In the case of forming a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film as the gate insulating film 17, it is preferable to use a deposition gas and an oxidation gas containing silicon as a source gas. Typical examples of the deposition gas containing silicon include silane, disilane,
Examples include trisilane and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

When a gallium oxide film is formed as the gate insulating film 17, MOCVD (Metal
(1 Organic Chemical Vapor Deposition) method.

Next, as illustrated in FIG. 2B, the oxide semiconductor film 18 and the oxide film 19 are formed over the gate insulating film 17.

A method for forming the oxide semiconductor film 18 and the oxide film 19 is described below. Over the gate insulating film 17, an oxide semiconductor film to be the oxide semiconductor film 18 and an oxide film to be the oxide film 19 are formed successively. Next, after a mask is formed over the oxide film by a photolithography step, the oxide semiconductor film and part of the oxide film are etched using the mask as illustrated in FIG. In addition, the gate electrode 15 is on the gate insulating film 17.
A multilayer film 20 including the oxide semiconductor film 18 and the oxide film 19 which are element-isolated so as to overlap with a part of the oxide film 19 is formed. Thereafter, the mask is removed.

The oxide semiconductor film to be the oxide semiconductor film 18 and the oxide film to be the oxide film 19 can be formed by a sputtering method, a coating method, a pulse laser deposition method, a laser ablation method, or the like.

In the case where the oxide semiconductor film and the oxide film are formed by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as appropriate as a power supply device for generating plasma.

As the sputtering gas, a rare gas (typically argon), an oxygen gas, a rare gas, and a mixed gas of oxygen are appropriately used. Note that in the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

The target may be selected as appropriate in accordance with the composition of the oxide semiconductor film and the oxide film to be formed.

The oxide semiconductor film 18 and the oxide film 19 are not simply laminated, but a continuous junction (here, a structure in which the energy at the lower end of the conduction band continuously changes between the films) is formed. Make as follows. That is, at the interface of each film, the oxide semiconductor film 18 has a stacked structure in which no defect level such as a trap center or a recombination center or an impurity that forms a barrier that hinders carrier flow exists. . Temporarily laminated oxide semiconductor film 1
If impurities are mixed between the oxide film 8 and the oxide film 19, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface and disappear.

In order to form a continuous bond, it is necessary to use a multi-chamber type film forming apparatus (sputtering apparatus) provided with a load lock chamber to continuously laminate each film without exposure to the atmosphere. Each chamber in the sputtering apparatus is subjected to high vacuum evacuation (1 × 10 ⁻⁷ Pa to 5 × 5) using an adsorption-type vacuum evacuation pump such as a cryopump in order to remove as much water as possible from the oxide semiconductor film. ^{X10 −4} Pa) is preferable. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that a gas, particularly a gas containing carbon or hydrogen, does not flow backward from the exhaust system into the chamber.

In order to obtain a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film, it is necessary not only to evacuate the chamber but also to increase the purity of the sputtering gas. The oxygen gas or argon gas used as the sputtering gas has a dew point of −40 ° C. or lower, preferably −80 ° C. or lower,
More preferably, moisture or the like is prevented from being taken into the oxide semiconductor film by using a gas highly purified to −100 ° C. or lower, more preferably −120 ° C. or lower.

Here, an In-Ga film with a thickness of 35 nm is formed as the oxide semiconductor film by a sputtering method.
After forming a Zn oxide film (In: Ga: Zn = 1: 1: 1), an In—Ga—Zn oxide film (In: Ga: Zn = 20 nm thick) was formed as an oxide film by a sputtering method. 1:
3: 2) is formed. Next, a mask is formed over the oxide film, and the oxide semiconductor film 18 and the oxide film 19 are selectively etched by partially etching the oxide semiconductor film and the oxide film.
Is formed.

After that, the first heat treatment is performed. By the first heat treatment, hydrogen, water, and the like contained in the oxide semiconductor film 18 can be eliminated, so that the hydrogen concentration and the water concentration in the oxide semiconductor film can be reduced. The temperature of the heat treatment is typically 300 ° C to 400 ° C, preferably 320 ° C to 370 ° C.

For the first heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

The first heat treatment is performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (such as argon or helium). Just do it. Note that it is preferable that hydrogen, water, and the like be not contained in the nitrogen, oxygen, ultra-dry air, or the rare gas. Further, after heat treatment in a nitrogen or rare gas atmosphere, the heat treatment may be performed in an oxygen or ultra-dry air atmosphere. As a result, hydrogen, water, and the like contained in the oxide semiconductor film can be eliminated and oxygen can be supplied into the oxide semiconductor film. As a result, the amount of oxygen vacancies contained in the oxide semiconductor film can be reduced.

  Next, as shown in FIG. 2C, a pair of electrodes 21 and 22 are formed.

A method for forming the pair of electrodes 21 and 22 will be described below. Introduction, sputtering, CVD
A conductive film is formed by a method, a vapor deposition method, or the like. Next, a mask is formed over the conductive film by a photolithography process. Next, the conductive film is etched using the mask to form a pair of electrodes 21, 2
2 is formed. Thereafter, the mask is removed.

Here, a 50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film are sequentially stacked by a sputtering method. Next, a mask is formed over the titanium film by a photolithography process, and the tungsten film, the aluminum film, and the titanium film are dry-etched using the mask to form the pair of electrodes 21 and 22.

Next, as illustrated in FIG. 2D, the oxide insulating film 23 is formed over the multilayer film 20 and the pair of electrodes 21 and 22. Next, the oxide insulating film 24 is formed over the oxide insulating film 23.

Note that after the oxide insulating film 23 is formed, the oxide insulating film 2 is continuously formed without being exposed to the atmosphere.
4 is preferably formed. After the oxide insulating film 23 is formed, the oxide insulating film 24 is continuously formed by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas without opening to the atmosphere. The impurity concentration derived from atmospheric components at the interface between the oxide insulating film 23 and the oxide insulating film 24 can be reduced, and oxygen contained in the oxide insulating film 24 can be moved to the oxide semiconductor film 18. In addition, the amount of oxygen vacancies in the oxide semiconductor film 18 can be reduced.

As the oxide insulating film 23, a substrate placed in a evacuated processing chamber of a plasma CVD apparatus is held at 180 ° C. or higher and 400 ° C. or lower, more preferably 200 ° C. or higher and 370 ° C. or lower. The pressure in the processing chamber is 20 Pa or more and 250 Pa or less,
More preferably, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film 23 under conditions where the pressure is 100 Pa to 250 Pa and high-frequency power is supplied to an electrode provided in the treatment chamber.

As a source gas for the oxide insulating film 23, a deposition gas containing silicon and an oxidation gas are preferably used. Typical examples of the deposition gas containing silicon include silane, disilane,
Examples include trisilane and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

By using the above conditions, an oxide insulating film that transmits oxygen can be formed as the oxide insulating film 23. In addition, by providing the oxide film 19 and the oxide insulating film 23, damage to the oxide semiconductor film 18 can be reduced in a step of forming the oxide insulating film 24 to be formed later.

Note that the oxide insulating film 23 is formed by using a substrate placed in a vacuum evacuated processing chamber of a plasma CVD apparatus at 180 ° C. to 400 ° C., preferably 300 ° C. to 400 ° C., more preferably 320 ° C. to 370 ° C. The silicon oxide film is formed as the oxide insulating film 23 under the condition that the source gas is introduced into the processing chamber and the pressure in the processing chamber is set to 100 Pa to 250 Pa and high frequency power is supplied to the electrode provided in the processing chamber. Alternatively, a silicon oxynitride film can be formed.

Under the film forming conditions, the bonding temperature between silicon and oxygen is increased by setting the substrate temperature to the above temperature. As a result, as the oxide insulating film 23, oxygen is permeated, dense, and hard oxide insulating film. Typically, an etching rate with respect to 0.5 wt% hydrofluoric acid at 25 ° C. is 10 nm / min or less. A silicon oxide film or a silicon oxynitride film which is preferably 8 nm / min or less can be formed.

Furthermore, since the water content in the oxide insulating film 23 is reduced by setting the pressure in the treatment chamber to 100 Pa or more and 250 Pa or less, variation in electric characteristics of the transistor 50 is reduced and the threshold voltage is reduced. Fluctuations can be suppressed. In addition, the processing chamber pressure is set to 1
When the oxide insulating film 23 is formed, the damage to the multilayer film 20 including the oxide semiconductor film 18 can be reduced when the oxide insulating film 23 is formed. It is possible to reduce the amount of oxygen deficiency. In particular, by increasing the deposition temperature of the oxide insulating film 23 or the oxide insulating film 24 to be formed later, typically a temperature higher than 220 ° C., one of oxygen contained in the oxide semiconductor film 18 is increased. The part is detached and oxygen vacancies are easily formed. In addition, in order to increase the reliability of the transistor, the use of film formation conditions for reducing the amount of defects in the oxide insulating film 24 to be formed later easily reduces the amount of released oxygen. As a result, it may be difficult to reduce oxygen vacancies in the oxide semiconductor film 18. However, the pressure in the treatment chamber is set to 100 Pa or more and 250 Pa or less, and the damage to the oxide semiconductor film 18 during the formation of the oxide insulating film 23 is reduced, so that even a small amount of oxygen desorption from the oxide insulating film 24 can be achieved. It is possible to reduce oxygen vacancies in the oxide semiconductor film 18.

In addition, by making the amount of oxidizing gas with respect to the deposition gas containing silicon 100 times or more,
The hydrogen content contained in the oxide insulating film 23 can be reduced. As a result, the amount of hydrogen mixed into the oxide semiconductor film 18 can be reduced, so that a negative shift in the threshold voltage of the transistor can be suppressed.

Here, as the oxide insulating film 23, silane with a flow rate of 30 sccm and a flow rate of 4000 sc are used.
By plasma CVD using a source gas of cm 2 dinitrogen monoxide, a processing chamber pressure of 200 Pa, a substrate temperature of 220 ° C., and a high frequency power of 150 W using a high frequency power supply of 27.12 MHz supplied to parallel plate electrodes, A silicon oxynitride film with a thickness of 50 nm is formed. Under such conditions, a silicon oxynitride film through which oxygen passes can be formed.

As the oxide insulating film 24, a substrate placed in a evacuated processing chamber of a plasma CVD apparatus is held at 180 ° C. or higher and 280 ° C. or lower, more preferably 200 ° C. or higher and 240 ° C. or lower. The pressure in the processing chamber is set to 100 Pa to 250 Pa, more preferably 100 Pa to 200 Pa, and 0 is applied to the electrode provided in the processing chamber.
. 17W / cm ² or more 0.5 W / cm ² or less, more preferably under the conditions for supplying high-frequency power of 0.25 W / cm ² or more 0.35 W / cm ² or less, a silicon oxide film or a silicon oxynitride film .

As a source gas for the oxide insulating film 24, a deposition gas and an oxidation gas containing silicon are preferably used. Typical examples of the deposition gas containing silicon include silane, disilane,
Examples include trisilane and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

As the conditions for forming the oxide insulating film 24, by supplying high-frequency power with the above power density in the processing chamber at the above pressure, the decomposition efficiency of the source gas in plasma is increased, oxygen radicals are increased, and the source gas is oxidized. Therefore, the oxygen content in the oxide insulating film 24 becomes higher than the stoichiometric composition. However, when the substrate temperature is the above temperature, since the bonding force between silicon and oxygen is weak, part of oxygen in the film is released by heat treatment in a later step. As a result,
An oxide insulating film which contains more oxygen than that in the stoichiometric composition and from which part of oxygen is released by heating can be formed. An oxide insulating film 23 is provided on the multilayer film 20. Therefore, the oxide insulating film 23 serves as a protective film for the multilayer film 20 in the step of forming the oxide insulating film 24. In addition, the oxide film 19 serves as a protective film for the oxide semiconductor film 18. As a result, the oxide insulating film 24 can be formed using high-frequency power with high power density while reducing damage to the oxide semiconductor film 18.

Note that the amount of defects in the oxide insulating film 24 can be reduced by increasing the flow rate of the deposition gas containing silicon with respect to the oxidizing gas under the deposition conditions of the oxide insulating film 24. Typically, g = 2.0 derived from silicon dangling bonds by ESR measurement.
The spin density of the signal appearing at 01 is less than 6 × 10 ¹⁷ spins / cm ³ , preferably 3 ×
An oxide insulating film with a small amount of defects which is 10 ¹⁷ spins / cm ³ or less, preferably 1.5 × 10 ¹⁷ spins / cm ³ or less can be formed. As a result, the reliability of the transistor can be improved.

Here, as the oxide insulating film 24, silane having a flow rate of 200 sccm and a flow rate of 4000 s are used.
ccm dinitrogen monoxide as source gas, processing chamber pressure 200Pa, substrate temperature 220 ° C
A silicon oxynitride film having a thickness of 400 nm is formed by plasma CVD using a 27.12 MHz high frequency power supply and supplying 1500 W high frequency power to the parallel plate electrodes. The plasma CVD apparatus is a parallel plate type plasma CVD having an electrode area of 6000 cm ^2.
0.25W when the supplied power is converted into power per unit area (power density)
/ Cm ² .

Next, heat treatment is performed. The temperature of the heat treatment is typically 300 ° C to 400 ° C, preferably 320 ° C to 370 ° C.

For the heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

Heat treatment is nitrogen, oxygen, ultra-dry air (water content is 20 ppm or less, preferably 1 p
pm or less, preferably 10 ppb or less air), or a rare gas (argon, helium, etc.)
It may be performed in the atmosphere. Note that it is preferable that hydrogen, water, and the like be not contained in the nitrogen, oxygen, ultra-dry air, or the rare gas.

Through the heat treatment, part of oxygen contained in the oxide insulating film 24 can be moved to the oxide semiconductor film 18, so that the amount of oxygen vacancies contained in the oxide semiconductor film 18 can be reduced.

In the case where the oxide insulating film 23 and the oxide insulating film 24 contain water, hydrogen, or the like, a nitride insulating film 25 having a function of blocking water, hydrogen, or the like is formed later, and heat treatment is performed. Water, hydrogen, and the like contained in the material insulating film 23 and the oxide insulating film 24 move to the oxide semiconductor film 18, and a defect is generated in the oxide semiconductor film 18. However, the heating can remove water, hydrogen, and the like contained in the oxide insulating film 23 and the oxide insulating film 24, reduce variation in electric characteristics of the transistor 50, and reduce the threshold voltage. Fluctuations can be suppressed.

Note that by forming the oxide insulating film 24 over the oxide insulating film 23 with heating, oxygen can be transferred to the oxide semiconductor film 18 and oxygen vacancies in the oxide semiconductor film 18 can be reduced. Since it is possible, it is not necessary to perform the heat treatment.

  Here, heat treatment is performed at 350 ° C. for one hour in a nitrogen and oxygen atmosphere.

Further, when the pair of electrodes 21 and 22 is formed, the multilayer film 20 is formed by etching the conductive film.
Is damaged, and the back channel of the multilayer film 20 (in the multilayer film 20, the gate electrode 15
Oxygen deficiency occurs on the side opposite the surface facing the surface. However, by applying an oxide insulating film containing more oxygen than the stoichiometric composition to the oxide insulating film 24, oxygen vacancies generated on the back channel side by heat treatment can be repaired. it can. Accordingly, defects included in the multilayer film 20 can be reduced, and the reliability of the transistor 50 can be improved.

  Next, the nitride insulating film 25 is formed by sputtering, CVD, or the like.

Note that when the nitride insulating film 25 is formed by a plasma CVD method, the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is set to 300 ° C. or higher and 400 ° C. or lower, more preferably 320 ° C. or higher and 370 ° C. or lower. It is preferable because a dense nitride insulating film can be formed.

When a silicon nitride film is formed as the nitride insulating film 25 by a plasma CVD method, it is preferable to use a deposition gas containing silicon, nitrogen, and ammonia as a source gas. By using a small amount of ammonia as a source gas compared to nitrogen, ammonia is dissociated in plasma and active species are generated. The active species breaks the bond between silicon and hydrogen contained in the deposition gas containing silicon and the triple bond of nitrogen. As a result, the bonding between silicon and nitrogen is promoted, the bonding between silicon and hydrogen is small, the number of defects is small, and a dense silicon nitride film can be formed. On the other hand, in the source gas, if the amount of ammonia relative to nitrogen is large, decomposition of the deposition gas containing silicon and nitrogen does not proceed, and silicon and hydrogen bonds remain, resulting in increased defects and coarse silicon nitride. A film is formed. For these reasons, in the source gas, the flow rate ratio of nitrogen to ammonia is preferably 5 or more and 50 or less, more preferably 10 or more and 50 or less.

Here, a silane with a flow rate of 50 sccm, a flow rate of 5000 is placed in a processing chamber of a plasma CVD apparatus.
The source gas is sccm nitrogen and 100 sccm ammonia, the processing chamber pressure is 100 Pa, the substrate temperature is 350 ° C., and a high frequency power source of 27.12 MHz is used.
A silicon nitride film having a thickness of 50 nm is formed by a plasma CVD method in which high frequency power of W is supplied to the parallel plate electrodes. In the plasma CVD apparatus is a plasma CVD apparatus of a parallel plate type electrode area is 6000 cm ^2, is converted to electric power supplied per unit area (power ^{density) 1.7 × 10 -1 W / cm} 2 It is.

Through the above steps, the protective film 26 including the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 can be formed.

Next, heat treatment may be performed. The temperature of the heat treatment is typically 300 ° C. or higher and 40 ° C.
0 ° C. or lower, preferably 320 ° C. or higher and 370 ° C. or lower.

  Through the above process, the transistor 50 can be manufactured.

In this embodiment, the first heat treatment and the second heat treatment are performed in the manufacturing process of the transistor; however, the transistor is included in the oxide semiconductor film by forming a multilayer film including the oxide semiconductor film. The impurity concentration can be reduced and carrier trapping at the defect level can be prevented. As a result, even when the temperature of each heat treatment is set to 400 ° C. or lower, a transistor having the same amount of variation in threshold voltage as a transistor heat treated at a high temperature can be manufactured. As a result, the cost of the semiconductor device can be reduced.

In addition, by forming an oxide insulating film containing oxygen in excess of the stoichiometric composition so as to overlap with the oxide semiconductor film functioning as a channel region, oxygen in the oxide insulating film is oxidized It can be moved to a physical semiconductor film. As a result, the content of oxygen vacancies contained in the oxide semiconductor film can be reduced.

In particular, by forming an oxide insulating film that transmits oxygen between an oxide semiconductor film that functions as channel formation and an oxide insulating film that contains more oxygen than the stoichiometric composition, In forming an oxide insulating film containing more oxygen than that in the stoichiometric composition,
Damage to the oxide semiconductor film can be suppressed. As a result, the amount of oxygen vacancies contained in the oxide semiconductor film can be reduced.

Then, when an oxide insulating film containing more oxygen than that in the stoichiometric composition is formed by forming an oxide film over the oxide semiconductor film, the oxide semiconductor film is damaged. Entering can be further suppressed. In addition, by forming the oxide film, an insulating film formed over the oxide semiconductor film, for example, a constituent element of the oxide insulating film can be prevented from being mixed into the oxide semiconductor film.

As described above, a semiconductor device in which the amount of defects is reduced in a semiconductor device including an oxide semiconductor film can be obtained. In addition, a semiconductor device with improved electrical characteristics can be obtained in a semiconductor device including an oxide semiconductor film.

<Band structure of transistor>
Next, the band structure of the multilayer film 20 will be described with reference to FIG.

Here, as an example, an In—Ga—Zn oxide with an energy gap of 3.15 eV is used as the oxide semiconductor film 18, and an energy gap of 3.5 e is used as the oxide film 19.
An In—Ga—Zn oxide which is V is used. The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300).

The energy difference (also referred to as ionization potential) between the vacuum level and the valence band top of the oxide semiconductor film 18 and the oxide film 19 is 8 eV and 8.2 eV, respectively. Note that the energy difference between the vacuum level and the top of the valence band is measured by ultraviolet photoelectron spectroscopy (UPS: Ultravio).
let Photoelectron Spectroscopy (PHI V)
ersaProbe).

Therefore, the energy difference (also referred to as electron affinity) between the vacuum level and the conduction band bottom of the oxide semiconductor film 18 and the oxide film 19 is 4.85 eV and 4.7 eV, respectively.

FIG. 3A schematically shows part of the band structure of the multilayer film 20. Here, a case where a silicon oxide film is provided in contact with the multilayer film 20 will be described. Note that EcI1 shown in FIG. 3A represents the energy at the lower end of the conduction band of the silicon oxide film, EcS1 represents the energy at the lower end of the conduction band of the oxide semiconductor film 18, and EcS2 represents the lower end of the conduction band of the oxide film 19. EcI2 represents the energy at the lower end of the conduction band of the silicon oxide film. EcI1
1 corresponds to the gate insulating film 17 in FIG. 1B, and EcI2 corresponds to the oxide insulating film 23 in FIG.

As shown in FIG. 3A, in the oxide semiconductor film 18 and the oxide film 19, the energy at the lower end of the conduction band changes gently without a barrier. In other words, it can be said that it changes continuously. This is because the multilayer film 20 includes an element common to the oxide semiconductor film 18, and a mixed layer is formed by oxygen moving between the oxide semiconductor film 18 and the oxide film 19. It can be said that there is.

3A, the oxide semiconductor film 18 of the multilayer film 20 becomes a well, and the multilayer film 2
It can be seen that the channel region is formed in the oxide semiconductor film 18 in the transistor using 0. In addition, since the energy at the lower end of the conduction band of the multilayer film 20 continuously changes,
It can be said that the oxide semiconductor film 18 and the oxide film 19 are continuously joined.

Note that as shown in FIG. 3A, a trap level due to impurities and defects can be formed in the vicinity of the interface between the oxide film 19 and the oxide insulating film 23. By being provided, the oxide semiconductor film 18 and the trap level can be separated from each other. However, when the energy difference between EcS1 and EcS2 is small, electrons in the oxide semiconductor film 18 may reach the trap level exceeding the energy difference. When electrons are trapped in the trap level, a negative charge is generated at the interface of the insulating film, resulting in a negative fixed charge, and the threshold voltage of the transistor is shifted in the positive direction. Therefore, it is preferable that the energy difference between EcS1 and EcS2 be 0.1 eV or more, preferably 0.15 eV or more, because fluctuations in threshold voltage of the transistor are reduced and stable electric characteristics are obtained.

FIG. 3B schematically shows a part of the band structure of the multilayer film 20 and is a modification of the band structure shown in FIG. Here, a case where a silicon oxide film is provided in contact with the multilayer film 20 will be described. Note that EcI1 shown in FIG. 3B represents the energy at the lower end of the conduction band of the silicon oxide film, EcS1 represents the energy at the lower end of the conduction band of the oxide semiconductor film 18, and E
cI2 represents the energy at the lower end of the conduction band of the silicon oxide film. In addition, EcI1 is shown in FIG.
) Corresponds to the gate insulating film 17, and EcI2 corresponds to the oxide insulating film 23 in FIG.

In the transistor shown in FIG. 1B, the multilayer film 20 is formed when the pair of electrodes 21 and 22 are formed.
In other words, the oxide film 19 may be etched. On the other hand, the oxide semiconductor film 1
8 may have a mixed layer of the oxide semiconductor film 18 and the oxide film 19 formed when the oxide film 19 is formed.

For example, the oxide semiconductor film 18 includes In: Ga: Zn = 1: 1: 1 [atomic ratio].
Ga—Zn oxide, or In: Ga: Zn = 3: 1: 2 [atomic ratio] In—Ga—Z
An oxide semiconductor film formed using an n-oxide as a sputtering target, and the oxide film 19 is In: Ga: Zn = 1: 3: 2 [atomic ratio] In—Ga—Zn oxide Or In: Ga: Zn = 1: 6: 4 [atomic ratio], an oxide film formed using an In—Ga—Zn oxide as a sputtering target is more than the oxide semiconductor film 18. Since the oxide film 19 has a high Ga content, a GaOx layer or a mixed layer containing more Ga than the oxide semiconductor film 18 can be formed on the top surface of the oxide semiconductor film 18.

Therefore, even when the oxide film 19 is etched, the energy at the lower end of the conduction band on the EcI2 side of EcS1 is increased, and the band structure shown in FIG. 3B may be obtained.

When the band structure shown in FIG. 3B is obtained, at the time of cross-sectional observation of the channel region,
In some cases, the multilayer film 20 is apparently observed only as the oxide semiconductor film 18. However, since a mixed layer containing more Ga than the oxide semiconductor film 18 is formed over the oxide semiconductor film 18, the mixed layer can be regarded as 1.5 layers. . In addition, the mixed layer, for example, when an element contained in the multilayer film 20 is measured by EDX analysis or the like,
This can be confirmed by analyzing the composition above the oxide semiconductor film 18. For example, it can be confirmed that the composition above the oxide semiconductor film 18 has a higher Ga content than the composition in the oxide semiconductor film 18.

<Modification 1, About base insulating film>
In the transistor 50 described in this embodiment, a base insulating film can be provided between the substrate 11 and the gate electrode 15 as needed. Examples of the material for the base insulating film include silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, and aluminum oxynitride. Note that by using silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, or the like as a material for the base insulating film, impurities, typically an alkali metal,
Diffusion of water, hydrogen, etc. into the multilayer film 20 can be suppressed.

  The base insulating film can be formed by a sputtering method, a CVD method, or the like.

<Modification 2, gate insulating film>
In the transistor 50 described in this embodiment, the gate insulating film 17 can have a stacked structure as necessary. Here, the structure of the gate insulating film 17 will be described with reference to FIG.

As shown in FIG. 5A, the gate insulating film 17 can have a stacked structure in which a nitride insulating film 17a and an oxide insulating film 17b are sequentially stacked from the gate electrode 15 side. By providing the nitride insulating film 17a on the gate electrode 15 side, impurities such as hydrogen, nitrogen, alkali metal, or alkaline earth metal from the gate electrode 15 are prevented from moving to the multilayer film 20. be able to.

Further, by providing the oxide insulating film 17b on the multilayer film 20 side, it is possible to reduce the density of defect states at the interface between the gate insulating film 17 and the multilayer film 20. As a result, a transistor with little deterioration in electrical characteristics can be obtained. Note that when the oxide insulating film 17b is formed using an oxide insulating film containing oxygen in excess of the stoichiometric composition like the oxide insulating film 24, the gate insulating film 17 and the multilayer film are formed. Since it is possible to further reduce the defect level density at the 20 interface, it is more preferable.

As shown in FIG. 5B, the gate insulating film 17 includes a nitride insulating film 17c with few defects,
A nitride insulating film 17d having a high hydrogen blocking property and an oxide insulating film 17b may be stacked in this order from the gate electrode 15 side. By providing the nitride insulating film 17c with few defects as the gate insulating film 17, the withstand voltage of the gate insulating film 17 can be improved. Further, by providing the nitride insulating film 17d with high hydrogen blocking property, it is possible to prevent hydrogen from the gate electrode 15 and the nitride insulating film 17c from moving to the multilayer film 20.

An example of a method for manufacturing the nitride insulating films 17c and 17d illustrated in FIG. First, a silicon nitride film with few defects is formed as the nitride insulating film 17c by a plasma CVD method using a mixed gas of silane, nitrogen, and ammonia as a source gas. Next, the source gas is switched to a mixed gas of silane and nitrogen, and a second silicon nitride film having a low hydrogen concentration and capable of blocking hydrogen is formed as the nitride insulating film 17d. By such a formation method, the gate insulating film 17 in which a nitride insulating film having few defects and having a hydrogen blocking property is stacked can be formed.

As shown in FIG. 5C, the gate insulating film 17 includes a nitride insulating film 17e with high impurity blocking properties, a nitride insulating film 17c with few defects, and a nitride insulating film 17d with high hydrogen blocking properties. The oxide insulating film 17b can be stacked in this order from the gate electrode 15 side. By providing the nitride insulating film 17e having a high impurity blocking property as the gate insulating film 17, impurities from the gate electrode 15, typically hydrogen, nitrogen,
Alkali metal or alkaline earth metal can be prevented from moving to the multilayer film 20.

An example of a method for manufacturing the nitride insulating films 17e, 17c, and 17d illustrated in FIG. First, a silicon nitride film having a high impurity blocking property is formed as the nitride insulating film 17e by a plasma CVD method using a mixed gas of silane, nitrogen, and ammonia as a source gas. Next, by increasing the flow rate of ammonia, a silicon nitride film with few defects is formed as the nitride insulating film 17c. Next, the source gas is switched to a mixed gas of silane and nitrogen, and a second silicon nitride film having a low hydrogen concentration and capable of blocking hydrogen is formed as the nitride insulating film 17d. By such a forming method, the gate insulating film 17 in which a nitride insulating film having few defects and having an impurity blocking property is stacked.
Can be formed.

<Modification 3, a pair of electrodes>
As the pair of electrodes 21 and 22 provided in the transistor 50 described in this embodiment, it is preferable to use a conductive material that easily bonds to oxygen, such as tungsten, titanium, aluminum, copper, molybdenum, chromium, or tantalum alone or an alloy. . As a result, the multilayer film 20
Oxygen and the conductive material contained in the pair of electrodes 21 and 22 are combined to form an oxygen deficient region in the multilayer film 20. In some cases, part of the constituent elements of the conductive material forming the pair of electrodes 21 and 22 is mixed in the multilayer film 20. As a result of these, as shown in FIG.
b is formed. The low resistance regions 20 a and 20 b are in contact with the pair of electrodes 21 and 22 and are formed between the gate insulating film 17 and the pair of electrodes 21 and 22. Since the low resistance regions 20a and 20b have high conductivity, the contact resistance between the multilayer film 20 and the pair of electrodes 21 and 22 can be reduced, and the on-state current of the transistor can be increased.

Alternatively, the pair of electrodes 21 and 22 may have a stacked structure of a conductive material that is easily bonded to oxygen and a conductive material that is not easily bonded to oxygen, such as titanium nitride, tantalum nitride, or ruthenium. With such a stacked structure, it is possible to prevent oxidation of the pair of electrodes 21 and 22 at the interface between the pair of electrodes 21 and 22 and the oxide insulating film 23. High resistance can be suppressed.

<Modification 4, Multilayer Film>
In the method for manufacturing the transistor 50 described in this embodiment, a compound generated by the reaction of the oxide semiconductor film 18 and / or a compound generated by the reaction of the oxide film 19 can be provided on the side surface of the multilayer film. Here, description will be made with reference to FIG. 7 which is an enlarged view of the vicinity of the multilayer film 20 of the transistor 50 in FIG.

For example, as illustrated in FIG. 7A, a compound 19 c generated by the reaction of the oxide film 19 can be provided on the back channel side of the multilayer film 20. Compound 19c includes a pair of electrodes 21
, 22 and TMAH (Tetramethylammonium Hydro
xide) The oxide film 19 can be formed by exposing it to an alkaline solution such as a solution, or an acidic solution such as phosphoric acid, nitric acid, hydrofluoric acid, hydrochloric acid, sulfuric acid, acetic acid, or oxalic acid.

Note that in this step, a part of the oxide film 19 is etched and reacts with the alkaline solution or the acidic solution to leave a reactant. In the case where the oxide film 19 is formed using In—Ga oxide or In—M—Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), Since In (indium oxide) contained in the oxide film 19 is preferentially removed, G is compared with In as compared with the oxide film 19.
Compound 19c having a high proportion of a or M is formed.

Compound 19c, which has a higher proportion of Ga or M than In, contains M, Al, Ti, and Ga.
, Y, Zr, La, Ce, Nd or Hf at a higher atomic ratio than In. For this reason,
Since impurities from the outside can be blocked, the amount of impurities moving from the outside to the oxide semiconductor film 18 can be reduced. As a result, a transistor with little variation in threshold voltage can be manufactured.

In addition, the etching residue between the pair of electrodes 21 and 22 can be removed by the treatment. As a result, it is possible to suppress the occurrence of a leak current flowing between the pair of electrodes 21 and 22.

Further, as shown in FIG. 7B, a compound 19d can be provided on the side surface of the multilayer film 20. When the compound 19d forms the multilayer film 20, TMAH (Tetramethyla
It can be formed by performing a wet etching process using an alkaline solution such as ammonium hydroxide) or an acidic solution such as phosphoric acid, nitric acid, hydrofluoric acid, hydrochloric acid, sulfuric acid, acetic acid, or oxalic acid. Alternatively, the compound 19d can be formed by performing a dry etching process using boron trichloride gas and chlorine gas as an etching gas. Alternatively, after forming the multilayer film 20, by exposing the oxide film 19 to the solution,
Compound 19d can be formed.

As in the compound 19c, the compound 19d has a higher ratio of Ga or M than In.
For this reason, since the compound 19d can shield impurities from the outside, the amount of impurities moving from the outside to the oxide semiconductor film 18 can be reduced. As a result, a transistor with little variation in threshold voltage can be manufactured.

<Modification 5, about multilayer film>
In the method for manufacturing the transistor 50 described in this embodiment, after the pair of electrodes 21 and 22 is formed, the multilayer film 20 is exposed to plasma generated in an oxygen atmosphere, and the oxide semiconductor film 18 and the oxide film 19 are exposed to oxygen. Can be supplied. Examples of the oxidizing atmosphere include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide. Further, in the plasma processing, the substrate 1
The multilayer film 20 is preferably exposed to plasma generated without applying a bias to one side. As a result, oxygen can be supplied without damaging the multilayer film 20, and the amount of oxygen vacancies contained in the multilayer film 20 can be reduced. In addition, impurities remaining on the surface of the multilayer film 20 such as halogen such as fluorine and chlorine can be removed by the etching process.

<Modification 6, protective film>
In the transistor 50 described in this embodiment, as illustrated in FIG.
A protective film 26a on which the oxide insulating film 24 and the nitride insulating film 25 are stacked can be provided. Since the transistor illustrated in FIG. 8 includes the oxide film 19 over the oxide semiconductor film 18, the oxide film 19 functions as a protective film when the oxide insulating film 24 is formed. As a result, when the oxide insulating film 24 is formed, the oxide semiconductor film 18 is not exposed to plasma, and plasma damage caused when the oxide insulating film 24 is formed by plasma CVD using relatively high power is reduced. it can.

Further, since oxygen contained in the oxide insulating film 24 can be directly transferred to the multilayer film 20, the amount of oxygen supplied to the oxide semiconductor film 18 can be increased. As a result, the amount of oxygen vacancies in the oxide semiconductor film 18 can be further reduced.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 2)
In this embodiment, a semiconductor device including a transistor that can further reduce the amount of defects in an oxide semiconductor film as compared with Embodiment 1 will be described with reference to drawings. The transistor described in this embodiment is different from that in Embodiment 1 in that an oxide film is provided between the gate insulating film and the oxide semiconductor film.

9A and 9B are a top view and a cross-sectional view of the transistor 60 included in the semiconductor device. FIG. 9 (A)
FIG. 9B is a top view of the transistor 60, FIG. 9B is a cross-sectional view taken along the dashed-dotted line AB in FIG. 9A, and FIG. 9C is the dashed-dotted line C in FIG. It is sectional drawing between -D. Note that FIG.
In (A), the substrate 11, some of the components of the transistor 60 (for example, the gate insulating film 17), the oxide insulating film 23, the oxide insulating film 24, the nitride insulating film 25, and the like are omitted for the sake of clarity. is doing.

A transistor 60 illustrated in FIG. 9 includes a gate electrode 15 provided over the substrate 11. In addition, a gate insulating film 17 formed on the substrate 11 and the gate electrode 15, and a gate insulating film 17
A multilayer film 34 overlapping the gate electrode 15 and a pair of electrodes 21 in contact with the multilayer film 34,
22. Further, the protective film 2 including the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 is formed on the gate insulating film 17, the multilayer film 34, and the pair of electrodes 21 and 22.
6 is formed.

In the transistor 60 described in this embodiment, the multilayer film 34 includes the oxide film 31, the oxide semiconductor film 32, and the oxide film 33. In addition, the oxide semiconductor film 32 functions as a channel region.

Further, the gate insulating film 17 and the oxide film 31 are in contact with each other. That is, the oxide film 31 is provided between the gate insulating film 17 and the oxide semiconductor film 18.

The multilayer film 34 and the oxide insulating film 23 are in contact with each other. In addition, the oxide insulating film 23 and the oxide insulating film 24 are in contact with each other. That is, the oxide film 33 is provided between the oxide semiconductor film 18 and the oxide insulating film 23.

For the oxide film 31 and the oxide film 33, a material and a formation method similar to those of the oxide film 19 described in Embodiment 1 can be used as appropriate.

The oxide film 31 is preferably smaller than the oxide semiconductor film 32. When the thickness of the oxide film 31 is 1 nm to 5 nm, preferably 1 nm to 3 nm, the amount of change in threshold voltage of the transistor can be reduced.

In addition, when the oxide films 31 and 33 are In-M-Zn oxides, the sum of In and M is 1
When the atomic ratio is set to 00 atomic%, the atomic ratio of In and M is preferably 50 at.
less than omic%, M is 50 atomic% or more, more preferably, In is 25 atom
It is assumed that it is less than ic% and M is 75 atomic% or more.

For the oxide semiconductor film 32, a material and a formation method similar to those of the oxide semiconductor film 18 described in Embodiment 1 can be used as appropriate.

Here, as the oxide film 31, an In—Ga film with a thickness of 30 nm is formed by a sputtering method.
A Zn oxide film (In: Ga: Zn = 1: 6: 4) is formed. In addition, the oxide semiconductor film 3
2, an In—Ga—Zn oxide film (In: Ga: Zn = 1: 1: 1) having a thickness of 10 nm is formed. As the oxide film 33, an In—Ga—Zn oxide film (In:
Ga: Zn = 1: 3: 2) is formed.

In the transistor described in this embodiment, the oxide insulating film 23 that transmits oxygen is formed on the back channel side of the multilayer film 34 (a surface opposite to the surface facing the gate electrode 15 in the multilayer film 34).
Thus, an oxide insulating film 24 containing more oxygen than the stoichiometric composition is provided. Therefore, oxygen contained in the oxide insulating film 24 containing more oxygen than that in the stoichiometric composition is moved to the oxide semiconductor film 32 included in the multilayer film 34, and the oxide semiconductor film 32 is moved to the oxide semiconductor film 32. The amount of oxygen deficiency contained can be reduced.

In addition, the multilayer film 34 is damaged by the etching for forming the pair of electrodes 21 and 22, and oxygen deficiency occurs on the back channel side of the multilayer film 34, but more oxygen than the stoichiometric composition is satisfied. The oxygen vacancies can be repaired by oxygen contained in the oxide insulating film 24 that is contained. Thereby, the reliability of the transistor 60 can be improved.

As described above, the stoichiometric amount of the multilayer film 34 including the oxide film 31, the oxide semiconductor film 32, and the oxide film 33 and the oxide insulating film 23 that transmits oxygen provided over the multilayer film 34 is reduced. By including the oxide insulating film 24 containing more oxygen than oxygen that satisfies the theoretical composition, oxygen vacancies in the multilayer film 34 can be reduced. An oxide film 31 is provided between the gate insulating film 17 and the oxide semiconductor film 32, and an oxide film 33 is provided between the oxide semiconductor film 32 and the oxide insulating film 23. Therefore, the concentration of silicon or carbon in the vicinity of the interface between the oxide film 31 and the oxide semiconductor film 32, the concentration of silicon or carbon in the oxide semiconductor film 32, or the oxide film 33 and the oxide semiconductor film 32 The concentration of silicon or carbon in the vicinity of the interface can be reduced. As a result, in the multilayer film 34, the absorption coefficient derived by the constant photocurrent measurement method is less than 1 × 10 ⁻³ / cm, preferably 1 × 10 ⁻⁴ / c.
The number of localized levels is very small.

Since the transistor 60 having such a structure has extremely few defects in the oxide semiconductor film 32, the transistor can have improved electrical characteristics. Typically, the transistor 60 has an increased on-state current and field-effect mobility. Improvement is possible. Further, the amount of variation in threshold voltage in the BT stress test and the optical BT stress test, which are examples of the stress test, is small, and the reliability is high.

(Embodiment 3)
In this embodiment, a semiconductor device including a transistor that can increase the on-state current of the transistor while further reducing the amount of defects in the oxide semiconductor film as compared with Embodiments 1 and 2 is described. Will be described with reference to FIG. The transistor described in this embodiment is different from that in Embodiment 1 in that an oxide film is provided between the pair of electrodes 21 and 22 and the oxide insulating film 23. Note that this embodiment mode is described using Embodiment Mode 1, but can be appropriately applied to Embodiment Mode 2.

10A and 10B are a top view and a cross-sectional view of the transistor 70 included in the semiconductor device. A top view of the transistor 70 is illustrated in FIG. 10A, a cross-sectional view taken along alternate long and short dash line A-B is shown in FIG. 10B, and a cross-sectional view taken along alternate long and short dash line CD is shown in FIG. Note that in FIG. 10A, for the sake of clarity, part of the components of the substrate 11, the transistor 70 (eg, the gate insulating film 17), the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film are illustrated. 25 etc. are omitted.

The transistor 70 is different from the transistor 50 in that the pair of electrodes 21 and 22 are surrounded by the oxide semiconductor film 18a and the oxide film 19a. Specifically, the transistor 70 includes an oxide semiconductor film 18 a provided over the gate insulating film 17 and the oxide semiconductor film 18.
a pair of electrodes 21 and 22 provided on a, an oxide semiconductor film 18a and a pair of electrodes 21,
22 and an oxide film 19a provided on the upper surface.

Since the pair of electrodes 21 and 22 are in contact with the oxide semiconductor film 18a, the transistor 70 has a lower contact resistance between the oxide semiconductor film 18a and the pair of electrodes 21 and 22 than the transistor 60. This is a transistor having an on-state current higher than that of 60.

Further, since the pair of electrodes 21 and 22 are in contact with the oxide semiconductor film 18a, the transistor 70 does not increase the contact resistance between the oxide semiconductor film 18a and the pair of electrodes 21 and 22, and thus the oxide film 19a can be thickened. By doing so, trap levels generated due to plasma damage or contamination of constituent elements of the protective film 26 when forming the protective film 26 are formed in the vicinity of the interface between the oxide semiconductor film 18a and the oxide film 19a. Can be suppressed.
That is, the transistor 65 can both improve the on-state current and reduce the amount of change in threshold voltage.

A method for manufacturing the transistor 70 will be described with reference to FIGS. First, similarly to FIG. 2A, the gate electrode 15 and the gate insulating film 17 are formed over the substrate 11 (see FIG. 11A).

Next, an oxide semiconductor film 28 to be the oxide semiconductor film 18a later is formed, and then a pair of electrodes 21 and 22 is formed. Next, an oxide film 29 to be an oxide film 19a later is formed (
Refer to FIG. ).

For the oxide semiconductor film 28, a material and a formation method similar to those of the oxide semiconductor film 18 described in Embodiment 1 can be used as appropriate. The pair of electrodes 21 and 22 can be formed in a manner similar to that shown in FIG. Note that the pair of electrodes 21 and 22 is formed over the oxide semiconductor film 28. For the oxide film 29, a material and a formation method similar to those of the oxide film 19 described in Embodiment 1 can be used as appropriate.

Next, a part of each of the oxide semiconductor film 28 and the oxide film 29 is etched at the same time to form the multilayer film 20 including the oxide semiconductor film 18a and the oxide film 19a (FIG. 11C
See). ). Note that the etching can be performed by using a mask after forming a mask over the oxide film to be the oxide film 29 by a photolithography process. In addition, since the oxide semiconductor film 28 and the oxide film 29 are etched at the same time, the oxide semiconductor film 18a
And the edge part of the oxide film 19a is substantially corresponded.

Next, a protective film 26 is formed so as to cover the gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 and 22. The protective film 26 can be formed in the same manner as in the first embodiment.
In the method for manufacturing the transistor 70, heat treatment can be performed with reference to Embodiment 1 as appropriate.

In addition, since the etching for forming the pair of electrodes 21 and 22 may cause defects such as oxygen vacancies in the oxide semiconductor film 18a and increase the carrier density, the oxidation may be performed before the oxide film 29 is formed. It is preferable to expose the oxide semiconductor film 18a to plasma generated in an oxygen atmosphere and supply oxygen to the oxide semiconductor film 18a. Thus, in the transistor 70, trap levels can be prevented from being formed in the vicinity of the interface between the oxide semiconductor film 18a and the oxide film 19a, and the amount of variation in threshold voltage can be reduced. it can. Alternatively, in the transistor 70, leakage current flowing in the vicinity of the side surface of the oxide semiconductor film 18a in the multilayer film 20 can be reduced, and increase in off-state current can be suppressed.

In addition, the multilayer film 20 is damaged by etching to form the pair of electrodes 21 and 22, and oxygen vacancies are generated on the back channel side of the multilayer film 20, but a part of oxygen contained in the oxide insulating film 24 is oxidized. The amount of oxygen vacancies contained in the oxide semiconductor film 18a can be reduced by moving the oxide semiconductor film 18a. Thereby, the reliability of the transistor 70 can be improved.

<Modification 1>
In the transistor 70 described in this embodiment, the multilayer film 20 and the pair of electrodes 21 and 22
The laminated structure can be changed as appropriate. For example, a transistor as shown in FIG. 12 can be used as a modification.

12 is different from the transistor 60 in that the oxide semiconductor film 18b and the oxide film 19b are formed in different steps. In other words, the end portion of the oxide semiconductor film 18b is covered with the pair of electrodes 21 and 22, and is different from the oxide semiconductor film 18b that does not contact the oxide film 19b.

12 has a low contact resistance between the multilayer film 20 and the pair of electrodes 21 and 22 because the pair of electrodes 21 and 22 and the oxide semiconductor film 18b are in direct contact with each other as compared with the transistor 50. This is a transistor having an on-state current higher than that of the transistor 50.

In the transistor illustrated in FIG. 12, the pair of electrodes 21 and 22 are in direct contact with the oxide semiconductor film 18 b, so that the oxidation resistance is not increased without increasing the contact resistance between the multilayer film 20 and the pair of electrodes 21 and 22. The material film 19b can be thickened. By doing so, trap levels generated due to plasma damage at the time of forming the protective film 26 or mixing of constituent elements of the protective film 26 are in the vicinity of the interface between the oxide semiconductor film 18b and the oxide film 19b. It can suppress forming. That is, both improvement in on-current and reduction in threshold voltage fluctuation can be achieved.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 4)
In this embodiment, a transistor having a structure different from those in Embodiments 1 to 3 will be described with reference to FIGS. The transistor 80 described in this embodiment includes a plurality of gate electrodes opposed to each other with an oxide semiconductor film interposed therebetween.

A transistor 80 illustrated in FIG. 13 includes a gate electrode 15 provided over the substrate 11.
In addition, the gate insulating film 17 formed on the substrate 11 and the gate electrode 15, and the gate insulating film 1
7, the multilayer film 20 overlapping the gate electrode 15, and a pair of electrodes 21 in contact with the multilayer film 20
, 22. Note that the multilayer film 20 includes an oxide semiconductor film 18 and an oxide film 19. A protective film 26 including an oxide insulating film 23, an oxide insulating film 24, and a nitride insulating film 25 is formed on the gate insulating film 17, the multilayer film 20, and the pair of electrodes 21 and 22. The In addition, a gate electrode 61 is provided so as to overlap the multilayer film 20 with the protective film 26 interposed therebetween.

The gate electrode 61 can be formed in a manner similar to that of the gate electrode 15 described in Embodiment 1.

In the transistor 70 described in this embodiment, the gate electrode 15 which is opposed to the multilayer film 20 is provided.
And a gate electrode 61. By applying different potentials to the gate electrode 15 and the gate electrode 61, the threshold voltage of the transistor 70 can be controlled.

In addition, with the multilayer film 20 including the oxide semiconductor film 18 in which the amount of oxygen vacancies is reduced, the electrical characteristics of the transistor can be improved. In addition, a transistor with less variation in threshold voltage and high reliability is obtained.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments and examples.

(Embodiment 5)
In this embodiment, a transistor having a structure different from those in Embodiments 1 to 4 will be described with reference to FIGS.

In this embodiment, as compared with Embodiments 1 to 4, a semiconductor device including a transistor that can further reduce the amount of defects in an oxide semiconductor film will be described with reference to drawings. In the transistor described in this embodiment, the back channel side of the multilayer film 20 is covered with a protective film as compared with Embodiments 1 to 4, and etching processing for forming a pair of electrodes is performed. The difference is that it is not exposed to the resulting plasma.

14A and 14B are a top view and a cross-sectional view of a transistor 90 included in a semiconductor device. FIG.
FIG. 14A is a top view of the transistor 90, and FIG. 14B is a dashed-dotted line A− in FIG.
FIG. 14C is a cross-sectional view taken along one-dot chain line CD in FIG. 14A. Note that in FIG. 14A, for the sake of clarity, part of the components of the substrate 11, the transistor 90 (eg, the gate insulating film 17), the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film are illustrated. 25 etc. are omitted.

A transistor 90 illustrated in FIG. 14 includes a gate electrode 15 provided over the substrate 11.
In addition, the gate insulating film 17 formed on the substrate 11 and the gate electrode 15, and the gate insulating film 1
7, a multilayer film 20 overlapping the gate electrode 15 is provided. Further, a protective film 26 formed of an oxide insulating film 23, an oxide insulating film 24, and a nitride insulating film 25 is formed on the gate insulating film 17 and the multilayer film 20, and the protective film is formed on the protective film 26. A pair of electrodes 21b and 22b connected to the multilayer film 20 are provided at the 26 openings.

  Next, a method for manufacturing the transistor 90 is described.

As in the first embodiment, the gate electrode 15 is formed over the substrate 11, and the gate insulating film 17 is formed over the substrate 11 and the gate electrode 15. Next, the multilayer film 20 is formed on the gate insulating film 17. After that, first heat treatment is performed to remove impurities contained in the oxide semiconductor film.

Next, as in Embodiment 1, the oxide insulating film 23 is formed over the gate insulating film 17 and the multilayer film 20.
Then, the oxide insulating film 24 and the nitride insulating film 25 are formed. Note that after the oxide insulating film 24 is formed, second heat treatment is performed to supply part of oxygen contained in the oxide insulating film 24 to the oxide semiconductor film 18.

Next, a part of each of the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 is etched to form an opening that exposes a part of the multilayer film 20. Thereafter, a pair of electrodes 21b and 22b in contact with the multilayer film 20 is formed in the same manner as in the first embodiment.

In the present embodiment, when the pair of electrodes 21b and 22b is etched, the multilayer film 20
Is covered with the protective film 26, the multilayer film 20, particularly the back channel region of the multilayer film 20, is not damaged by the etching for forming the pair of electrodes 21 b and 22 b. Further, the oxide insulating film 24 is formed using an oxide insulating film containing more oxygen than that in the stoichiometric composition. Therefore, part of oxygen contained in the oxide insulating film 24 is removed from the oxide semiconductor film 1.
8, the amount of oxygen vacancies contained in the oxide semiconductor film 18 can be reduced.

Through the above steps, defects included in the multilayer film 20 can be reduced, and the reliability of the transistor 90 can be improved.

(Embodiment 6)
In this embodiment, a transistor having a structure different from those in Embodiments 1 to 5 will be described with reference to FIGS.

In this embodiment, as compared with Embodiments 1 to 4, a semiconductor device including a transistor that can further reduce the amount of defects in an oxide semiconductor film will be described with reference to drawings. The transistor described in this embodiment includes a multilayer film 2 as in the fifth embodiment.
The difference between Embodiments 1 to 4 is that the back channel side of 0 is covered with a protective film and is not exposed to plasma generated by etching treatment for forming a pair of electrodes.

15A and 15B are a top view and a cross-sectional view of the transistor 100 included in the semiconductor device. FIG.
A transistor 100 shown in FIG. 5 is a channel protection type transistor. 15A is a top view of the transistor 100, FIG. 15B is a cross-sectional view taken along the dashed-dotted line A-B in FIG. 15A, and FIG. 15C is a cross-sectional view in FIG. It is sectional drawing between the dashed-dotted lines CD. Note that in FIG. 15A, some components of the substrate 11 and the transistor 100 (for clarity,
For example, the gate insulating film 17 is omitted.

A transistor 100 illustrated in FIG. 15 includes a gate electrode 15 provided over a substrate 11. In addition, a gate insulating film 17 formed over the substrate 11 and the gate electrode 15 and a multilayer film 20 overlapping the gate electrode 15 with the gate insulating film 17 interposed therebetween. Further, the gate insulating film 17
On the multilayer film 20, the oxide insulating film 23a, the oxide insulating film 24a, and the nitride insulating film 25 are provided.
a protective film 26a composed of a, a gate insulating film 17, a multilayer film 20, and a pair of electrodes 21c and 22bc formed on the protective film 26a.

  Next, a method for manufacturing the transistor 100 is described.

As in the first embodiment, the gate electrode 15 is formed over the substrate 11, and the gate insulating film 17 is formed over the substrate 11 and the gate electrode 15. Next, the multilayer film 20 is formed on the gate insulating film 17. After that, first heat treatment is performed to remove impurities contained in the oxide semiconductor film.

Next, as in Embodiment 1, the oxide insulating film 2 is formed on the gate insulating film 17 and the multilayer film 20.
3. An oxide insulating film 24 and a nitride insulating film 25 are formed. Note that after the oxide insulating film 24 is formed, second heat treatment is performed to supply part of oxygen contained in the oxide insulating film 24 to the oxide semiconductor film 18.

Next, the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25 are partially etched to form the oxide insulating film 23a, the oxide insulating film 24a, and the nitride insulating film 25a. A protective film 26a to be formed is formed.

Next, a pair of electrodes 21c and 22c in contact with the multilayer film 20 is formed in the same manner as in the first embodiment.

In the present embodiment, when the pair of electrodes 21c and 22c is etched, the multilayer film 20
Is covered with the protective film 26a, the multilayer film 20 is not damaged by the etching for forming the pair of electrodes 21c and 22c. Further, the oxide insulating film 24a is formed using an oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition. For this reason, part of oxygen contained in the oxide insulating film 24a is moved to the oxide semiconductor film 18 so that the oxide semiconductor film 1
8 can reduce the amount of oxygen deficiency included.

In FIG. 15, the nitride insulating film 25a is formed as the protective film 26c.
A stacked structure of the oxide insulating film 23a and the oxide insulating film 24a may be employed. In this case, it is preferable to form the nitride insulating film 25a after forming the pair of electrodes 21c and 22c. As a result, entry of hydrogen, water, etc. into the multilayer film 20 from the outside can be prevented.

Through the above steps, defects included in the multilayer film 20 can be reduced, and the reliability of the transistor 100 can be improved.

(Embodiment 7)
Various films such as a metal film, an oxide semiconductor film, and an inorganic insulating film disclosed in the above embodiments can be formed by a sputtering method or a plasma CVD (Chemical Vapor Deposition) method. You may form by CVD method. As an example of the thermal CVD method, MOCVD (Metal Organic Chemical Va)
por deposition) and ALD (Atomic Layer Deposi)
(ionion) method may be used.

The thermal CVD method has an advantage that no defect is generated due to plasma damage because it is a film forming method that does not use plasma.

In the thermal CVD method, film formation may be performed by sending a source gas and an oxidant into the chamber at the same time, making the inside of the chamber under atmospheric pressure or reduced pressure, reacting in the vicinity of the substrate or on the substrate and depositing on the substrate. .

Further, in the ALD method, film formation may be performed by setting the inside of the chamber to atmospheric pressure or reduced pressure, sequentially introducing source gases for reaction into the chamber, and repeating the order of introducing the gases. For example, each switching valve (also referred to as a high-speed valve) is switched to supply two or more types of source gases to the chamber in order, so that a plurality of types of source gases are not mixed with the first source gas at the same time or thereafter. Introduce an active gas (such as argon or nitrogen)
A second source gas is introduced. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced. Further, instead of introducing the inert gas, the second raw material gas may be introduced after the first raw material gas is exhausted by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first layer, reacts with a second source gas introduced later, and the second layer is stacked on the first layer. As a result, a thin film is formed. By repeating this gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible.
This is suitable for manufacturing a fine FET.

Thermal CVD methods such as MOCVD and ALD methods can form various films such as metal films, oxide semiconductor films, and inorganic insulating films disclosed in the embodiments described so far.
When an nGaZnO film is formed, trimethylindium, trimethylgallium, and dimethylzinc are used. Note that the chemical formula of trimethylindium is In (CH ₃ ) ₃ . The chemical formula of trimethylgallium is Ga (CH ₃ ) ₃ . The chemical formula of dimethylzinc is Zn (CH ₃ ) ₂ . Moreover, it is not limited to these combinations, Triethylgallium (chemical formula Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn (C ₂ H ₅ ) is used instead of dimethylzinc. ₂ ) can also be used.

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide solution, typically tetrakisdimethylamide hafnium (TDMAH)) is vaporized. Two kinds of gases, that is, a source gas and ozone (O3) as an oxidizing agent are used. Note that the chemical formula of tetrakisdimethylamide hafnium is Hf [N (CH ₃ ) ₂ ] ₄ . Other material liquids include tetrakis (ethylmethylamide) hafnium.

For example, in the case where an aluminum oxide film is formed by a film forming apparatus using ALD, a source gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA)) containing a solvent and an aluminum precursor compound, and H ₂ as an oxidizing agent. Two kinds of gases of O are used. Note that the chemical formula of trimethylaluminum is Al (CH ₃ ) ₃ . Other material liquids include Tris (
Dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2
2,6,6-tetramethyl-3,5-heptanedionate) and the like.

For example, in the case where a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the surface to be formed, chlorine contained in the adsorbate is removed, and an oxidizing gas (O
₂ , radicals of dinitrogen monoxide) are supplied to react with the adsorbate.

For example, when a tungsten film is formed by a film forming apparatus using ALD, WF ₆
Gas and B ₂ H ₆ gas are sequentially introduced repeatedly to form an initial tungsten film, and then WF
_A tungsten film is formed by introducing ₆ gases and H ₂ gas simultaneously. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, an oxide semiconductor film such as In—Ga—Zn— is formed by a film formation apparatus using ALD.
In the case of forming an O film, In (CH ₃ ) ₃ gas and O ₃ gas are repeatedly introduced in succession.
-O layer is formed, and then Ga (CH ₃ ) ₃ gas and O ₃ gas are simultaneously introduced to form a GaO layer, and then Zn (CH ₃ ) ₂ and O ₃ gas are simultaneously introduced to form a ZnO layer. Form.
Note that the order of these layers is not limited to this example. In addition, these gases are mixed to produce In—Ga—
A mixed compound layer such as an O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred. Further, In (C ₂ H ₅ ) ₃ gas may be used instead of In (CH ₃ ) ₃ gas. Instead of Ga (CH ₃ ) ₃ gas,
Ga (C ₂ H ₅ ) ₃ gas may be used. Also, instead of In (CH ₃ ) ₃ gas, In (
C ₂ H ₅ ) ₃ gas may be used. Alternatively, Zn (CH ₃ ) ₂ gas may be used.

(Embodiment 8)
In this embodiment, a semiconductor device which is one embodiment of the present invention will be described with reference to drawings. Note that in this embodiment, a semiconductor device which is one embodiment of the present invention is described using a display device as an example.

FIG. 16A illustrates an example of a semiconductor device. In the semiconductor device illustrated in FIG. 16A, the pixel portion 101, the scan line driver circuit 104, and the signal line driver circuit 106 are provided in parallel or substantially in parallel, and the potential is supplied by the scan line driver circuit 104. There are m scanning lines 107 to be controlled, and n signal lines 109, each of which is arranged in parallel or substantially in parallel and whose potential is controlled by the signal line driver circuit 106. Further, the pixel portion 101 includes a plurality of pixels 301 arranged in a matrix. In addition, along the scanning line 107, each has a capacitive line 115 arranged in parallel or substantially in parallel. Note that the capacitor lines 115 may be arranged in parallel or substantially in parallel along the signal lines 109. In some cases, the scanning line driver circuit 104 and the signal line driver circuit 106 are collectively referred to as a driver circuit portion.

Each scanning line 107 is electrically connected to n pixels 301 arranged in one of the pixels 301 arranged in m rows and n columns in the pixel portion 101. In addition, each signal line 109
Are m pixels 30 arranged in any column among the pixels 301 arranged in m rows and n columns.
1 is electrically connected. m and n are both integers of 1 or more. In addition, each capacitance line 115
Are the n pixels 30 arranged in any row among the pixels 301 arranged in m rows and n columns.
1 is electrically connected. When the capacitor lines 115 are arranged in parallel or substantially in parallel along the signal line 109, the capacitor lines 115 are arranged in any column among the pixels 301 arranged in m rows and n columns. The m pixels 301 are electrically connected.

FIGS. 16B and 16C illustrate circuit structures that can be used for the pixel 301 of the display device illustrated in FIG.

A pixel 301 illustrated in FIG. 16B includes a liquid crystal element 132, a transistor 131_1, and a capacitor 133_1.

One potential of the pair of electrodes of the liquid crystal element 132 is appropriately set according to the specification of the pixel 301. The alignment state of the liquid crystal element 132 is set according to written data. Note that a common potential may be applied to one of the pair of electrodes of the liquid crystal element 132 included in each of the plurality of pixels 301. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 132 for each pixel 301 in each row.

For example, as a method for driving a display device including the liquid crystal element 132, TN mode, STN mode, VA mode, ASM (Axial Symmetric Aligned M)
micro-cell) mode, OCB (Optically Compensated)
Birefringence mode, FLC (Ferroelectric Liquid)
id Crystal) mode, AFLC (Antiferroelectric Li)
(quid Crystal) mode, MVA mode, PVA (Patterned Ve)
ritual alignment) mode, IPS mode, FFS mode, or TB
An A (Transverse Bend Alignment) mode or the like may be used. Further, as a driving method of the display device, in addition to the driving method described above, ECB (Electri)
cally controlled birefringence) mode, PDLC (
(Polymer Dispersed Liquid Crystal) mode, PNL
C (Polymer Network Liquid Crystal) mode, guest host mode, and the like. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

In addition, a liquid crystal element may be formed using a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent. A liquid crystal exhibiting a blue phase has a response speed as short as 1 msec or less and is optically isotropic. Therefore, alignment treatment is unnecessary and viewing angle dependency is small.

In the pixel 301 in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor 131_1 is electrically connected to the signal line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 132. . The gate electrode of the transistor 131_1 is connected to the scan line G.
It is electrically connected to L_m. The transistor 131_1 has a function of controlling data writing of the data signal by being turned on or off.

One of the pair of electrodes of the capacitor 133_1 is a wiring to which a potential is supplied (hereinafter referred to as a capacitor line CL).
And the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 132. Note that the value of the potential of the capacitor line CL is set as appropriate in accordance with the specifications of the pixel 301. The capacitor 133_1 functions as a storage capacitor for storing written data.

For example, in the display device including the pixel 301 in FIG. 16B, the pixel 301 in each row is sequentially selected by the scan line driver circuit 104, the transistor 131_1 is turned on, and data signal data is written.

The pixel 301 into which data is written is in a holding state when the transistor 131_1 is turned off. By sequentially performing this for each row, an image can be displayed.

In addition, the pixel 301 illustrated in FIG. 16C includes a transistor 131_2 and a capacitor 133.
_2, a transistor 134, and a light-emitting element 135.

One of a source electrode and a drain electrode of the transistor 131_2 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n). Further, the gate electrode of the transistor 131_2 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).

The transistor 131_2 has a function of controlling data writing of the data signal by being turned on or off.

One of the pair of electrodes of the capacitor 133_2 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 131_2. Is done.

The capacitor 133_2 functions as a storage capacitor for storing written data.

One of a source electrode and a drain electrode of the transistor 134 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 134 is connected to the transistor 131_
It is electrically connected to the other of the two source and drain electrodes.

One of an anode and a cathode of the light-emitting element 135 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 134.

As the light-emitting element 135, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 135 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

Note that one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.

In the display device including the pixel 301 in FIG. 16C, the pixel 301 in each row is sequentially selected by the scan line driver circuit 104, the transistor 131_2 is turned on, and data signal data is written.

The pixel 301 into which data is written is in a holding state when the transistor 131_2 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 134 is controlled in accordance with the potential of the written data signal, and the light emitting element 135 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.

Note that in this specification and the like, a display element, a display device that includes a display element, a light-emitting element, and a light-emitting device that includes a light-emitting element have various modes or have various elements. I can do it. As an example of a display element, a display device, a light emitting element, or a light emitting device, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED) , Blue LED
Etc.), transistor (transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, grating light valve (GLV), plasma display (PDP), MEMS (micro electro mechanical system) ), Digital micromirror device (DMD), DMS (digital micro shutter), M
IRASOL (registered trademark), IMOD (interference modulation) element, piezoelectric ceramic display, carbon nanotube, etc.
Some have a display medium in which contrast, luminance, reflectance, transmittance, and the like change. EL
An example of a display device using an element is an EL display. As an example of a display device using an electron-emitting device, a field emission display (FED) or S
ED type flat display (SED: Surface-conduction Ele
ctron-emitter display). As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink or an electrophoretic element is electronic paper.

As an example of an EL element, there is an element having an anode, a cathode, and an EL layer sandwiched between the anode and the cathode. As an example of the EL layer, one using light emission (fluorescence) from a singlet exciton, one using light emission from a triplet exciton (phosphorescence), light emission from a singlet exciton (
Including those using fluorescence) and those using triplet excitons (phosphorescence),
Includes organic materials, inorganic materials, organic and inorganic materials, high molecular materials, low molecular materials Or a material including a high-molecular material and a low-molecular material. However, the present invention is not limited to this, and various EL elements can be used.

As an example of a liquid crystal element, there is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal. The element can be structured by a pair of electrodes and a liquid crystal layer. Note that the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Specifically, examples of liquid crystal elements include nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, and polymer dispersed liquid crystal (
PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain type liquid crystal, side chain type polymer liquid crystal, banana type liquid crystal and the like.

Next, a specific example of a liquid crystal display device using a liquid crystal element for the pixel 301 will be described.
Here, a top view of the pixel 301 illustrated in FIG. 16B is illustrated in FIG. In FIG. 17, the counter electrode and the liquid crystal element are omitted.

In FIG. 17, a conductive film 304c functioning as a scanning line is in a direction substantially orthogonal to the signal line (
It is extended and provided in the left-right direction in the figure. The conductive film 310d functioning as a signal line is provided to extend in a direction substantially perpendicular to the scanning line (vertical direction in the figure). The conductive film 310f functioning as a capacitor line is provided so as to extend in a direction parallel to the signal line. Note that the conductive film 304c functioning as a scan line is electrically connected to the scan line driver circuit 104 (see FIG. 16A) and functions as a conductive film 310d functioning as a signal line and a capacitor line. The conductive film 310f is electrically connected to the signal line driver circuit 106 (see FIG. 16A).

The transistor 103 is provided in a region where the scan line and the signal line intersect. The transistor 103 includes a conductive film 304c functioning as a gate electrode, a gate insulating film (not shown in FIG. 17), a multilayer film 308b in which a channel region formed over the gate insulating film is formed, and a source electrode and a drain electrode The conductive films 310d and 310e function. Note that the conductive film 304 c also functions as a scan line, and a region overlapping with the multilayer film 308 b functions as a gate electrode of the transistor 103. The conductive film 310d also functions as a signal line, and a region overlapping with the multilayer film 308b functions as a source electrode or a drain electrode of the transistor 103. In FIG. 17, the scanning line has an end portion located outside the end portion of the multilayer film 308 b in the upper surface shape. Therefore, the scanning line functions as a light shielding film that blocks light from a light source such as a backlight. As a result, the multilayer film 308b included in the transistor is not irradiated with light, and variation in electrical characteristics of the transistor can be suppressed.

The conductive film 310e is electrically connected to the light-transmitting conductive film 316b functioning as a pixel electrode in the opening 362c.

The capacitor 105 is connected to the conductive film 310 f functioning as a capacitor line in the opening 362. The capacitor 105 includes a light-transmitting conductive film 308 c formed over the gate insulating film, a dielectric film formed with a nitride insulating film provided over the transistor 103, and a light-transmitting film functioning as a pixel electrode. A conductive film 316c having optical properties. That is, the capacitor 105 has a light-transmitting property.

Thus, since the capacitor 105 has a light-transmitting property, the capacitor 105 can be formed large (in a large area) in the pixel 301. Therefore, while increasing the aperture ratio, it is possible to obtain 50% or more, preferably 55% or more, preferably 60% or more, and obtain a semiconductor device having an increased charge capacity. For example, in a semiconductor device with high resolution, for example, a liquid crystal display device, the area of a pixel is reduced and the area of a capacitor element is also reduced. For this reason, in a semiconductor device with high resolution, the charge capacity stored in the capacitor element is reduced. However, since the capacitor 105 described in this embodiment has a light-transmitting property, the aperture ratio can be increased while obtaining a sufficient charge capacity in each pixel by providing the capacitor in the pixel. Typically, it can be suitably used for a high-resolution semiconductor device having a pixel density of 200 ppi or more, further 300 ppi or more.

In addition, the pixel 301 illustrated in FIGS. 17A and 17B has a shape in which a side parallel to the conductive film 304c functioning as a scanning line is longer than a side parallel to the conductive film 310d functioning as a signal line and a capacitor line. A conductive film 310f that functions is provided so as to extend in a direction parallel to the conductive film 310d that functions as a signal line. As a result, the area of the conductive film 310f occupying the pixel 301 can be reduced, so that the aperture ratio can be increased. Further, since the conductive film 310f functioning as a capacitor line is in direct contact with the conductive film 308c having a light-transmitting property without using a connection electrode, the aperture ratio can be further increased.

Further, according to one embodiment of the present invention, since the aperture ratio can be increased even in a high-resolution display device, light from a light source such as a backlight can be efficiently used, and power consumption of the display device can be reduced. be able to.

18 is a cross-sectional view taken along the alternate long and short dash line CD in FIG. Note that in FIG. 18, a cross-sectional view of a driver circuit portion (a top view is omitted) including the scan line driver circuit 104 and the signal line driver circuit 106 is shown in AB. In this embodiment mode, a vertical electric field liquid crystal display device will be described.

In the liquid crystal display device described in this embodiment, a liquid crystal element 322 is sandwiched between a pair of substrates (a substrate 302 and a substrate 342).

The liquid crystal element 322 includes a light-transmitting conductive film 316b above the substrate 302, films for controlling alignment (hereinafter referred to as alignment films 318 and 352), a liquid crystal layer 320, a conductive film 350,
Have Note that the light-transmitting conductive film 316 b functions as one electrode of the liquid crystal element 322 and the conductive film 350 functions as the other electrode of the liquid crystal element 322.

Thus, a liquid crystal display device refers to a device having a liquid crystal element. Note that the liquid crystal display device includes a driving circuit and the like for driving a plurality of pixels. The liquid crystal display device includes a control circuit, a power supply circuit, a signal generation circuit, a backlight module, and the like disposed on another substrate,
Sometimes called a liquid crystal module.

In the driver circuit portion, a conductive film 304a functioning as a gate electrode, an insulating film 305 and an insulating film 306 functioning as a gate insulating film, a multilayer film 308a in which a channel region is formed, a conductive film 310a functioning as a source electrode and a drain electrode, The transistor 102 is configured by 310b. The multilayer film 308a is provided on the gate insulating film.

In the pixel portion, a conductive film 304c functioning as a gate electrode, an insulating film 305 and an insulating film 306 functioning as a gate insulating film, a multilayer film 308b in which a channel region formed over the gate insulating film is formed, a source electrode and a drain electrode Conductive films 310d and 31 that function as
The transistor 103 is configured by 0e. The multilayer film 308b is provided over the gate insulating film. An insulating film 312 and an insulating film 314 are provided as protective films over the conductive films 310d and 310e.

A light-transmitting conductive film 316b functioning as a pixel electrode is connected to the conductive film 310e in an opening provided in the insulating film 312 and the insulating film 314.

Further, the capacitor 105 is formed using the light-transmitting conductive film 308 c functioning as one electrode, the insulating film 314 functioning as a dielectric film, and the light-transmitting conductive film 316 b functioning as the other electrode. The light-transmitting conductive film 308c is provided over the gate insulating film.

In the driver circuit portion, the conductive film 30 formed simultaneously with the conductive films 304a and 304c.
4b and the conductive film 31 formed simultaneously with the conductive films 310a, 310b, 310d, and 310e.
0c means a light-transmitting conductive film 31 formed at the same time as the light-transmitting conductive film 316b.
6a is connected.

The conductive film 304b and the light-transmitting conductive film 316a include the insulating film 306 and the insulating film 312.
The connection is made at the opening provided in. The conductive film 310c and the light-transmitting conductive film 3
16 a is connected in an opening provided in the insulating film 312 and the insulating film 314.

  Here, components of the display device shown in FIG. 18 will be described below.

On the substrate 302, conductive films 304a, 304b, and 304c are formed. Conductive film 3
04a has a function as a gate electrode of a transistor in the driver circuit portion. The conductive film 304c is formed in the pixel portion 101 and functions as a gate electrode of a transistor in the pixel portion. The conductive film 304b is formed in the scan line driver circuit 104 and connected to the conductive film 310c.

  As the substrate 302, the material of the substrate 11 described in Embodiment 1 can be used as appropriate.

As the conductive films 304a, 304b, and 304c, the material and manufacturing method of the gate electrode 15 described in Embodiment 1 can be used as appropriate.

An insulating film 305 and an insulating film 306 are formed over the substrate 302 and the conductive films 304a, 304c, and 304b. The insulating films 305 and 306 function as a gate insulating film of the transistor in the driver circuit portion and a gate insulating film of the transistor in the pixel portion 101.

The insulating film 305 is preferably formed using the nitride insulating film described in the gate insulating film 17 described in Embodiment 1. The insulating film 306 is preferably formed using the oxide insulating film described in the gate insulating film 17 described in Embodiment 1.

Over the insulating film 306, multilayer films 308a and 308b and a light-transmitting conductive film 308c are formed. The multilayer film 308a is formed so as to overlap with the conductive film 304a and functions as a channel region of the transistor in the driver circuit portion. The multilayer film 308b is formed of the conductive film 30.
It is formed at a position overlapping with 4c and functions as a channel region of the transistor in the pixel portion.
The light-transmitting conductive film 308 c functions as one electrode of the capacitor 105.

For the multilayer films 308a and 308b and the light-transmitting conductive film 308c, the materials and manufacturing methods of the multilayer film 20 described in Embodiment 1 and the multilayer film 34 described in Embodiment 3 can be used as appropriate.

The light-transmitting conductive film 308c is a multilayer film similar to the multilayer films 308a and 308b,
In addition, impurities are included. An impurity is hydrogen. Note that boron, phosphorus, tin, antimony, a rare gas element, an alkali metal, an alkaline earth metal, or the like may be contained as an impurity instead of hydrogen.

The multilayer films 308a and 308b and the light-transmitting conductive film 308c are both formed over the gate insulating film but have different impurity concentrations. Specifically, the impurity concentration of the light-transmitting conductive film 308c is higher than that of the multilayer films 308a and 308b. For example, the multilayer films 308a, 3
The hydrogen concentration contained in 08b is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 1
Less than 0 ¹⁸ atoms / cm ³ , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms
The concentration of hydrogen contained in the light-transmitting conductive film 308c is 8 × 1 or less ms / cm ^3.
It is 0 ¹⁹ atoms / cm ³ or more, preferably 1 × 10 ²⁰ atoms / cm ³ or more, more preferably 5 × 10 ²⁰ atoms / cm ³ or more. In addition, the multilayer films 308a and 308
Compared with b, the hydrogen concentration contained in the light-transmitting conductive film 308c is doubled, preferably 1
0 times or more.

The light-transmitting conductive film 308c has a lower resistivity than the multilayer films 308a and 308b. The resistivity of the light-transmitting conductive film 308c is 1 × the resistivity of the multilayer films 308a and 308b.
It is preferably 10 ⁻⁸ times or more and 1 × 10 ⁻¹ times or less, and typically 1 × 10 ⁻³ Ωc.
m or more and less than 1 × 10 ⁴ Ωcm, more preferably, the resistivity is 1 × 10 ⁻³ Ωcm or more and 1 ×
It is good that it is less than 10 ⁻¹ Ωcm.

The multilayer films 308a and 308b are in contact with a film formed of a material that can improve interface characteristics with the multilayer film, such as the insulating film 306 and the insulating film 312.
08b functions as a semiconductor, and the transistor including the multilayer films 308a and 308b has excellent electrical characteristics.

On the other hand, the light-transmitting conductive film 308c is in contact with the insulating film 314 in the opening 362 (see FIG. 21A). The insulating film 314 is a film formed of a material that prevents external impurities such as water, alkali metal, alkaline earth metal, and the like from diffusing into the multilayer film, and further contains hydrogen. Therefore, when hydrogen in the insulating film 314 diffuses into the multilayer film formed at the same time as the multilayer films 308a and 308b, hydrogen is combined with oxygen in the oxide semiconductor film included in the multilayer film, and electrons serving as carriers are generated. The As a result, the oxide semiconductor film included in the multilayer film has high conductivity and functions as a conductor. That is, it can be said that the oxide semiconductor film has high conductivity. Here, a metal oxide whose main component is the same material as that of the multilayer films 308a and 308b and whose hydrogen concentration is higher than that of the multilayer films 308a and 308b is used as a light-transmitting conductive film 308c. Called.

Note that one embodiment of the present invention is not limited to this, and the conductive film 30 having a light-transmitting property is used.
8c may not be in contact with the insulating film 314 in some cases.

One embodiment of the present invention is not limited to this, and the light-transmitting conductive film 308 is not limited thereto.
In some cases, c may be formed in a separate step from the multilayer film 308a or 308b. In that case, the light-transmitting conductive film 308c includes the multilayer films 308a and 308b,
You may have a different material. For example, the light-transmitting conductive film 308c may be formed using indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or the like.

In the semiconductor device described in this embodiment, an electrode serving as one of capacitor elements is formed at the same time as a multilayer film of a transistor. A light-transmitting conductive film functioning as a pixel electrode is used as the other electrode of the capacitor. Therefore, a process for forming a new conductive film is not required to form a capacitor element, and the manufacturing process of a semiconductor device can be reduced. In addition, the capacitor has a light-transmitting property because the pair of electrodes is formed using a light-transmitting conductive film. As a result, the aperture ratio of the pixel can be increased while increasing the area occupied by the capacitive element.

For the conductive films 310a, 310b, 310c, 310d, and 310e, the material and the manufacturing method of the pair of electrodes 21 and 22 described in Embodiment 1 can be used as appropriate.

The insulating film 312 and the insulating film 3 are formed over the insulating film 306, the multilayer films 308a and 308b, the light-transmitting conductive film 308c, and the conductive films 310a, 310b, 310c, 310d, and 310e.
14 is formed. As the insulating film 312, it is preferable to use a material capable of improving the interface characteristics with the multilayer film as in the case of the insulating film 306, and at least the same material and manufacturing as the oxide insulating film 24 described in Embodiment 1 The method can be used as appropriate. Further, as illustrated in Embodiment 1, the oxide insulating film 23 and the oxide insulating film may be stacked.

As in the insulating film 305, the insulating film 314 is preferably formed using a material that prevents external impurities such as water, alkali metal, alkaline earth metal, and the like from diffusing into the multilayer film. The material and manufacturing method of the nitride insulating film 25 shown in FIG.

In addition, light-transmitting conductive films 316 a and 316 b are formed over the insulating film 314. The light-transmitting conductive film 316a is electrically connected to the conductive film 304b in the opening 364a (see FIG. 21C) and is connected to the conductive film 310c in the opening 364b (see FIG. 21C). Electrically connected. That is, it functions as a connection electrode for connecting the conductive film 304b and the conductive film 310c. The light-transmitting conductive film 316b includes an opening 364c (see FIG.
See C). ) Is electrically connected to the conductive film 310e and functions as a pixel electrode of the pixel. The light-transmitting conductive film 316b can function as one of a pair of electrodes of the capacitor.

In order to obtain a connection structure in which the conductive film 304b and the conductive film 310c are in direct contact, the conductive film 3
Before forming 10c, it is necessary to perform patterning to form openings in the insulating film 305 and the insulating film 306 to form a mask, but the connection structure in FIG. 18 does not require the photomask. . However, as shown in FIG. 18, the light-transmitting conductive film 316a
The conductive films 304b and 310c are connected by connecting the conductive films 304b and 310c.
There is no need to prepare a connection portion in which c is in direct contact, and one photomask can be reduced. That is, the number of manufacturing steps of the semiconductor device can be reduced.

The light-transmitting conductive films 316a and 316b include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium A light-transmitting conductive material such as zinc oxide or indium tin oxide to which silicon oxide is added can be used.

In addition, a colored film (hereinafter referred to as a colored film 346) is formed over the substrate 342. The colored film 346 functions as a color filter. In addition, the colored film 346
A light shielding film 344 adjacent to the substrate 342 is formed on the substrate 342. The light shielding film 344 functions as a black matrix. Further, the colored film 346 is not necessarily provided. For example, the colored film 346 may not be provided depending on the case where the display device is monochrome.

The colored film 346 may be a colored film that transmits light in a specific wavelength band. For example,
A red (R) color filter that transmits light in the red wavelength band, a green (G) color filter that transmits light in the green wavelength band, and a blue (B) color filter that transmits light in the blue wavelength band Etc. can be used.

As the light-blocking film 344, it is sufficient if it has a function of blocking light in a specific wavelength band, and a metal film, an organic insulating film containing a black pigment, or the like can be used.

An insulating film 348 is formed on the colored film 346. The insulating film 348 has a function as a planarization layer or a function of suppressing diffusion of impurities that can be contained in the colored film 346 to the liquid crystal element side.

A conductive film 350 is formed over the insulating film 348. The conductive film 350 functions as the other of the pair of electrodes included in the liquid crystal element in the pixel portion. Note that an insulating film having a function as an alignment film may be additionally formed over the light-transmitting conductive films 316 a and 316 b and the conductive film 350.

Further, the liquid crystal layer 3 is provided between the light-transmitting conductive films 316 a and 316 b and the conductive film 350.
20 is formed. The liquid crystal layer 320 is formed on the substrate 3 using a sealing material (not shown).
02 and the substrate 342 are sealed. Note that the sealing material is preferably in contact with an inorganic material in order to suppress entry of moisture and the like from the outside.

Further, the liquid crystal layer 320 is provided between the light-transmitting conductive films 316 a and 316 b and the conductive film 350.
A spacer for maintaining the thickness (also referred to as a cell gap) may be provided.

A method for manufacturing an element portion provided over the substrate 302 illustrated in the semiconductor device illustrated in FIG.
This will be described with reference to FIGS.

  First, the substrate 302 is prepared. Here, a glass substrate is used as the substrate 302.

Next, a conductive film is formed over the substrate 302, and the conductive film is processed into a desired region, whereby conductive films 304a, 304b, and 304c are formed. Note that the conductive films 304a, 304b, and 304
The formation of c can be performed by forming a mask by first patterning in a desired region and etching a region not covered by the mask. (See FIG. 19A)
.

The conductive films 304a, 304b, and 304c can be typically formed by an evaporation method, a CVD method, a sputtering method, a spin coating method, or the like.

Next, the insulating film 305 is formed over the substrate 302 and the conductive films 304a, 304b, and 304c, and the insulating film 306 is formed over the insulating film 305 (see FIG. 19A).

The insulating film 305 and the insulating film 306 can be formed by a sputtering method, a CVD method, or the like. Note that it is preferable that the insulating film 305 and the insulating film 306 be formed successively in a vacuum because entry of impurities is suppressed.

  Next, a multilayer film 307 is formed over the insulating film 306 (see FIG. 19B).

The multilayer film 307 can be formed by a sputtering method, a coating method, a pulse laser deposition method, a laser ablation method, or the like.

Next, by processing the multilayer film 307 into a desired region, the island-shaped multilayer films 308a and 308b
, 308d. The multilayer films 308a, 308b, and 308d can be formed by forming a mask by second patterning in a desired region and etching a region that is not covered with the mask. As the etching, dry etching, wet etching, or a combination of both can be used (FIG. 19).
(See (C)).

Next, first heat treatment is performed. The first heat treatment uses conditions similar to those of the first heat treatment described in Embodiment 1. By the first heat treatment, the multilayer films 308a, 308b, and 308d
The crystallinity of the oxide semiconductor used for the insulating film 306 and the multilayer films 308a and 30
Impurities such as hydrogen and water can be removed from 8b and 308d. Note that the first heating step may be performed before the oxide semiconductor is etched.

Next, a conductive film 309 is formed over the insulating film 306 and the multilayer films 308a, 308b, and 308d (see FIG. 20A).

  For example, the conductive film 309 can be formed by a sputtering method.

Next, the conductive film 309 is processed into a desired region, whereby the conductive films 310a, 310b, and 31 are processed.
0c, 310d, and 310e are formed. The conductive films 310a, 310b, 310c, 3
10d and 310e can be formed by forming a mask by a third patterning in a desired region and etching a region not covered with the mask (FIG. 2).
0 (see B)).

Next, the insulating film 306, the multilayer films 308a, 308b, and 308d, and the conductive films 310a and 3
An insulating film 311 is formed to cover 10b, 310c, 310d, and 310e (FIG. 2).
0 (C)).

The insulating film 311 can be formed by stacking using the same conditions as the oxide insulating film 23 and the oxide insulating film 24 described in Embodiment 1.

Next, the insulating film 311 and the opening 362 are processed by processing the insulating film 311 into a desired region.
Form. Note that the insulating film 311 and the opening 362 can be formed by forming a mask by a fourth patterning in a desired region and etching a region not covered with the mask. (See FIG. 21A).

Note that the opening 362 is formed so that the surface of the multilayer film 308d is exposed. Opening 36
As a forming method of 2, for example, a dry etching method can be used. However, the method for forming the opening 362 is not limited to this, and may be a wet etching method or a formation method in which a dry etching method and a wet etching method are combined.

After that, the second heat treatment is performed so that part of oxygen contained in the insulating film 311 is removed from the multilayer film 30.
Oxygen is transferred to the oxide semiconductor films included in 8a and 308b, so that the multilayer films 308a and 308b
The amount of oxygen vacancies in the oxide semiconductor film contained in the oxide semiconductor film can be reduced.

Next, the insulating film 313 is formed over the insulating film 312 and the multilayer film 308d (see FIG. 21B).

As the insulating film 313, impurities from the outside, for example, oxygen, hydrogen, water, alkali metal,
It is preferable to use a material that prevents alkaline earth metal or the like from diffusing into the multilayer film, and further preferably includes hydrogen. Typically, an inorganic insulating material containing nitrogen, such as a nitride insulating film, is used. Can do. The insulating film 313 can be formed using, for example, a CVD method.

The insulating film 314 is a film formed of a material that prevents external impurities such as water, alkali metal, alkaline earth metal, and the like from diffusing into the multilayer film, and further contains hydrogen. Therefore, when hydrogen in the insulating film 314 diffuses into the multilayer film 308d, hydrogen is combined with oxygen in the oxide semiconductor film included in the multilayer film 308d, and electrons serving as carriers are generated. As a result,
The oxide semiconductor film included in the multilayer film 308d has high conductivity and becomes a light-transmitting conductive film 308c.

In addition, the silicon nitride film is preferably formed at a high temperature in order to improve the block property.
It is preferable to form a film by heating at a temperature of 00 ° C. or lower. In the case where the film is formed at a high temperature, oxygen may be desorbed from the oxide semiconductor used as the multilayer films 308a and 308b, and the carrier concentration may increase. Therefore, the temperature is set such that such a phenomenon does not occur.

Next, the insulating film 313 and the opening 364 are processed by processing the insulating film 313 into a desired region.
a, 364b and 364c are formed. Note that the insulating film 314 and the openings 364a and 364
b and 364c can be formed by forming a mask by a fifth patterning in a desired region and etching a region not covered with the mask (see FIG. 21C).

The opening 364a is formed so that the surface of the conductive film 304b is exposed. The opening 364b is formed so that the conductive film 310c is exposed. The opening 364c is
The conductive film 310e is formed so as to be exposed.

As a method for forming the openings 364a, 364b, and 364c, for example, a dry etching method can be used. However, the method for forming the openings 364a, 364b, and 364c is not limited to this, and a wet etching method or a formation method that combines a dry etching method and a wet etching method may be used.

Next, the conductive film 31 is formed on the insulating film 314 so as to cover the openings 364a, 364b, and 364c.
5 is formed (see FIG. 22A).

  The conductive film 315 can be formed by a sputtering method, for example.

Next, the conductive film 315 is processed into a desired region, whereby a light-transmitting conductive film 316a,
316b is formed. Note that the light-transmitting conductive films 316a and 316b can be formed by forming a mask by sixth patterning in a desired region and etching a region not covered with the mask ( (See FIG. 22B).

Through the above process, a pixel portion and a driver circuit portion each including a transistor can be formed over the substrate 302. Note that in the manufacturing process described in this embodiment, a transistor and a capacitor can be formed at the same time with first to sixth patterning, that is, with six masks.

Note that in this embodiment, hydrogen contained in the insulating film 314 is diffused into the multilayer film 308d to increase the conductivity of the oxide semiconductor film included in the multilayer film 308d.
8b is covered with a mask, and an impurity, typically hydrogen, boron, phosphorus, tin, antimony, a rare gas element, an alkali metal, an alkaline earth metal, or the like is added to the multilayer film 308d.
The conductivity of the oxide semiconductor film included in 8d may be increased. Examples of a method for adding hydrogen, boron, phosphorus, tin, antimony, a rare gas element, or the like to the multilayer film 308d include an ion doping method and an ion implantation method. On the other hand, as a method for adding an alkali metal, an alkaline earth metal, or the like to the multilayer film 308d, there is a method in which a solution containing the impurity is exposed to the multilayer film 308d.

Next, a structure formed over the substrate 342 provided to face the substrate 302 will be described below.

First, the substrate 342 is prepared. As the substrate 342, the material shown in the substrate 302 can be used. Next, a light-shielding film 344 and a colored film 346 are formed over the substrate 342 (FIG. 23 (
A)).

The light-blocking film 344 and the colored film 346 are formed using various materials using a printing method, an inkjet method,
Each is formed at a desired position by an etching method using a photolithography technique.

Next, an insulating film 348 is formed over the light-blocking film 344 and the colored film 346 (see FIG. 23B).

As the insulating film 348, for example, an organic insulating film such as an acrylic resin, an epoxy resin, or polyimide can be used. By forming the insulating film 348, for example, the colored film 346
It is possible to suppress the diffusion of impurities contained therein into the liquid crystal layer 320 side. Note that the insulating film 348 is not necessarily provided and a structure in which the insulating film 348 is not formed may be employed.

Next, a conductive film 350 is formed over the insulating film 348 (see FIG. 23C). Conductive film 350
For example, the material shown in the conductive film 315 can be used.

  Through the above steps, a structure formed over the substrate 342 can be formed.

Next, the insulating film 31 formed on the substrate 302 and the substrate 342, more specifically, on the substrate 302.
4. Light-transmitting conductive films 316a and 316b and a conductive film 35 formed over the substrate 342
An alignment film 318 and an alignment film 352 are formed on 0, respectively. Alignment film 318, Alignment film 352
Can be formed using a rubbing method, a photo-alignment method, or the like. After that, the liquid crystal layer 320 is formed between the substrate 302 and the substrate 342. As a method for forming the liquid crystal layer 320, a dispenser method (a dropping method) or an injection method in which liquid crystal is injected using a capillary phenomenon after the substrate 302 and the substrate 342 are bonded to each other can be used.

  Through the above process, the display device illustrated in FIG. 18 can be manufactured.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

<Modification 1>

A modification of the liquid crystal display device using a liquid crystal element for the pixel 301 will be described. Here, a top view of the pixel 301 illustrated in FIG. 16B is illustrated in FIG. In FIG. 24, the counter electrode and the liquid crystal element are omitted. Note that the description of the same configuration as that of Embodiment 7 is omitted.

<Configuration of semiconductor device>
24 differs from the pixel 301 shown in FIG. 17 in that an opening 374c is provided inside the opening 372c. 17 is different from the pixel shown in FIG. 17 in that an opening 372 is provided instead of the opening 364. The conductive film 310e is electrically connected to the light-transmitting conductive film 316b functioning as a pixel electrode in the opening 372c and the opening 374c.

Next, FIG. 25 shows a cross-sectional view taken along the alternate long and short dash line CD in FIG. Note that in FIG. 25, a cross-sectional view of the driver circuit portion (a top view is omitted) is shown in AB.

As shown in FIG. 25, an opening 372a (see FIG. 26A) provided in the insulating film 306 and the insulating film 312 and an opening 374 provided in the insulating film 314 are formed over the conductive film 304a.
a (see FIG. 26C). The opening 374a (see FIG. 26C) is located inside the opening 372a (see FIG. 26A). In the opening 374a (see FIG. 26C), the conductive film 304a and the light-transmitting conductive film 316a are connected.

Further, an opening 372b (see FIG. 26A provided in the insulating film 312 is provided over the conductive film 310c.
)reference. And an opening 374b (see FIG. 26C) provided in the insulating film 314. The opening 374b (see FIG. 26C) is the opening 372b (see FIG. 26A).
) Is located inside. In the opening 374b (see FIG. 26C), the conductive film 310c is formed.
And the light-transmitting conductive film 316a are connected to each other.

An opening 372c (see FIG. 26A provided in the insulating film 312 is provided over the conductive film 310e.
)reference. ) And an opening 374c (see FIG. 26C) provided in the insulating film 314. The opening 374c (see FIG. 26C) is the opening 372c (see FIG. 26A).
) Is located inside. In the opening 374c (see FIG. 26C), the conductive film 310e is formed.
Are connected to the light-transmitting conductive film 316b.

Further, an opening 372 provided in the insulating film 312 is provided over the light-transmitting conductive film 308c.
(See FIG. 26A). In the opening 372, the light-transmitting conductive film 308 is formed.
c is in contact with the insulating film 314.

A connection portion between the conductive film 304b and the light-transmitting conductive film 316a, a connection portion between the conductive film 310c and the light-transmitting conductive film 316a, a conductive film 310e, and a light-transmitting conductive film 316b.
These connection portions are each covered with an insulating film 305 and / or an insulating film 314. Insulating film 3
05 and the insulating film 314 are formed of an insulating film formed of a material that prevents impurities from the outside, for example, water, alkali metal, alkaline earth metal, and the like from diffusing into the multilayer film. The side surfaces of the openings 372a, 372b, 372c, and 372 (see FIG. 26A) are insulating films 305.
Or / and the insulating film 314 is covered. Since a multilayer film is provided inside the insulating film 305 and the insulating film 314, impurities from the outside, for example, water, alkali metal, alkaline earth metal, or the like can be supplied from the conductive film 304b, the conductive films 310c, 310e, and the transparent film. Photoconductive film 30 having optical properties
It is possible to prevent diffusion from the connection portion of 8c, 316a, and 316b to the multilayer film included in the transistor. For this reason, it is possible to prevent variation in the electrical characteristics of the transistor, and the reliability of the semiconductor device can be improved.

<Method for Manufacturing Semiconductor Device>
A method for manufacturing an element portion provided over the substrate 302 shown in the semiconductor device shown in FIG.
This will be described with reference to FIGS. 19, 20, 26, and 27.

Similarly to Embodiment 7, through the steps of FIGS. 19 and 20, the conductive films 304a, 304b, and 304c that function as gate electrodes, the insulating films 305 and 306 that function as gate insulating films, over the substrate 302, Multilayer films 308a, 308b, 308d, conductive films 310a, 3
10b, 310c, 310d, 310e, and an insulating film 311 are formed. Note that in this process, first to third patterning are performed, and the conductive films 304a and 3b are respectively formed.
04b, 304c, multilayer films 308a, 308b, 308d, conductive films 310a, 310b,
310c, 310d, and 310e are formed.

Next, as illustrated in FIG. 26A, the insulating film 311 and the openings 372, 372b, and 372c are formed by processing the insulating film 311 into a desired region. Further, the opening 372a is formed by processing the insulating film 306 which is a part of the gate insulating film into a desired region. Note that the insulating film 305, the insulating film 312, and the openings 372, 372a, 372b, and 372c are formed by forming a mask by a fourth patterning in a desired region and etching a region that is not covered by the mask. Thus, it can be formed. Openings 372 and 372a
, 372b, and 372c can be formed using the method for forming the opening 362 described in Embodiment 7 as appropriate.

In the etching step, at least the opening 372a is formed, so that the etching amount can be reduced in the etching step using a mask formed by the fifth patterning performed later.

  Thereafter, as in Embodiment 7, second heat treatment is performed.

Next, the insulating film 305, the conductive films 310c and 310e, the insulating film 312, and the multilayer film 308d
An insulating film 313 is formed thereon (see FIG. 26B).

Next, as in Embodiment 7, the insulating film 313 is processed into a desired region, so that the insulating film 3
14 and openings 374a, 374b, 374c. Note that the insulating film 314 and the openings 374a, 374b, and 374c can be formed by forming a mask by a fifth patterning in a desired region and etching a region that is not covered with the mask ( (See FIG. 26C).

Next, as in Embodiment 7, a conductive film 315 is formed over the insulating film 314 so as to cover the openings 374a, 374b, and 374c (see FIG. 27A).

Next, the conductive film 315 is processed into a desired region, whereby a light-transmitting conductive film 316a,
316b is formed. Note that the light-transmitting conductive films 316a and 316b can be formed by forming a mask by sixth patterning in a desired region and etching a region not covered with the mask ( FIG. 27 (B)).

Through the above process, a pixel portion and a driver circuit portion each including a transistor can be formed over the substrate 302. Note that in the manufacturing process described in this embodiment, a transistor and a capacitor can be formed at the same time with first to sixth patterning, that is, with six masks.

In FIG. 26A, in the case where the opening 372a is not formed, the insulating film 305, the insulating film 306, the insulating film 312, and the insulating film 31 are formed in the etching step illustrated in FIG.
4 has to be etched, and the amount of etching increases compared to other openings. For this reason, variations occur in the etching process, and in some areas,
The opening 374a is not formed, and a light-transmitting conductive film 316a and a conductive film 3 are formed later.
The contact failure 04b occurs. However, in this embodiment mode, the opening 372a and the opening 374a are formed by two etching processes, so that etching defects are unlikely to occur in the opening forming process. As a result, the yield of the semiconductor device can be improved. Although the description has been given here using the opening 372a, the opening 374b and the opening 374c have the same effect.

<Modification 2>
A modification of the liquid crystal display device using a liquid crystal element for the pixel 301 will be described. In the liquid crystal display device illustrated in FIGS. 18 and 25, the light-transmitting conductive film 308 is in contact with the insulating film 314, but can have a structure in contact with the insulating film 305. In this case, since there is no need to provide the opening 362 as illustrated in FIG. 21, steps on the surfaces of the light-transmitting conductive films 316a and 316b can be reduced. For this reason, it is possible to reduce alignment disorder of the liquid crystal material included in the liquid crystal layer 320. In addition, a semiconductor device with high contrast can be manufactured.

In such a structure, the insulating film 30 is formed before the multilayer film 307 is formed in FIG.
6 may be selectively etched to expose part of the insulating film 305.

<Modification 3>
Here, a modified example of the semiconductor device described in Embodiment 1 is described with reference to FIGS. 28A and 28B, a cross-sectional view of the driver circuit portion is shown in AB, and a cross-sectional view of the pixel portion is shown in CD.

The semiconductor device illustrated in FIG. 28 is different from the semiconductor device described in Embodiment 1 in that a channel protection transistor is used.

In the driver circuit portion, a conductive film 304a functioning as a gate electrode, an insulating film 305 and an insulating film 306 functioning as a gate insulating film, a multilayer film 308a in which a channel region is formed, a conductive film 310a functioning as a source electrode and a drain electrode, The transistor 102 is configured by 310b. An insulating film 312 that functions as a channel protective film is provided between the multilayer film 308a and the conductive films 310a and 310b. In addition, the conductive films 310a, 310b, and 310c
On the top, an insulating film 314 is provided as a protective film.

In the pixel portion, a conductive film 304c functioning as a gate electrode, an insulating film 305 and an insulating film 306 functioning as a gate insulating film, a multilayer film 308b in which a channel region formed over the gate insulating film is formed, a source electrode and a drain electrode Conductive films 310d and 31 that function as
The transistor 103 is configured by 0e. Multilayer film 308b and conductive films 310d and 310e
An insulating film 312 functioning as a channel protective film is provided between the two. In addition, the conductive film 310
An insulating film 314 is provided as a protective film over the conductive films 308c having d and 310e and a light-transmitting property.

A light-transmitting conductive film 316b functioning as a pixel electrode is connected to the conductive film 310e in an opening provided in the insulating film 314.

Further, the capacitor 105 is formed using the light-transmitting conductive film 308 c functioning as one electrode, the insulating film 314 functioning as a dielectric film, and the light-transmitting conductive film 316 b functioning as the other electrode.

In the driver circuit portion, the conductive film 30 formed simultaneously with the conductive films 304a and 304c.
4b and the conductive film 31 formed simultaneously with the conductive films 310a, 310b, 310d, and 310e.
0c means a light-transmitting conductive film 31 formed at the same time as the light-transmitting conductive film 316b.
6a is connected.

In this modification, when the conductive films 310a, 310b, 310d, and 310e are etched, the multilayer films 308a and 308b are covered with the insulating film 312.
Multilayer films 308a and 308 are formed by etching to form 310b, 310d and 310e.
b takes no damage. Further, the insulating film 312 is formed using an oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition. Therefore, part of oxygen contained in the insulating film 312 can be moved to the multilayer films 308a and 308b, so that the amount of oxygen vacancies contained in the multilayer films 308a and 308b can be reduced.

28A to 28C, a method for manufacturing an element portion provided over the substrate 302 illustrated in the semiconductor device illustrated in FIG.
This will be described with reference to FIGS. 19, 29, and 30. FIG.

Similarly to Embodiment 7, through the process of FIG. 19, conductive films 304a, 304b, and 304c that function as gate electrodes, insulating films 305 and 306 that function as gate insulating films, and a multilayer film 308a are formed over the substrate 302. , 308b, 308d. Note that in this step, the first patterning and the second patterning are performed, and the conductive films 304a and 3b are respectively formed.
04b and 304c and multilayer films 308a, 308b and 308d are formed.

  Next, as illustrated in FIG. 29A, an insulating film 311 is formed in a manner similar to that in Embodiment 7.

  Thereafter, as in Embodiment 7, second heat treatment is performed.

Next, as illustrated in FIG. 29B, the insulating film 311 is processed into a desired region, whereby the insulating film 312 is formed over the multilayer films 308a and 308b. In this step, in the case where the insulating film 306 is formed using a material similar to that of the insulating film 312, a part of the insulating film 306 is etched and only a region covered with the multilayer films 308a and 308b remains. Note that the insulating film 306 and the insulating film 312 can be formed by forming a mask by third patterning in a desired region and etching a region not covered with the mask.

Next, after a conductive film is formed over the insulating film 305, the insulating film 306, and the multilayer films 308a and 308b, the conductive film 310a, 310b, 310c, 310d,
310e is formed (see FIG. 29C). The conductive films 310a, 310b, 310
The formation of c, 310d, and 310e can be performed by forming a mask by the fourth patterning in a desired region and etching the region not covered with the mask.

Next, the insulating film 305, the insulating film 312, the multilayer film 308d, the conductive films 310a, 310b, 3
An insulating film 313 is formed over 10c, 310d, and 310e (see FIG. 30A).

Next, as in Embodiment 7, the insulating film 313 is processed into a desired region, so that the insulating film 3
14 and openings 384a, 384b, 384c. Note that the insulating film 314 and the openings 384a, 384b, and 384c can be formed by forming a mask by a fifth patterning in a desired region and etching a region that is not covered with the mask ( (See FIG. 30B).

Next, as in Embodiment 7, a conductive film is formed over the insulating film 314 so as to cover the openings 384a, 384b, and 384c, and then the conductive film is processed into a desired region, so that translucency can be obtained. The conductive films 316a and 316b are formed (see FIG. 30C). Note that the light-transmitting conductive films 316a and 316b can be formed by forming a mask by sixth patterning in a desired region and etching a region not covered with the mask.

Through the above process, a pixel portion and a driver circuit portion each including a transistor can be formed over the substrate 302. Note that in the manufacturing process described in this embodiment, a transistor and a capacitor can be formed at the same time with first to sixth patterning, that is, with six masks.

<Modification 4>
In this embodiment and the modification, the light-transmitting conductive film 308c and the light-transmitting conductive film 316b are used as the pair of electrodes included in the capacitor 105. Instead, FIG. As shown, a light-transmitting conductive film 31 is provided between the insulating film 312 and the insulating film 314.
7, a light-transmitting conductive film 316 c is formed over the insulating film 314, and the light-transmitting conductive film 317 and the light-transmitting conductive film 316 c are formed into a pair of electrodes for forming the capacitor 105. Can be used as

Further, an organic insulating film such as an acrylic resin, an epoxy resin, or polyimide may be provided over the insulating film 312. Since an organic insulating film such as an acrylic resin has high flatness, a step on the surface of the light-transmitting conductive film 316a can be reduced. For this reason, it is possible to reduce alignment disorder of the liquid crystal material included in the liquid crystal layer 320. In addition, a semiconductor device with high contrast can be manufactured.

<Modification 5>
In this embodiment and the modification, the light-transmitting conductive film 308c and the light-transmitting conductive film 316b are used as the pair of electrodes included in the capacitor;
04b and 304c, conductive films formed simultaneously with the conductive films 310a, 310b, 310c, 3
Two or more of a conductive film formed simultaneously with 10d and 310e, a light-transmitting conductive film 308c, and a light-transmitting conductive film 316b can be selected as appropriate.

(Embodiment 9)
In this embodiment, one mode applicable to the multilayer film 20 and the multilayer film 34 in the transistor included in the semiconductor device described in the above embodiment is described. Note that the oxide semiconductor film included in the multilayer film is described here as an example; however, the oxide film can have a similar structure.

An oxide semiconductor film is an oxide semiconductor having a single crystal structure (hereinafter referred to as a single crystal oxide semiconductor).
A polycrystalline oxide semiconductor (hereinafter referred to as a polycrystalline oxide semiconductor), a microcrystalline oxide semiconductor (hereinafter referred to as a microcrystalline oxide semiconductor), and an amorphous oxide semiconductor (hereinafter referred to as a microcrystalline oxide semiconductor). Or an amorphous oxide semiconductor). The oxide semiconductor film may be formed using a CAAC-OS. The oxide semiconductor film may be formed using an amorphous oxide semiconductor and an oxide semiconductor having crystal grains. A single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor are described below.

<Single crystal oxide semiconductor>
For example, a single crystal oxide semiconductor has a low impurity concentration and a low density of defect states (a small amount of oxygen vacancies); therefore, the carrier density can be reduced. Therefore, a transistor in which a single crystal oxide semiconductor is used for a channel region often has normally-on electrical characteristics. In addition, since the single-crystal oxide semiconductor has a low density of defect states, the density of trap levels may be low. Therefore, a transistor using a single crystal oxide semiconductor for a channel region may have a small change in electrical characteristics and be a highly reliable transistor.

<CAAC-OS>
The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts are large enough to fit in a cube whose one side is less than 100 nm. Therefore, CAAC-
The crystal part included in the OS film includes a case where one side has a size that fits in a cube of less than 10 nm, less than 5 nm, or less than 3 nm. The CAAC-OS film is characterized by having a lower density of defect states than a microcrystalline oxide semiconductor film. Hereinafter, the CAAC-OS film is described in detail.

The CAAC-OS is, for example, a transmission electron microscope (TEM: Transmission).
In some cases, the crystal part can be confirmed by an observation image obtained by an electron microscope (Electron Microscope). The crystal part included in the CAAC-OS is, for example, an observation image by TEM.
In many cases, the size is within a cube of 100 nm on a side. In addition, CAAC-OS
There may be a case where the boundary between the crystal part and the crystal part cannot be clearly confirmed in the observation image by TEM. The CAAC-OS is an observation image obtained by a TEM and is a grain boundary (also referred to as a grain boundary).
May not be clearly confirmed. For example, the CAAC-OS does not have a clear grain boundary; In addition, since the CAAC-OS does not have a clear grain boundary, for example, the density of defect states is rarely increased. In addition, the CAAC-OS is, for example,
Since there is no clear grain boundary, the decrease in electron mobility is small.

For example, the CAAC-OS includes a plurality of crystal parts, and the c-axis is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface of the plurality of crystal parts.
Therefore, the CAAC-OS is, for example, an X-ray diffraction (XRD: X-Ray Diffrac).
2) showing orientation when analyzed by the out-of-plane method using a
There may be a peak where θ is around 31 °. In the CAAC-OS, for example, spots (bright spots) may be observed in an electron beam diffraction pattern. In particular, the beam diameter is 1
An electron diffraction pattern obtained using an electron beam of 0 nmφ or less or 5 nmφ or less is referred to as a micro electron diffraction pattern. In the CAAC-OS, for example, the directions of the a-axis and the b-axis may not be uniform between different crystal parts. For example, the CAAC-OS may be c-axis oriented and the a-axis and / or b-axis may not be aligned in a macro manner.

FIG. 31 is an example of a microelectron beam diffraction pattern of a sample including a CAAC-OS. Here, the sample is cut in a direction perpendicular to the surface on which the CAAC-OS is formed, and thinned so that the thickness becomes approximately 40 nm. Here, an electron beam having a beam diameter of 1 nmφ is made incident from a direction perpendicular to the cut surface of the sample. FIG. 31 shows that spots are observed in the microelectron beam diffraction pattern of the CAAC-OS.

The crystal part included in the CAAC-OS is aligned so that, for example, the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS or the normal vector of the surface, and from a direction perpendicular to the ab plane. The metal atoms are arranged in a triangular shape or a hexagonal shape as viewed, and the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, the term “perpendicular” includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. In addition, a simple term “parallel” includes a range of −10 ° to 10 °, preferably −5 ° to 5 °.

Since the c-axis of the crystal part included in the CAAC-OS is aligned in a direction parallel to the normal vector of the surface where the CAAC-OS is formed or the normal vector of the surface, the shape of the CAAC-OS (
Depending on the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface, they may face in different directions. The crystal part is formed when a film is formed or when a crystallization process such as a heat treatment is performed after the film formation. Accordingly, the c-axes of the crystal parts are aligned in a direction parallel to the normal vector of the surface where the CAAC-OS is formed or the normal vector of the surface.

In some cases, the CAAC-OS can be formed by reducing the impurity concentration, for example. Here, the impurity is an element other than the main component of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor. Therefore, in the case where the element deprives oxygen from the oxide semiconductor, the atomic arrangement of the oxide semiconductor may be disturbed and crystallinity may be reduced. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which may disturb the atomic arrangement of the oxide semiconductor and decrease the crystallinity of the oxide semiconductor. Therefore,
The CAAC-OS is an oxide semiconductor with a low impurity concentration. Further, an impurity contained in the oxide semiconductor might serve as a carrier generation source.

Note that in the CAAC-OS, the distribution of crystal parts may not be uniform. For example, CAA
In the C-OS formation process, in the case where crystal growth is performed from the surface side of the oxide semiconductor, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor may be higher in the vicinity of the surface. CAAC
When impurities are mixed into -OS, the crystallinity of the crystal part in the impurity-mixed region may be lowered.

In addition, the CAAC-OS can be formed by reducing the density of defect states, for example. In an oxide semiconductor, for example, when there is an oxygen vacancy, the density of defect states increases. Oxygen deficiency may become a carrier generation source by becoming a carrier trap or capturing hydrogen. In order to form the CAAC-OS, for example, it is important to prevent oxygen vacancies from being generated in the oxide semiconductor. Therefore, the CAAC-OS is an oxide semiconductor with a low density of defect states. Alternatively, the CAAC-OS is an oxide semiconductor with a small amount of oxygen vacancies.

In CAAC-OS, a constant photocurrent measurement method (CPM: Constant Photo)
The absorption coefficient derived by current method is less than 1 × 10 ⁻³ / cm, preferably less than 1 × 10 ⁻⁴ / cm, and more preferably less than 5 × 10 ⁻⁵ / cm. Since the absorption coefficient has a positive correlation with the energy (converted according to the wavelength) corresponding to the localized level derived from oxygen vacancies and impurity contamination, the defect level in the CAAC-OS is extremely small.

In addition, the absorption coefficient by a defect level is computable from the following formula | equation by remove | excluding the absorption coefficient part called the arback tail resulting from the base of a band from the curve of the absorption coefficient obtained by CPM measurement. Note that the back tail refers to a region having a certain slope in the curve of the absorption coefficient obtained by CPM measurement, and the slope is referred to as the back back energy.

Here, α (E) represents an absorption coefficient at each energy, and α _u represents an absorption coefficient due to the Arback tail.

In addition, a transistor using a high-purity intrinsic or substantially high-purity intrinsic CAAC-OS has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

<Method for Manufacturing CAAC-OS>
Since the c-axis of the crystal part included in the CAAC-OS is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS or the normal vector of the surface, the shape of the CAAC-OS (the cross-sectional shape of the formation surface) Or, depending on the cross-sectional shape of the surface, they may face different directions. In addition,
The c-axis direction of the crystal part is a direction parallel to the normal vector of the surface where the CAAC-OS is formed or the normal vector of the surface. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

  There are three methods for forming the CAAC-OS.

The first method is to form an oxide semiconductor film at a deposition temperature of 100 ° C. to 450 ° C. so that the c-axis of a crystal part included in the oxide semiconductor film is a normal vector of a formation surface or This is a method of forming crystal parts aligned in a direction parallel to the surface normal vector. Note that in this specification, the deposition temperature is preferably 100 ° C. or higher and 400 ° C. or lower.

The second method is to form a thin oxide semiconductor film and then perform heat treatment at 200 ° C. to 700 ° C. so that the c-axis of the crystal part included in the oxide semiconductor film is formed. This is a method of forming a crystal part aligned in a direction parallel to a surface normal vector or a surface normal vector. Note that in this specification, the heating temperature is preferably 200 ° C. or higher and 400 ° C. or lower.

The third method is to form a first oxide semiconductor film with a small thickness, and then at 200 ° C. or higher and 700 ° C.
By performing heat treatment at a temperature of less than or equal to 0 ° C. and further forming a second oxide semiconductor film, the c-axis of the crystal part included in the oxide semiconductor film is the normal vector of the surface to be formed or the surface method This is a method of forming crystal parts aligned in a direction parallel to a line vector. Note that in this specification, the heating temperature is preferably 200 ° C. or higher and 400 ° C. or lower.

  Here, a method for forming a CAAC-OS using the first method is described.

<Target and target fabrication method>
The CAAC-OS is formed by a sputtering method using a polycrystalline oxide semiconductor sputtering target, for example. When ions collide with the sputtering target, the crystal region included in the sputtering target is cleaved from the ab plane, and may be separated as flat or pellet-like sputtering particles having a plane parallel to the ab plane. is there. In this case, the CAAC-OS can be formed by allowing the flat-plate-like or pellet-like sputtered particles to reach the formation surface while maintaining a crystalline state.

  In order to form the CAAC-OS, it is preferable to apply the following conditions.

By reducing the mixing of impurities during film formation, the crystal state can be prevented from being broken by impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) existing in the deposition chamber may be reduced. Further, the impurity concentration in the deposition gas may be reduced. Specifically, a film forming gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower, more preferably −100 ° C. or lower is used.

Further, by increasing the heating temperature (for example, substrate heating temperature) of the formation surface during film formation, migration of the sputtering particles occurs after reaching the formation surface. Specifically, the film is formed at a surface temperature of 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C.
By increasing the temperature of the formation surface during film formation, when flat sputtered particles reach the formation surface, migration occurs on the formation surface and the flat surface of the sputtered particles adheres to the formation surface. To do. Note that although different depending on the type of oxide, the sputtered particles have a diameter (equivalent circle diameter) of a plane parallel to the ab plane of about 1 nm to 30 nm, or about 1 nm to 10 nm. The flat-plate-like sputtered particles may have a hexagonal column shape in which a hexagonal plane is a plane parallel to the ab plane. In this case, the direction perpendicular to the hexagonal surface is the c-axis direction.

Note that plasma damage during film formation can be reduced by sputtering the sputtering target with the use of oxygen cations. Therefore, when ions collide with the surface of the sputtering target, it is possible to suppress the crystallinity of the sputtering target from being lowered or becoming amorphous.

In addition, when the sputtering target is sputtered using a cation of oxygen or argon, when the flat-plate-like sputtered particle has a hexagonal column shape, positive charges can be charged at the corners of the hexagonal surface. By having positive charges at the corners of the hexagonal surface, positive charges repel each other in one sputtered particle, and a flat plate shape can be maintained.

In order for the corners in the plane of the flat sputtered particles to have a positive charge, direct current (
DC) power supply is preferably used. A high frequency (RF) power source or an alternating current (AC) power source can also be used. However, it is difficult to apply the RF power source to a sputtering apparatus that can form a film on a large-area substrate. Further, from the viewpoint shown below, a DC power source is considered preferable to an AC power source.

When an AC power supply is used, adjacent targets repeat a cathode potential and an anode potential. When the flat-plate-like sputtered particles are positively charged, the flat plate-like shape can be maintained by repelling each other. However, when an AC power supply is used, a time during which an electric field is not applied instantaneously occurs, so that the charge charged in the flat-plate-like sputtered particles may disappear and the structure of the sputtered particles may be destroyed. Therefore, it is understood that it is preferable to use a DC power supply rather than an AC power supply.

In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing electric power. The oxygen ratio in the film forming gas is 30% by volume or more, preferably 100%.
Volume%.

As an example of the sputtering target, an In—Ga—Zn—O compound target is described below.

In-G that is polycrystalline by mixing InO _X powder, GaO _Y powder, and ZnO _Z powder in a predetermined number of moles, and after heat treatment at a temperature of 1000 ° C. to 1500 ° C.
The a-Zn-O compound target is used. In addition, the said pressurization process may be performed while cooling (or standing to cool), and may be performed while heating. X, Y, and Z are arbitrary positive numbers. Here, the predetermined mole number ratio is, for example, 2: 2: 1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4 for InO _X powder, GaO _Y powder, and ZnO _Z powder. : 2: 3, 3: 1: 2, 1
: 3: 2, 1: 6: 4, or 1: 9: 6. In addition, what is necessary is just to change suitably the kind of powder, and the mol number ratio to mix with the sputtering target to produce.

By using the sputtering target in the above manner, an oxide semiconductor film with a uniform thickness and uniform crystal orientation can be formed.

<Polycrystalline oxide semiconductor>
An oxide semiconductor including polycrystal is referred to as a polycrystalline oxide semiconductor. A polycrystalline oxide semiconductor includes a plurality of crystal grains.

In some cases, a polycrystalline oxide semiconductor can confirm crystal grains in an observation image by a TEM, for example. The crystal grains included in the polycrystalline oxide semiconductor are, for example, a particle size of 2 nm to 300 nm, 3 nm to 100 nm, or 5 nm to 50 nm in an observation image by TEM. In addition, for a polycrystalline oxide semiconductor, for example, the boundary between crystal grains may be confirmed by an observation image obtained by TEM. In addition, in a polycrystalline oxide semiconductor, for example, a grain boundary may be confirmed by an observation image by TEM.

For example, a polycrystalline oxide semiconductor has a plurality of crystal grains, and the plurality of crystal grains may have different orientations. In addition, the polycrystalline oxide semiconductor uses, for example, an XRD apparatus,
When analysis by the out-of-plane method is performed, a peak in which 2θ indicating orientation is near 31 ° or a peak indicating a plurality of types of orientations may appear. In addition, the polycrystalline oxide semiconductor
For example, spots may be observed with an electron diffraction pattern.

A polycrystalline oxide semiconductor, for example, has high crystallinity, and thus may have high electron mobility. Therefore, a transistor in which a polycrystalline oxide semiconductor is used for a channel region has high field effect mobility. However, in a polycrystalline oxide semiconductor, impurities may segregate at grain boundaries. Further, the grain boundary of the polycrystalline oxide semiconductor becomes a defect level. In a polycrystalline oxide semiconductor, a grain boundary may be a carrier generation source or a trap level. Therefore, a transistor using a polycrystalline oxide semiconductor for a channel region is different from a transistor using a CAAC-OS for a channel region. Thus, the transistor may have a large variation in electrical characteristics and low reliability.

The polycrystalline oxide semiconductor can be formed by heat treatment at high temperature or laser light treatment.

<Microcrystalline oxide semiconductor>
In a microcrystalline oxide semiconductor film, for example, a crystal portion may not be clearly confirmed in an observation image obtained by a TEM. The crystal part included in the microcrystalline oxide semiconductor film has a thickness of 1 nm to 10 nm.
In many cases, the size is 0 nm or less, or 1 nm to 10 nm. In particular, a nanocrystal (nc: nano) which is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm.
an oxide semiconductor film including crystal) is formed using an nc-OS (nanocrystalli).
ne Oxide Semiconductor) film. In the nc-OS film, for example, a crystal grain boundary may not be clearly confirmed in an observation image using a TEM.

The nc-OS film has periodicity in atomic arrangement in a very small region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS film may not be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus using X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron beam diffraction (also referred to as limited-field electron diffraction) using an electron beam with a larger probe diameter (eg, 50 nm or more) than the crystal part is performed on the nc-OS film, diffraction like a halo pattern is performed. A pattern is observed. On the other hand, nc
When an electron beam diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter (for example, 1 nm or more and 30 nm or less) that is close to the crystal part or smaller than the crystal part is performed on the OS film, spots are observed. Is done. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed so as to draw a circle (in a ring shape). Nc-
When nanobeam electron diffraction is performed on the OS film, a plurality of spots may be observed in the ring-shaped region.

FIG. 32 illustrates an example in which nanobeam electron diffraction is performed on a sample having an nc-OS film at different measurement locations. Here, the sample is cut in a direction perpendicular to the formation surface of the nc-OS film,
It slices so that thickness may be 10 nm or less. Here, an electron beam having a probe diameter of 1 nmφ is incident from a direction perpendicular to the cut surface of the sample. From FIG. 32, when nanobeam electron diffraction is performed on a sample having an nc-OS film, a diffraction pattern indicating a crystal plane is obtained.
It turned out that the orientation to the crystal plane of a specific direction is not seen.

The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. Note that the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, nc-
The OS film has a higher density of defect states than the CAAC-OS film.

Therefore, the nc-OS film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film with a high carrier density may have a high electron mobility. Therefore, a transistor including the nc-OS film may have high field effect mobility. Further, since the nc-OS film has a higher density of defect states than the CAAC-OS film, carrier traps may increase. Therefore, a transistor using an nc-OS film is a CAAC-
Compared with a transistor using an OS film, a variation in electrical characteristics is large and a transistor with low reliability is obtained. Note that the nc-OS film can be formed even if it contains a relatively large amount of impurities; therefore, the nc-OS film can be formed more easily than the CAAC-OS film and can be preferably used depending on the application. Therefore, a semiconductor device including a transistor including an nc-OS film can be manufactured with high productivity.

<Amorphous oxide semiconductor>
An amorphous oxide semiconductor has, for example, disordered atomic arrangement and no crystal part. Alternatively, an amorphous oxide semiconductor has an amorphous state such as quartz and has no regularity in atomic arrangement.

For an amorphous oxide semiconductor, for example, a crystal part may not be confirmed by an observation image obtained by a TEM.

When an amorphous oxide semiconductor is analyzed by an out-of-plane method using an XRD apparatus, a peak indicating orientation may not be detected in some cases. In addition, the amorphous oxide semiconductor film is
For example, a halo pattern may be observed with an electron beam diffraction pattern. In addition, the amorphous oxide semiconductor film, for example, can not observe spots with a micro-electron beam diffraction pattern,
A halo pattern may be observed.

In some cases, an amorphous oxide semiconductor can be formed by containing an impurity such as hydrogen at a high concentration. Therefore, an amorphous oxide semiconductor is an oxide semiconductor containing impurities at a high concentration, for example.

When an oxide semiconductor contains an impurity at a high concentration, defect levels such as oxygen vacancies may be formed in the oxide semiconductor. Therefore, an amorphous oxide semiconductor with a high impurity concentration has a high density of defect states. In addition, an amorphous oxide semiconductor has low crystallinity, so that a CAAC-OS or an nc-OS
The density of defect states is higher than

Therefore, the amorphous oxide semiconductor may have a higher carrier density than the nc-OS. Therefore, a transistor using an amorphous oxide semiconductor for a channel region may have normally-on electrical characteristics. Therefore, the transistor can be preferably used for a transistor that requires normally-on electrical characteristics. Since an amorphous oxide semiconductor has a high defect level density, the trap level density may also increase. Therefore, a transistor in which an amorphous oxide semiconductor is used for a channel region has a large variation in electric characteristics and has low reliability as compared with a transistor in which CAAC-OS or nc-OS is used for a channel region. There is. Note that an amorphous oxide semiconductor can be formed by a film formation method in which a relatively large amount of impurities is contained. Therefore, the amorphous oxide semiconductor can be easily formed and can be preferably used depending on applications. For example, an amorphous oxide semiconductor is formed by a film forming method such as a spin coating method, a sol-gel method, an immersion method, a spray method, a screen printing method, a contact printing method, an ink jet printing method, a roll coating method, or a mist CVD method. May be.
Therefore, a semiconductor device including a transistor in which an amorphous oxide semiconductor is used for a channel region can be manufactured with high productivity.

Note that an oxide semiconductor has a high density when the number of defects is small. For example, the density of an oxide semiconductor increases when the crystallinity of hydrogen or the like is high. For example, the density of an oxide semiconductor increases when the concentration of impurities such as hydrogen is low. For example, a single crystal oxide semiconductor is a CA.
The density may be higher than that of the AC-OS. For example, the CAAC-OS may have a higher density than the microcrystalline oxide semiconductor. For example, a polycrystalline oxide semiconductor may have a higher density than a microcrystalline oxide semiconductor. For example, a microcrystalline oxide semiconductor may have a higher density than an amorphous oxide semiconductor.

(Embodiment 10)
In this embodiment, a human interface to which the semiconductor device of one embodiment of the present invention can be applied is described. In particular, a configuration example of a sensor (hereinafter referred to as a touch sensor) capable of detecting the proximity or contact of a detection target will be described.

As the touch sensor, various methods such as a capacitance method, a resistance film method, a surface elasticity method, an infrared method, and an optical method can be used.

Typical examples of the capacitive touch sensor include a surface capacitive method and a projected capacitive method. Further, as the projected capacitance method, there are a self-capacitance method, a mutual capacitance method, etc. mainly due to a difference in driving method. Here, it is preferable to use the mutual capacitance method because simultaneous detection of multiple points (also referred to as multi-point detection (multi-touch)) is possible.

The touch sensor is described in detail here, but in addition to this, the movement (gesture) of the detected object (for example, a finger or hand) or the viewpoint movement of the user is detected by a camera (including an infrared camera). A sensor that can do this can also be used as a human interface.

<Example of sensor detection method>
33A and 33B are a schematic diagram illustrating a configuration of a mutual capacitive touch sensor and a schematic diagram of input / output waveforms. The touch sensor includes a pair of electrodes, and a capacitor is formed between them. An input voltage is input to one of the pair of electrodes. In addition, a detection circuit that detects a current flowing through the other electrode (or a potential of the other electrode) is provided.

For example, as shown in FIG. 33A, when a rectangular wave is used as the waveform of the input voltage, a waveform having a sharp peak is detected as the output current waveform.

Further, as shown in FIG. 33B, when the conductive object to be detected is close to or in contact with the capacitance, the capacitance value between the electrodes decreases, and accordingly, the output current value decreases accordingly.

In this way, by detecting the change in the capacitance using the change in the output current (or potential) with respect to the input voltage, it is possible to detect the proximity or contact of the detection target.

<Configuration example of touch sensor>
FIG. 33C illustrates an example of a structure of a touch sensor including a plurality of capacitors arranged in a matrix.

The touch sensor includes a plurality of wirings extending in the X direction (horizontal direction on the paper surface) and a plurality of wirings intersecting with the plurality of wirings and extending in the Y direction (vertical direction on the paper surface). A capacitance is formed between two intersecting wires.

In addition, an input voltage or a common potential (including a ground potential and a reference potential) is input to the wiring extending in the X direction. In addition, a detection circuit (for example, a source meter, a sense amplifier, or the like) is electrically connected to the wiring extending in the Y direction, and a current (or potential) flowing through the wiring can be detected.

The touch sensor scans a plurality of wirings extending in the X direction so that an input voltage is sequentially input, and detects a change in current (or potential) flowing through the wiring extending in the Y direction.
Two-dimensional sensing of the detected object is possible.

<Configuration example of touch panel>
Below, the structural example of the touchscreen provided with the display part and touch sensor which have a some pixel, and the example in the case of incorporating this touchscreen in an electronic device are demonstrated.

  FIG. 34A is a schematic cross-sectional view of an electronic device including a touch panel.

The electronic device 3530 includes a housing 3531 and at least the touch panel 3 in the housing 3531.
532, a battery 3533, and a controller 3534. The touch panel 3532 is electrically connected to the control unit 3534 through the wiring 3535. The control unit 3534 controls display of an image on the display unit and sensing operation of the touch sensor. The battery 3533 is electrically connected to the control unit 3534 through the wiring 3536 and can supply power to the control unit 3534.

The touch panel 3532 is provided so that the display surface side is exposed to the outside of the housing 3531. While displaying an image on the exposed surface of the touch panel 3532, it is possible to detect an object to be detected that touches or approaches.

  34B to 34E show configuration examples of the touch panel.

A touch panel 3532 illustrated in FIG. 34B includes a first substrate 3541 and a second substrate 354.
3, a display panel 3540 including a display portion 3542, a third substrate 3545 including a touch sensor 3544, and a protective substrate 3546.

As the display panel 3540, a liquid crystal element, organic EL (Electro Lumines)
(cence) Various display devices such as a display device to which an element is applied and electronic paper can be applied. Note that the touch panel 3532 may include a backlight, a polarizing plate, or the like depending on the structure of the display panel 3540.

Since the detection target is in contact with or close to one surface of the protective substrate 3546, at least the surface thereof preferably has increased mechanical strength. For example, tempered glass that has been subjected to physical or chemical treatment by an ion exchange method, an air-cooling tempering method, or the like and applied a compressive stress to the surface can be used for the protective substrate 3546. Alternatively, a flexible substrate such as a plastic whose surface is coated can be used. Note that a protective film or an optical film may be provided over the protective substrate 3546.

The touch sensor 3544 is provided on at least one surface of the third substrate 3545. Alternatively, a pair of electrodes included in the touch sensor 3544 may be formed on both surfaces of the third substrate 3545. Further, a flexible film may be used as the third substrate 3545 in order to reduce the thickness of the touch panel. The touch sensor 3544 may be sandwiched between a pair of substrates (including a film).

FIG. 34B illustrates a structure in which the protective substrate 3546 and the third substrate including the touch sensor 3544 are bonded to each other with the adhesive layer 3547; however, they are not necessarily bonded. Alternatively, the third substrate 3545 and the display panel 3540 may be bonded to each other with an adhesive layer.

A touch panel 3532 illustrated in FIG. 34B is provided with a display panel and a substrate including a touch sensor independently. A touch panel having such a configuration can also be referred to as an external touch panel. With such a structure, a display panel and a substrate including a touch sensor can be separately manufactured, and the touch sensor function can be added to the display panel by stacking them, and thus a special manufacturing process is performed. A touch panel can be easily manufactured without any problems.

In the touch panel 3532 illustrated in FIG. 34C, the touch sensor 3544 includes the second substrate 35.
43 is provided on the surface of the protective substrate 3546 side. A touch panel having such a structure can also be referred to as an on-cell touch panel. With such a configuration, since the number of necessary substrates can be reduced, the touch panel can be reduced in thickness and weight.

In the touch panel 3532 illustrated in FIG. 34D, the touch sensor 3544 has a protective substrate 354.
6 is provided on one surface. With such a structure, a display panel and a touch sensor can be separately manufactured, so that a touch panel can be easily manufactured. Furthermore, since the number of necessary substrates can be reduced, the touch panel can be reduced in thickness and weight.

In the touch panel 3532 illustrated in FIG. 34E, the touch sensor 3544 has the display panel 35.
It is provided inside a pair of 40 substrates. A touch panel having such a configuration can also be referred to as an in-cell type touch panel. With such a configuration, since the number of necessary substrates can be reduced, the touch panel can be reduced in thickness and weight. Such a touch panel can be realized by, for example, forming a circuit functioning as a touch sensor on the first substrate 3541 or the second substrate 3543 with a transistor, a wiring, an electrode, or the like included in the display portion 3542. In the case where an optical touch sensor is used, a configuration including a photoelectric conversion element may be employed.

<Configuration example of in-cell type touch panel>
Hereinafter, a configuration example of a touch panel in which a touch sensor is incorporated in a display unit having a plurality of pixels will be described. Here, an example in which a liquid crystal element is used as a display element provided in a pixel is shown.

FIG. 35A is an equivalent circuit diagram in part of a pixel circuit provided in the display portion of the touch panel exemplified in this configuration example.

One pixel includes at least a transistor 3503 and a liquid crystal element 3504. A wiring 3501 is provided at the gate of the transistor 3503 and a wiring 35 is provided at one of the source and the drain.
02 are electrically connected to each other.

The pixel circuit includes a plurality of wirings extending in the X direction (for example, the wiring 3510_1 and the wiring 3510).
_2) and a plurality of wirings (for example, wiring 3511) extending in the Y direction, these are provided so as to cross each other, and a capacitor is formed therebetween.

In addition, among some pixels provided in the pixel circuit, one electrode of a liquid crystal element provided in each of a plurality of adjacent pixels is electrically connected to form one block. The blocks are classified into two types: island-shaped blocks (for example, block 3515_1 and block 3515_2) and line-shaped blocks (for example, block 3516) extending in the Y direction. In FIG. 35, only a part of the pixel circuit is shown, but actually these two types of blocks are repeatedly arranged in the X direction and the Y direction.

The wiring 3510_1 (or 3510_2) extending in the X direction is an island-shaped block 351.
5_1 (or block 3515_2) is electrically connected. Although not shown, X
The wiring 3510_1 extending in the direction electrically connects a plurality of island-shaped blocks 3515_1 arranged discontinuously along the X direction via line-shaped blocks. The wiring 3511 extending in the Y direction is electrically connected to the line-shaped block 3516.

FIG. 35B is an equivalent circuit diagram illustrating a connection configuration of a plurality of wirings 3510 extending in the X direction and a plurality of wirings 3511 extending in the Y direction. An input voltage or a common potential can be input to each of the wirings 3510 extending in the X direction. Further, the wiring 3 extending in the Y direction
A ground potential can be input to each of 511, or the wiring 3511 and the detection circuit can be electrically connected.

<Operation example of touch panel>
Hereinafter, the operation of the touch panel described above will be described with reference to FIG.

As shown in FIG. 36A, one frame period is divided into a writing period and a detection period. The writing period is a period in which image data is written to the pixels, and wirings 3510 (also referred to as gate lines) are sequentially selected. On the other hand, the detection period is a period during which sensing by the touch sensor is performed, and the wiring 3510 extending in the X direction is sequentially selected and an input voltage is input.

FIG. 36B is an equivalent circuit diagram in the writing period. In the writing period, a common potential is input to both the wiring 3510 extending in the X direction and the wiring 3511 extending in the Y direction.

FIG. 36C is an equivalent circuit diagram at a certain point in the detection period. In the detection period, each of the wirings 3511 extending in the Y direction is electrically connected to the detection circuit. In addition, among the wirings 3510 extending in the X direction, an input voltage is input to selected ones, and a common potential is input to the other wirings.

As described above, it is preferable to provide the image writing period and the period for sensing by the touch sensor independently. Thereby, it is possible to suppress a decrease in sensitivity of the touch sensor due to noise at the time of pixel writing.

(Embodiment 11)
In this embodiment, a driving method for reducing power consumption of a display device will be described.
With the driving method of this embodiment, power consumption of a display device in which an oxide semiconductor transistor is used for a pixel can be further reduced. Hereinafter, the reduction in power consumption of a liquid crystal display device which is an example of a display device will be described with reference to FIGS.

FIG. 37 is a block diagram illustrating a configuration example of the liquid crystal display device of the present embodiment. As shown in FIG. 37, the liquid crystal display device 500 includes a liquid crystal panel 501 as a display module, and further includes a control circuit 510 and a counter circuit 520.

The liquid crystal display device 500 receives an image signal (Video) that is digital data and a synchronization signal (SYNC) for controlling rewriting of the screen of the liquid crystal panel 501. Examples of the synchronization signal include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a reference clock signal (CLK).

The liquid crystal panel 501 includes a display unit 530, a scanning line driving circuit 540, and a data line driving circuit 5.
50. The display portion 530 includes a plurality of pixels 531. The pixels 531 in the same row are connected to the scan line driver circuit 540 by a common scan line 541, and the pixels 531 in the same column are connected to the data line driver circuit 550 by a common data line 551.

The liquid crystal panel 501 has a common voltage (Vcom) and a high power supply voltage (Vcom) as a power supply voltage.
VDD) and a low power supply voltage (VSS). The common voltage (Vcom) is displayed on the display 5
30 pixels 531 are supplied.

The data line driver circuit 550 processes the input image signal, generates a data signal, and outputs the data signal to the data line 551. The scan line driver circuit 540 outputs a scan signal for selecting the pixel 531 to which the data signal is written to the scan line 541.

The pixel 531 includes a switching element whose electrical connection with the data line 551 is controlled by a scanning signal. When the switching element is turned on, a data signal is written from the data line 551 to the pixel 531.

  The electrode to which Vcom is applied corresponds to the common electrode.

The control circuit 510 is a circuit that controls the entire liquid crystal display device 500, and the liquid crystal display device 50.
A circuit for generating a control signal of a circuit constituting the zero.

The control circuit 510 includes a control signal generation circuit that generates control signals for the scanning line driving circuit 540 and the data line driving circuit 550 from the synchronization signal (SYNC). The control signal for the scan line driver circuit 540 includes a start pulse (GSP), a clock signal (GCLK), and the like, and the control signal for the data line driver circuit 550 includes a start pulse (SSP) and a clock signal (SC
LK). For example, the control circuit 510 generates a plurality of clock signals having the same period and shifted phases as the clock signals (GCLK, SCLK).

The control circuit 510 also receives an image signal (Vide) input from the outside of the liquid crystal display device 500.
o) The output to the data line driving circuit 550 is controlled.

The data line driving circuit 550 includes a digital / analog conversion circuit (hereinafter referred to as a DA conversion circuit 55).
Call it 2. ). The DA conversion circuit 552 performs analog conversion on the image signal to generate a data signal.

When the image signal input to the liquid crystal display device 500 is an analog signal, the control circuit 510 converts the image signal into a digital signal and outputs the digital signal to the liquid crystal panel 501.

The image signal is image data for each frame. The control circuit 510 has a function of performing image processing on the image signal and controlling output of the image signal to the data line driver circuit 550 based on information obtained by the processing. Therefore, the control circuit 510 includes a motion detection unit 511 that detects motion from image data for each frame. When the motion detector 511 determines that there is no motion, the control circuit 510 stops outputting the image signal to the data line driver circuit 550, and when it determines that there is motion, it resumes outputting the image signal.

There is no particular restriction on image processing for motion detection performed by the motion detection unit 511. For example, as a motion detection method, for example, there is a method of obtaining difference data from image data between two consecutive frames. The presence or absence of motion can be determined from the obtained difference data. There is also a method for detecting a motion vector.

In addition, the liquid crystal display device 500 can be provided with an image signal correction circuit that corrects an input image signal. For example, the image signal is corrected so that a voltage higher than the voltage corresponding to the gradation of the image signal is written to the pixel 531. By performing such correction, the response time of the liquid crystal element can be shortened. The method of correcting the image signal and driving the control circuit 510 in this manner is called overdrive driving. In addition, when performing double speed driving in which the liquid crystal display device 500 is driven at an integer multiple of the frame frequency of the image signal, the control circuit 510 creates image data that interpolates between the two frames, or creates black data between the two frames. Image data for display may be generated.

Hereinafter, using the timing chart shown in FIG. 38, an image having a motion like a moving image,
An operation of the liquid crystal display device 500 for displaying an image having no motion such as a still image will be described.
In FIG. 38, the vertical synchronization signal (Vsync) and the data line 5 from the data line driving circuit 550 are shown.
The signal waveform of the data signal (Vdata) output to 51 is shown.

FIG. 38 is a timing chart of the liquid crystal display device 500 in a 3 m frame period. Here, it is assumed that there is a motion in the image data in the first k frame period and the last j frame period, and there is no motion in the image data in the other frame periods. K and j are 1 each.
It is an integer of m-2 or less.

In the first k frame period, the motion detector 511 determines that there is motion in the image data of each frame. The control circuit 510 outputs a data signal (Vdata) to the data line 551 based on the determination result of the motion detection unit 511.

Then, when the motion detection unit 511 performs image processing for motion detection and determines that there is no motion in the image data of the (k + 1) th frame, the control circuit 510, based on the determination result of the motion detection unit 511, In the period, the image signal (Vid) to the data line driver circuit 550
The output of eo) is stopped. Accordingly, the output of the data signal (Vdata) from the data line driver circuit 550 to the data line 551 is stopped. Further, in order to stop rewriting of the display portion 530, supply of control signals (a start pulse signal, a clock signal, and the like) to the scan line driver circuit 540 and the data line driver circuit 550 is stopped. In the control circuit 510, the motion detector 51
1, output of image signals to the data line driver circuit 550 and output of control signals to the scanning line driver circuit 540 and the data line driver circuit 550 are stopped until a determination result that there is movement in the image data is obtained. Then, the rewriting of the display unit 530 is stopped.

Note that in this specification, “does not supply a signal” to a liquid crystal panel means that a voltage different from a predetermined voltage for operating a circuit is applied to a wiring that supplies the signal, or the wiring is electrically connected It means to make it float.

When the rewriting of the display portion 530 is stopped, an electric field in the same direction is continuously applied to the liquid crystal element, and the liquid crystal of the liquid crystal element may be deteriorated. If such a problem becomes apparent,
Regardless of the determination result of the motion detection unit 511, a signal is supplied from the control circuit 510 to the scanning line driver circuit 540 and the data line driver circuit 550 at a predetermined timing, and a data signal with the polarity reversed is written to the data line 551. The direction of the electric field applied to the liquid crystal element may be reversed.

Note that the polarity of the data signal input to the data line 551 is determined based on Vcom.
The polarity is positive when the voltage of the data signal is higher than Vcom, and negative when it is lower.

Specifically, as shown in FIG. 38, in the (m + 1) th frame period, the control circuit 510 outputs a control signal to the scanning line driver circuit 540 and the data line driver circuit 550, and outputs an image signal to the data line driver circuit 550. Video is output. The data line driver circuit 550 outputs to the data line 551 a data signal (Vdata) whose polarity is inverted with respect to the data signal (Vdata) output to the data line 551 in the k-th frame period. Therefore, the data signal (Vdata) with the polarity reversed is written to the data line 551 in the (m + 1) th frame period and the (2m + 1) th frame period in which no motion is detected in the image data. Since the display unit 530 is rewritten intermittently during a period in which there is no change in image data, it is possible to prevent deterioration of the liquid crystal element while reducing power consumption due to rewriting.

When the motion detection unit 511 determines that there is motion in the image data after the 2m + 1th frame, the control circuit 510 causes the scanning line driving circuit 540 and the data line driving circuit 550 to move.
And the display portion 530 is rewritten.

As described above, according to the driving method of FIG. 38, the polarity of the data signal (Vdata) is inverted every m frame periods regardless of whether the image data (Video) is moving. On the other hand, regarding the rewriting of the display unit 530, the display unit 530 is rewritten every frame during the display period of an image including motion, and the display unit 530 is displayed every m frames during the display period of an image without motion.
Will be rewritten. As a result, power consumption accompanying rewriting of the display portion can be reduced. Therefore, an increase in power consumption due to an increase in driving frequency and the number of pixels can be suppressed.

As described above, the liquid crystal display device 500 maintains the display quality by suppressing the deterioration of the liquid crystal by changing the driving method of the liquid crystal display device between the mode for displaying moving images and the mode for displaying still images. However, a power-saving liquid crystal display device can be provided.

In addition, when displaying a still image, if the pixel is rewritten every frame, the human eye may feel the pixel rewriting as flickering, which causes tired eyes. The liquid crystal display device of this embodiment is effective in reducing tired eyes because the frequency of pixel rewriting is low during the still image display period.

Therefore, by using a liquid crystal panel in which a backplane is formed using an oxide semiconductor transistor, it is possible to provide a high-definition, low-power-consumption medium-sized display liquid crystal display device that is very suitable for portable electronic devices. .

In order to prevent deterioration of the liquid crystal, the polarity inversion interval (here, m frame period) of the data signal is 2 seconds or less, preferably 1 second or less.

Although the motion detection of the image data is performed by the motion detection unit 511 of the control circuit 510, the motion detection need not be performed only by the motion detection unit 511. Data on the presence or absence of movement is displayed on the liquid crystal display device 500.
May be input to the control circuit 510 from the outside.

Further, the condition for determining that there is no motion in the image data is not based on the image data between two consecutive frames, and the number of frames necessary for the determination can be appropriately determined according to the usage mode of the liquid crystal display device 500. . For example, rewriting of the display unit 530 may be stopped when there is no movement in the image data of continuous m frames.

Note that although a liquid crystal display device is used as a display device in this embodiment mode, the driving method of this embodiment mode can be used for another display device such as a light-emitting display device.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 12)
The semiconductor device which is one embodiment of the present invention can be applied to a variety of electronic devices (including game machines). As the electronic device, a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, Sound reproducing devices, gaming machines (pachinko machines, slot machines, etc.), and game cases are listed. Examples of these electronic devices are illustrated in FIGS.

FIG. 39A illustrates a table 9000 having a display portion. In the table 9000, a display portion 9003 is incorporated in a housing 9001, and an image can be displayed on the display portion 9003. Note that a structure in which the housing 9001 is supported by four legs 9002 is shown. In addition, the housing 9001 has a power cord 9005 for supplying power.

The semiconductor device described in any of the above embodiments can be used for the display portion 9003. Therefore, display quality of the display portion 9003 can be improved.

The display portion 9003 has a touch input function and the display portion 9003 of the table 9000.
By touching the display button 9004 displayed on the screen with a finger or the like, screen operation, information can be input, communication with other home appliances can be performed, or control can be performed.
It is good also as a control apparatus which controls other household appliances by screen operation. For example, when a semiconductor device having an image sensor function is used, the display portion 9003 can have a touch input function.

Further, the hinge of the housing 9001 can be used to stand the screen of the display portion 9003 perpendicular to the floor, which can be used as a television device. In a small room,
When a television device with a large screen is installed, the free space becomes narrow, but if the display portion is built in the table, the room space can be used effectively.

FIG. 39B illustrates a television device 9100. Television apparatus 9100
The display portion 9103 is incorporated in the housing 9101 and an image can be displayed on the display portion 9103. Note that here, a structure in which the housing 9101 is supported by a stand 9105 is illustrated.

The television device 9100 can be operated with an operation switch included in the housing 9101 or a separate remote controller 9110. Channels and volume can be operated with an operation key 9109 provided in the remote controller 9110, and an image displayed on the display portion 9103 can be operated. The remote controller 9110 may be provided with a display portion 9107 for displaying information output from the remote controller 9110.

A television device 9100 illustrated in FIG. 39B includes a receiver, a modem, and the like.
The television device 9100 can receive a general television broadcast by a receiver.
In addition, by connecting to a wired or wireless communication network via a modem, information communication in one direction (from sender to receiver) or bidirectional (between sender and receiver, or between receivers) is performed. Is also possible.

The semiconductor device described in any of the above embodiments can be used for the display portions 9103 and 9107. Therefore, the display quality of the television device can be improved.

FIG. 39C illustrates a computer 9200, which includes a main body 9201, a housing 9202, and a display portion 9.
203, keyboard 9204, external connection port 9205, pointing device 920
6 etc. are included.

The semiconductor device described in any of the above embodiments can be used for the display portion 9203. Therefore, the display quality of the computer 9200 can be improved.

The display portion 9203 has a touch input function and the display portion 92 of the computer 9200.
By touching the display button 9004 displayed in 03 with a finger or the like, screen operation, information can be input, communication with other home appliances can be performed, or control can be performed. It is good also as a control apparatus which controls other household appliances by screen operation.

40A and 40B illustrate a tablet terminal that can be folded. FIG.
) Is an open state, and the tablet terminal includes a housing 9630, a display portion 9631a, a display portion 9631b, a display mode change switch 9034, a power switch 9035, a power saving mode change switch 9036, a fastener 9033, and an operation switch 9038. Have.

The semiconductor device described in any of the above embodiments includes a display portion 9631a and a display portion 9631b.
Can be used. Therefore, the display quality of the tablet terminal can be improved.

Part of the display portion 9631 a can be a touch panel region 9632 a and data can be input when a displayed operation key 9638 is touched. The display unit 96
In FIG. 31a, as an example, a configuration in which half of the area has a display-only function and a configuration in which the other half has a touch panel function is shown, but the configuration is not limited thereto. Display unit 96
All the regions 31a may have a touch panel function. For example, the display unit 9
The entire surface of 631a can be displayed as a keyboard button and used as a touch panel, and the display portion 9631b can be used as a display screen.

Further, in the display portion 9631b, as in the display portion 9631a, part of the display portion 9631b can be a touch panel region 9632b. Further, a keyboard button can be displayed on the display portion 9631b by touching a position where the keyboard display switching button 9539 on the touch panel is displayed with a finger or a stylus.

Touch input can be performed simultaneously on the touch panel region 9632a and the touch panel region 9632b.

A display mode switching switch 9034 can switch the display direction such as vertical display or horizontal display, and can select switching between monochrome display and color display. The power saving mode change-over switch 9036 can optimize the display luminance in accordance with the amount of external light during use detected by an optical sensor built in the tablet terminal. The tablet terminal may include not only an optical sensor but also other detection devices such as a gyroscope, an acceleration sensor, and other sensors that detect inclination.

FIG. 40A illustrates an example in which the display areas of the display portion 9631b and the display portion 9631a are the same, but there is no particular limitation. One size and the other size may be different, and the display quality is also high. May be different. For example, one display panel may be capable of displaying images with higher definition than the other.

FIG. 40B illustrates a closed state, in which the tablet terminal includes a housing 9630, a solar cell 9
633 and a charge / discharge control circuit 9634. In FIG. 40B, the charge / discharge control circuit 96 is used.
34, a configuration including a battery 9635 and a DCDC converter 9636 is shown.

Note that since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Therefore, since the display portion 9631a and the display portion 9631b can be protected,
It is possible to provide a tablet terminal with excellent durability and high reliability from the viewpoint of long-term use.

In addition, the tablet terminal shown in FIGS. 40A and 40B has a function for displaying various information (still images, moving images, text images, etc.), a calendar, a date, or a time. A function for displaying on the display unit, a touch input function for performing touch input operation or editing of information displayed on the display unit, a function for controlling processing by various software (programs), and the like can be provided.

Electric power can be supplied to the touch panel, the display unit, the video signal processing unit, or the like by the solar battery 9633 mounted on the surface of the tablet terminal. Note that the solar cell 9633 is preferable because it can be provided on one or both surfaces of the housing 9630 and the battery 9635 can be charged efficiently. Note that as the battery 9635, when a lithium ion battery is used, there is an advantage that reduction in size can be achieved.

Further, the structure and operation of the charge / discharge control circuit 9634 illustrated in FIG.
C) will be described with reference to a block diagram. FIG. 40C illustrates a solar cell 9633, a battery 9
635, DCDC converter 9636, converter 9637, switches SW1 to SW3
, A display portion 9631, a battery 9635, a DCDC converter 963
6, the converter 9637 and the switches SW1 to SW3 are portions corresponding to the charge / discharge control circuit 9634 shown in FIG.

First, an example of operation in the case where power is generated by the solar cell 9633 using external light is described. The electric power generated by the solar cell becomes a voltage for charging the battery 9635 D
The CDC converter 9636 performs step-up or step-down. When power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on, and the converter 9637 increases or decreases the voltage required for the display portion 9631. In the case where display on the display portion 9631 is not performed, the battery 9635 may be charged by turning off the switch SW1 and turning on the switch SW2.

Note that although the solar cell 9633 is shown as an example of the power generation unit, the configuration is not particularly limited, and the battery 9635 is charged by another power generation unit such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). It may be. For example, a non-contact power transmission module that wirelessly (contactlessly) transmits and receives power for charging and other charging means may be combined.

Note that the structure and the like described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

In this example, Vg-Id characteristics of a transistor and measurement results of an optical BT stress test will be described.

First, a manufacturing process of the transistor included in Sample 1 is described. This embodiment will be described with reference to FIG.

First, as illustrated in FIG. 2A, a glass substrate was used as the substrate 11, and the gate electrode 15 was formed over the substrate 11.

A tungsten film having a thickness of 100 nm was formed by a sputtering method, a mask was formed over the tungsten film by a photolithography process, and a part of the tungsten film was etched using the mask to form the gate electrode 15.

  Next, a gate insulating film 17 (corresponding to GI in FIG. 41) was formed on the gate electrode 15.

As the gate insulating film 17, a first silicon nitride film having a thickness of 50 nm, a second silicon nitride film having a thickness of 300 nm, a third silicon nitride film having a thickness of 50 nm, and a silicon oxynitride film having a thickness of 50 nm are stacked. Formed.

The first silicon nitride film supplies silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and ammonia at a flow rate of 100 sccm as a source gas to the processing chamber of the plasma CVD apparatus, and controls the pressure in the processing chamber to 100 Pa, 27.12 MHz. A high frequency power source of 2000 W was used to supply 2000 W of power.

Next, the flow rate of ammonia is set to 2000 under the conditions of the source gas of the first silicon nitride film.
A second silicon nitride film was formed by changing to sccm.

Next, silane having a flow rate of 200 sccm and nitrogen having a flow rate of 5000 sccm are supplied as source gases to the processing chamber of the plasma CVD apparatus, and the pressure in the processing chamber is controlled to 100 Pa.
A third silicon nitride film was formed by supplying 2000 W of power using a 2 MHz high frequency power source.

Next, silane having a flow rate of 20 sccm and dinitrogen monoxide having a flow rate of 3000 sccm are supplied as source gases to the processing chamber of the plasma CVD apparatus, and the pressure in the processing chamber is controlled to 40 Pa. 27.
A silicon oxynitride film was formed by supplying power of 100 W using a 12 MHz high frequency power source.

Note that the substrate temperature was set to 350 ° C. in the steps of forming the first silicon nitride film to the third silicon nitride film and the silicon oxynitride film.

  Next, the multilayer film 20 was formed so as to overlap the gate electrode 15 with the gate insulating film 17 interposed therebetween.

Here, after an oxide semiconductor film having a thickness of 35 nm (corresponding to S2 in FIG. 41) is formed over the gate insulating film 17 by a sputtering method, an oxide film having a thickness of 20 nm is formed over the oxide semiconductor film (FIG. 4).
1 corresponding to S3). Next, a mask was formed over the oxide film by a photolithography process, and the oxide semiconductor film and part of the oxide film were etched using the mask, so that the oxide semiconductor film 18 and the oxide film 19 were formed. Then, the 1st heat processing was performed and the multilayer film 20 was formed.

For the oxide semiconductor film (S2), a sputtering target is In: Ga: Zn = 1: 1:
1 target (atomic ratio), argon at a flow rate of 100 sccm and a flow rate of 100 scc
It was formed by supplying m oxygen as a sputtering gas into the processing chamber of the sputtering apparatus, controlling the pressure in the processing chamber to 0.6 Pa, and supplying DC power of 5 kW. Note that the substrate temperature in forming the oxide semiconductor film was 200 ° C.

The oxide film (S3) has a sputtering target of In: Ga: Zn = 1: 3: 2 (atomic ratio), 180 sccm of Ar and 20 sc as a sputtering gas.
It was formed by supplying cm of oxygen into the processing chamber of the sputtering apparatus, controlling the pressure in the processing chamber to 0.6 Pa, and supplying DC power of 5 kW. Note that the substrate temperature when forming the oxide film was set to 200 ° C.

In the first heat treatment, heat treatment was performed at 350 ° C. for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 350 ° C. for 1 hour in a nitrogen and oxygen atmosphere.

  The structure obtained through the steps up to here can be referred to FIG.

Next, after part of the gate insulating film 17 was etched to expose the gate electrode (not shown), a pair of electrodes 21 and 22 in contact with the multilayer film 20 was formed as shown in FIG. .

Here, a conductive film is formed over the gate insulating film 17 and the multilayer film 20. As the conductive film,
An aluminum film having a thickness of 400 nm was formed on a tungsten film having a thickness of 50 nm, and a titanium film having a thickness of 100 nm was formed on the aluminum film. Next, a mask was formed over the conductive film by a photolithography process, and part of the conductive film was wet-etched using the mask to form a pair of electrodes 21 and 22. Thereafter, the surface of the multilayer film 20 was washed with a phosphoric acid aqueous solution in which 85% phosphoric acid was diluted 100 times.

Next, the substrate is moved to a depressurized processing chamber and heated at 220 ° C., and then 150 W of high frequency power is supplied to the upper electrode provided in the processing chamber using a 27.12 MHz high frequency power source. The multilayer film 20 was exposed to oxygen plasma generated in a nitrogen atmosphere.

Next, the protective film 26 was formed over the multilayer film 20 and the pair of electrodes 21 and 22 (see FIG. 2D). Here, as the protective film 26, the oxide insulating film 23 (corresponding to P1 in FIG. 41), the oxide insulating film 24 (corresponding to P2 in FIG. 41), and the nitride insulating film 25 were formed.

First, after the plasma treatment, the oxide insulating film 23 and the oxide insulating film 24 were continuously formed without being exposed to the atmosphere. A 50-nm-thick silicon oxynitride film was formed as the oxide insulating film 23, and a 400-nm-thick silicon oxynitride film was formed as the oxide insulating film 24.

The oxide insulating film 23 is a plasma in which silane having a flow rate of 30 sccm and dinitrogen monoxide having a flow rate of 4000 sccm are used as a raw material gas, a processing chamber pressure is 200 Pa, a substrate temperature is 220 ° C., and 150 W high-frequency power is supplied to parallel plate electrodes. It formed by CVD method.

The oxide insulating film 24 is formed by using silane having a flow rate of 200 sccm and dinitrogen monoxide having a flow rate of 4000 sccm as a source gas, a processing chamber pressure of 200 Pa, a substrate temperature of 220 ° C., and 1500.
It formed by the plasma CVD method which supplied the high frequency electric power of W to the parallel plate electrode. Under such conditions, a silicon oxynitride film containing more oxygen than that in the stoichiometric composition and from which part of oxygen is released by heating can be formed.

Next, second heat treatment is performed, so that water, nitrogen,
Hydrogen and the like were desorbed and a part of oxygen contained in the oxide insulating film 24 was supplied to the multilayer film 20. Here, heat treatment was performed at 350 ° C. for 1 hour in a nitrogen and oxygen atmosphere.

Next, a nitride insulating film 25 was formed over the oxide insulating film 24. Here, the nitride insulating film 2
5, a silicon nitride film having a thickness of 100 nm was formed.

The nitride insulating film 25 uses silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia with a flow rate of 100 sccm as a source gas, a processing chamber pressure of 100 Pa, a substrate temperature of 350 ° C., and 1000 W of high-frequency power applied to parallel plate electrodes. It formed by the supplied plasma CVD method.

Next, although not shown, a part of the protective film 26 was etched to form an opening exposing a part of the pair of electrodes 21 and 22.

Next, a planarizing film was formed on the nitride insulating film 25 (not shown). Here, after the composition was applied on the nitride insulating film 25, exposure and development were performed to form a planarization film having an opening for exposing part of the pair of electrodes. Note that an acrylic resin having a thickness of 1.5 μm was formed as the planarizing film. After that, heat treatment was performed. The heat treatment was performed in an atmosphere containing nitrogen at a temperature of 250 ° C. for 1 hour.

Next, a conductive film connected to part of the pair of electrodes was formed (not shown). Here, ITO containing silicon oxide with a thickness of 100 nm was formed by a sputtering method. Thereafter, heat treatment was performed at 250 ° C. for 1 hour in a nitrogen atmosphere.

  Through the above process, Sample 1 including a transistor was manufactured.

In the transistor of Sample 1, the multilayer film 20 has a three-layer structure, and the gate insulating film 17
An oxide film having a thickness of 5 nm (corresponding to S1 in FIG. 41) is formed between the oxide film 19 and the oxide semiconductor film 18 under the same conditions as the oxide film 19, and the oxide film 19 (in FIG. 41). A sample having a transistor manufactured with a thickness of 15 nm (corresponding to S3) is referred to as a sample 2.

In the transistor of Sample 1, the multilayer film 20 has a three-layer structure, and the gate insulating film 17
A sample including a transistor in which an oxide film having a thickness of 10 nm (corresponding to S1 in FIG. 41) is formed between the oxide semiconductor film 18 and the oxide semiconductor film 18 under the same conditions as the oxide film 19 is referred to as a sample 3.

In the transistor of Sample 1, only the oxide semiconductor film 18 is formed instead of the multilayer film 20, the heating temperature is 450 ° C. in the first heat treatment, and the pressure is set in the film formation conditions of the oxide insulating film 23. A sample including a transistor manufactured at 40 Pa and having a silane flow rate of 160 sccm under the deposition conditions of the oxide insulating film 24 is referred to as a comparative sample 1.

In addition, in the transistor of Sample 1, a sample including a transistor in which only the oxide semiconductor film 18 is formed instead of the multilayer film 20 and the heating temperature is 350 ° C. in the first heat treatment is referred to as Comparative Sample 2.

Note that the transistor included in each sample has a channel length (L) of 6 μm and a channel width (W
) Is 50 μm.

Next, as initial characteristics of the transistors included in Sample 1 to Sample 3 and Comparative Sample 1, V
The g-Id characteristic was measured. Here, the substrate temperature is 25 ° C., the source-drain potential difference (hereinafter referred to as drain voltage) is 1 V and 10 V, and the source-gate electrode potential difference (hereinafter referred to as gate voltage) is −15 V to +15 V. Characteristic of the current flowing between the source and drain (hereinafter referred to as drain current), that is, Vg-Id
Characteristics were measured.

FIG. 41 shows Vg-Id characteristics of transistors included in each sample. In each graph shown in FIG. 41, the horizontal axis represents the gate voltage Vg, the left vertical axis represents the drain current Id, and the right vertical axis represents the field effect mobility. The horizontal axis is shown as -15V to 15V. The solid lines indicate the Vg-Id characteristics when the drain voltage Vd is 1V and 10V, respectively, and the broken lines indicate the field effect mobility with respect to the gate voltage when the drain voltage Vd is 10V. In addition,
The field effect mobility is a result in the saturation region of each sample.

  In each sample, 20 transistors with the same structure were manufactured in the substrate.

From FIG. 41, it can be seen that good switching characteristics are obtained in each of Sample 1 to Sample 3 and Comparative Sample 1.

Next, BT stress test and optical BT stress test of Sample 1 to Sample 3 and Comparative Sample 1 were performed. The BT stress test is a kind of accelerated test, and it is possible to evaluate a change in characteristics (that is, a change with time) of a transistor caused by long-term use in a short time. Examining the amount of variation in transistor characteristics before and after the BT stress test is an important index for investigating reliability.

  First, a gate BT stress test and an optical gate BT stress test were performed.

Here, a measurement method of the gate BT stress test will be described. First, as described above, the Vg-Id characteristic in the initial characteristic of the transistor is measured.

Next, the substrate temperature is maintained at an arbitrary temperature (hereinafter referred to as stress temperature), a pair of electrodes functioning as a source and a drain of a transistor are set to the same potential, and a pair of electrodes functioning as a source electrode and a drain electrode Is applied to the gate electrode for a certain period of time (hereinafter referred to as stress time). Next, the substrate temperature is set as appropriate, and the electrical characteristics of the transistor are measured. As a result, the difference between the threshold voltage and the shift value in the electrical characteristics before and after the gate BT stress test can be obtained as the fluctuation amount.

A stress test in which a negative voltage is applied to the gate electrode is referred to as a negative gate BT stress test (Dark-GBT), and a stress test in which a positive voltage is applied is defined as a positive gate BT.
This is called a stress test (Dark + GBT). In addition, a stress test in which a negative voltage is applied to the gate electrode while irradiating light is referred to as an optical minus gate BT stress test (Photo-GBT
), A stress test that applies a positive voltage is an optical plus gate BT stress test (Pho)
to + GBT).

Here, as the gate BT stress condition, the stress temperature is 60 ° C. and the stress time is 3
600 seconds, -30V or + 30V for the gate electrode, 0 for the source and drain electrodes
V was applied. The electric field strength applied to the gate insulating film at this time was 0.66 MV / cm.

Further, using the same conditions as in the above BT stress test, a light gate BT stress test was performed by irradiating the transistor with white LED light of 10000 lx. Note that the measurement temperature of the Vg-Id characteristic of the transistor after the BT stress test was set to 60 ° C.

Difference between the threshold voltage of the initial characteristics of the transistors included in Sample 1 to Sample 3 and Comparative Sample 1 and the threshold voltage after the BT stress test (that is, threshold voltage fluctuation amount (ΔVth))
FIG. 42A shows the difference between the shift values (that is, the shift amount variation (ΔShift)). In FIG. 42A, a plus gate BT stress test (Dark + GBT), a minus gate BT stress test (Dark−GBT), and an optical plus gate BT stress test (P
photo + GBT) and light minus gate BT stress test (Photo-GBT).

Next, the stress test was performed by changing the stress temperature. Here, the gate BT stress test was performed at a stress temperature of 125 ° C. under the conditions of the gate BT stress test. Note that the measurement temperature of the Vg-Id characteristic of the transistor after the gate BT stress test is 4
The temperature was 0 ° C.

FIG. 42B shows threshold voltage variation (ΔVth) and shift value variation (ΔShift) included in Samples 1 to 3 and Comparative Sample 1. FIG. In FIG. 42B, a plus gate BT stress test (Dark + GBT), a minus gate BT stress test (D
ark-GBT) indicates the amount of variation.

Here, the threshold voltage and the shift value in this specification will be described with reference to FIG.

In this specification, the threshold voltage (Vth) is the gate voltage (Vg [V]) on the horizontal axis,
In the curve 612 in which the square root of the drain current (Id ^1/2 [A]) is plotted as the vertical axis, the tangent line 614 and the Vg axis (ie, Id ^1/2 ) when the tangent line 614 of Id ^1/2 that is the maximum slope is extrapolated. ^It is defined by the gate voltage at the intersection with ^1/2 being 0 A) (see FIG. 43A). In addition,
In this specification, the threshold voltage is calculated by setting the drain voltage Vd to 10V. In this specification, the threshold voltage (Vth) is an average value of Vth of each of the 20 transistors included in each sample.

In this specification, the shift value (Shift) has a maximum slope in a curve 616 in which the gate voltage (Vg [V]) is plotted on the horizontal axis and the logarithm of the drain current (Id [A]) is plotted on the vertical axis. It is defined by the gate voltage at the intersection with the straight line Id = 1.0 × 10 ⁻¹² [A] when a tangent line 618 of a certain Id is extrapolated (see FIG. 43B). In the present specification, the shift value is calculated by setting the drain voltage Vd to 10V. Further, in this specification, the shift value is an average value of shift values of 20 transistors included in each sample.

42A, compared with the comparative sample 1, the samples 1 to 3 are minus gate BT.
It can be seen that the amount of fluctuation in the stress test (Dark-GBT) is small. It can also be seen that the amount of fluctuation in the optical minus gate BT stress test (Photo-GBT) is small.

It can also be seen that sample 2 has less variation in each stress test than sample 1 and sample 3. From this, it can be seen that the variation amount of the threshold voltage and the shift value can be reduced by making the multilayer film into three layers and reducing the thickness of the first oxide film.

From FIG. 42B, compared with the comparative sample 1, the samples 1 to 3 are minus gate BT.
It can be seen that the amount of fluctuation in the stress test (Dark-GBT) is small.

From the above, in the heat treatment for desorbing impurities from the oxide semiconductor film and the multilayer film, by providing the oxide film in contact with the oxide semiconductor film even when the heating temperature is reduced from 450 ° C. to 350 ° C., It can be seen that the amount of variation in transistor characteristics can be reduced.

Next, in Sample 1 and Sample 2, and Comparative Sample 1 and Comparative Sample 2, plus gate B
A T-stress test (Dark + GBT) was performed. Here, the stress temperature is 60 ° C. or 125 ° C., and the stress time is 100 seconds, 500 seconds, 1500 seconds,
The amount of change in threshold voltage was measured at 2000 seconds and 3600 seconds. FIG. 44 shows the variation amount of the threshold voltage at each stress time and an approximate curve obtained from each variation amount. The horizontal axis represents the stress time, and the vertical axis represents the threshold voltage fluctuation amount (ΔVth). 44A shows the measurement results when the stress temperature is 60 ° C., and FIG. 44B shows the stress temperature of 125 ° C.
It is a measurement result at the time of ° C.

From FIG. 44, it can be seen that the variation amount of the threshold voltage of sample 1 and sample 2 is smaller than that of comparative sample 2. Accordingly, even when the temperature of the multilayer film or the oxide semiconductor film is lowered from 450 ° C. to 350 ° C., by providing an oxide in contact with the oxide semiconductor film, that is, by forming a multilayer film, transistor characteristics It was found that the fluctuation amount of can be reduced.

In addition, although the variation amount of the transistor characteristics of Sample 1 and Sample 2 is slightly larger than that of Comparative Sample 1, it can be seen that the variation amount is equivalent to that of Comparative Sample 1.

Next, a positive gate BT stress test (Dark + GBT) was performed on Sample 1, Sample 2, and Comparative Sample 2. Here, the fluctuation amount of the threshold voltage was measured by setting the stress temperature to 125 ° C. and the stress time to 3600 seconds. Note that the measurement temperature of the Vg-Id characteristic of the transistor after the gate BT stress test was 40 ° C.

Sample 1 and sample 2 and comparative sample 2 were subjected to a negative source BT stress test (Dark-SBT). The source BT stress test is a kind of accelerated test similar to the gate BT stress test, and it is possible to evaluate a change in characteristics (that is, a change with time) of a transistor caused by long-term use in a short time.

Here, a measurement method of the source BT stress test will be described. First, as described above, the Vg-Id characteristic in the initial characteristic of the transistor is measured.

Next, an arbitrary temperature is kept constant, the gate electrode and the drain electrode of the transistor are set to the same potential, and a potential different from the gate electrode and the drain electrode is applied to the source electrode in a pulsed manner. Next, the substrate temperature is set in the same manner as when measuring the electrical characteristics, and the electrical characteristics of the transistor are measured. As a result, it is possible to observe the fluctuation amount of the electrical characteristics before and after the source BT stress test.

Here, as source BT stress conditions, the stress temperature is 125 ° C., the stress time is 3600 seconds, the pulse frequency is 60 Hz (period is 16.7 milliseconds), and the application time is 0.00.
-30 V was applied in a pulsed manner to the source electrode as 6% (100 μsec). In addition, 0 V was applied to the gate electrode and the drain electrode. Note that the measurement temperature of the Vg-Id characteristic of the transistor after the source BT stress test was 40 ° C.

Vg− in the initial characteristics of the transistors included in Sample 1 and Sample 2 and Comparative Sample 2
FIG. 45 shows the Id characteristics and the Vg-Id characteristics of the transistor after the stress test. In FIG. 45, the measurement result of the plus gate BT stress test (Dark + GBT) is shown in the upper stage, and the measurement result of the minus source BT stress test (Dark-SBT) is shown in the lower stage. Note that the thin solid line indicates the Vg-Id characteristic in the initial characteristics of the transistor, and the thick solid line indicates the Vg-Id characteristic of the transistor after the stress test. The Vg-Id characteristics when the drain voltage Vd is 1V and 10V, respectively. The thin broken line indicates the field effect mobility in the initial characteristics of the transistor, and the thick broken line indicates the field effect mobility in the transistor after the stress test. The field effect mobility with respect to the gate voltage when the drain voltage Vd is 10 V is shown.

Compared with Comparative Sample 2, in Sample 1 and Sample 2, both the positive gate BT stress test (Dark + GBT) and the negative source BT stress test (Dark-SBT) have reduced threshold voltage variation after the stress test. I understand that Further, in the positive gate BT stress test (Dark + GBT), in the comparative sample 2, the on-current is reduced after the stress test, but in the sample 1 and the sample 2, the on-current is not reduced. From the above, when the heat treatment temperature for desorbing impurities from the oxide semiconductor film and the multilayer film is a relatively low temperature of 350 ° C., a multilayer film having an oxide film in contact with the oxide semiconductor film is obtained. It was found that the fluctuation amount of the electrical characteristics of the transistor can be reduced.

Claims (2)

Forming a gate electrode and a gate insulating film on the substrate;
Forming an oxide semiconductor film on the gate insulating film;
Forming an oxide film on the oxide semiconductor film;
The oxide semiconductor film and the oxide film each include In, Ga, and Zn,
The atomic ratio of Ga to In of the oxide film is larger than the atomic ratio of Ga to In of the oxide semiconductor film,
After forming the oxide film, a first heat treatment is performed,
After the first heat treatment, a pair of electrodes in contact with the oxide film is formed,
Forming an oxide insulating film on the pair of electrodes;
The oxide insulating film is in contact with the oxide film between the pair of electrodes,
A method for manufacturing a semiconductor device is characterized in that after the oxide insulating film is formed, second heat treatment is performed. Forming a gate electrode and a gate insulating film on the substrate;
Forming an oxide semiconductor film on the gate insulating film;
Forming an oxide film on the oxide semiconductor film;
The oxide semiconductor film and the oxide film each include In, Ga, and Zn,
The atomic ratio of Ga to In of the oxide film is larger than the atomic ratio of Ga to In of the oxide semiconductor film,
After forming the oxide film, a first heat treatment is performed,
After the first heat treatment, a pair of electrodes in contact with the oxide film is formed,
The temperature of the substrate is 180 ° C. or higher and 280 ° C. or lower, the pressure in the processing chamber is 100 Pa or higher and 250 Pa or lower, and an oxide insulating film is formed on the pair of electrodes by a plasma CVD method.
The oxide insulating film is in contact with the oxide film between the pair of electrodes,
After forming the oxide insulating film, a second heat treatment is performed,
After the second heat treatment, a temperature of the substrate is set to be 300 ° C. or higher and 400 ° C. or lower, and a nitride insulating film is formed over the oxide insulating film by a plasma CVD method.