JP6540073B2 - Circuit device, electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to a circuit device, an electro-optical device, an electronic apparatus, and the like.

  The display driver for driving the display panel requires various voltages such as the power supply of the source drive amplifier, the power supply of the gate drive amplifier, the power supply of the gradation voltage generation circuit, the common voltage of the display panel, etc. Power supply circuit to generate For example, in Patent Documents 1 and 2, a power supply circuit having a plurality of booster circuits (primary booster circuit to fourth order booster circuit) and a source operated by supplying power generated by the boosting operation of the booster circuit of the power supply circuit. There is disclosed a display driver including a driver and a gate driver.

JP 2007-212897 A JP, 2010-145738, A

  As described above, in a display driver that generates a driving power supply by a boosting operation, a large current flows in a parasitic bipolar of a boosting circuit or the like due to noise or data digitization of a register value, causing so-called power supply jamming. The boosting operation of the boosting circuit can not be restored to the normal state.

  In the case of a display driver for portable devices, even when such a power source jam occurs, the user can turn off the power source switch of the mobile device or the like to eliminate the power source jamming and restore the normal state. it can. However, in an on-vehicle display driver, for example, the power supplied to the display driver can not be turned off unless the engine is turned off, so that it is difficult to recover from the jamming of the power supply.

  According to some aspects of the present invention, there is provided a circuit device, an electro-optical device, an electronic device, etc. which can return the normal operation of the step-up operation of the step-up circuit by detecting an abnormality in the step-up voltage generated by the step-up circuit. Can be provided.

  One aspect of the present invention includes a power supply circuit having a booster circuit, and an abnormality detection circuit that detects an abnormality in a boosted voltage generated based on the boosting operation of the booster circuit, the anomaly detection circuit having a high potential side It is provided between the node of the first power supply voltage which is one of the power supply voltage and the low potential side power supply voltage and the node of the boosted voltage, and is the other of the high potential side power supply voltage and the low potential side power supply voltage. The circuit device includes a detection transistor having a gate to which an input voltage based on a second power supply voltage is input, and detects an abnormality in the boosted voltage based on a change in one of the source and the drain of the detection transistor. .

  According to one aspect of the present invention, the abnormality detection circuit can detect the abnormality of the boosted voltage based on the voltage change of one of the source and the drain of the detection transistor, whereby the abnormality of the boosted voltage generated by the booster circuit can be self-detected. . Then, since the abnormality detection circuit can detect the abnormality in the boosted voltage, it is possible to perform the recovery operation based on the detection result, and it becomes possible to restore the boosting operation of the booster circuit to a normal state.

  In one aspect of the present invention, the abnormality detection circuit may include a resistive element provided between the one of the source and the drain of the detection transistor and a node of the first power supply voltage.

  The voltage of one of the source and the drain of the detection transistor is a voltage obtained by resistively dividing the first power supply voltage and the boosted voltage by the resistance element and the on resistance of the detection transistor. When the boosted voltage changes, the other voltage of the source and drain of the detection transistor changes, so that the on-resistance of the detection transistor changes. As a result, since the resistance division ratio changes, the voltage of one of the source and the drain of the detection transistor changes, and it becomes possible to detect an abnormality in the boosted voltage.

  Further, in one aspect of the present invention, the abnormality detection circuit is provided between the one of the source and the drain of the detection transistor and a node of the first power supply voltage, and the input voltage is input to a gate. It may have a first transistor.

  The voltage of one of the source and the drain of the detection transistor is a voltage obtained by resistively dividing the first power supply voltage and the boosted voltage by the on resistance of the first transistor and the on resistance of the detection transistor. When the boosted voltage changes, the other voltage of the source and drain of the detection transistor changes, so that the on-resistance of the detection transistor changes. As a result, since the resistance division ratio changes, the voltage of one of the source and the drain of the detection transistor changes, and it becomes possible to detect an abnormality in the boosted voltage.

  In one embodiment of the present invention, a second transistor may be provided between the other of the source and the drain of the detection transistor and the node of the boosted voltage, and the drain and the gate are connected.

  As described above, by providing the second transistor in which the drain and the gate are connected to the other side of the source and the drain of the detection transistor, the detection voltage of the abnormality detection can be adjusted. That is, the second transistor is a so-called diode connection, and the voltage of the other of the source and the drain of the detection transistor is increased by the amount of the forward voltage. As a result, the gate-source voltage of the detection transistor is reduced by the amount of the forward voltage of the diode connection, and the detection voltage is adjusted.

  In one aspect of the present invention, the abnormality detection circuit may detect that the boosted voltage is abnormal when the boosted voltage exceeds a detected voltage, and the detected voltage may have hysteresis characteristics.

  Since the detection voltage has a hysteresis characteristic, when the boosted voltage is near the detection voltage, it is possible to suppress that the result of abnormality detection repeats normal / abnormal inversion.

  In one embodiment of the present invention, the abnormality detection circuit includes a buffer circuit buffering the one of the source and drain voltages of the detection transistor, the gate of the detection transistor, and a node of the second power supply voltage. And a third transistor which is turned on / off based on the output of the buffer circuit, and a first transistor provided between the node of the first power supply voltage and the gate of the detection transistor. It may have a resistive element, and a second resistive element provided between the gate of the detection transistor and the node of the second power supply voltage and connected in parallel to the third transistor.

  The output of the buffer circuit that buffers the voltage of one of the source and the drain of the detection transistor is logically inverted when an abnormality in the boosted voltage is detected, whereby the on / off of the third transistor is controlled. The third transistor is connected in parallel to the second resistance element provided between the gate of the detection transistor and the node of the second power supply voltage, so that the detection transistor is turned on / off by the third transistor. Gate voltage changes. Thus, the detected voltage has hysteresis characteristics.

  In one aspect of the present invention, the boosted voltage is a negative voltage, the first power supply voltage is the high potential side power supply voltage, and the second power supply voltage is the low potential side power supply voltage. It may be.

  According to this configuration, the detection transistor is provided between the node of the high potential side power supply voltage and the node of the boosted voltage of the negative voltage, and an input voltage based on the low potential side power supply voltage is input to the gate of the detection transistor. It will be. Since the on resistance of the detection transistor increases when the boosted voltage rises to near the low potential side power supply voltage, it is possible to detect that the boosted voltage is abnormal when the boosted voltage rises to near the low potential side power supply voltage.

  In one aspect of the present invention, the boosted voltage may be a substrate voltage of a circuit device.

  For example, when the substrate is a P substrate, the lowest voltage among the voltages generated by the power supply circuit is set as the substrate voltage. In the case where an abnormality occurs in the power supply and a current flows in the parasitic bipolar of the substrate, the current often flows finally to the substrate voltage which is the lowest voltage. Therefore, the abnormality of the power supply can be detected by detecting the abnormality of the boosted voltage which is the substrate voltage.

  In one aspect of the present invention, the control circuit may control the power supply circuit, and the control circuit may re-execute the start-up sequence of the power supply circuit when an abnormality in the boosted voltage is detected.

  When the start-up sequence is re-executed, the operation of the power supply circuit including the booster circuit is temporarily stopped, so that the current supply from the booster circuit to the parasitic transistor on the substrate is lost, and the power supply can be recovered from the abnormality.

  One embodiment of the present invention may include a drive circuit which drives a display panel based on the power supplied from the power supply circuit.

  Another aspect of the present invention is an electro-optical device characterized by including the circuit device described above and a display panel.

  Another aspect of the present invention relates to an electronic device including the circuit device described in any of the above.

The structural example of a circuit apparatus, and the 1st detailed structural example of an abnormality detection circuit. Operation | movement explanatory drawing of an abnormality detection circuit. The 2nd detailed example of composition of an unusual detection circuit. The 1st example of composition of a driver. FIG. 5A shows a second configuration example of the driver. FIG. 5B is a timing chart of a second configuration example of the driver. FIG. 6A shows a third configuration example of the driver. FIG. 6B is a timing chart of a third configuration example of the driver. The structural example of the j-th voltage booster circuit. FIG. 8A shows a fourth configuration example of the driver. FIG. 8B shows a fifth configuration example of the driver. Driver's variant. Detailed configuration example of power supply circuit. The example of composition of the driver to which the power supply circuit was applied. Power supply circuit startup sequence. An example of the configuration of an electro-optical device and an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are essential as the solution means of the present invention. Not necessarily.

1. As described above, the driver for driving the display panel generates a plurality of voltages by the power supply circuit, and operates a circuit such as a source driver with the plurality of voltages. For example, as will be described later with reference to FIG. 10 and FIG. 11, the power supply circuit 110 of the driver 100 uses the system power supply voltages VDD and VSS supplied from the system power supply 210 to supply power voltages VDDHSP and VDDHSN of the source driver 120 and the common voltage VCOM. Generate

  These voltages are supplied to each node and substrate of the transistor in each circuit (that is, to P-type / N-type diffusion layers, etc.), but as long as each voltage maintains a predetermined magnitude relationship, Since a reverse voltage is applied to the PN junction in the substrate, the parasitic bipolar does not turn on. However, if the magnitude relationship of the voltage is broken for some reason, the parasitic bipolar is turned on, and a current path may be generated between the voltages generated by the power supply circuit. Then, when such a current path is maintained, the voltage at which the current is drawn decreases and the voltage at which the current flows in increases, so that the voltage generated by the power supply circuit is not a predetermined voltage. I get stuck in it.

  As a factor to turn on the parasitic bipolar, it is possible to assume, for example, noise or data corruption of the register value. For example, in the case of an on-vehicle application, there is a noise source such as an engine and so on, which is a very noisy environment. If such noise appears on the voltage generated by the driver's power supply circuit, it is possible that the noise turns on the parasitic bipolar and causes the power supply to jam. Further, when the data in the register value is damaged due to noise or the like, the power supply circuit is set so as not to occur in a normal use condition, and the PN junction may become a forward voltage. For example, when the power supply of the driver is turned off, the charge of the capacitor holding each voltage generated by the power supply circuit is shorted to ground and discharged. During normal operation of the driver, if the value of the register value instructing discharge is garbled, part of the voltage generated by the power supply circuit will be shorted to the ground. As a result, the magnitude relationship of the voltage may be broken and the power source may be jammed.

  FIG. 1 shows a configuration example of a circuit device capable of detecting an abnormality of the power supply as described above, and a first detailed configuration example of the abnormality detection circuit. The circuit device includes a power supply circuit having a booster circuit 160, and an abnormality detection circuit 130 for detecting an abnormality in the boosted voltage VB generated based on the boosting operation of the booster circuit 160. The abnormality detection circuit 130 includes a detection transistor TDET. Detection transistor TDET is provided between a node of a first power supply voltage which is one of high potential side power supply voltage VDD and low potential side power supply voltage VSS and a node of boosted voltage VB, and has high potential side power supply voltage VDD and The input voltage VNB1 based on the second power supply voltage which is the other of the low potential side power supply voltage VSS is input to the gate. Then, the abnormality detection circuit 130 detects an abnormality in the boosted voltage VB based on the voltage change of one of the source and the drain of the detection transistor TDET.

  In the following, the detection transistor TDET is an N-type transistor, the first power supply voltage is the high potential side power supply voltage VDD, the second power supply voltage is the low potential side power supply voltage VSS, and the abnormality detection circuit 130 detects The case of detecting an abnormality based on the voltage change of the drain (node NB2) of the transistor TDET will be described as an example.

  The high potential side power supply voltage VDD and the low potential side power supply voltage VSS are not voltages generated by the power supply circuit 110, but are power supply voltages supplied from, for example, a system power supply external to the circuit device. That is, the power supply voltages VDD and VSS do not fluctuate even when an abnormality occurs in the boosted voltage VB, and are voltages that can be relied upon to be constant voltages.

  A detection transistor TDET is provided between the node of such a reliable first power supply voltage VDD and the node of the boosted voltage VB, and the input voltage VNB1 based on the reliable second power supply voltage VSS is input to its gate. Thus, the abnormality of the boosted voltage VB can be accurately detected. That is, since the first power supply voltage VDD and the second power supply voltage VSS do not change, the change of the drain voltage VNB2 of the detection transistor TDET is caused by the change of the boosted voltage VB. That is, by detecting the change of the drain voltage VNB2 of the detection transistor TDET, an abnormality of the boosted voltage VB can be detected.

  Further, since the abnormality detection circuit 130 can self-detect the abnormality of the boosted voltage VB, the recovery operation can be performed based on the detection result, and the boosting operation of the booster circuit 160 can be restored to the normal state. . For example, in the driver 100 described later with reference to FIG. 4, the ith booster circuit BCi corresponds to the booster circuit 160 of FIG. In the driver 100 of FIG. 4, when the abnormality detection circuit 130 detects an abnormality of the ith boost voltage VBi, the j-th boost circuit BCj performs a low-power step-up operation or the like to recover from power supply jamming. . That is, when the jth booster circuit BCj is a current supply source to a parasitic bipolar in a power supply jamming state, the parasitic voltage can be reduced by lowering the current supply capability of the jth booster circuit BCj. You can release the on state of the poller.

  Further, in the present embodiment, the abnormality detection circuit 130 includes the resistive element RC provided between the drain (one of the source and the drain) of the detection transistor TDET and the node of the first power supply voltage VDD.

  That is, the resistance element RC and the detection transistor TDET are connected in series between the node of the first power supply voltage VDD and the node of the boosted voltage VB. The drain voltage VNB2 of the detection transistor TDET is a voltage divided by the resistance element RC and the on resistance of the detection transistor TDET. When the boosted voltage VB changes, the source voltage of the detection transistor TDET changes, so that the on resistance changes, and the resistance division ratio changes. Therefore, the drain voltage VNB2 of the detection transistor TDET changes, and an abnormality in the boosted voltage VB is detected. Is possible.

  In the embodiment, the second transistor TB2 is provided between the source (the other of the source and the drain) of the detection transistor and the node of the boosted voltage VB, and the drain and the gate are connected. For example, the second transistor TB2 is an N-type transistor.

  As described above, by providing the so-called diode-connected second transistor TB2 on the source side of the detection transistor TDET, the detection voltage for abnormality detection can be adjusted. Specifically, the boosted voltage VB is a voltage (negative voltage) lower than the second power supply voltage VSS, and the boosted voltage VB is a substrate voltage of the semiconductor substrate of the circuit device as described later. When the power supply is jammed, the boosted voltage VB, which is the substrate voltage, rises, but since a diode (such as a parasitic diode) is present between the substrate and the second power supply voltage VSS, the rise of the boosted voltage VB is It is up to about the second power supply voltage VSS. Therefore, the abnormality in the boosted voltage VB is performed at a detection voltage slightly lower than the second power supply voltage VSS. At this time, the detection voltage can be lowered by providing the second transistor TB2, and an appropriate detection voltage can be set.

  Although the detection voltage can be changed also by changing the gate voltage of the detection transistor TDET, this gate voltage is related to the hysteresis characteristic and can not be changed only for the adjustment of the detection voltage. Therefore, the second transistor TB2 is provided to adjust the detection voltage.

  Further, in the present embodiment, the abnormality detection circuit 130 detects that the boosted voltage VB is abnormal when the boosted voltage VB exceeds the detection voltage. This detected voltage has hysteresis characteristics.

  Specifically, the abnormality detection circuit 130 buffers the voltage of the drain (one of the source and the drain) of the detection transistor TDET, the buffer circuit BFB, the gate of the detection transistor TDET, and the node of the second power supply voltage VSS. And a third transistor TB3 provided between the node of the first power supply voltage VDD and the gate of the detection transistor TDET, provided between the third transistor TB3 and turned on / off based on the output (voltage VNB4) of the buffer circuit BFB. And a second resistor element RB2 provided between the gate of the detection transistor TDET and the node of the second power supply voltage VSS and connected in parallel to the third transistor TB3.

  The buffer circuit BFB includes a first inverter (P-type transistor TB4 and N-type transistor TB5) receiving the drain voltage VNB2 of the detection transistor TDET, and a second inverter IVB2 receiving the output of the first inverter. . The abnormality detection circuit 130 includes an inverter IVB2 that receives the output of the buffer circuit BFB and outputs a detection signal SDT.

  The operation of the abnormality detection circuit 130 will be described with reference to FIG. FIG. 2 shows simulation results of the drain voltage VNB2 and the gate voltage VNB1 of the detection transistor TDET when the boosted voltage VB is changed. The boosted voltage VB is changed along the time axis for the convenience of simulation.

  First, the operation when changing from normal to abnormal will be described. In the normal state, it operates around boosted voltage VB = −10V. At this time, since the drain voltage VNB2 of the detection transistor TDET is lower than VSS = 0 V, the output of the buffer circuit BFB is at the low level, and the transistor TB3 is off. The gate voltage VNB1 of the detection transistor TDET is determined by the resistance division of the resistance elements RB1 and RB2.

  As the boosted voltage VB rises from −10 V (toward the right from the center of the drawing), the source voltage of the detection transistor TDET rises, and the on resistance of the detection transistor TDET rises. Thereby, the drain voltage VNB2 of the detection transistor TDET rises. When the boosted voltage VB becomes the detection voltage VD1, the detection transistor TDET is turned off, and the drain voltage VNB2 of the detection transistor TDET rises to the power supply voltage VDD. Then, the output of the buffer circuit BFB goes from low level to high level. That is, when the boosted voltage VB exceeds the detection voltage VD1, it is detected that the boosted voltage VB is abnormal.

  Next, the operation when returning from the abnormal state to the normal state will be described. As the boosted voltage VB decreases from VSS = 0 V (moving from the left to the center in the drawing), the source voltage of the detection transistor TDET decreases accordingly. When the boosted voltage VB becomes the detection voltage VD2, the detection transistor TDET is turned on, and the drain voltage VNB2 of the detection transistor TDET becomes lower than VSS = 0V. Then, the output of the buffer circuit BFB goes from high level to low level. When the output of the buffer circuit BFB is at high level, the transistor TB3 is on, and the gate voltage VNB1 of the detection transistor TDET is VSS = 0V. Since this is lower than the divided voltage of the resistance elements RB1 and RB2, the detection transistor TDET can not be turned on unless the source voltage of the detection transistor TDET becomes lower. That is, VD2 <VD1, and the detected voltage has hysteresis characteristics.

  FIG. 3 shows a second detailed configuration example of the abnormality detection circuit 130. As shown in FIG. In this configuration example, the abnormality detection circuit 130 is provided between the drain (one of the source and the drain) of the detection transistor TDET and the node of the first power supply voltage VDD, and the gate receives the input voltage VNB1. It has one transistor TB1. In addition, about the component similar to a 1st detailed structural example, the same code | symbol is attached | subjected and description is abbreviate | omitted suitably.

  The operation is basically the same as in the first detailed configuration example. That is, the on resistance of the first transistor TB1 corresponds to the resistance element RC in the first detailed configuration example. The drain voltage VNB2 of the detection transistor TDET is determined by the resistance division of the on resistance of the first transistor TB1 and the on resistance of the detection transistor TDET. When the boosted voltage VB rises and the on resistance of the detection transistor TDET increases, the detection transistor TDET The drain voltage VNB2 of the voltage of the buffer circuit BFB rises, the output of the buffer circuit BFB is inverted, and an abnormality is detected.

2. First Configuration Example of Driver Next, a circuit device capable of self-restoration from a power supply abnormality to a normal state will be described when an abnormality in the boosted voltage is detected. Although the case where the circuit device is a driver will be described below as an example, the present invention can be applied to any circuit device including a power supply circuit having a booster circuit.

  FIG. 4 shows a first configuration example of the driver. The driver 100 of FIG. 4 includes a power supply circuit 110 having first to nth booster circuits BC1 to BCn (n is an integer of nn2), and a drive circuit 120 that operates based on the power supplied from the power supply circuit 110. (A circuit in a broad sense) and an abnormality detection circuit 130. The booster circuit 160 of FIG. 1 corresponds to the ith booster circuit BCi of FIG.

  The abnormality detection circuit 130 detects an abnormality of the ith boosted voltage VBi generated based on the boosting operation of the ith boosting circuit BCi (i is an integer of 1 ≦ i ≦ n). The jth booster circuit BCj (j is an integer of 1 ≦ j ≦ n, j ≠ i) is lower in current supply capability than the normal booster operation when an abnormality of the ith boosted voltage VBi is detected. Perform the capability boosting operation or stop the boosting operation.

  Specifically, the power supply circuit 110 generates a plurality of power supplies based on the first to nth boosted voltages VB1 to VBn generated by the first to nth booster circuits BC1 to BCn. For example, the power supply circuit 110 may further include a plurality of regulators that regulate the boosted voltages VB1 to VBn generated by the first to nth booster circuits BC1 to BCn. Then, the outputs of the plurality of regulators or the first to nth boosted voltages are output as a power supply.

  Each boosting circuit of the first to nth boosting circuits BC1 to BCn is, for example, a charge pump circuit that performs a boosting operation by a switched capacitor operation. Alternatively, it may be a switching regulator that performs a boost operation by PWM drive of an inductor. Each booster circuit generates a boosted voltage by boosting a system voltage supplied from the outside of the driver 100 or a boosted voltage generated by a booster circuit other than itself or an output of a regulator. Here, “boosting” is not only the case of generating a positive (or negative) boosted voltage of the same sign from a positive (or negative) input voltage, but also “negative (negative)” from a positive (or negative) input voltage Or positive) includes the case of generating a boosted voltage.

  The abnormality detection circuit 130 detects that the ith boost voltage VBi is an abnormal (abnormal) voltage, and outputs the detection signal SDT to the jth boost circuit BCj. For example, since it is considered that the i-th boosted voltage VBi is in the predetermined voltage range in the normal state, it is out of the predetermined voltage range (for example, a predetermined voltage or more as described later). Detected as an abnormal condition). In response to the detection signal SDT becoming active, the j-th boosting circuit BCj performs the low-performance boosting operation or stops the boosting operation.

  The low-performance boost operation is a boost operation that reduces the current supply capability to the load. That is, assuming that the maximum value of the output current at which the booster circuit can maintain the boosted voltage at the specified voltage is the current supply capacity, the boosted voltage is maintained at the specified voltage with an output current smaller than that of the normal boost operation in low-performance boost operation. become unable. For example, in the case of a charge pump circuit, it is possible to change the current supply capability by changing the size (on resistance) of the switch element of the switched capacitor. For example, the low-power step-up operation can be realized by the step-up operation performed by the soft start transistor of FIG. The normal boosting operation is an operation with an original current supply capability of the boosting circuit, and is, for example, the boosting operation performed by the transistor for the normal boosting operation in the boosting circuit of FIG.

  The stop of the boosting operation is a state in which the boosting circuit does not perform the boosting operation, for example, a state in which the charge pump circuit or the switching regulator has stopped the switching operation. In this state, one of the plurality of phases repeated in the switching operation is stopped, or the output of the booster circuit is set to a high impedance state.

  As described above, when the abnormality detection circuit 130 detects an abnormality in the ith boosted voltage VBi, the driver 100 can self-detect an abnormality in the boosted voltage. When the abnormality detection circuit 130 detects an abnormality in the ith boost voltage VBi, the jth boost circuit BCj performs a low-performance boost operation or stops the boost operation, thereby bringing the boost voltage to a normal state. It is possible to recover.

  That is, when the current flows between the power supplies generated by the power supply circuit 110 through the parasitic bipolar in the substrate of the driver 100, the power supply jam occurs. Since the power supply circuit 110 generates the power supply voltage based on the boosted voltage, the source of the current flowing through the parasitic bipolar is the booster circuit. As long as sufficient current is supplied to the parasitic bipolar, the parasitic bipolar on state is maintained. Therefore, when the boosting circuit which is the supply source of the current performs the low-performance boosting operation or stops the boosting operation, the ON state of the parasitic bipolar is released, and the jamming of the power supply can be released.

3. Second and Third Configuration Examples of Driver FIGS. 5A and 6A show second and third configuration examples of the driver 100. FIG. 5A and 6A, illustration of a part of the booster circuit and the drive circuit 120 is omitted. 5B and 6B show timing charts of the second and third configuration examples.

  As shown in FIGS. 5B and 6B, the j-th boosting circuit BCj performs low-performance boosting operation or boosting operation in a period in which an abnormality of the ith boosted voltage VBi is detected. When the abnormality of the ith boosted voltage VBi is not detected, the normal boosting operation is resumed.

  In the examples of FIGS. 5B and 6B, the period in which the abnormality of the ith boosted voltage VBi is detected is a period in which the detection signal SDT is at the high level (active), When the abnormality of the boosted voltage VBi is not detected, the detection signal SDT changes from the high level to the low level (inactive).

  As described above, in the present embodiment, the i-th boosted voltage can be restored to the normal state by the j-th boosting circuit BCj performing the low-performance boosting operation or stopping the boosting operation. If the i-th boost voltage returns to the normal state, the abnormality is not detected. Therefore, the jth boost circuit BCj can restart normal boost operation with this as a trigger, and the operation of the boost circuit and the boost voltage are in the normal state. Can be returned to This return operation is completed in the driver 100, and the user need not turn off the power switch or the like. For example, in an on-vehicle application, even if an abnormality occurs in the power supply of the driver 100, it may be difficult to stop and turn off the engine. Therefore, it is desirable to be able to recover from the power supply abnormality and recover the display.

  Further, in the present embodiment, the ith boosted voltage VBi is a substrate voltage of the driver 100. The abnormality detection circuit 130 detects an abnormality in the substrate voltage.

  That is, the driver 100 is configured by an integrated circuit device, and the voltage set on the semiconductor substrate of the integrated circuit device is the substrate voltage. For example, when the semiconductor substrate is P-type, the lowest voltage among the power supplies generated by the power supply circuit 110 is set as the substrate voltage. For example, in the power supply circuit of FIG. 10 described later, the voltage VEE generated by the booster circuit BC4 is a substrate voltage.

  When the semiconductor substrate is P-type, since the substrate voltage is the lowest voltage, there is a high possibility that the current flowing to the parasitic bipolar may finally flow into the substrate in the power failure. When such an abnormal current flows into the substrate, the substrate voltage rises, so that the substrate voltage abnormality can be detected by detecting the potential.

  Specifically, as shown in FIGS. 5B and 6B, the abnormality detection circuit 130 detects that the ith boosted voltage VBi is abnormal when the ith boosted voltage VBi exceeds the detection voltage VD1. To be detected. This detected voltage has hysteresis characteristics. That is, when not being detected, a detection voltage VD2 (<VD1) different from the detection voltage VD1 is used.

  As described above, by detecting that the i-th boosted voltage VBi has exceeded the detection voltage VD1, it is possible to detect that the substrate voltage has risen due to the power source being stuck. Since it is considered that the ith boosted voltage VBi fluctuates within a predetermined range in a normal operation state (that is, a state in which the power supply generated by the power supply circuit 110 is normal), the detection voltage VD1 is set outside the predetermined range. Alternatively, when it is known how much the i-th boosted voltage VBi will be when the power supply is jammed (for example, experimentally), the detection voltage VD1 is set to that voltage.

  In the second configuration example shown in FIG. 5A, the ith boosted voltage VBi is a voltage generated based on the jth boosted voltage VBj generated based on the boosting operation of the jth booster circuit BCj. . Then, as shown in FIG. 5B, the j-th boosting circuit BCj performs low-performance boosting operation when an abnormality of the ith boosted voltage VBi is detected, and the abnormality of the ith boosted voltage VBi is not When it is detected, the normal boosting operation is resumed.

  Specifically, power supply circuit 110 includes an ith booster circuit BCi, a jth booster circuit BCj, and a regulator RGA. Then, the regulator RGA generates a voltage VGA from the j-th boosted voltage VBj, and an ith boosting circuit BCi boosts the voltage VGA to generate an ith boosted voltage VBi. The regulator RGA is, for example, a linear regulator, and regulates the jth boosted voltage VBj to a voltage VGA obtained by multiplying the reference voltage by a predetermined amount. For example, in the power supply circuit of FIG. 10 described later, the first booster circuit BC1 corresponds to the j-th booster circuit BCj, the regulator RG8 corresponds to the regulator RGA, and the fourth booster circuit BC4 corresponds to the i-th booster circuit BCi. It corresponds.

  In such a configuration, the output voltage VGA of the regulator RGA is necessary for the ith boosted voltage VBi to recover from the abnormal state. That is, it is necessary to generate the j-th boosted voltage VBj which is the input voltage of the regulator RGA. Therefore, in the configuration of FIG. 5A, the j-th boosting circuit BCj performs low-performance operation without stopping the boosting operation in the abnormal state, and the output of the regulator RGA with respect to the ith boosting circuit BCi also in the abnormal state. Supply voltage VGA. As a result, it is possible to eliminate the jamming of the power supply and to restore the ith boosted voltage VBi to a normal voltage.

  In the third configuration example shown in FIG. 6A, the ith boosted voltage VBi is generated based on the boosting operation of the kth booster circuit (k is an integer of 1 ≦ k ≦ n, k ≠ i, j). It is a voltage generated based on the kth boosted voltage VBk. Then, as shown in FIG. 6B, the j-th booster circuit BCj stops the booster operation when an abnormality of the ith boosted voltage VBi is detected.

  Specifically, the power supply circuit 110 includes the i-th booster circuit BCi, the j-th booster circuit BCj, the k-th booster circuit BCk, and the regulator RGB. Then, the regulator RGB generates the voltage VGB from the kth boosted voltage VBk, and the ith boosting circuit BCi boosts the voltage VGB to generate the ith boosted voltage VBi. The regulator RGB is, for example, a linear regulator, and regulates the kth boosted voltage VBk to a voltage VGB obtained by multiplying the reference voltage by a predetermined amount. For example, in the power supply circuit of FIG. 10 described later, the second and third booster circuits BC2 and BC3 correspond to the jth booster circuit BCj, and the first booster circuit BC1 corresponds to the kth booster circuit BCk. RG8 corresponds to the regulator RGB, and the fourth booster circuit BC4 corresponds to the ith booster circuit BCi.

  In such a configuration, the ith boosted voltage VBi can be recovered from the abnormal state even if the jth boosted voltage VBj is not generated. Therefore, in the configuration of FIG. 6A, the jth booster circuit BCj stops the boosting operation in the abnormal state. As a result, the jth boosted voltage VBj is not generated in the abnormal state, but it is possible to self-reset from the power supply jamming as long as the ith boosting circuit BCi can generate the ith boosted voltage VBi. It becomes.

  Further, in the present embodiment, the jth booster circuit BCj is a booster circuit having the highest current supply capability among the first to nth booster circuits BC1 to BCn.

  Power supply jamming is a state in which the parasitic bipolar on state is maintained, but a current sufficient to maintain the on state must be supplied to the parasitic bipolar. Therefore, at the output of the booster circuit having a small current supply capability, even if the parasitic bipolar is turned on, it is considered that the on state is naturally eliminated. Therefore, the boosting operation of the boosting circuit having a high current supply capability for maintaining the on state of the parasitic bipolar may be reduced or stopped.

  For example, in the power supply circuit of FIG. 10, the first booster circuit BC1 is a booster circuit having the highest current supply capability. The first booster circuit BC1 is provided with a plurality of regulators and booster circuits as circuits in the latter stage, and it is necessary to supply the output current and consumption current of these regulators and the booster circuits. Current supply capacity is the largest. Even if the parasitic bipolar is turned on at the end of the regulator or step-up circuit following the first step-up circuit BC1, the current supply of the first step-up circuit BC1 which is the current supply source of the previous stage is narrowed or stopped. , You can recover from the plugging in the power supply.

  Further, in the present embodiment, the drive circuit 120 drives the display panel 200 (electro-optical panel) based on the j-th boost voltage VBj generated based on the boost operation of the j-th boost circuit BCj.

  The drive circuit 120 is a source driver that drives a source line of the display panel. Since the source driver needs to drive the pixel capacity at high speed, the driver 100 is a circuit that consumes a large amount of current. Therefore, when the power supply of drive circuit 120 is generated based on j-th boosted voltage VBj, j-th boosted voltage VBj has a large current supply capability. Since the jth booster circuit BCj having such a large current supply capability can be a current supply source for a parasitic bipolar, it is possible to recover from the jamming of the power supply by reducing or stopping the boosting operation. .

  For example, in the power supply circuit of FIG. 10, the output voltages VDDHSP, VDDRMP, VDDHSN and VDDRMN of the regulators RG5, RG7, RG11 and RG12 are power supply voltages of the source driver. That is, the first booster circuit BC1 and the third booster circuit BC3 correspond to the j-th booster circuit BCj.

  In the power supply circuit of FIG. 10, the second booster circuit BC2, the fourth booster circuit BC4, and the fifth booster circuit BC5 may perform the low-performance step-up operation or stop the step-up operation when the power supply is engaged. .

4. Boosting Circuit FIG. 7 shows a configuration example of the j-th boosting circuit BCj capable of performing a low-performance boosting operation. FIG. 7 shows an example of the configuration when the jth booster circuit BCj is a charge pump circuit.

  The j-th boosting circuit BCj includes boosting transistors TA3 and TA4 for normal boosting operation and boosting transistors TA5 and TA6 for soft start. In the low-performance boosting operation, boosting operation is performed by the boosting transistors TA5 and TA6 for soft start.

  More specifically, the jth booster circuit BCj includes fifth and sixth transistors connected in parallel to the first to fourth transistors TA1 to TA4 connected in series and the third and fourth transistors TA3 and TA4. Transistors TA5 and TA6. Then, in the normal boost operation, the boost operation is performed by turning on and off the first to fourth transistors TA1 to TA4, and in the low-performance boost operation, the third and fourth transistors TA3 and TA4 are turned off, Soft start of the boosting operation is performed using the first and second transistors TA1 and TA2 and the fifth and sixth transistors TA5 and TA6.

  The transistors TA1 to TA3 and TA5 are P-type transistors, and the transistors TA4 and TA6 are N-type transistors. In a normal boost operation, the transistors TA2 and TA4 are turned on in the first period (first phase), the transistors TA1 and TA3 are turned off, one end of the capacitor CA is connected to the ground voltage VSS, and the other end of the capacitor CA Is connected to the input voltage VIN. In the second period (second phase), the transistors TA2 and TA4 are turned off, the transistors TA1 and TA3 are turned on, one end of the capacitor CA is connected to the input voltage VIN, and the other end of the capacitor CA from the transistor TA. The output voltage VQ = 2 × VIN is output. The transistors TA5 and TA6 are both off during the first period and the second period. Alternatively, the soft start transistors TA5 and TA6 may be used together in the normal boosting operation. That is, the transistor TA6 may be turned on in the first period, the transistor TA5 may be turned off, the transistor TA5 may be turned on in the second period, and the transistor TA6 may be turned off. In the low-power step-up operation, the transistors TA2 and TA6 are turned on in the first period, the transistors TA1 and TA5 are turned off, the transistors TA2 and TA6 are turned off in the second period, and the transistors TA1 and TA5 are turned on.

  The size (for example, channel width W / channel length L channel width W etc.) of the soft start boosting transistors TA3 and TA4 is smaller than the size of the normal boost operation boosting transistors TA5 and TA6. Therefore, the on-resistance of the step-up transistors TA3 and TA4 for soft start becomes larger, and the current supply capability of the jth step-up circuit BCj is lowered by performing the step-up operation by the transistors TA3 and TA4. The soft start step-up transistors TA3 and TA4 are provided to suppress inrush current when starting the step-up operation when the power supply circuit 110 is started. By using the soft start circuit originally provided in this manner, it is possible to realize the low-power step-up operation at the time of the power source being engaged.

5. Fourth and Fifth Configuration Examples FIG. 8A shows a fourth configuration example of the driver 100. The fourth configuration example is a configuration example in which the j-th boosting circuit BCj stops the boosting operation when the power supply is stuck. In FIG. 8A, illustration of part of the drive circuit 120 and the booster circuit is omitted.

  The driver 100 includes a control circuit 140, a jth booster circuit BCj, and an abnormality detection circuit 130. The jth booster circuit BCj includes an enable signal generator GEN, a booster clock generator CKG, and a booster BST.

  The boosting unit BST is configured of the charge pump circuit described with reference to FIG. The boost clock generation unit CKG generates a clock signal for driving the boost unit BST. That is, a clock signal for on / off controlling the transistors TA1 to TA6 constituting the boosting unit BST is generated corresponding to a normal boosting operation or a soft start operation (low capability boosting operation).

  The control circuit 140 outputs the enable signal EN and the soft start signal SFT to the jth booster circuit BCj. The j-th boosting circuit BCj performs a boosting operation in a period in which the enable signal EN is active, and performs a soft-start operation in a period in which the soft start signal SFT is active.

  The enable signal generation unit GEN generates a new enable signal ENA based on the enable signal EN from the control circuit 140 and the detection signal SDT from the abnormality detection circuit 130. When the enable signal EN is active, when the abnormality detection circuit 130 detects an abnormality in the ith boosted voltage VBi and the detection signal SDT becomes active, the enable signal generation unit GEN outputs the inactive enable signal ENA. Do. That is, when the power supply is engaged, the j-th boosting circuit BCj is instructed to stop the boosting operation. For example, when the enable signal EN and the detection signal SDT are high active, the enable signal generation unit GEN includes an inverter that logically inverts the detection signal SDT, and an AND circuit that outputs a logical product of an output of the inverter and the enable signal EN. Configured

  The 5th structural example of the driver 100 is shown in FIG. 8 (B). The fifth configuration example is a configuration example in which the low-power step-up operation is performed when the jth booster circuit BCj is engaged with the power supply. In FIG. 8B, illustration of part of the drive circuit 120 and the booster circuit is omitted.

  The driver 100 includes a control circuit 140, a jth booster circuit BCj, and an abnormality detection circuit 130. The jth booster circuit BCj includes a soft start signal generator GSF, a booster clock generator CKG, and a booster BST.

  The soft start signal generation unit GSF generates a new soft start signal SFTA based on the soft start signal SFT from the control circuit 140 and the detection signal SDT from the abnormality detection circuit 130. When soft start signal SFT is inactive, abnormality detection circuit 130 detects an abnormality of ith boost voltage VBi and detection signal SDT becomes active, soft start signal generation unit GSF is an active soft start signal Output SFTA. That is, the soft start operation (low-power step-up operation) is instructed to the j-th booster circuit BCj at the time of power supply engagement. For example, when the soft start signal SFT and the detection signal SDT are high active, the enable signal generation unit GEN is configured of a logical sum circuit that outputs a logical sum of the detection signal SDT and the soft start signal SFT.

6. Modified Example A modified example of the driver 100 is shown in FIG. In this modification, when an abnormality of the boosted voltage (i-th boosted voltage VBi) is detected, the start sequence of the power supply circuit 110 is re-executed.

  Specifically, the abnormality detection circuit 130 outputs a detection signal SDT to the control circuit 140. When the detection signal SDT becomes active, the control circuit 140 temporarily suspends the operation of the power supply circuit 110, and then restarts the power supply circuit 110. The start-up sequence is a sequence for controlling the operation timing of each part of the power supply circuit 110. As will be described later with reference to FIG. 12, for example, the timing at which the first to nth boosting circuits BC1 to BCn start boosting operation, the timing at which soft start is started / stopped, the regulator operation starts (or the output is enabled). Control the timing etc.

  As described above, it is possible to recover from the power source jamming by re-executing the start-up sequence as well as stopping the low-performance step-up operation and the step-up operation. That is, when the start-up sequence is re-executed, the operation of the power supply circuit including the booster circuit is temporarily stopped, so that the current supply to the parasitic transistor is lost, and the power supply can be recovered from the jamming.

7. Power Supply Circuit FIG. 10 shows a detailed configuration example of the power supply circuit 110. FIG. 11 shows a configuration example of the driver 100 to which the power supply circuit 110 of FIG. 10 is applied.

  The driver 100 of FIG. 11 includes a power supply circuit 110, a source driver 120 (drive circuit), a gate driver 150, and a control circuit 140. The source driver 120 (data driver) is a circuit for driving the source line (data line) of the display panel 200, and includes, for example, a gradation voltage generation circuit, a D / A conversion circuit, a source amplifier and the like. The gate driver 150 (scan driver) is a circuit that drives the gate lines (scan lines) of the display panel 200, and includes, for example, a level shifter, a buffer, and the like. The control circuit 140 includes, for example, an interface circuit that communicates with the display controller 300, a line latch that latches image data transmitted from the display controller 300, and a timing controller that controls timing of display control. For example, the control circuit 140 is configured of a gate array or the like.

  The power supply circuit 110 of FIG. 10 includes first to fifth booster circuits BC1 to BC5 and first to thirteenth regulators RG1 to RG13. For example, the first to fifth booster circuits BC1 to BC5 are charge pump circuits, and the first to thirteenth regulators RG1 to RG13 are linear regulators. In FIG. 10, the positional relationship in the vertical direction in the drawing of each voltage represents an approximate magnitude relationship of voltages. For example, VDDL, VLDO and the like are voltages between VDD and VSS, VOUTM, VOUT3 and the like are voltages (negative voltages) lower than VSS, and VOUT and the like are voltages higher than VDD.

  The regulators RG1, RG2, and RG3 step down the power supply voltage VDD to generate voltages VDDL, VLDO1, and VLDO2. As shown in FIG. 10, the voltage VDDL is a power supply voltage of the control circuit 140 (logic circuit).

  The booster circuit BC1 doubles the voltage VLDO1 based on the voltage VSS to generate a voltage VOUT. The regulators RG4, RG5, RG6, RG7, RG8, RG9 step down the voltage VOUT to generate voltages VREG, VDDHSP, VDDRHP, VDDRMP, VOFREG, VONREG. The regulator RG4 generates a voltage VREG based on an output voltage of a band gap circuit (not shown). The other regulators RG1 to RG3 and RG5 to RG13 output respective voltages based on the voltage VREG. As shown in FIG. 10, voltages VDDHSP and VDDRMP are positive power supply voltages of the source driver 120 (power supply voltages used for positive electrode drive of dot inversion drive). The voltage VDDRHP is a power supply voltage of the gradation voltage generation circuit.

  The booster circuit BC2 inverts the voltage VLDO2 on the basis of the voltage VSS to generate a negative voltage VOUTM. The regulator RG10 generates a voltage VCOM from the voltage VLDO2 and the voltage VOUTM. The voltage VCOM is a common voltage when driving the source line of the display panel 200.

  The booster circuit BC3 inverts and boosts the voltage VDD four times with reference to the voltage VSS to generate a negative voltage VOUT3. The regulator RG11 steps down the voltage VOUT3 to generate a voltage VDDHSN, and the regulator RG12 steps down the voltage VDDHSN to generate a voltage VDDRMN. As shown in FIG. 10, voltages VDDHSN and VDDRMP are negative power supply voltages of the source driver 120 (power supply voltages used for negative electrode driving of dot inversion driving).

  The booster circuit BC4 inverts and boosts the voltage VOFREG three times with reference to the voltage VSS to generate a negative voltage VEE. The voltage VEE is a substrate voltage of the semiconductor substrate (P-type substrate) of the driver 100. The regulator RG13 steps down the voltage VEE to generate a voltage VGL. As shown in FIG. 10, the voltage VGL is a negative power supply voltage of the gate driver 150.

  The booster circuit BC5 generates a voltage VDDHG = VONREG × 2-VGL from the voltage VONREG and the voltage VGL. As shown in FIG. 10, the voltage VDDHG is a positive power supply voltage of the gate driver 150.

  FIG. 12 shows the start-up sequence of the power supply circuit 110 executed by the control circuit 140. The start-up sequence is not limited to that shown in FIG. 12. For example, the boosting operation of the boosting circuits BC1 to BC5 may be started simultaneously. For example, the setting of the register may be configured to allow the user to set the activation sequence.

  As shown in FIG. 12, when the register value DISON instructing activation of the power supply circuit 110 is activated by the display controller (processing unit) outside the driver 100, the control circuit 140 starts the activation sequence of the power supply circuit 110. . For example, the execution period of the activation sequence is six frames F1 to F6. The regulator RG1 is turned on together with the band gap circuit and the like when the driver 100 is powered on.

  In the start-up sequence, first, at the start of the second frame F2, the enable signal of the booster circuits BC1 to BC3 is activated to start the booster operation. Also, turn on the regulators RG1 to RG4. In the second to fifth frames F2 to F5, the soft start signal of the booster circuits BC1 to BC3 is activated to perform the soft start operation. Next, at the start of the third frame F3, the enable signals of the regulators RG5 to 7, 11 and 12 are activated to turn on the operation. By the third frame F3, the first to third boost systems rise, and the reference voltage and the common voltage of the regulator and the power supply voltage of the source driver are output.

  At the start of the third frame F3, the enable signal of the regulator RG8 is activated to turn on the operation, and the enable signal of the booster circuit BC4 is activated to start the boosting operation. Next, at the start of the fourth frame F4, the enable signal of the regulator RG13 is activated to turn on the operation. The enable signal of the regulator RG9 is activated to turn on the operation, and the enable signal of the booster circuit BC5 is activated to start the boost operation. By the fourth frame F4, the fourth and fifth boosting systems rise, and the power supply voltage of the gate driver and the substrate voltage are output.

  Next, during the fifth frame F5 (before the start of the sixth frame F6), the enable signal of the regulator RG10 is activated to turn on the operation. The common voltage is output in the fifth frame. At the start of the sixth frame F6, the soft start operation of the booster circuits BC1 to BC3 ends and shifts to the normal boost operation, and the start sequence ends at the end of the sixth frame F6.

  In the re-execution of the start-up sequence described in FIG. 6, when the detection signal SDT from the abnormality detection circuit 130 becomes active, the control circuit 140 deactivates the register value DISON and activates the register value DISON again. To execute the boot sequence again.

8. Electro-Optical Device, Electronic Device FIG. 13 shows a configuration example of an electro-optical device and an electronic device to which the driver 100 of the present embodiment can be applied. As the electronic device of the present embodiment, various electronic devices equipped with display devices such as a projector, a television device, an information processing device (computer), a portable information terminal, a car navigation system, a portable game terminal and the like are assumed. it can.

  The electronic device illustrated in FIG. 13 includes an electro-optical device 350, a display controller 300 (host controller, first processing unit), a CPU 310 (second processing unit), a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 350 includes a driver 100 and a display panel 200.

  The display panel 200 is, for example, a matrix liquid crystal display panel. Alternatively, the display panel 200 may be an EL (Electro-Luminescence) display panel using a self light emitting element. For example, a flexible substrate is connected to the display panel 200, the driver 100 is mounted on the flexible substrate, and the electro-optical device 350 is configured. The driver 100 and the display panel 200 may not be configured as the electro-optical device 350, and may be incorporated into an electronic device as individual components. For example, a flexible substrate for wiring extraction is connected to the display panel 200, the driver 100 is mounted on a rigid substrate together with the display controller 300 and the like, and the display panel 200 is mounted by connecting the flexible substrate to the rigid substrate. Good.

  The user interface unit 330 is an interface unit that receives various operations from the user. For example, it is configured by a button, a mouse, a keyboard, a touch panel attached to the display panel 200, and the like. The data interface unit 340 is an interface unit that inputs and outputs image data and control data. For example, it is a wired communication interface such as USB or a wireless communication interface such as a wireless LAN. The storage unit 320 stores the image data input from the data interface unit 340. Alternatively, the storage unit 320 functions as a working memory of the CPU 310 or the display controller 300. The CPU 310 performs control processing of each part of the electronic device and various data processing. The display controller 300 performs control processing of the driver 100. For example, the display controller 300 converts the image data transferred from the data interface unit 340 or the storage unit 320 into a format that can be received by the driver 100, and outputs the converted image data to the driver 100. The driver 100 drives the display panel 200 based on the image data transferred from the display controller 300.

  It should be understood by those skilled in the art that although the present embodiment has been described in detail as described above, many modifications can be made without departing substantially from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention. For example, in the specification or the drawings, the terms described together with the broader or synonymous different terms at least once can be replaced with the different terms anywhere in the specification or the drawings. Further, all combinations of the present embodiment and the modifications are also included in the scope of the present invention. Further, the configuration and operation of the power supply circuit, the abnormality detection circuit, the circuit device, the electro-optical device, and the electronic apparatus are not limited to those described in the present embodiment, and various modifications can be made.

100 drivers, 110 power circuits, 120 source drivers,
120 drive circuit, 130 fault detection circuit, 140 control circuit,
150 gate drivers, 160 boost circuits, 200 display panels,
210 system power, 300 display controller, 310 CPU,
320 storage unit, 330 user interface unit,
340 data interface unit, 350 electro-optical device,
BCi i-th booster circuit, BCj j-th booster circuit, BCk k-th booster circuit
BFB buffer circuit, TDET detection transistor,
VB boosted voltage, VBi i-th boosted voltage, VBj j-th boosted voltage,
VBk kth boosted voltage, VD1, VD2 detection voltage,
VDD High side power supply voltage, VSS Low side power supply voltage

Claims (12)

A power supply circuit having a booster circuit;
An abnormality detection circuit that detects an abnormality of a boosted voltage generated based on the boosting operation of the booster circuit;
Including
The abnormality detection circuit
The high potential side power supply voltage and the low potential side power supply voltage are provided between a node of a first power supply voltage that is one of a high potential side power supply voltage and a low potential side power supply voltage and a node of the boosted voltage. A detection transistor in which an input voltage based on the other second power supply voltage is input to the gate ;
A first transistor provided between one of a source and a drain of the detection transistor and a node of the first power supply voltage and having the gate receiving the input voltage;
Have
Wherein said source and drain of the detection transistor based on the voltage change of the one, the circuit device and detects an abnormality of the boosting voltage. A power supply circuit having a booster circuit;
An abnormality detection circuit that detects an abnormality of a boosted voltage generated based on the boosting operation of the booster circuit;
Including
The abnormality detection circuit
The high potential side power supply voltage and the low potential side power supply voltage are provided between a node of a first power supply voltage that is one of a high potential side power supply voltage and a low potential side power supply voltage and a node of the boosted voltage. It has a detection transistor in which an input voltage based on the other second power supply voltage is input to the gate,
Detecting an abnormality of the boosted voltage based on a voltage change of one of the source and the drain of the detection transistor;
The abnormality detection circuit
A circuit device comprising: a second transistor provided between the other of the source and the drain of the detection transistor and the node of the boosted voltage, wherein the drain and the gate are connected . In claim 2 ,
The abnormality detection circuit
A circuit device comprising: a resistance element provided between the one of the source and the drain of the detection transistor and the node of the first power supply voltage. In claim 2 ,
The abnormality detection circuit
A circuit device comprising: a first transistor provided between the one of the source and the drain of the detection transistor and the node of the first power supply voltage and having the gate to which the input voltage is input. A power supply circuit having a booster circuit;
An abnormality detection circuit that detects an abnormality of a boosted voltage generated based on the boosting operation of the booster circuit;
Including
The abnormality detection circuit
The high potential side power supply voltage and the low potential side power supply voltage are provided between a node of a first power supply voltage that is one of a high potential side power supply voltage and a low potential side power supply voltage and a node of the boosted voltage. A detection transistor in which an input voltage based on the other second power supply voltage is input to the gate ;
A buffer circuit for buffering one of the source and drain voltages of the detection transistor;
A third transistor provided between the gate of the detection transistor and a node of the second power supply voltage, which is turned on / off based on the output of the buffer circuit;
A first resistance element provided between the node of the first power supply voltage and the gate of the detection transistor;
A second resistance element provided between the gate of the detection transistor and the node of the second power supply voltage and connected in parallel to the third transistor;
Have
Wherein said source and drain of the detection transistor based on the voltage change of the one, the circuit device and detects an abnormality of the boosting voltage. In any one of claims 1 to 5 ,
The abnormality detection circuit
When the boosted voltage exceeds the detection voltage, it is detected that the boosted voltage is abnormal;
The circuit device characterized in that the detection voltage has a hysteresis characteristic. In any one of claims 1 to 6,
The boosted voltage is a negative voltage,
The first power supply voltage is the high potential side power supply voltage,
The circuit device characterized in that the second power supply voltage is the low potential side power supply voltage. In any one of claims 1 to 7,
The circuit device wherein the boosted voltage is a substrate voltage of the circuit device. In any one of claims 1 to 8,
A control circuit for controlling the power supply circuit,
The control circuit
A circuit device characterized by re-executing a start-up sequence of the power supply circuit when an abnormality of the boosted voltage is detected. In any one of claims 1 to 9,
A circuit device comprising: a drive circuit for driving a display panel based on power supplied from the power supply circuit. A circuit arrangement according to claim 10;
Display panel,
An electro-optical device comprising:   An electronic apparatus comprising the circuit device according to any one of claims 1 to 10.

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