WO2007072402A2

WO2007072402A2 - Voltage conversion circuit

Info

Publication number: WO2007072402A2
Application number: PCT/IB2006/054923
Authority: WO
Inventors: Andy C. Negoi
Original assignee: Nxp B.V.
Priority date: 2005-12-22
Filing date: 2006-12-18
Publication date: 2007-06-28
Also published as: WO2007072402A3

Abstract

A voltage generation circuit comprises a voltage conversion circuit (12) for receiving a first voltage and generating a second, lower, voltage from the first voltage. A control circuit (10) is provided for activating the voltage conversion circuit in response to a control input (buf&lowbar;cmd), and a logic circuit (22) generates the control input. The logic circuit receives as input the second voltage level (Vddd), and a power saving command signal (pwr&lowbar;off) for placing the voltage conversion circuit into a power saving mode. The logic circuit (22) is adapted to provide as control input (buf&lowbar;cmd) a non-activation output signal in response to the power saving command until the second voltage level (Vddd) reaches a predetermined level, and then to provide an activation output signal. This circuit operates the voltage conversion circuit only intermittently, so that power consumption is reduced. Before the second voltage reaches a level that could result in state information being lost, the logic circuit operates to pulse the voltage conversion circuit on, to recharge the output. The power consumption of the logic circuit is lower than the power consumption of the voltage conversion circuit when operating, so that power savings are obtained.

Description

DESCRIPTION

VOLTAGE CONVERSION CIRCUIT

This invention relates to voltage conversion circuits, particularly but not exclusively for generating the power supply for a digital circuit from the higher voltage power supply of an analogue circuit of the same electronic device.

Mixed digital and analogue signal integrated circuits (ICs) are common in all sorts of portable electronic devices.

By way of example, liquid crystal display (LCD) modules are mixed signal integrated circuits, found in many different consumer products, such as mobile phones and Personal Digital Assistants (PDA). Mixed signal ICs generally use several supply voltages in order to save power, for example a low voltage supply for the digital circuitry such as logic circuits, RAM, interface circuits, and a higher, more accurate supply voltage for the analogue circuitry. It is known that for economic reasons it is desirable to use a single power supply for the multiple functions. For example, in the case of a display driver, a single higher voltage supply can be used which supplies both the analogue and the digital circuitry. The digital circuitry is implemented with very small transistors to consume only a very small power, and this requires a supply voltage which is smaller than the single voltage which would be required for the analogue circuitry.

The lower supply voltage for the digital circuitry logic can be derived internally on the IC, with a voltage down-converter circuit such as a linear regulator. This part of the circuit has to work stand-alone and start when an analogue supply voltage is ramping up. Furthermore, when the digital circuitry is switched to a sleep mode (which is a common mode of operation in electronic devices), the down-converter still has to be active to enable the digital circuit to come out of the sleep mode, and for this purpose it will draw from the supply its whole quiescent current. The resulting power consumption is essentially wasted on maintaining the digital circuitry in a sleep state. Depending on the implementation, the voltage conversion circuit can draw for example 30 to 50 microamperes. Because the sleep state can only be maintained if the digital supply voltage is available, this part of the circuit cannot be turned off as part of the sleep mode.

The power consumption is of vital interest in portable devices, and the current flowing in an inactive mode of a device is of particular importance, as this determines the standby time of a device.

There is therefore a need to reduce current consumption in the sleep mode of a digital circuit which has a power supply derived by voltage down-conversion, and without losing the state of the circuit.

According to the invention, there is provided a voltage generation circuit, comprising: a voltage conversion circuit for receiving a first voltage and generating a second, lower, voltage from the first voltage; a control circuit for activating the voltage conversion circuit in response to a control input; and a logic circuit for generating the control input, wherein the logic circuit receives as input the second voltage level, and a power saving command signal for placing the voltage conversion circuit into a power saving mode, wherein the logic circuit is adapted to provide as control input a non-activation output signal in response to the power saving command until the second voltage level reaches a predetermined level, and then to provide an activation output signal.

This circuit operates the voltage conversion circuit only intermittently, so that power consumption is reduced. Before the second voltage reaches a level that could result in state information being lost, the logic circuit operates to pulse the voltage conversion circuit on, to recharge the output. The power consumption of the logic circuit is lower than the power consumption of the voltage conversion circuit when operating, so that power savings are obtained, even though the logic circuit has to function even in standby or sleep mode. The normal operation of the voltage conversion circuit can then be restored by a software command.

The circuit of the invention can provide significant power savings, for example up to two orders of magnitude. The logic circuit may comprise a switching element with a switching response with hysteresis, for example a Schmitt trigger, in order to provide a pulsed output that responds to the second voltage level.

The logic circuit may comprise the switching element and a first logic gate arrangement for providing a power up command signal when the power saving command signal is on and when the switching element toggles in response to the second voltage level dropping more than a hysteresis threshold below the desired second voltage level.

The logic circuit is preferably powered by the first voltage, and the output of the logic circuit can be either a low power line voltage or the first voltage level. In this case, the control circuit can comprises a comparator for comparing the control input with the first voltage level.

The voltage conversion circuit may comprise a reference voltage generation circuit and an output buffer or buffer amplifier.

The invention also provides an electronic device comprising: analogue circuit components; digital circuit components; a power supply for providing a first voltage for the analogue circuit components; and a voltage generation circuit of the invention for generating a second voltage for the digital circuit components from the first voltage.

The device may be a display, and the analogue circuit components comprise at least digital to analogue converter circuits, and the digital circuit components comprise at least memory devices or control circuits. The power saving command signal can be provided in response to a standby or sleep mode of operation of the device. The invention also provides a method of generating from a first voltage, a second, lower, voltage, the method comprising: using a voltage conversion circuit to generate the second voltage from the first voltage; receiving a power saving command signal; switching off the voltage conversion circuit; monitoring the second voltage while the conversion circuit is turned off; and switching on the voltage conversion circuit when the second voltage has dropped a predetermined threshold below the desired voltage level, until the second voltage has returned to the desired second voltage level. An example of the invention will now be described in detail with reference to the accompanying drawings, in which: Fig. 1 shows a known voltage generation circuit;

Fig. 2 shows a voltage generation circuit of the invention; and Fig. 3 shows an electronic device of the invention.

The invention provides a voltage conversion circuit which is controlled by a control circuit for activating the voltage conversion circuit in response to a control input. The control input is generated by a logic circuit which processes a power saving command signal for placing the voltage conversion circuit into a power saving mode. The voltage conversion circuit is operated only intermittently, so that power consumption is reduced. The voltage conversion circuit can comprise a voltage down-converter, and this is turned on in the sleep mode only if the output voltage (which may be a digital supply voltage) drops below a threshold level. This output voltage is for example stored on an external decoupling capacitor. When the voltage conversion circuit is turned on again, it restores the required level and returns to the sleep mode.. In the sleep mode, the logic circuit can consume less than 5 microamperes from the system supply.

A known way of generating a second (lower) power supply voltage from a first power supply voltage will be explained with reference to Figure 1. As will be clear from the description above, this will for example be used to generate a digital supply voltage from an analogue supply voltage, for use in mixed signal circuits that are supplied by a single supply voltage.

A comparator 10 compares an input "Vddd high" with the analogue supply voltage "Vdda", which may for example be 2.8V for the example of a display driver for a portable electronic device having a liquid crystal display.

When the input "Vddd high" is equal to the analogue supply voltage "Vdda", then the comparator 10 provides an output which operates to activate the voltage down- converter (the voltage conversion circuit) 12.

The comparator is designed to detect only when the supplies are tied together. The comparator thus acts as a control circuit for activating the voltage conversion circuit 12 in response to a control input Vddd high. The output of the comparator is a command signal "buf on" for switching on and off the voltage conversion circuit.

The voltage conversion circuit 12 comprises a reference generation circuit 14 for example a bandgap circuit. This bandgap circuit may for example be formed using two bipolar transistors, at least one resistor and one operational amplifier 16 or an arrangement of NMOS and/or PMOS transistors fulfilling this role. The operational amplifier 16 (buffer) which amplifies the reference voltage to the required digital voltage supply level Vddd, for example 1.8V for the mobile display driver example.

The reference generation circuit provides a reference output Vref, and a feedback path 18 having a potentiometer generates the reference voltage Vref from the digital output voltage Vddd to provide feedback control which provides the desired digital supply voltage Vddd at the output.

The current to operate the voltage conversion circuit 12 is taken from the analogue voltage supply line Vdda. When the digital supply voltage is not available from the system and is generated internally in this way, the operational amplifier 16 and the reference generation circuit 14 have to be turned on at ramp-up of the analogue voltage Vdda, and be active all the time. This is required even if the chip is in sleep mode, so that the digital circuit can respond to an input for bringing the circuit out of sleep mode. While the reference voltage generation circuit 14 and the operational amplifier 16 are switched on, they will consume power. This represents a main contributor to the power consumption of the device when in the sleep mode.

Turning off the voltage reference generation circuit 14 and the operational amplifier 16 will result in a loss of the digital supply voltage, which will fade out after a certain time. This output voltage is effectively provided to a decoupling capacitor Cdec with a series resistance, as shown in Figure 1. The output Vddd supplies the digital circuitry which is not shown in the figure.

Consequently, turning off the voltage conversion circuit 12 will result in the chip will losing state information, and the circuit would not be able to receive commands from the interface to end the sleep mode. As a result, the voltage conversion circuit cannot be turned on again without a hardware reset and ramping of the analogue voltage supply level Vdda.

Figure 2 shows the circuit of the invention. The circuit uses the same voltage conversion circuit 12, and the difference resides in the way in which the circuit is controlled. As shown in Figure 2, a different control input 20 is provided to the comparator 10, which is the control circuit for activating the voltage conversion circuit 12. This control input 20 "buf cmd" (buffer command) is generated by a logic circuit 22.

The logic circuit receives as input the second voltage level, namely the digital voltage supply level Vddd. Thus, the logic circuit is part of a feedback mechanism. The logic circuit 22 also operates on a power saving command signal "pwr off ' for placing the voltage conversion circuit 12 into a power saving mode. The output of the logic circuit is the control input 20 "buf cmd", and this is a non-activation signal when the power saving command is operating, but only until the digital voltage level Vddd reaches a predetermined (minimum) level. When this minimum level is reached, the control signal is switched to an activation signal, to turn on the voltage conversion circuit. This circuit maintains the digital supply voltage Vddd on the external decoupling capacitor. The voltage converter is thus switched off by a software command which generates the "pwr_off" signal, but the off state is only maintained as long as possible to prevent the loss of state information, so that a software command can always be used to come out of the sleep mode, without needing a reset of the analogue supply voltage Vdda. The logic circuit 22 has a switching element 24 with a switching response with hysteresis. By this is meant that the switching characteristic/point in a voltage increasing mode is different to the switching characteristic/point in a voltage decreasing mode. This means the device can be used to sense two voltage limits. The device responds when the input voltage increases to a first predetermined level, and responds when the input voltage decreases to a second predetermined level.

The switching element can be implemented as a Schmitt trigger. In this application, the Schmitt trigger is designed to switch on when the input Vddd increases to the desired voltage level of 1.8V in this example. As will be explained below, when this happens, the voltage Vddd starts to drop because the voltage converter is turned off. The Schmitt trigger is then designed to turn off again when the output has dropped to a lower level, for example 1.5 V.

The logic circuit comprises the switching element 24 and a NAND gate 28 which provides a power up command signal 29 when the power saving command signal "pwr_off" is high, and when the switching element 24 is providing a low signal. Thus, a low output signal of the element 24 is a signal to power up, and a high output signal of the element 24 is a signal to save power.

As explained above, the switching element 24 provides a low signal when the output voltage Vddd increases to 1.8V or when it decreases to 1.5V. The difference of 0.3V is a hysteresis threshold level.

An AND gate 30 provides the control circuit actuation signal 20 when the power up command signal 29 is high and when a power supply line Vddd high is on.

The signal Vddd high is the control signal used in the prior art of Figure 1 , and indicates that the digital supply voltage Vddd is being provided by the system and is correct. This signal can be used to override the on-chip generation of the digital supply voltage if an external digital supply is instead available. Thus, the switching level of the input signal Vddd high is chosen in such way that an externally provided digital supply voltage Vddd can be used to switch the whole on-chip voltage generation to be in an OFF state.

The logic circuit is powered by the first, analogue supply voltage Vdda, and the output 20 of the logic circuit is either a low power line voltage or the first voltage level Vdda.

The logic circuit enables the voltage conversion circuit to be switched off with a digital software-generated signal The very low current consumption of the digital circuitry driven by the second voltage level Vddd in the non-active mode means that the recharge operation will be needed only periodically and infrequently. The recharge operation will consume energy only when the output voltage Vddd drops too low. In this case, the signal buf cmd at the input of the comparator 10 is driven to the analogue voltage Vdda and the voltage down-converter is active.

The logic circuit remains active all the time, but this consumes a much lower power than the voltage reference circuit and buffer amplifier.

When the voltage is restored, the voltage conversion circuit will again switch to the inactive mode. The average current drain can be reduced to approximately 1 to 2 microamps compared with 30 to 50 microamps when all the voltage conversion circuit is active all the time. During start up of the circuit, no voltage is available on Vddd.

The voltage supply line Vddd high can be hard- wired to the analogue voltage Vdda, and at start up, the power off signal "pwr off ' is 0 (even if the device is to be in sleep mode, because there is no digital voltage supply yet for the generation of any high digital output). The 0 input to the NAND gate 28 gives a high output, and the logic function of the circuit thus provides an active command to the voltage conversion circuit, so that it will start correctly.

The circuit thus has the advantage that in the sleep mode the voltage conversion circuit generating the digital supply voltage consumes only the required current to maintain a voltage at the output and only infrequently. This translates into a very low system consumption.

The voltage generation circuit can be used in any circuit application where one power supply voltage is converted to generate a further power line voltage. The invention can be used whenever there is a desire to have different supply voltage levels. This will often arise when there are analogue devices, such as physical input or output devices (like sensors, displays, audio output devices) combined with digital control and signal processing devices.

One specific example is shown in Figure 3.

Figure 3 shows a portable electronic device 40 (a mobile telephone by way of example) which has an LCD screen 42. The LCD module has a driver IC 44, which includes a voltage generation circuit 46 of the invention.

The display module includes the LCD cell and the display driver ICs 44, which may be mounted on the same glass substrate as the pixel circuitry, or connected to the substrate with a TCP or foil. The voltage generation circuit 46 is part of the driver IC and provides the digital supply voltage necessary to drive the LCD cell. The display module can be used in small portable devices such as cellular phones (as shown) or in other devices such as Personal Digital Assistants (PDAs).

The invention can of course be applied to other display driver circuits, whether based on liquid crystal technology or other display technologies. The invention is not limited to portable devices, and may find application in LCD television sets or computer LCD monitors for example.

The invention thus provides a method to supply a mixed signal circuit which needs at least two supply voltages from one and unique supply voltage, for example available from a power management unit. The integrated voltage conversion unit no longer has to function and consume power constantly from the supply, namely in sleep (or inactive) mode, but still enables no loss of stored information in the digital circuits.

A small circuit of a few logic gates and an appropriate threshold selection is required to enable the digital power supply to be maintained. The power saving in the inactive mode may be of the order of 100, depending on the implementation. Only one detailed example has been given above, but it should appreciated that there are many other examples of voltage conversion circuit 12 to which the invention could be applied. The invention relates to the control of any such voltage conversion circuit between active and inactive states in order to preserve state in the circuits driven by the converted voltage and to reduce power consumption in the non-active mode.

Similarly, only one example of logic circuit has been given for implementing the control function. Many other logic circuit implementations are possible, and using different hysteresis elements or arrangements. The desired hysteresis function can of course be implemented without requiring a single device with hysteresis, as the function is essentially the monitoring of two voltage levels, with an appropriate control decision being taken each time one of the two voltage levels is reached.

The voltage conversion circuit is conventional and has not been described in detail. Other than the bandgap circuit mentioned, many other types of voltage shift circuits will be well known to those skilled in the art. Various other modifications will be apparent to those skilled in the art.

Claims

CLAIMS:

1. A voltage generation circuit, comprising: a voltage conversion circuit (12) for receiving a first voltage (vdda) and generating a second, lower, voltage (vddd) from the first voltage; a control circuit (10) for activating the voltage conversion circuit in response to a control input (buf cmd); and a logic circuit (22) for generating the control input (buf cmf); wherein the logic circuit (22) receives as input the second voltage level (vddd), and a power saving command signal (pwr off) for placing the voltage conversion circuit into a power saving mode; wherein the logic circuit (22) is adapted to provide as control input (buf cmd) a non-activation output signal in response to the power saving command (pwr off) until the second voltage level (vddd) reaches a predetermined level, and then to provide an activation output signal.

2. A circuit as claimed in claim 1, wherein the logic circuit (22) comprises a switching element (24) with a switching response with hysteresis.

3. A circuit as claimed in claim 2, wherein the switching element (24) comprises a Schmitt trigger.

4. A circuit as claimed in claim 2 or 3, wherein the logic circuit (22) comprises: the switching element (24); a first logic gate arrangement (28) for providing a power up command signal (29) when the power saving command signal is on and when the switching element toggles in response to the second voltage level dropping more than a hysteresis threshold below the desired second voltage level.

5. A circuit as claimed in claim 4, wherein the first logic gate arrangement (28) comprises a NAND gate (28).

6. A circuit as claimed in claim 4 or 5, wherein the logic circuit further comprises a second logic gate arrangement (30) for providing a control circuit actuation signal when the power up command signal (29) is on and when a power supply line is on.

7. A circuit as claimed in claim 6, wherein the second logic gate arrangement comprises an AND gate (30).

8. A circuit as claimed in any preceding claim, wherein the logic circuit is powered by the first voltage (vdda).

9. A circuit as claimed in claim 8, wherein the output of the logic circuit (22) is either a low power line voltage or the first voltage level.

10. A circuit as claimed in claim 9, wherein the control circuit (10) comprises a comparator (10) for comparing the control input (buf cmd) with the first voltage level (vdda).

11. A circuit as claimed in any preceding claim, wherein the voltage conversion circuit (12) comprises a reference voltage generation circuit (14) and an output buffer (16).

12. A circuit as claimed in claim 11, wherein the output buffer (16) comprises a buffer amplifier.

13. An electronic device (42) comprising: analogue circuit components; digital circuit components (44); a power supply for providing a first voltage (vdda) for the analogue circuit components; and a voltage generation circuit (46) as claimed in any preceding claim for generating a second voltage for the digital circuit components from the first voltage.

14. A device as claimed in claim 13, comprising a display device (42), wherein the analogue circuit components comprise at least digital to analogue converter circuits, and the digital circuit components comprise at least memory devices or control circuits.

15. A device as claimed in claim 13 or 14, wherein the power saving command signal is provided in response to a standby or sleep mode of operation of the device.

16. A device as claimed in any preceding claim, wherein the power consumption of the logic circuit when operating is lower than the power consumption of the voltage conversion circuit when operating.

17. A method of generating from a first voltage (vdda), a second, lower, voltage (vddd), the method comprising: using a voltage conversion circuit (12) to generate the second voltage from the first voltage; receiving a power saving command signal (pwr off); switching off the voltage conversion circuit (12); monitoring the second voltage (vddd) while the conversion circuit (12) is turned off; switching on the voltage conversion circuit (12) when the second voltage

(vddd) has dropped a predetermined threshold below the desired voltage level, until the second voltage has returned to the desired second voltage level.

18. A method as claimed in claim 17, wherein the monitoring is carried out using a switching element (24) with a switching response with hysteresis.

19. A method as claimed in claim 18, wherein the monitoring is carried out using a Schmitt trigger (24).

20. A method as claimed in claim 18 or 19, wherein the monitoring is carried out using a logic circuit (22) which comprises: the switching element (24); a logic gate arrangement (28) for providing a power up command signal when the power saving command signal is on and when the switching element toggles in response to the second voltage level dropping more than a hysteresis threshold below the desired second voltage level.

21. A method as claimed in claim 20, further comprising powering the logic circuit (22) with the first voltage (vdda).

22. A method as claimed in any one of claims 17 to 21 wherein the power saving command signal (pwr off) is generated in response to a sleep or standby mode of operation.