JP6538369B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a function of protecting a circuit from a high voltage frequency signal.

  In the wireless communication system, the received electric field strength at the receiving device changes depending on the communication distance between the transmitting device and the receiving device. Therefore, when the communication distance becomes extremely small, a carrier signal having a relatively large voltage value is supplied to the input stage on the receiving device side, and the circuit that performs signal processing on the carrier signal There is a possibility that the malfunction that it does not operate normally may occur.

  Therefore, in order to eliminate such a problem, a semiconductor device provided with a protective circuit has been proposed (see, for example, Patent Document 1).

  The protection circuit first rectifies a carrier signal supplied via one end of the antenna circuit to obtain a DC voltage representing the amplitude of the carrier signal, and the DC voltage is higher than a predetermined voltage, that is, so-called over voltage It detects whether or not it is in the state. Under the present circumstances, when it is detected that it is in the state of overvoltage, the one end of an antenna circuit is set to earth potential by setting the transistor connected to the end of an antenna circuit in an ON state. As a result, the protection circuit is in a protection operation state, and the voltage value of the carrier signal is forcibly reduced. On the other hand, when it is detected that there is no overvoltage state, the transistor is set to the off state, and the protection operation by this protection circuit is cancelled.

Unexamined-Japanese-Patent No. 2010-259066

  However, in the configuration of the protection circuit described above, there is a problem that the time from when the voltage value of the frequency signal such as the carrier signal transitions from the non-overvoltage state to the overvoltage state is long until the protection circuit actually starts the protection operation. was there.

  Therefore, an object of the present invention is to provide a semiconductor device capable of quickly starting a protection operation by following changes in voltage value of a frequency signal.

The semiconductor device according to the present invention receives the frequency signal at the first line, a semiconductor device is supplied to the internal circuit and amplifies it, one terminal of the source terminal and the drain terminal to the first line A first transistor connected and having a ground potential applied to the other of the source terminal and the drain terminal, and a divided voltage obtained by dividing the voltage of the first line is the first transistor. A voltage protection circuit including a voltage dividing circuit for supplying to the gate terminal of the transistor, and one end connected to the first line, and supplying a DC removal frequency signal obtained by removing a DC component from the frequency signal to the second line A bias circuit for applying a bias voltage to the second line, and an amplified frequency signal obtained by amplifying the DC removal frequency signal supplied to the second line. And a detection circuit for generating a bias adjustment signal having a level corresponding to the amplitude of the amplified frequency signal, wherein the bias circuit increases the level of the bias adjustment signal as the level of the bias adjustment signal increases. The bias voltage is suppressed .

  In the present invention, the following voltage protection circuit is provided for relaying the frequency signal supplied via the first line to the internal circuit. The voltage protection circuit includes a first transistor in which one of the source terminal and the drain terminal is connected to the first line and the ground potential is applied to the other terminal, and a voltage of the first line. And a voltage dividing circuit for supplying a divided voltage obtained by dividing the voltage to the gate terminal of the first transistor.

  According to this voltage protection circuit, when the voltage value of the frequency signal becomes a high voltage equal to or higher than the predetermined voltage value, the first transistor is turned on, and the current from the first line flows into the first transistor. . As a result, the amplitude of the frequency signal supplied via the first line is reduced, and the voltage applied to the circuit that performs signal processing on the frequency signal is reduced. It is possible to protect.

  Furthermore, in the voltage protection circuit, the first transistor is directly controlled by the divided voltage obtained by dividing the voltage value of the frequency signal. On the other hand, it becomes possible to start the voltage drop process.

  Therefore, according to the present invention, it is possible to quickly start the protection operation by following the change in the voltage value of the frequency signal.

It is a circuit diagram showing composition of signal relay part 100 as a semiconductor device concerning the present invention. It is a figure showing the voltage value of the high frequency signal RF corresponding to the receiving electric field strength of the antenna 10 in the structure shown in FIG. 5 is a circuit diagram showing another configuration of the signal relay unit 100. FIG. It is a figure showing the voltage value of the high frequency signal AF corresponding to the receiving electric field strength of the antenna 10 in the structure shown in FIG. Bias circuit 13 employed when a single bias circuit 13 (13a) is provided to each of the input signal line connected to the non-inverted input terminal of the differential circuit and the input signal line connected to the inverted input terminal It is a circuit diagram which shows an example of an internal structure of (13a).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a signal relay unit 100 as a semiconductor device according to the present invention. The signal relay unit 100 shown in FIG. 1 is included in the front stage of the low noise amplifier for high frequency signal amplification formed in the wireless receiving apparatus.

  In FIG. 1, a high frequency signal RF received and obtained by the antenna 10 is supplied to the line L1 via the input terminal of the signal relay unit 100 formed in the semiconductor chip.

  The electrostatic protection circuit 11 has an anode terminal connected to the line L1 and a cathode terminal to which a power supply voltage VDD is applied, a cathode terminal connected to the line L1, and an anode terminal to the ground potential GND. And the diode D2 to which is applied. With such a configuration, the electrostatic protection circuit 11 causes a large current, which flows into the line L1 through the antenna 10, to flow to the ground line or the power supply line (not shown) in response to electrostatic discharge to absorb the large current.

  One end of the capacitor 12 is connected to the line L1, and the other end of the capacitor 12 is connected to the line L2. The capacitor 12 supplies to the line L2 a DC-removed high-frequency signal RFQ from which the DC component of the high-frequency signal RF supplied from the antenna 10 via the line L1 has been removed.

  The bias circuit 13 includes a current source G1, an n-channel MOS (Metal-Oxide-Semiconductor) type transistor Q1, and resistors R1 and R2. The output terminal of the current source G1 is connected to one end of the resistor R2 and the drain and gate terminals of the transistor Q1. The other end of the resistor R2 is connected to the line L2. One end of a resistor R1 is connected to the source terminal of the transistor Q1. The ground potential GND is applied to the other end of the resistor R1. The current source G1 receives the supply of the power supply voltage VDD to generate a predetermined constant current, and sends the constant current to the line L2 through the resistor R2, and the constant current to the drain terminal and the gate terminal of the transistor Q1. Send out. With such a configuration, the bias circuit 13 uses the resistor R2 as a bias voltage VB for reliably operating the transistor 14, with the voltage generated at the connection point between the drain terminal and the gate terminal of the transistor Q1 and the output terminal of the current source G1. The voltage is applied to the line L2 via The resistor R2 is provided to prevent the direct current removal high frequency signal RFQ from flowing into the current source G1 and the transistor Q1 through the line L2. Therefore, the resistor R2 has a high resistance value that can prevent the flow into the current source G1 and the transistor Q1 due to the DC removal high frequency signal RFQ. Further, in order to prevent the flow into the current source G1 and the transistor Q1 due to the direct current removal high frequency signal RFQ, an inductor may be used instead of the resistor R2. If the flow into the bias circuit 13 does not occur due to the DC removal high frequency signal RFQ, or the problem does not occur, the output terminal of the current source G1 may be directly connected to the line L2.

  The transistor 14 is, for example, an n-channel MOS transistor, the ground terminal GND is applied to the source terminal, and the drain terminal is connected to one end of the load resistor 15 and the line L3. The power supply voltage VDD is applied to the other end of the load resistor 15. With this configuration, the transistor 14 supplies the amplified high frequency signal AF obtained by amplifying the DC-removed high frequency signal RFQ supplied to the gate terminal to the next stage internal circuit (not shown) via the line L3.

  That is, the signal relay unit 100 relays the high frequency signal received and obtained by the antenna 10 to the internal circuit of the next stage via the line L 1, the capacitor 12 and the transistor 14.

  The high voltage protection circuit 20 has a voltage dividing circuit including resistors 21 and 22 and a transistor 23 which is an n channel MOS type transistor. One end of the resistor 21 is connected to the line L 1, and the other end of the resistor 21 is connected to the gate terminal of the transistor 23 and one end of the resistor 22. The ground potential GND is applied to the other end of the resistor 22. The drain terminal of the transistor 23 is connected to the line L1, and the ground potential GND is applied to the source terminal.

  With this configuration, the divided voltage DV obtained by dividing the voltage value of the high frequency signal RF by the voltage dividing circuit (21 and 22) is supplied to the gate terminal of the transistor 23 of the high voltage protection circuit 20. The transistor 23 is turned off when the voltage value of the divided voltage DV is lower than its own threshold voltage Vth. On the other hand, when the voltage value of the divided voltage DV is equal to or higher than the threshold voltage Vth, the transistor 23 is turned on, and a current flows from the line L1 to the ground line. Accordingly, the high voltage protection circuit 20 reduces the voltage value of the line L1, that is, the voltage value of the high frequency signal RF input to the signal relay unit 100 (voltage reduction process).

  Hereinafter, the operation of the high voltage protection circuit 20 will be described with reference to FIG. In FIG. 2, the broken line H represents the voltage value of the high frequency signal RF corresponding to the received electric field strength of the antenna 10 when the high voltage protection circuit 20 is not provided. The solid line J represents the voltage value of the high frequency signal RF corresponding to the received electric field strength of the antenna 10 when the high voltage protection circuit 20 is provided.

  First, as shown in FIG. 2, when the received electric field strength is lower than the strength Y1, that is, when the voltage value of the high frequency signal RF supplied to the line L1 through the antenna 10 is lower than the voltage value V1 shown in FIG. The transistor 23 of the high voltage protection circuit 20 is turned off. Therefore, at this time, the voltage reduction process by the high voltage protection circuit 20 is not performed, and as shown by the solid line J in FIG. It is supplied to the gate terminal of the transistor 14 via the line L2 as RFQ.

  On the other hand, when the received electric field strength is higher than the strength Y1, that is, when the voltage value of the high frequency signal RF is higher than the voltage value V1, the transistor 23 of the high voltage protection circuit 20 is turned on. A brownout process is performed. As a result, current flows from the line L1 to the ground line through the transistor 23, and the voltage value of the line L1, that is, the voltage value of the high frequency signal RF decreases. Therefore, as shown by the solid line J in FIG. 2, when the voltage value of the high frequency signal RF is equal to or higher than the voltage value V1, the voltage value of the high frequency signal RF when the high voltage protection circuit 20 is not provided (broken line In comparison with H), the voltage value of the high frequency signal RF is lower. That is, when the voltage value of the high frequency signal RF becomes a high voltage equal to or higher than the voltage value V1, the voltage value applied to the gate terminal of the transistor 14 becomes lower than when the high voltage protection circuit 20 is not provided. is there.

  Here, in the n-channel MOS transistor, when the drain voltage or the gate voltage becomes high, electrons that have obtained energy by the high electric field, that is, so-called hot carriers may jump into the gate insulating film. At this time, so-called hot carrier deterioration occurs, which is characteristic deterioration such as fluctuation of the threshold voltage Vth and reduction of the mutual conductance Gm.

  Therefore, when the voltage value of the high frequency signal RF is a high voltage equal to or higher than the voltage value V1, the high voltage protection circuit 20 is configured to execute voltage reduction processing to reduce the voltage value. As a result, the amplitude of the high frequency signal RF is reduced, and the voltage value supplied to the gate terminal of the n-channel MOS transistor 14 is reduced, so that the transistor 14 can be protected from hot carrier deterioration.

  Furthermore, in the high voltage protection circuit 20, the divided voltage DV obtained by dividing the voltage value of the high frequency signal RF transmitted through the line L1 is directly supplied to the gate terminal of the transistor 23, thereby controlling the transistor 23. It is like that.

  Therefore, according to the high voltage protection circuit 20, the voltage is processed more quickly than in the conventional protection circuit in which the voltage reduction process is performed on the frequency signal according to the direct current voltage obtained by converting the frequency signal into a direct current by the rectification circuit. It is possible to start degradation processing.

  FIG. 3 is a circuit diagram showing another configuration of signal relay unit 100 shown in FIG. In the configuration shown in FIG. 3, the configuration shown in FIG. 1 is newly provided with the detection circuit 16, and the other configuration except that the bias circuit 13a is employed instead of the bias circuit 13 is the one shown in FIG. Is the same as Further, the configuration of the bias circuit 13a is the same as that shown in FIG. 1 except that the variable current source GC1 is employed instead of the current source G1 shown in FIG.

  The detection circuit 16 detects the amplitude of the amplified high frequency signal AF output from the transistor 14, and supplies a bias adjustment signal BC having a voltage value corresponding to the amplitude to the variable current source GC1.

  The variable current source GC1 receives the supply of the power supply voltage VDD, and generates a current having a smaller amount of current as the voltage value of the bias adjustment signal BC is higher, to the line L2 and to the drain and gate terminals of the transistor Q1. Send out.

  Therefore, the bias circuit 13a applies a bias voltage VB having a voltage value that decreases as the amplitude of the amplified high frequency signal AF increases, to the gate terminal of the transistor 14 via the line L2. Accordingly, when the amplitude of the amplified high frequency signal AF is large, the bias voltage VB is small as compared with the case where the amplitude is small, and the gain of the transistor 14 is reduced. Thereby, it is possible to set the limit value of the voltage value that can be taken as the drain voltage of the transistor 14, that is, the maximum value of the amplitude of the amplified high frequency signal AF.

  That is, in this case, when the amplitude of the amplified high frequency signal AF becomes larger than the predetermined reference amplitude, the detection circuit 16 changes the bias adjustment signal BC having a voltage value corresponding to the magnitude of the variable current source GC1. Supply to As a result, the bias circuit 13a and the detection circuit 16 operate as a so-called limiter in which amplitude limitation is performed so that the maximum value of the amplitude of the amplified high frequency signal AF does not exceed a predetermined value.

  Therefore, transistor 14 can be protected from hot carrier degradation by setting the above reference amplitude to a maximum voltage value that can be taken as a voltage value that does not cause hot carrier degradation in transistor 14 in detection circuit 16. .

  Hereinafter, the protection operation by the configuration shown in FIG. 3, which has been made in view of the above point, will be described with reference to FIG. 4. In FIG. 4, the broken line H represents the voltage value of the high frequency signal AF corresponding to the received electric field strength of the antenna 10 when the high voltage protection circuit 20 and the detection circuit 16 are not provided. The solid line J represents the voltage value of the high frequency signal AF corresponding to the received electric field strength of the antenna 10 when the high voltage protection circuit 20 and the detection circuit 16 are provided.

  First, as shown in FIG. 4, when the received electric field strength is lower than the strength Y1, that is, when the voltage value of the high frequency signal RF supplied to the line L1 through the antenna 10 is lower than the voltage value V1, it is high. The transistor 23 of the voltage protection circuit 20 is turned off. Therefore, at this time, the voltage reduction process by the high voltage protection circuit 20 is not performed, and as indicated by the solid line J in FIG. It is supplied to the gate terminal of the transistor 14 via the line L2 as RFQ.

  Here, when the received electric field strength is higher than the strength Y1, that is, as shown in FIG. 4, when the voltage value of the high frequency signal RF is higher than the voltage value V1, the transistor 23 of the high voltage protection circuit 20 is turned on. In the high voltage protection circuit 20, voltage reduction processing is performed. As a result, a current flows from the line L1 to the ground line through the transistor 23, and the voltage value of the line L1, that is, the voltage value of the high frequency signal RF decreases. Therefore, as indicated by the solid line J in FIG. 4, when the voltage value of the high frequency signal RF is equal to or higher than the voltage value V1, the voltage value of the high frequency signal RF when the high voltage protection circuit 20 is not provided (broken line In comparison with H), the voltage value of the high frequency signal RF is lower. Therefore, when the voltage value of the high frequency signal RF is a high voltage equal to or higher than the voltage value V1, the voltage value applied to the gate terminal of the transistor 14 is lower than in the case where the high voltage protection circuit 20 is not provided. . As a result, the voltage value supplied to the gate terminal of the n-channel MOS transistor 14 is reduced, so that the transistor 14 can be protected from hot carrier deterioration.

  Then, when the received electric field strength is higher than the strength Y1 or higher, that is, the voltage value of the high frequency signal RF becomes higher than the voltage value V2 shown in FIG. 4, the detection circuit 16 adjusts the bias to reduce the voltage value of the bias voltage VB. The signal BC is supplied to the bias circuit 13a. Thereby, the limiter processing by the bias circuit 13a is performed, and as shown in FIG. 4, the voltage value of the high frequency signal RF is maintained at the voltage value V2 regardless of the increase of the reception electric field strength. The voltage value V2 is the maximum value of the gate voltage value at which there is no risk of hot carrier deterioration in the transistor 14.

  Therefore, the voltage value applied to the drain terminal of the transistor 14 is limited to the maximum value (V2) of the voltage value at which the hot carrier deterioration does not occur in the transistor 14, so that the hot carrier deterioration can be suppressed. It becomes.

  In the embodiment shown in FIG. 3, the high voltage protection circuit 20 is provided together with the bias circuit 13a and the detection circuit 16. However, the high voltage protection circuit 20 is not provided but only the bias circuit 13a and the detection circuit 16 are It is possible to suppress hot carrier deterioration.

  In addition, although FIG. 1 and FIG. 3 show an example of the configuration in the case where the input signal protects the transistor 14 which is one amplifier system from hot carrier deterioration, the differential circuit where the input signal is two systems is hot. The same is applicable to the case of protecting from carrier deterioration. In short, at this time, the high voltage protection circuit 20 and the bias voltage circuit 13 (13a) are connected to the input signal line connected to the non-inverted input terminal of the differential circuit and the input signal line connected to the inverted input terminal. And the detection circuit 16 are provided. As for the bias voltage circuit 13 (13a) and the detection circuit 16, each single bias voltage circuit 13 (13a) and the detection circuit 16 are input signal lines connected to the non-inversion input terminal of the differential circuit, Alternatively, they may be commonly connected to each of the input signal lines connected to the inverting input terminal. However, in this case, in place of the bias voltage circuit 13 (13a), the bias voltage circuit 13X shown in FIG. 5 is employed.

  As shown in FIG. 5, the bias circuit 13X has the same configuration as the configuration shown in FIG. 1 or FIG. 3 except that a resistor R3 is newly provided. In the bias circuit 13X, one end of the resistor R2 is connected to the output terminal of the current source G1 (GC1) and the drain and gate terminals of the transistor Q1, and the other end of the resistor R2 is the non-inverting input of the differential circuit. It is connected to the line L2a connected to the terminal. In the bias circuit 13X, one end of the resistor R3 is connected to the output terminal of the current source G1 (GC1) and the drain and gate terminals of the transistor Q1, and the other end of the resistor R3 is the inverting input of the differential circuit. It is connected to the line L2b connected to the terminal. That is, the bias voltage VB generated by each single current source G1 (GC1) and the transistor Q1 is connected to the line L2a connected to the non-inverted input terminal of the differential circuit and to the inverted input terminal of the differential circuit Is applied to the line L2b.

  Further, in the configurations shown in FIG. 1 and FIG. 3, although the source grounded circuit is adopted as the amplification circuit by the transistor 14, a gate grounded circuit may be adopted.

  Further, in the configuration shown in FIG. 3, the detection circuit 16 is connected to the drain terminal of the transistor 14. However, when a plurality of transistors are connected in cascode between the drain terminal of the transistor 14 and the line L3, The detection circuit 16 is connected to the drain terminal of the transistor connected to the line L3.

  Although the embodiment shown in FIGS. 1 and 3 shows the configuration in the case where the signal relay unit 100 including the high voltage protection circuit 20 is provided at the front stage of the low noise amplifier provided in the wireless receiving apparatus, May be provided in a signal processing device other than the wireless receiving device. That is, as the signal relay unit 100, not only the high frequency signal transmitted from the antenna but also frequency signals having various frequencies may be input targets.

  Further, in the embodiment shown in FIG. 1 and FIG. 3, the protection target in the high voltage protection circuit 20 is the transistor 14 for amplifying the DC removed high frequency signal RFQ, but circuit elements or signal processing circuits other than amplification transistors May be protected.

  In the embodiment shown in FIGS. 1 and 3, the n-channel MOS transistor is employed as the transistor 23 of the high voltage protection circuit 20. However, a p-channel MOS transistor may be used. When a p-channel MOS transistor is used as the transistor 23, the source terminal of the transistor 23 is connected to the line L1, and the ground potential GND is applied to the drain terminal.

  In short, in relaying the frequency signal to the internal circuit through the first line (L1), the signal relay unit 100 includes the following first transistor (23) and the voltage dividing circuit (21, 22): What is necessary is just to include the voltage protection circuit (20) included. That is, in the first transistor, one of the source terminal and the drain terminal is connected to the first line, and the ground potential is applied to the other of the source terminal and the drain terminal. The voltage dividing circuit supplies a divided voltage (DV) obtained by dividing the voltage of the first line to the gate terminal of the first transistor.

  With this configuration, when the voltage value of the frequency signal is a high voltage equal to or higher than a predetermined voltage value, the first transistor is turned on, and the amplitude of the frequency signal supplied via the first line is reduced. As a result, the voltage applied to the circuit that performs signal processing on the frequency signal is reduced, so that the circuit for signal processing can be protected from the high voltage state.

12 capacitor 13, 13 a bias circuit 14, 23 transistor 15, 21, 22 resistor 16 detection circuit 20 high voltage protection circuit

Claims (4)

Receiving the frequency signal at the first line, a semiconductor device is supplied to the internal circuit and amplifies it,
A first transistor in which one of a source terminal and a drain terminal is connected to the first line, and a ground potential is applied to the other of the source terminal and the drain terminal; A voltage protection circuit including: a voltage dividing circuit that supplies a divided voltage obtained by dividing the voltage of the first line to the gate terminal of the first transistor ;
A capacitor having one end connected to the first line, and supplying a DC removal frequency signal obtained by removing a DC component from the frequency signal to the second line;
A bias circuit for applying a bias voltage to the second line;
A second transistor for supplying an amplification frequency signal obtained by amplifying the DC removal frequency signal supplied to the second line to the internal circuit;
A detection circuit that generates a bias adjustment signal having a level corresponding to the amplitude of the amplification frequency signal;
The semiconductor device, wherein the bias circuit suppresses the bias voltage as the level of the bias adjustment signal is higher .   In the voltage dividing circuit, a first resistor having one end connected to the first line and the other end connected to the gate terminal of the first transistor, and the ground potential applied to one end 2. The semiconductor device according to claim 1, further comprising: a second resistor to which the other end of the first resistor is connected at the other end. The detection circuit, the semiconductor device according to the bias adjustment signal when the amplitude becomes larger than the reference amplitude to claim 1 or 2, characterized in that to be supplied to the bias circuit. Before Symbol bias circuit,
The current source generates a current of a smaller amount as the level of the bias adjustment signal is higher, and sends the current from the output terminal,
A third transistor whose drain terminal and gate terminal are connected to the output terminal and the second line;
A resistor having one end connected to the source terminal of the third transistor and a ground potential applied to the other end,
The semiconductor according to any one of claims 1 to 3, wherein a voltage generated at a connection point between the drain terminal and the gate terminal of the third transistor and the output terminal is generated as the bias voltage. Device .

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