JP6533553B2 - 暗号化/復号装置及びその電力解析保護方法 - Google Patents
暗号化/復号装置及びその電力解析保護方法 Download PDFInfo
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- 238000005516 engineering process Methods 0.000 description 4
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- 238000013478 data encryption standard Methods 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
- G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
- H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/12—Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Health & Medical Sciences (AREA)
- Bioethics (AREA)
- General Health & Medical Sciences (AREA)
- Storage Device Security (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
110 データ暗号化/復号ユニット
120 乱数発生器
130 電力解析保護回路
200 論理演算ユニット
210 記憶ユニット
300_1〜300_N 電力信号発生器
500 リング発振器(リング・オシレータ)
510 NANDゲート
520 第1インバータ
530 第2インバータ
D1 デジタルデータ
D2 乱数データ
D1_1〜D2_N ビットデータ
K1 秘密鍵
SP1,SP2,SP3 電力信号
S610,S620 ステップ
Claims (6)
- 暗号化/復号演算をデジタルデータに対して実行するための暗号化/復号装置であって、
前記デジタルデータを受け取って、前記デジタルデータに対して暗号化/復号演算を実行するデータ暗号化/復号ユニットと、
乱数データを生成するよう構成され、前記乱数データはNビットを有し、Nは正の整数である乱数発生器と、
前記乱数発生器に接続された電力解析保護回路であって、前記乱数データを電力解析保護回路が受け取るとき前記乱数データの各ビットデータに基づく異なるレベルのM種類の電力信号を生成し、Mは2のN乗に等しい、該電力解析保護回路と、を備え、
前記電力解析保護回路はN個の電力信号発生器を備え、各電力信号発生器は、それぞれ乱数データにおける各ビットデータを受け取り、これにより異なる電力レベルの電力信号を生成し、
n番目の電力信号発生器が生成する電力信号は、2の(n−1)乗倍の単位電力に等しく、nは正の整数であり、1≦n≦Nであり、
n番目の電力信号発生器は、2の(n−1)乗個のリング発振器を備え、各リング発振器は、電力信号の1単位電力を生成し、
前記リング発振器は、
NANDゲートであって、前記NANDゲートの第1入力端子は、前記乱数データにおけるそのNANDゲートに対応する1つのビットデータを受け取る、該NANDゲートと、
第1インバータであって、前記第1インバータの入力端子は、前記NANDゲートの出力端子に接続されている、該第1インバータと、
第2インバータであって、前記第2インバータの入力端子は、前記第1インバータの出力端子に接続されており、また前記第2インバータの出力端子は、前記NANDゲートの第2入力端子に接続されている、該第2インバータと、
を備える、暗号化/復号装置。 - 前記データ暗号化/復号ユニットが前記暗号化/復号演算を実行しないとき、前記暗号化/復号装置は乱数発生器を停止させて、これにより前記電力解析保護回路が演算を停止するように制御する、請求項1に記載の暗号化/復号装置。
- 前記データ暗号化/復号ユニットは、
秘密鍵及び前記デジタルデータを受け取り、前記暗号化/復号演算を前記デジタルデータに対して前記鍵に基づいて実行する論理演算ユニットを備える、請求項1又は2に記載の暗号化/復号装置。 - 前記受け取られるビットデータが論理0であるとき、前記電力信号発生器は演算を停止する、請求項1に記載の暗号化/復号装置。
- 暗号化/復号装置に適用される電力解析保護方法であって、
乱数データを生成する乱数データ生成ステップであって、前記乱数データはNビットであり、Nは正の整数である、該乱数データ生成ステップと、 前記乱数データに基づいて電力解析保護回路の動作を開始させ、前記電力解析保護回路に対して、前記乱数データを電力解析保護回路が受け取るとき前記乱数データの各ビットデータに基づく異なるレベルのM種類の電力信号を生成させ、Mは2のN乗に等しいものである、ステップと、
を含み、
前記電力解析保護回路はN個の電力信号発生器を備え、各電力信号発生器は、それぞれ乱数データにおける各ビットデータを受け取り、これにより異なる電力レベルの電力信号を生成し、
n番目の電力信号発生器が生成する電力信号は、2の(n−1)乗倍の単位電力に等しく、nは正の整数であり、1≦n≦Nであり、
n番目の電力信号発生器は、2の(n−1)乗個のリング発振器を備え、各リング発振器は、電力信号の1単位電力を生成し、
前記リング発振器は、
NANDゲートであって、前記NANDゲートの第1入力端子は、前記乱数データにおけるそのNANDゲートに対応する1つのビットデータを受け取る、該NANDゲートと、
第1インバータであって、前記第1インバータの入力端子は、前記NANDゲートの出力端子に接続されている、該第1インバータと、
第2インバータであって、前記第2インバータの入力端子は、前記第1インバータの出力端子に接続されており、また前記第2インバータの出力端子は、前記NANDゲートの第2入力端子に接続されている、該第2インバータと、
を備える、電力解析保護方法。 - 前記暗号化/復号演算が実行されないとき、前記乱数データが生成されるのを停止し、これにより前記電力解析保護回路が演算を停止する、請求項5に記載の電力解析保護方法。
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CN201610242072.6A CN107306180B (zh) | 2016-04-19 | 2016-04-19 | 加解密装置及其功率分析防御方法 |
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JP6888377B2 (ja) * | 2017-04-05 | 2021-06-16 | 富士電機株式会社 | 情報処理装置、情報処理システム及びプログラム |
KR101876498B1 (ko) * | 2018-01-24 | 2018-08-09 | 국민대학교산학협력단 | 마스킹 대응책을 무력화하는 암호 해독 장치 및 방법, 이를 기록한 기록매체 |
CN110717201B (zh) * | 2019-09-12 | 2021-06-11 | 华中科技大学 | 一种抗简单功耗分析攻击的高斯采样电路 |
CN113312648B (zh) * | 2021-06-23 | 2023-10-31 | 国网黑龙江省电力有限公司绥化供电公司 | 一种基于数据加密的通讯模块及通讯方法 |
CN116522351A (zh) * | 2022-01-20 | 2023-08-01 | 瑞昱半导体股份有限公司 | 降低成功率的方法、密码系统处理电路及电子装置 |
US20240020383A1 (en) * | 2022-07-13 | 2024-01-18 | Nxp B.V. | Method and circuit for protecting an electronic device from a side-channel attack |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4799259A (en) * | 1986-04-10 | 1989-01-17 | Rockwell International Corporation | Monolithic random digital noise generator |
US6415032B1 (en) * | 1998-12-01 | 2002-07-02 | Xilinx, Inc. | Encryption technique using stream cipher and block cipher |
US6419159B1 (en) * | 1999-06-14 | 2002-07-16 | Microsoft Corporation | Integrated circuit device with power analysis protection circuitry |
DE59914370D1 (de) | 1999-11-03 | 2007-07-19 | Infineon Technologies Ag | Kodiervorrichtung |
US8145691B2 (en) * | 2006-02-24 | 2012-03-27 | Novell, Inc. | Techniques for random bit generation |
US7554865B2 (en) | 2006-09-21 | 2009-06-30 | Atmel Corporation | Randomizing current consumption in memory devices |
JP5203594B2 (ja) | 2006-11-07 | 2013-06-05 | 株式会社東芝 | 暗号処理回路及び暗号処理方法 |
US8522052B1 (en) * | 2010-04-07 | 2013-08-27 | Xilinx, Inc. | Method and integrated circuit for secure encryption and decryption |
TWI422203B (zh) * | 2010-12-15 | 2014-01-01 | Univ Nat Chiao Tung | 防禦差分功率分析攻擊之方法及電子裝置 |
CN102509036B (zh) | 2011-09-28 | 2014-11-12 | 东南大学 | 一种可重构密码处理器及抗功耗攻击方法 |
CN102710413A (zh) | 2012-04-25 | 2012-10-03 | 杭州晟元芯片技术有限公司 | 一种抗dpa/spa攻击的系统和方法 |
US9959429B2 (en) | 2013-03-15 | 2018-05-01 | Cryptography Research, Inc. | Asymmetrically masked multiplication |
US9755822B2 (en) | 2013-06-19 | 2017-09-05 | Cryptography Research, Inc. | Countermeasure to power analysis attacks through time-varying impedance of power delivery networks |
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CN107306180A (zh) | 2017-10-31 |
US10326586B2 (en) | 2019-06-18 |
JP2017195595A (ja) | 2017-10-26 |
US20170302435A1 (en) | 2017-10-19 |
CN107306180B (zh) | 2020-05-19 |
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