JP6529082B2 - Abnormality detection device for detecting an abnormality in voltage difference - Google Patents

Description

  The present invention relates to an abnormality detection apparatus that detects an abnormality in a voltage difference between two voltages.

  Conventionally, in various fields, an abnormality detection apparatus is used to detect an abnormality in a voltage difference between a predetermined first voltage and a second voltage corresponding to a detected physical quantity or the like. As such an apparatus, for example, in Patent Document 1, a voltage difference between two voltages V1X and V2X generated in an output winding 112X is detected by a transformer 30X, and the detected voltage difference is rectified by a rectification circuit 124 and rectified. , And a threshold (first voltage) generated from the reference voltage V are compared by the comparison circuit 125 (see FIG. 5).

  According to this circuit, it is possible to detect that a voltage difference larger than the threshold is generated between the two voltages V1X and V2X which should be identical, that is, a nonnegligible failure is generated in the output winding 112X. it can. Similarly, according to this circuit, it is also possible to detect that an unignorable failure has occurred in the output winding 112Y.

JP 2001-349748 A

  According to the circuit described in Patent Document 1, it can be detected that the voltage difference as the second voltage of the voltages V1X and V2X (or V1Y and V2Y) is larger than the threshold as the first voltage. However, since the circuit described in Patent Document 1 detects a failure of the output winding 112X (or 112Y) by one comparator 125A, the first limit value generated between the lower limit value and the upper limit value generated based on the first voltage It can not be detected that the two voltages are contained, and conversely, that the second voltage is out of the predetermined voltage range.

  The present invention has been made in view of the above circumstances, and the problem to be solved is an abnormality detection device capable of detecting that the second voltage is out of the voltage range generated based on the first voltage. To provide.

  In order to solve the above problems, the abnormality detection device according to the present invention detects an abnormality in a voltage difference between a predetermined first voltage and a second voltage input as a comparison target of the first voltage. A first amplifier circuit that inverts and amplifies a first voltage based on a predetermined first reference level; and a second reference that has an output voltage of the first amplifier circuit smaller than the first reference level As a lower limit, a second amplification circuit that performs inversion amplification on the basis of the level, a third amplification circuit that performs inversion amplification on the output voltage of the first amplification circuit on the basis of a third reference level that is larger than the first reference level A detection circuit for detecting an abnormality based on the magnitude relation between the output voltage of the second amplification circuit and the second voltage, and the magnitude relation between the output voltage of the third amplification circuit as the upper limit value and the second voltage, Of the second and third amplifier circuits Equal in the product of the gain of the gain and the second amplifier circuit of the first amplifier circuit is characterized in that it is a 1-fold.

  According to this configuration, it is possible to detect that the second voltage is out of the voltage range generated based on the first voltage. More specifically, an output voltage of a first amplifier circuit that inverts and amplifies the first voltage with reference to a predetermined first reference level is set to a second reference level (where the second reference level <the first reference level). The voltage generated by inverting and amplifying as a reference is the lower limit value, and the output voltage of the first amplification circuit is inverted and amplified based on a third reference level (where the third reference level> the first reference level) It is possible to detect that the second voltage is out of the voltage range with the upper limit value of the generated voltage.

  The detection circuit of the above-mentioned abnormality detection device can have various configurations.

  For example, the detection circuit includes a first comparator that compares the output voltage of the second amplifier circuit input to the negative terminal with the second voltage input to the positive terminal, and a third comparator input to the positive terminal. And a second comparator that compares the output voltage of the amplifier circuit with the second voltage input to the negative terminal, and an AND circuit or NAND circuit that logically outputs the outputs of the first and second comparators as inputs It may be

  Further, the detection circuit includes a first comparator for comparing the output voltage of the second amplification circuit input to the positive terminal with the second voltage input to the negative terminal, and a third comparator input to the negative terminal And a second comparator that compares the output voltage of the amplifier circuit with the second voltage input to the positive terminal, and an OR circuit or NOR circuit that logically outputs the outputs of the first and second comparators. It may be

  Preferably, in the abnormality detection device, the first reference level is the GND level, and the absolute values of the second and third reference levels are equal.

  According to this configuration, the circuit configuration is simplified and the design of the voltage range is facilitated.

  According to the present invention, it is possible to provide an abnormality detection device capable of detecting that the second voltage is out of the voltage range generated based on the first voltage.

FIG. 1 is a circuit diagram of an abnormality detection device according to a first embodiment of the present invention. FIG. 7 is a waveform diagram showing an operation of the abnormality detection device according to the first example at the normal time. FIG. 6 is a waveform diagram showing an operation at the time of abnormality of the abnormality detection device according to the first embodiment. It is a circuit diagram of an abnormality detection device concerning a 2nd example of the present invention. It is a circuit diagram of the conventional abnormality detection device.

  Hereinafter, with reference to the accompanying drawings, an embodiment of an abnormality detection apparatus according to the present invention will be described.

[First embodiment]
FIG. 1 shows an abnormality detection apparatus 1A according to a first embodiment of the present invention. As shown to the same figure, the abnormality detection apparatus 1A is provided with the 1st amplifier circuit 2, the 2nd amplifier circuit 3, the 3rd amplifier circuit 4, and the detection circuit 5A. According to the abnormality detection device 1A, it is possible to detect that the second voltage Vin2 input as a comparison target of the first voltage Vin1 is out of the voltage range generated based on the first voltage Vin1.

  The first amplifier circuit 2 includes an operational amplifier OP1 and two resistors R1 and R2. One end of the resistor R1 is connected to the first input terminal IN1, and the other end is connected to the inverting input terminal (-) of the operational amplifier OP1. One end of the resistor R2 is connected to the inverting input terminal of the operational amplifier OP1, and the other end is connected to the output terminal of the operational amplifier OP1. The noninverting input terminal (+) of the operational amplifier OP1 is grounded. The resistance value of each of the resistors R1 and R2 is 10 k [Ω].

  The first amplifier circuit 2 uses the first voltage Vin1 input from the first input terminal IN1 as a reference to a predetermined first reference level Vref1 (in this embodiment, Vref1 = GND level (0 [V])). Then, the voltage is inverted and amplified, and the voltage Vop1 obtained thereby is output. The gain G1 of the first amplifier circuit 2 is 1 (= R2 / R1 = 10 k / 10 k) times.

  The second amplification circuit 3 includes an operational amplifier OP2 and two resistors R3 and R4. One end of the resistor R3 is connected to the output of the first amplifier circuit 2, and the other end is connected to the inverting input terminal (-) of the operational amplifier OP2. One end of the resistor R4 is connected to the inverting input terminal (-) of the operational amplifier OP2, and the other end is connected to the output terminal of the operational amplifier OP2. The non-inverted input terminal (+) of the operational amplifier OP2 is connected to a DC power supply that outputs a voltage of the second reference level Vref2 (where Vref2 <Vref1). The resistance value of each of the resistors R3 and R4 is 10 k [Ω].

  The second amplifier circuit 3 inverts and amplifies the output voltage Vop1 of the first amplifier circuit 2 with reference to the second reference level Vref2, and outputs a voltage Vop2 obtained thereby. The gain G2 of the second amplifier circuit 3 is 1 (= R4 / R3 = 10 k / 10 k) times. Therefore, the product of the gain G2 of the second amplifier circuit 3 and the gain G1 of the first amplifier circuit 2 is one time.

In this embodiment, the output voltage Vop2 of the second amplifier circuit 3 can be expressed by the following equation. The output voltage Vop2 is obtained by shifting the first voltage Vin1 by Vref2.

Vop2 = Vin1 * (-G1) * (-G2) + Vref2
= Vin1 x (-1.0) x (-1.0) + Vref2
= Vin1 + Vref2

  The third amplifier circuit 4 includes an operational amplifier OP3 and two resistors R5 and R6. One end of the resistor R5 is connected to the output of the first amplifier circuit 2, and the other end is connected to the inverting input terminal (-) of the operational amplifier OP3. One end of the resistor R6 is connected to the inverting input terminal (-) of the operational amplifier OP3, and the other end is connected to the output terminal of the operational amplifier OP3. The noninverting input terminal (+) of the operational amplifier OP3 is connected to a DC power supply that outputs a voltage of a third reference level Vref3 (where Vref3> Vref1). The resistance value of each of the resistors R5 and R6 is 10 k [Ω].

  The third amplifier circuit 4 inverts and amplifies the output voltage Vop1 of the first amplifier circuit 2 with reference to the third reference level Vref3, and outputs a voltage Vop3 obtained thereby. The gain G3 of the third amplifier circuit 4 is 1.0 (= R6 / R5 = 10 k / 10 k) times. Therefore, the product of the gain G3 of the third amplifier circuit 4 and the gain G1 of the first amplifier circuit 2 is one time.

In this embodiment, the output voltage Vop3 of the third amplifier circuit 4 can be expressed by the following equation. The output voltage Vop3 is obtained by shifting the first voltage Vin1 by Vref3.

Vop3 = Vin1 × (−G1) × (−G3) + Vref3
= Vin1 x (-1.0) x (-1.0) + Vref3
= Vin1 + Vref3

  The detection circuit 5A includes a first comparator COMP1, a second comparator COMP2, an AND circuit AND, and two resistors R7 and R8. The resistance value of each of the resistors R7 and R8 is 2.2 k [Ω].

  The first comparator COMP1 is an output terminal having an open collector type, with the negative terminal (-) connected to the output of the second amplifier circuit 3, the positive terminal (+) connected to the second input terminal IN2, and Are connected to VCC (5 [V] in this embodiment) via the resistor R7. The output terminal of the second comparator COMP2 has an open collector type, with the positive terminal (+) connected to the output of the third amplifier circuit 4 and the negative terminal (−) connected to the second input terminal IN2. Are connected to VCC via resistor R8. In the AND circuit AND, one input terminal is connected to the output terminal of the first comparator COMP1, the other input terminal is connected to the output terminal of the second comparator COMP2, and the output terminal is connected to the detection result output terminal OUT. It is connected.

  The first comparator COMP1 compares the second voltage Vin2 input from the second input terminal IN2 with the voltage Vop2. Then, if the second voltage Vin2 is larger, a voltage Vcomp1 of VCC level (also referred to as “High level”) is output, and if the voltage Vop2 is larger, a voltage Vcomp1 of GND level (also referred to as “Low level”) is output. Do. The second comparator COMP2 compares the second voltage Vin2 with the voltage Vop3. When the voltage Vop3 is larger, the voltage Vcomp2 at the VCC level is output, and when the voltage Vin2 is higher, the voltage Vcomp2 at the GND level is output. The AND circuit AND outputs the voltage Vdet at the VCC level if both of the voltages Vcomp1 and Vcomp2 are at the VCC level, and outputs the voltage Vdet at the GND level otherwise.

  As described above, the detection circuit 5A sets the output voltage Vop2 (= Vin1 + Vref2) of the second amplification circuit 3 as the lower limit value and the output voltage Vop3 (= Vin1 + Vref3) of the third amplification circuit 4 as the upper limit value. If the voltage Vin2 is lower, the voltage Vdet at the VCC level is output, and otherwise the voltage Vdet at the GND level is output.

  For example, when the first voltage Vin1 is 5.0 [V], the second reference level Vref2 is -1.5 [V], and the third reference level Vref3 is +1.5 [V], the detection circuit 5A 2 Outputs a voltage Vdet of VCC level which indicates normal if the voltage Vin2 is within the range of 3.5 to 6.5 [V], and a voltage of GND level which indicates abnormal if the voltage Vin2 is not within Output Vdet.

  FIG. 2 is an operation waveform diagram when the voltage difference between the first voltage Vin1 and the second voltage Vin2 is small. In the entire region, the second voltage Vin2 is larger than the voltage Vop2 and smaller than the voltage Vop3. Therefore, detection circuit 5A outputs voltage Vdet at the VCC level in the entire region.

  FIG. 3 is an operation waveform diagram when the voltage difference between the first voltage Vin1 and the second voltage Vin2 is large. In a region where the second voltage Vin2 is smaller than the voltage Vop2, the voltage Vcomp1 is at the GND level, so the detection circuit 5A outputs the voltage Vdet at the GND level. Further, in a region where the second voltage Vin2 is larger than the voltage Vop3, the voltage Vcomp2 is at the GND level, so the detection circuit 5A outputs the voltage Vdet at the GND level. On the other hand, in the other region, both of the voltages Vcomp1 and Vcomp2 are at the VCC level, so the detection circuit 5A outputs the voltage Vdet at the VCC level.

  As described above, according to the abnormality detection device 1A according to the first embodiment, it is detected that the second voltage Vin2 is between the lower limit value and the upper limit value generated based on the first voltage Vin1. it can.

Second Embodiment
FIG. 4 shows an abnormality detection apparatus 1B according to a second embodiment of the present invention. As shown in the figure, the abnormality detection device 1B is different from the abnormality detection device 1A in that the abnormality detection device 1B includes the detection circuit 5B instead of the detection circuit 5A, but the other points are the same as the abnormality detection device 1A. doing.

  Similar to the detection circuit 5A, the detection circuit 5B includes a first comparator COMP1 and a second comparator COMP2. However, in the first comparator COMP1, the positive terminal (+) is connected to the output of the second amplifier circuit 3, and the negative terminal (−) is connected to the second input terminal IN2. The second comparator COMP2 has a negative terminal (-) connected to the output of the third amplifier circuit 4 and a positive terminal (+) connected to the second input terminal IN2.

  The detection circuit 5B includes a NOR circuit NOR instead of the AND circuit AND.

  The first comparator COMP1 compares the second voltage Vin2 with the voltage Vop2. When the second voltage Vin2 is larger, a voltage at the GND level is output, and when the voltage Vop2 is larger, a voltage at the VCC level is output. The second comparator COMP2 compares the second voltage Vin2 with the voltage Vop3. When the voltage Vop3 is larger, a voltage at the GND level is output, and when the second voltage Vin2 is larger, a voltage at the VCC level is output. The NOR circuit NOR outputs the voltage Vdet at the VCC level when both of the voltages Vcomp1 and Vcomp2 are at the GND level, and outputs the voltage Vdet at the GND level otherwise.

  As described above, the detection circuit 5B, like the detection circuit 5A, has the second voltage between the output voltage Vop2 (= Vin1 + Vref2) of the second amplifier circuit 3 and the output voltage Vop3 (= Vin1 + Vref3) of the third amplifier circuit 4. The voltage Vdet at the VCC level indicating that the operation is normal is output when Vin2 is within, and the voltage Vdet at the GND level indicating the abnormality is output otherwise.

[Modification]
As mentioned above, although the Example of the abnormality detection apparatus concerning this invention was described, this invention is not limited to these.

  For example, the detection circuits 5A and 5B can detect an abnormality based on the magnitude relationship between the voltage Vop2 as the lower limit value and the second voltage Vin2 and the magnitude relationship between the voltage Vop3 as the upper limit value and the second voltage Vin2. Any circuit configuration can be taken. For example, the AND circuit AND of the detection circuit 5A can be replaced with a NAND circuit. In this case, the detection circuit 5A outputs the voltage Vdet at the GND level indicating that it is normal, or the voltage Vdet at the VCC level indicating that it is abnormal. Similarly, the NOR circuit NOR of the detection circuit 5B can be replaced by an OR circuit. In this case, the detection circuit 5B outputs the voltage Vdet at the GND level indicating that it is normal, or the voltage Vdet at the VCC level indicating that it is abnormal.

  The gain G1 of the first amplifier circuit 2, the gain G2 of the second amplifier circuit 3, and the gain G3 of the third amplifier circuit 4 can be changed as appropriate. However, in the present invention, the gain G2 and the gain G3 must be equal, and the product of the gain G1 and the gain G2 (G3) must be one. As an example, when the gain G1 is doubled, the gains G2 and G3 need to be 0.5 times.

  The first reference level Vref1, the second reference level Vref2, and the third reference level Vref3 can be changed as appropriate. However, in the present invention, it is necessary to set the second reference level Vref2 smaller than the first reference level Vref1 and set the third reference level Vref3 larger than the first reference level Vref1. As an example, when the first reference level Vref1 is 1.5 [V], the second reference level Vref2 can be 0 [V] and the third reference level Vref3 can be 3 [V]. How much the second reference level Vref2 is to be reduced relative to the first reference level Vref1 and how high the third reference level Vref3 is to be relative to the first reference level Vref1 depends on the allowable voltage difference. You should decide.

  The circuit that generates the first reference level Vref1, the second reference level Vref2, and the third reference level Vref3 can be changed as appropriate. An applicable circuit is, for example, a voltage dividing circuit that divides a constant voltage with two or more resistors.

1A, 1B abnormality detection circuit 2 first amplifier circuit 3 second amplifier circuit 4 third amplifier circuit 5A, 5B detection circuit OP1 operational amplifier OP2 operational amplifier OP3 operational amplifier COMP1 first comparator COMP2 second comparator AND AND circuit NOR NOR circuit

Claims (4)

An abnormality detection device for detecting an abnormality in a voltage difference between a predetermined first voltage and a second voltage input as a comparison target of the first voltage,
A first amplifier circuit that inverts and amplifies the first voltage with reference to a predetermined first reference level;
A second amplification circuit that inverts and amplifies an output voltage of the first amplification circuit with reference to a second reference level that is smaller than the first reference level;
A third amplifier circuit that inverts and amplifies an output voltage of the first amplifier circuit with reference to a third reference level which is larger than the first reference level;
The abnormality is based on the magnitude relationship between the output voltage of the second amplification circuit as the lower limit value and the second voltage, and the magnitude relationship between the output voltage of the third amplification circuit as the upper limit value and the second voltage A detection circuit for detecting
Equipped with
An abnormality detection device characterized in that the gains of the second and third amplifier circuits are equal, and the product of the gain of the first amplifier circuit and the gain of the second amplifier circuit is one.   A first comparator for comparing the output voltage of the second amplifier circuit input to the negative terminal with the second voltage input to the positive terminal, and the detection circuit is input to the positive terminal A second comparator that compares the output voltage of the third amplifier circuit with the second voltage input to the negative terminal, and an AND circuit or NAND circuit that logically outputs the outputs of the first and second comparators as inputs The anomaly detection apparatus according to claim 1, further comprising:   A first comparator for comparing the output voltage of the second amplifier circuit input to the positive terminal with the second voltage input to the negative terminal; and the first input to the negative terminal A second comparator that compares the output voltage of the third amplifier circuit with the second voltage input to the positive terminal, and an OR circuit or NOR circuit that logically outputs the outputs of the first and second comparators as inputs The anomaly detection apparatus according to claim 1, further comprising:   The abnormality detection device according to any one of claims 1 to 3, wherein the first reference level is a GND level, and absolute values of the second and third reference levels are equal.

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