JP6527777B2 - Semiconductor device and mounting board having the same - Google Patents

Semiconductor device and mounting board having the same Download PDF

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JP6527777B2
JP6527777B2 JP2015153578A JP2015153578A JP6527777B2 JP 6527777 B2 JP6527777 B2 JP 6527777B2 JP 2015153578 A JP2015153578 A JP 2015153578A JP 2015153578 A JP2015153578 A JP 2015153578A JP 6527777 B2 JP6527777 B2 JP 6527777B2
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heat sink
semiconductor
semiconductor chip
stress
semiconductor device
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JP2017034131A (en
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隆雄 秋葉
隆雄 秋葉
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Ablic Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

本発明は、半導体装置及びそれを有する実装基板に関する。 The present invention relates to a semiconductor device and a mounting substrate having the same .

近年、自動車のエンジンルームなど高温の環境で高性能の動作が要求される半導体集積回路が組み込まれた半導体チップにおいては、半導体集積回路での自己発熱によりかかる回路部分を含む領域がさらに高温化してしまい、動作温度の上昇による熱暴走や特性劣化が問題となっている。従って、半導体チップにおいて、発熱部分を冷却する技術の開発が重要視されている。 In recent years, in a semiconductor chip incorporating a semiconductor integrated circuit in which high performance operation is required in a high temperature environment such as an automobile engine room, a region including the circuit portion is further heated by self heat generation in the semiconductor integrated circuit. As a result, thermal runaway and characteristic deterioration due to the rise in operating temperature are becoming problems. Therefore , in the semiconductor chip, development of a technique for cooling the heat generation portion is regarded as important.

図５は、ダイパッド１２の表面上に半導体チップ２を固定し、その全体を封止樹脂１で封止した半導体装置を図示している。ダイパッド１２の裏面が封止樹脂１から露出しているので放熱性が高い（例えば、特許文献１参照）。 FIG. 5 illustrates a semiconductor device in which the semiconductor chip 2 is fixed on the surface of the die pad 12 and the whole is sealed with the sealing resin 1. Since the back surface of the die pad 12 is exposed from the sealing resin 1, the heat dissipation is high (see, for example, Patent Document 1).

特開平０９−１９９６３９号公報Unexamined-Japanese-Patent No. 09-199639 gazette

特許文献１に示した発明における主な放熱経路は半導体チップ２の裏面からダイパッド１２へ、そして（図示していない）実装基板へ、という経路である。しかしながら、発熱する半導体集積回路は半導体チップの表面に配置されており、しかも、半導体チップ表面での発熱は不均一である。すなわち、局所的に高温となる部分が存在することになり、半導体集積回路の動作が不安定となる。   The main heat radiation path in the invention shown in Patent Document 1 is from the back surface of the semiconductor chip 2 to the die pad 12 and to the mounting substrate (not shown). However, the semiconductor integrated circuit that generates heat is disposed on the surface of the semiconductor chip, and the heat generation on the surface of the semiconductor chip is not uniform. That is, there is a locally high temperature portion, and the operation of the semiconductor integrated circuit becomes unstable.

本発明は、上記課題に鑑みてなされたもので、高温状況下でも半導体装置を構成する半導体チップ表面の熱を効率的に放熱し、半導体集積回路を正常に動作させることを目的とする。   The present invention has been made in view of the above problems, and has an object to efficiently dissipate heat of the surface of a semiconductor chip constituting a semiconductor device even under high temperature conditions, and to operate a semiconductor integrated circuit normally.

上記課題を解決するために以下の手段を用いた。
まず、半導体チップと、前記半導体チップの表面に設けられたバンプと、前記バンプが上面に接続されたリードと、前記半導体チップの表面に一端が接続された単層の応力緩衝放熱板と、前記半導体チップ、前記バンプ、前記リードの前記上面および前記応力緩衝放熱板の側面を覆う封止樹脂と、からなり、前記リードの下面および前記応力緩衝放熱板の他端が前記封止樹脂から露出しているとともに、同一水平面をなすように配置されていることを特徴とする半導体装置とした。また、前記応力緩衝放熱板は、金属フィラーを混練させた樹脂であることを特徴とする半導体装置とした。 The following means were used to solve the above problems.
First, a semiconductor chip, a bump provided on the surface of the semiconductor chip, a lead with the bump connected to the upper surface, a single-layer stress-buffered heat sink with one end connected to the surface of the semiconductor chip, And a sealing resin covering the semiconductor chip, the bump, the upper surface of the lead, and the side surface of the stress buffer heat sink, and the lower surface of the lead and the other end of the stress buffer heat sink are exposed from the sealing resin. The semiconductor device is characterized in that the semiconductor devices are arranged to form the same horizontal plane . Further, a semiconductor device is characterized in that the stress buffer heat sink is a resin obtained by kneading a metal filler.

また、前記応力緩衝放熱板は、他よりも発熱性の高い半導体集積回路領域に設けられ、前記発熱性の高い半導体集積回路領域を覆う形状であることを特徴とする半導体装置とした。
また、前記応力緩衝放熱板は、断面視的に台型で、前記半導体チップ側の前記一端の面積よりも前記封止樹脂から露出する前記他端の面積のほうが大きいことを特徴とする半導体装置とした。 In the semiconductor device, the stress-buffering heat sink may be provided in a semiconductor integrated circuit region having higher heat generation than the other, and may cover the semiconductor integrated circuit region having high heat generation.
The semiconductor device is characterized in that the stress buffer heat sink is trapezoidal in cross section and the area of the other end exposed from the sealing resin is larger than the area of the one end on the semiconductor chip side. And

さらに、前記応力緩衝放熱板の前記他端および前記リードの前記下面が半田によりランドと接続されている上述の半導体装置を有することを特徴とする実装基板とした。 Furthermore, the mounting substrate is characterized by including the above-described semiconductor device in which the other end of the stress buffer heat sink and the lower surface of the lead are connected to a land by solder .

上記手段を用いることで、半導体チップで発生した熱を効率的に放熱することが可能となり、半導体集積回路を正常に動作させることができる。   By using the above means, the heat generated in the semiconductor chip can be dissipated efficiently, and the semiconductor integrated circuit can be operated normally.

本発明の第１の実施形態にかかる半導体装置の断面図であるFIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施形態にかかる半導体装置の実装状態での断面図であるFIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention in a mounted state. 本発明の応力緩衝放熱板の拡大平面図であるIt is an enlarged plan view of the stress buffer heat sink of this invention. 本発明の第２の実施形態にかかる半導体装置の断面図であるFIG. 7 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. 従来の半導体装置の断面図であるFIG. 10 is a cross-sectional view of a conventional semiconductor device

図１は、本発明の第１の実施形態にかかる半導体装置の断面図である。本図においては下方の面となる半導体チップ２の表面には半導体集積回路が設けられ、この半導体チップ２の表面に設けられたバンプ３を介して外部接続のための端子となるリード４の上面と電気的導通がとれるように接続されている。半導体チップ２はフェイスダウン方式で表面に設けられた電極とリード４がバンプ３を介して接続され、半導体チップ２の内側の半導体集積回路領域は応力緩衝放熱板５の一端と絶縁性接着剤もしくは導電性接着剤６を介して接続されている。また、半導体チップ２、バンプ３、下面と側面の一部を除くリード４、他端を除く応力緩衝放熱板５はそれぞれ封止樹脂１によって被覆されている。応力緩衝放熱板５は側面が封止樹脂１によって被覆されることになる。従って、応力緩衝放熱板５の他端とリード４の下面は封止樹脂１によって覆われておらず、封止樹脂１から外部へと露出している。 FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. In the figure, the semiconductor integrated circuit is provided on the surface of the semiconductor chip 2 which is the lower surface, and the upper surface of the lead 4 which is a terminal for external connection through the bumps 3 provided on the surface of the semiconductor chip 2. It is connected so as to be able to establish electrical continuity. In the semiconductor chip 2, electrodes provided on the surface and the leads 4 are connected via the bumps 3 in a face-down manner, and the semiconductor integrated circuit region inside the semiconductor chip 2 is connected to one end of the stress buffer heat sink 5 and an insulating adhesive or It is connected via the conductive adhesive 6. The semiconductor chip 2, the bumps 3, the leads 4 except for the lower surface and the side surface, and the stress-buffering heat sink 5 except for the other end are covered with the sealing resin 1. The side surfaces of the stress-buffering heat sink 5 are covered with the sealing resin 1. Therefore, the other end of the stress buffer heat sink 5 and the lower surface of the lead 4 are not covered by the sealing resin 1, and are exposed from the sealing resin 1 to the outside.

応力緩衝放熱板５は半導体チップ２の半導体集積回路へかかる応力を緩衝しつつ半導体集積回路からの熱を半導体装置外へ効率的に放熱する機能を有するものである。半導体集積回路の動作による発熱時に半導体チップ２と応力緩衝放熱板との熱膨張率に差があると半導体集積回路にダメージが加わり動作しなくなる。これを回避するために応力緩衝放熱板５の熱膨張率は半導体チップ２のそれに近いものである。半導体チップ２がシリコンであれば応力緩衝放熱板５の熱膨張率がシリコンの熱膨張率に近いものとする。半導体チップ２が化合物半導体基板からなるのであれば、それに準ずる材質のものとする。 The stress buffer heat sink 5 has a function of efficiently radiating the heat from the semiconductor integrated circuit to the outside of the semiconductor device while buffering the stress applied to the semiconductor integrated circuit of the semiconductor chip 2. If there is a difference in the thermal expansion coefficient between the semiconductor chip 2 and the stress buffer heat sink at the time of heat generation due to the operation of the semiconductor integrated circuit, the semiconductor integrated circuit will be damaged and will not operate. In order to avoid this, the thermal expansion coefficient of the stress buffer heat sink 5 is close to that of the semiconductor chip 2 . If the semiconductor chip 2 is silicon, it is assumed that the thermal expansion coefficient of the stress buffer heat sink 5 is close to the thermal expansion coefficient of silicon. If the semiconductor chip 2 is made of a compound semiconductor substrate, it is made of the same material as that.

応力緩衝放熱板５には上述したような、半導体集積回路にかかる応力を減じるという機能とともに高い放熱性も必要とされる。これは半導体集積回路で発生した熱を素早く半導体装置１００外へ放出するためである。応力緩衝放熱板５は単層であっても良いし、応力緩衝機能を担う層と放熱機能を担う層の積層であっても構わない。また、金属フィラーを樹脂に混練させた熱伝導性の高いものでも良い。応力緩衝放熱板５は上面である一端が半導体チップ２と接着剤６を介して接合され、その反対側の底部である他端を封止樹脂１から露出し、その露出面は、封止樹脂１からその下面が露出しているリード４の露出面と同一水平面をなすように配置される。 The above-mentioned function of reducing the stress applied to the semiconductor integrated circuit is required for the stress-buffering heat sink 5 as well as high heat dissipation. This is to quickly release the heat generated in the semiconductor integrated circuit to the outside of the semiconductor device 100. The stress-buffering heat sink 5 may be a single layer, or may be a laminate of a layer carrying a stress-buffering function and a layer carrying a heat-dissipating function. In addition, a metal filler having a high thermal conductivity obtained by kneading the resin may be used. One end of the stress-buffering heat sink 5 is joined to the semiconductor chip 2 via the adhesive 6 at one end, and the other end, the bottom at the opposite side, is exposed from the sealing resin 1. The lower surface of the lead 1 is arranged on the same horizontal plane as the exposed surface of the lead 4.

図２は、上述した本発明の第１の実施形態にかかる半導体装置の実装状態を示す断面図である。半導体装置１００の下面にはランド８を配置した実装基板９が設けられ、各々のランド８とリード４または応力緩衝放熱板５とが半田を介して接続されている。このような構成とすることで半導体チップ表面の半導体集積回路にて発生した熱が応力緩衝放熱板５を伝って実装基板９へ効率的に放熱される。   FIG. 2 is a cross-sectional view showing the mounted state of the semiconductor device according to the first embodiment of the present invention described above. A mounting substrate 9 on which lands 8 are disposed is provided on the lower surface of the semiconductor device 100, and the lands 8 are connected to the leads 4 or the stress-buffering heat sink 5 via solder. With such a configuration, the heat generated in the semiconductor integrated circuit on the surface of the semiconductor chip is efficiently dissipated to the mounting substrate 9 through the stress-buffering heat sink 5.

図３は、本発明の応力緩衝放熱板の拡大平面図である。応力緩衝放熱板５は半導体チップ２に形成された、相対的に他の領域よりも発熱性の高い特定の半導体集積回路領域１３を含む領域を覆う形状であっても良いし、発熱性の高い特定の半導体集積回路領域１３のみを覆う形状であっても良い。この場合、半導体集積回路が平面視的に矩形であれば、これと同じ形状で同じ大きさ、あるいは僅かに大きい応力緩衝放熱板５とするのが良い。発熱性の高い特定の半導体集積回路領域１３が複数ある場合には複数の応力緩衝放熱板５を設けるのが良い。発熱性の高い特定の半導体集積回路領域１３は回路の消費電流により決まるので、半導体集積回路の設計時に容易に推定することが可能である。 FIG. 3 is an enlarged plan view of the stress buffer heat sink of the present invention. The stress-buffering heat sink 5 may be shaped to cover a region including a specific semiconductor integrated circuit region 13 formed on the semiconductor chip 2 and having a relatively higher heat generation than other regions, or the heat generation may be high. It may be shaped to cover only a specific semiconductor integrated circuit region 13. In this case, if the semiconductor integrated circuit is rectangular in a plan view, it is preferable to use the stress buffer heat sink 5 having the same shape and the same size or a slightly larger size. In the case where there are a plurality of specific semiconductor integrated circuit regions 13 having a high heat generating property, it is preferable to provide a plurality of stress buffer heat sinks 5 . Since the specific semiconductor integrated circuit region 13 having high heat generating property is determined by the current consumption of the circuit, it can be easily estimated at the design of the semiconductor integrated circuit.

図４は、本発明の第２の実施形態にかかる半導体装置の断面図である。図１では応力緩衝放熱板５は断面視的に矩形で図示されている。つまり、応力緩衝放熱板５は直方体あるいは円柱状であり、半導体チップ２と接する上面と実装基板と接する下面の面積は同じであることを示している。これに対し、図４では断面形状が台形となる錐台型の応力緩衝放熱板５を用いている。放熱性を高めるためにはこのような上面の面積よりも下面の面積が大きい形状にすることが好ましい。 FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. In FIG. 1, the stress buffer heat sink 5 is illustrated in a rectangular shape in a cross sectional view. That is, the stress buffer heat sink 5 is a rectangular parallelepiped or a column, and it is shown that the area of the upper surface in contact with the semiconductor chip 2 and the area of the lower surface in contact with the mounting substrate are the same. On the other hand, in FIG. 4, a frustum-type stress-buffering heat sink 5 whose sectional shape is trapezoidal is used. In order to enhance heat dissipation, it is preferable to make the area of the lower surface larger than the area of such an upper surface.

以上、説明した実施形態とすることで、半導体チップ２の表面の発熱部と実装基板９のランド８に、応力緩衝放熱板５を通じて接触させる事ができ、放熱性を向上する事が出来る。 As described above, according to the embodiment described above, the heat generating portion on the surface of the semiconductor chip 2 and the land 8 of the mounting substrate 9 can be brought into contact through the stress-buffering heat dissipation plate 5, and the heat dissipation can be improved.

１ 封止樹脂
２ 半導体チップ
３ バンプ
４ リード
５ 応力緩衝放熱板
６ 絶縁性接着剤、導電性接着剤
７ 半田
８ ランド
９ 実装基板
１０ ボンディングワイヤー
１１ リード
１２ ダイパッド
１３ 発熱性の高い半導体集積回路領域
１００ 半導体装置 Reference Signs List 1 sealing resin 2 semiconductor chip 3 bump 4 lead 5 stress buffer heat sink 6 insulating adhesive, conductive adhesive 7 solder 8 land 9 mounting substrate 10 bonding wire 11 lead 12 die pad 13 semiconductor integrated circuit region 100 having high heat generation property Semiconductor device

Claims (5)

半導体チップと、
前記半導体チップの表面に設けられたバンプと、
前記バンプが上面に接続されたリードと、
前記半導体チップの表面に一端が接続された単層の応力緩衝放熱板と、
前記半導体チップ、前記バンプ、前記リードの前記上面および前記応力緩衝放熱板の側面を覆う封止樹脂と、
からなり、
前記リードの下面および前記応力緩衝放熱板の他端が前記封止樹脂から露出しているとともに、同一水平面をなすように配置されていることを特徴とする半導体装置。 A semiconductor chip,
Bumps provided on the surface of the semiconductor chip;
A lead connected to the upper surface of the bump;
A single-layer stress-buffering heat sink with one end connected to the surface of the semiconductor chip;
A sealing resin that covers the semiconductor chip, the bump, the upper surface of the lead, and the side surface of the stress-buffering heat sink;
Consists of
A semiconductor device characterized in that the lower surface of the lead and the other end of the stress buffer heat sink are exposed from the sealing resin and are formed in the same horizontal plane. 前記応力緩衝放熱板は、金属フィラーを混練させた樹脂であることを特徴とする請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the stress buffer heat sink is a resin in which a metal filler is kneaded . 前記応力緩衝放熱板は、相対的に発熱性の高い半導体集積回路領域に設けられ、前記発熱性の高い半導体集積回路領域を覆う形状であることを特徴とする請求項１又は２に記載の半導体装置。 3. The semiconductor according to claim 1, wherein the stress-buffering heat sink is provided in a semiconductor integrated circuit region having a relatively high heat build-up, and covers the semiconductor integrated circuit region having a high heat build-up. apparatus. 前記応力緩衝放熱板は、断面視的に台型で、前記半導体チップ側の前記一端の面積よりも前記封止樹脂から露出する前記他端の面積のほうが大きいことを特徴とする請求項１乃至３のいずれか１項記載の半導体装置。   The stress buffer heat dissipating plate is trapezoidal in cross section, and the area of the other end exposed from the sealing resin is larger than the area of the one end on the side of the semiconductor chip. The semiconductor device according to any one of 3. 前記応力緩衝放熱板の前記他端および前記リードの前記下面が半田によりランドと接続されている請求項１乃至４のいずれか１項記載の半導体装置を有する実装基板。   The mounting substrate having a semiconductor device according to any one of claims 1 to 4, wherein the other end of the stress buffer heat sink and the lower surface of the lead are connected to a land by solder.
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