JP6523114B2 - Memory control device and memory control method - Google Patents

Description

  The present invention relates to a memory control device and a memory control method for accessing data to a semiconductor memory.

  2. Description of the Related Art In recent years, with the increase of memory capacity, NAND type flash memory superior in bit unit price has become widespread. In such a NAND flash memory, the problem that data can not be read correctly becomes remarkable as the capacity increases and the degree of integration increases. Here, there has been proposed a memory access control device capable of preventing so-called read disturb that the stored data is destroyed by repeatedly reading a specific memory cell (for example, Patent Document) 1). The memory access control device reads data from the memory when normal data reading is not performed, and performs an error check to detect whether an error occurs in the read data. Then, so-called refresh processing is performed to rewrite data in a block in which an error occurs.

  Here, if the above error check is performed on all the blocks, there is a possibility that the data may be destroyed by the read disturb in this block before the error check is performed on the block having the possibility of the read disturb. The Therefore, in the memory access control device described in Patent Document 1, a block having a large number of reads is subjected to error check.

JP, 2013-117840, A

  However, in the NAND type flash memory, read disturb may occur even in a memory cell in which reading is not performed. Therefore, in the method disclosed in Patent Document 1, there is a possibility that a block having a high possibility of read disturb may not be selected as an error inspection target, and there is a case where data destruction can not be prevented in advance.

  Therefore, an object of the present invention is to provide a memory control device and a memory control method capable of preventing the destruction of data accompanying read disturb in advance and reliably.

  A memory control device according to the present invention is a memory control device that reads or writes data to a semiconductor memory in which a plurality of blocks are arranged and a plurality of blocks are formed. Based on the read count counter that counts the number of pages read from the target block as the read count for each block, and based on the read count, monitors a block to be monitored for error check from among the plurality of blocks Number of error bits obtained by reading data from the monitoring target registration unit selected as a target block, the block to be read or the monitoring target block, and performing read processing on the read data A monitoring unit that executes a monitoring process that counts each block, and the number of error bits corresponding to the monitoring target block is And a refresh unit that performs a refresh process on the monitoring target block when the first error threshold is larger than a predetermined error threshold, and a read number correction unit that corrects the read number, and the read number correction unit When reading is performed sequentially from pages adjacent to each other in a block to be read, a value corresponding to the number of pages to be read is added to the number of readings, and the block is to be read When the interval between pages to be read is less than n pages (n is an integer of 2 or more), a predetermined fixed value is added to the number of times of reading.

  A memory control method according to the present invention is a memory control method for reading or writing data in a semiconductor memory in which a plurality of blocks in which a plurality of pages are arranged are formed. The number of pages read from the block to be read by this is counted for each block as the number of reads, and based on the number of reads, the block to be monitored for error check is selected as the monitoring target block among the plurality of blocks. Selecting and reading data from the block to be read or the monitoring target block, performing error detection processing on the read data, counting the number of error bits obtained for each block; If the number of error bits corresponding to the monitoring target block is larger than a predetermined first error threshold, the monitoring target block is selected. Refresh is performed, and when reading is performed sequentially from adjacent pages in the block to be read, a value corresponding to the number of pages to be read is added to the number of times of reading, A predetermined fixed value is added to the number of readings when the interval between pages to be read is less than n pages (n is an integer of 2 or more) in a block to be read.

  In the present invention, among the plurality of blocks formed in the semiconductor memory, the following corrections are applied to the number of times of reading the block whose number of times of reading of data is to be monitored. ing. That is, when each of the pages adjacent to each other in the block to be read is to be read, stress applied to one page is concentrated compared to the case where each page to be distant from each other is to be read. growing. Therefore, in the present invention, when reading is sequentially performed from pages adjacent to each other in a block to be read, a value corresponding to the number of pages to be read is added to the number of times of reading. Further, if the interval between pages to be read is less than n pages, a predetermined fixed value is added to the number of readings, and if the interval between pages to be read is equal to n pages or more, reading is performed It does not add the number of times.

  According to this configuration, the block to be monitored is selected based on the number of readings reflecting the influence of read disturbance, so that data destruction due to read disturbance can be reliably and surely prevented. It becomes possible.

FIG. 2 is a block diagram showing a configuration of a memory 100. It is a flowchart which shows a reading post-process. It is a flow chart which shows reading frequency increase amendment processing. It is a figure which shows an example of the correspondence of the number of pages by which read access was carried out and the addition value AD. It is a figure for demonstrating the influence of a read disturb.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a memory 100 including a memory controller 20 as a memory control device according to the present invention. In FIG. 1, a memory cell array 10 is a non-volatile semiconductor memory such as, for example, a NAND flash memory. In the memory cell array 10, a plurality of memory cells form a page serving as a minimum unit of reading, and a plurality of pages form a block. Each block is composed of a plurality of pages arranged adjacent to each other in the address order.

  In a specific block of the memory cell array 10, a priority monitoring list area SA is provided. In the priority monitoring list area SA, for example, a block address or a block number is stored as information indicating a block (hereinafter referred to as a priority monitoring block) to which a priority monitoring process (described later) is applied when the power is turned on. Therefore, even after power-off, the information indicating the priority monitoring block is held in the priority monitoring list area SA of the memory cell array 10.

  The memory controller 20 accesses the memory cell array 10 for reading, writing, erasing and the like based on various externally supplied command signals CMD (read command, write command, etc.), address AD and data DAT. Do.

  The memory controller 20 includes a random access memory (RAM) 21, an error detection unit 22, a read number counter 23, a read number correction unit 24, a refresh processing unit 25, a centralized monitoring target registration unit 26, a priority monitoring target registration unit 27, and overall monitoring. The unit 28 includes a central monitoring unit 29 and a priority monitoring unit 30.

  The error detection unit 22 performs error detection on data read from the memory cell array 10 according to an externally supplied read command (hereinafter referred to as a read access), and for each block, a page belonging to the block Count the number of erroneous bits detected when read out. The error detection unit 22 writes, for example, information indicating the number of error bits in the RAM 21 as error information in association with each block.

  The read number counter 23 counts, for each block, the number of times the page which has become the read target by the read access is read. The read number counter 23 writes information indicating the read number in the RAM 21 in association with each block. Further, the read number counter 23 writes in the RAM 21 information indicating the total number of read numbers of each block. Hereinafter, the block to which the page to be read by the read access belongs is referred to as a "block to be read".

  The read number correction unit 24 corrects the read number stored in the RAM 21 in association with the block to be read each time a read access is made, and the read number subjected to the correction is stored in the RAM 21. Overwrite. The method of correcting the number of readings by the number of readings correction unit 24 will be described later.

  If the number of error bits stored in the RAM 21 in association with the block to be read out is larger than a predetermined first error threshold value TE1, the refresh processing unit 25 sets the block to be read out. On the other hand, so-called refresh processing is performed to rewrite the data after error correction. Further, the refresh processing unit 25 writes, in the RAM 21, information indicating the number of times of the refresh process performed in the block in association with each block. The error threshold value TE1 is a value that represents the upper limit of the number of error bits that can be corrected.

  The centralized monitoring target registration unit 26 has become the reading target when the number of readings stored in the RAM 21 in association with the block to be reading is larger than the predetermined first monitoring target threshold TM1. The block is registered as a centralized monitoring target block for intensively monitoring the error check. In addition, the centralized monitoring target registration unit 26 also registers, as the centralized monitoring target block, a block for which an error detected by the error detection unit 22 is more than a predetermined second error threshold TE2 (TE1> TE2) at the time of the read access. Do. That is, the centralized monitoring target registration unit 26 writes, for example, a block address, a block number, and the like in the RAM 21 as information representing the centralized monitoring target block described above.

  The priority monitoring target registration unit 27 prioritizes blocks in a state immediately before data destruction as monitoring targets for error check based on error information for each block, reading count information, and refresh count information stored in the RAM 21. To be selected as a priority monitoring target block. The priority monitoring target registration unit 27 writes information representing the priority monitoring target block in the priority monitoring list area SA of the memory cell array 10. A method of selecting a priority monitoring target block by the priority monitoring target registration unit 27 will be described later.

  The overall monitoring unit 28 performs the following overall monitoring process on all the blocks in the memory cell array 10. That is, the entire monitoring unit 28 reads data from all pages of all blocks of the memory cell array 10. Since it is necessary to read all pages of all blocks uniformly in the whole monitoring process here, for example, the whole monitoring unit 28 sequentially reads data of the fourth r (r is a positive integer) page of the first block, Next, the data of the fourth r + 1 page of the second block are sequentially read, and the data of the fourth r + 2 page of the third block are sequentially read. When reading of data is finished every four pages until the final block, the process returns to the first block, sequentially reads data of the 4r + 1 page, then reads data of the 4 r + 2 page of the second block in order, and 4 r + 3 of the third block Read page data in order. By repeating this, it is possible to read out data from all pages of all blocks uniformly every four pages. Here, an example in which the entire monitoring process is performed every four pages is shown, but reading of data may be set every few pages depending on the accuracy of the entire monitoring process. At this time, the error detection unit 22 writes error information detected for each block in the RAM 21 in association with each block.

  The centralized monitoring unit 29 executes the following centralized monitoring processing based on the information representing the centralized monitoring target block stored in the RAM 21. That is, the centralized monitoring unit 29 first reads data from all pages in the block corresponding to the centralized monitoring target block in the memory cell array 10. Then, the centralized monitoring unit 29 writes the error information detected by the error detection unit 22 in the RAM 21 in association with the block corresponding to the centralized monitoring target block.

  Further, when the number of times of reading stored in the RAM 21 in correspondence with the block which is the target of the read access reaches the first monitoring target threshold value TM1, the centralized monitoring unit 29 described above for the block. Perform centralized monitoring processing. That is, the concentration monitoring unit 29 reads out data from the block in which the number of correction readings reaches the first monitoring target threshold value TM1. At this time, the error information indicating the number of error bits detected in the error detection unit 22 is It writes in RAM21 corresponding to a block. The centralized monitoring unit 29 performs the centralized monitoring described above every time a read access is performed a predetermined number of times thereafter for a block whose read number has reached the first monitoring target threshold TM1. Do the processing.

  When the power is turned on, the priority monitoring unit 30 reads information representing a priority monitoring target block from the priority monitoring list area SA of the memory cell array 10, and executes the following priority monitoring process on the memory cell array 10. That is, the priority monitoring unit 30 first reads data from the block corresponding to the priority monitoring target block in the memory cell array 10. Then, the priority monitoring unit 19 writes error information indicating the number of error bits detected by the error detection unit 22 in the RAM 21 in association with the block corresponding to the priority monitoring target block.

When the power is turned on, the values of the number of error bits, the number of times of reading, the number of times of refreshing, and the block address (block number) stored in the RAM 21 are all initialized to, for example, zero.
Next, an operation performed by the memory controller 20 when a read access is made to the memory 100 will be described.

  In response to the read access, the memory controller 20 reads data from the page to be read by the read access and outputs it as data DAT. Furthermore, the memory controller 20 writes read address information indicating the address of each page to be read to the RAM 21.

  Thereafter, memory controller 20 executes control in accordance with the post-reading process shown in FIG.

  In FIG. 2, first, the read number counter 23 of the memory controller 20 stores the number of reads performed in the block to be read by the above-described read operation in the RAM 21 in association with the block. The number of times of reading is updated by adding to the number of times of reading (step S1).

  Next, it is determined whether the number of readings RN as the number of updated readings is larger than the first monitoring target threshold TM1 (step S2).

  If it is determined in step S2 that the read number RN is larger than the first monitoring target threshold value TM1, the centralized monitoring unit 29 of the memory controller 20 performs the above-described operation on the block that is the target of the read access. The centralized monitoring process is executed (step S3).

  On the other hand, when it is determined in step S2 that the read number RN is equal to or less than the first monitoring target threshold value TM1, the error detection unit 22 of the memory controller 20 reads data read from the block that is the target of read access. An error detection process is performed on the image data, and the number of error bits obtained at this time is obtained as the number of error bits EN (step S4).

  Next, the memory controller 20 determines whether the number of error bits EN is larger than the first error threshold TE1 (step S5).

  When it is determined in step S5 that the error bit number EN is larger than the first error threshold value TE1, the refresh processing unit 25 of the memory controller 20 executes the above-described process for the block that is the target of the read access. A refresh process is performed (step S6). That is, when the number of error bits detected in the block exceeds the error correctable upper limit number (TE1), the refresh processing unit 25 performs the refresh process on the block. By the refresh process, the number of times of reading stored in the RAM 21 in association with the block which is the target of the read access is initialized to zero. Furthermore, the number of refreshes stored in the RAM 21 in association with the block which is the target of the read access is incremented by this refresh process.

  On the other hand, if it is determined in step S5 that the error bit number EN is less than or equal to the first error threshold value TE1, the memory controller 20 determines whether the error bit number EN is greater than the second error threshold value TE2. It is determined (step S7).

  If it is determined in step S7 that the error bit number EN is larger than the second error threshold value TE2, the read number correction unit 24 of the memory controller 20 associates the block with the block that is the target of the read access. The number of readings stored in the RAM 21 is replaced with the same value as the monitoring target threshold value TM2 (step S8). That is, when a number of bit errors that can be corrected for errors, that is, smaller than TE1 and larger than TE2, is detected, the number of readings in this block is forcibly set equal to the monitoring target threshold TM2. To replace.

  On the other hand, when it is determined in step S7 that the error bit number EN is equal to or less than the second error threshold value TE2, the read number correction unit 24 executes read number increase correction processing shown in FIG. 3 (step S9).

  In FIG. 3, first, based on the information indicating the read address of each page stored in the RAM 21 by the read access, the read number correction unit 24 starts the read access from the pages arranged adjacent to each other. It is determined whether or not it is a sequential read access in which data is read out in the order of arrangement (step S31). If it is determined in step S31 that the read access is a sequential read access, the read number correction unit 24 sets an addition value AD having a value corresponding to the number of pages to be read (step S32). That is, as the number of pages targeted for reading by the sequential read access increases, the addition value AD also increases. When setting the addition value AD having a value corresponding to the number of pages targeted for reading, as shown in FIG. 4, the number of pages targeted for reading reaches N (N is an integer of 2 or more). The addition value AD may be set to a size corresponding to the number of pages until the number of pages reaches N, and the addition value AD fixed at the limit value UL may be set when the number of pages is N or more.

  On the other hand, when it is determined in step S31 that the read access is not a sequential read access, the read count correction unit 24 separates the pages to be read from each other by n (n is an integer of 2 or more) pages or more. It is determined whether or not it is (step S33).

  If it is determined in step S33 that the interval between the pages to be read is less than n pages, the read number correction unit 24 sets the predetermined fixed value K (K is a positive integer) as the addition value AD. It sets (step S34).

  On the other hand, when it is determined in step S33 that the interval between the pages to be read is separated by n pages or more, the read number correction unit 24 sets zero as the addition value AD (step S35). If it is determined in step S33 that the interval between pages to be read is separated by n pages or more, the read number correction unit 24 does not perform addition to the read number. good.

  After execution of step S32, S34 or S35 described above, the read number correction unit 24 adds the addition value AD to the read number stored in the RAM 21 in association with the block targeted for read access, and The addition result is overwritten on the RAM 21 as a new number of readings (step S36). After execution of step S36, the read number correction unit 24 exits the read number increase correction routine and ends step S9 shown in FIG.

  After step S8 or S9 in FIG. 2 ends, the priority monitoring target registration unit 27 of the memory controller 20 executes priority monitoring target registration processing (step S10).

  That is, the priority monitoring target registration unit 27 first selects a block in a state in which the possibility of data destruction is high, based on error information, read count information, and refresh count information for each block stored in the RAM 21. That is, in each block, the priority monitoring target registration unit 27 has the number of error bits larger than the predetermined third error threshold TE3, the number of refreshes is larger than the predetermined number of executions threshold TX, and the number of reads A block larger than the third monitoring target threshold TM3 (TM1> TM3) is selected as a priority monitoring target block having a high risk of destruction. Then, the priority monitoring target registration unit 27 writes information indicating the priority monitoring target block, such as a block address or a block number, in the priority monitoring list area SA of the memory cell array 10. When a plurality of priority monitoring target blocks are detected, the priority monitoring target registration unit 27 adds information indicating each priority monitoring target block to the priority monitoring list area SA. At this time, the priority monitoring target registration unit 27 sets information indicating a priority monitoring target block in the priority monitoring list area SA so that the priority monitoring process described above is executed among the priority monitoring target blocks in descending order of the number of refreshes. I will add it. If the number of refreshes is the same, the priority monitoring target registration unit 27 sends information indicating the priority monitoring target block to the priority monitoring list area SA so that the priority monitoring process is executed in descending order of the number of error bits. I will add it. Therefore, the priority monitoring unit 30 sets the priority in the order of the block having a large number of refreshes, the block having a large number of error bits, and the block having a large number of readings, and executes the priority monitoring process in the order according to the priority.

  After execution of the priority monitoring target registration process in step S10, the memory controller 20 ends the execution of the post-reading process shown in FIG. 2 and shifts to an external access waiting state.

  While in the access waiting state, the overall monitoring process by the overall monitoring unit 28 and the centralized monitoring process by the centralized monitoring unit 29 may be executed. Furthermore, the overall monitoring process by the overall monitoring unit 28 may be executed immediately after the priority monitoring process executed by the priority monitoring unit 30 in response to the power-on, regardless of whether or not the read access is made. . If read access is made during execution of the overall monitoring process, the overall monitoring process is temporarily interrupted, and after the end of the post-reading process shown in FIG. 2, the overall monitoring process is performed from the interrupted point. The priority monitoring process by the priority monitoring unit 30 may be performed not only at the time of power-on but also at predetermined intervals after power-on.

  As described above, the memory controller 20 shown in FIG. 1 counts, for each block, the number of pages to be read in the block as the number of times of reading. The memory controller 20 determines that deterioration due to the read operation is progressing for a block whose number of times of reading is larger than a predetermined threshold (TM1), registers the block as a block to be centrally monitored, and all blocks The central monitoring target block is centrally monitored. That is, data is read from each of the centralized monitoring target blocks to perform error detection, and the number of error bits is totaled for each block. At this time, the memory controller 20 performs the refresh process (step S6 in FIG. 2) on the block where the number of error bits exceeds the predetermined threshold (TE1), thereby destroying the data accompanying the deterioration of the memory cell. To avoid.

  At this time, since centralized monitoring target blocks, which are estimated to be relatively deteriorated, are intensively monitored among all blocks, it is necessary to select a block requiring refresh processing at an early stage. Can.

  However, the read number information used to select the centralized monitoring target block from among all the blocks is initialized to zero when the power is shut off. Therefore, the number of readings corresponding to this block is zero at the time of power-on, although there is a block whose deterioration is about to be destroyed. Therefore, before this block is registered in the centralized monitoring target block, data corruption may occur due to read access to the block.

Therefore, in the memory controller 20, when a bit error of a number (a number smaller than TE1 and a number larger than TE2) to which error correction is possible is detected in the block subjected to read access, The number of times of reading is forcibly replaced with the monitoring target threshold value TM2 by the same value (S8 in FIG. 2). As the monitoring target threshold TM2, the same value as the above-described monitoring target threshold TM1 may be used. As a result, the block is registered as a centralized monitoring target block, and centralized monitoring processing is immediately performed.

  As a result, even though there is a block whose deterioration is progressing, even if the number of readings stored in the RAM 21 corresponding to the block is initialized to zero by power-off, this block On the other hand, centralized monitoring processing can be performed at an early stage, or it can be selected as a priority monitoring target block. Thus, data corruption can be prevented in advance.

  Furthermore, in the memory controller 20, among all the blocks, a block whose deterioration is in progress and which has a high risk of destruction is registered as a priority monitoring target block. That is, in the memory controller 20, the number of times of reading is larger than the predetermined threshold (TM1) (first condition), the number of error bits is larger than the predetermined threshold (TE3) (second condition), and the number of times of refreshing A block satisfying any one of the conditions (third condition) of which is larger than a predetermined number of times (TX) is selected as a priority monitoring target block. That is, the degree of deterioration of the block is reflected not only in the number of readings but also in the number of refresh operations and the number of error bits. Therefore, in consideration of these, blocks with a high risk of destruction are accurately detected. It did so. Then, the memory controller 20 writes the information (block address or block number) indicating the priority monitoring target block in the memory cell array 20 as the nonvolatile semiconductor memory. Therefore, the information indicating the priority monitoring target block is held in the memory cell array 20 even after the power is turned off. Therefore, the memory controller 20 first reads the information indicating the priority monitoring target block stored in the memory cell array 20 in response to power on, and performs monitoring processing on the priority monitoring target block. For example, since the monitoring target threshold TM1 is not reached before the power is turned off, the monitoring target threshold TM3 is also applied to the blocks that are not the central monitoring processing target. Priority monitoring processing is performed at the time of injection. That is, since the number of readings is initialized to zero when the power is turned off, the number of readings is counted from 1 again, but this block is given priority by leaving a history of blocks having a large number of readings. It becomes possible to monitor.

  Therefore, according to the registration of the priority monitoring target block and the priority monitoring processing described above, it is possible to perform the refresh processing at an early stage on a block whose deterioration is about to be destroyed. This makes it possible to prevent data destruction even if there is a block whose deterioration is about to be destroyed.

  By the way, although the deterioration of the block progresses as the number of reading increases as mentioned above, for example, in the NAND type flash memory etc., not only the page which is the reading object but also at least one page adjacent to the page. There is a so-called lead disturb, which is stressed and degraded.

  Hereinafter, stress caused by a read operation applied to each page (hereinafter referred to as read stress) will be described taking a case where stress is applied to a range of one page adjacent to the page to be read due to the influence of read disturb. This will be described with reference to FIGS. 5 (a) to 5 (c). 5 (a) to 5 (c) are diagrams schematically showing an area of eight pages formed in one block.

  For example, as shown in FIG. 5A, when pages P3 and P7 arranged at positions separated by two or more pages from each other are to be read (indicated by hatching), P2 adjacent to P3 together with page P3. Stress is also applied to P4. Furthermore, stress is also applied to P6 and P8 adjacent to the page P7 as well as the page P7. Therefore, in this case, a read stress of one time is applied to each of the pages P2 to P4 and P6 to P8.

  Further, as shown in FIG. 5B, when the pages P3 and P5 arranged at positions separated by one page from each other are to be read, stress is applied to the pages P2 and P4 adjacent to the page P3 as well as the page P3. Furthermore, stress is also applied to P4 and P6 adjacent to the page P5 together with the page P5. Therefore, in this case, although reading stress of one time is applied to pages P2, P3, P5 and P6, reading stress of two times is applied to page P4.

  In addition, as shown in FIG. 5C, when so-called sequential reading is performed in which pages P3 and P4 arranged adjacent to each other are continuously read, they are adjacent to the page P3 together with page P3. Stress is also applied to P2 and P4. Furthermore, stress is also applied to P3 and P5 adjacent to the page P4 as well as the page P4. Therefore, in this case, although read stress of one time is applied to pages P2 and P5, read stress of two times is applied to pages P3 and P4, respectively.

  Thus, in the read access shown in FIGS. 5A to 5C, the number of readings is all two. However, as shown in FIG. 5B, when the interval between the pages to be subjected to the read access is short to such an extent that the ranges (P2, P4, P4, P6) affected by the read disturb overlap, as shown in FIG. As shown in (a), the read stress concentrated on one page is greater than when the ranges (P2, P4, P6, P8) are separated to such an extent that they do not overlap each other. Further, as shown in FIG. 5C, in the case of performing so-called sequential access in which pages adjacent to each other are sequentially read, more concentration on one page than in the state shown in FIG. 5B. The read stress is large.

  Therefore, although the number of readings is all two in the example shown in FIGS. 5A to 5C, the degree of progress of the block deterioration is obtained when the reading access is performed in the form of FIG. 5C. The earliest is when the read access is performed in the form of FIG. 5A.

  Therefore, the memory controller 20 performs correction as shown in FIG. 3 with respect to the number of readings actually executed so that the number of readings takes into consideration the stress applied to the memory cells due to the read disturbance. There is.

That is, as shown in FIG. 5A, if the interval between pages to be read out is larger than n pages or more, that is, if the range affected by read disturbance does not overlap, zero. Is added to the actual number of readings (S35, S36 in FIG. 3). That is, at this time, addition to the number of readings is not performed. In addition, as shown in FIG. 5B, when the interval between the pages to be read is less than n (n is an integer of 2 or more) pages, that is, the ranges affected by the read disturb overlap. Adds the addition value AD having a predetermined fixed value K to the actual number of readings (S34 and S36 in FIG. 3). Further, as shown in FIG. 5C, in the case where sequential access in which adjacent pages are to be read is performed, that is, the influence of read disturb associated with reading of the page to be read is the read object. If it extends to the adjacent page, the addition value AD having a value corresponding to the number of pages is added to the actual number of readings (S32, S36 in FIG. 3). For example, when the number of pages to be sequentially accessed is w (w is an integer of 2 or more) pages, the addition value AD is set to a value obtained by multiplying “w” or “w” by a predetermined coefficient, and this addition The value AD is added to the actual number of reads.
In FIGS. 5 (a) to 5 (c), the range affected by the read disturbance is only for one adjacent page, but for two adjacent pages or three or more adjacent pages, The added value AD may be set as a range affected by the read disturb. At this time, since the stress applied to the page farther from the read target page is less stressed, the value of the addition value AD to be added corresponding to a plurality of adjacent pages according to the distance from the read target page is added. You may set it. That is, the value of the addition value AD is decreased as the page is further from the page to be read.

  Therefore, according to the read number correction, since the block to be monitored is selected based on the read number reflecting the influence of read disturbance, data destruction due to read disturbance can be surely and surely prevented. It becomes possible.

  In short, the memory controller 20 as a memory control device has the following read number counter, monitoring target registration unit, monitoring unit, and read number correction unit to prevent data destruction accompanying read disturb in a reliable manner. It is That is, the read number counter (23) counts the number of pages read from the block to be read by the data read for each block as the read number. The monitoring target registration unit (26, 27) selects a block to be a monitoring target of the error check from among the plurality of blocks as the monitoring target block based on the number of times of reading. The monitoring unit (29, 30) reads data from the block to be read or the monitoring target block and counts the number of error bits obtained by performing error detection processing on the read data for each block Execute monitoring processing. The refresh unit (25) performs the refresh process on the monitoring target block when the number of error bits corresponding to the monitoring target block is larger than a predetermined first error threshold (TE1). The read number correction unit (24) adds a value corresponding to the number of pages to be read to the number of reads when reading is sequentially performed from adjacent pages in a block to be read S31, S32, S36 of FIG. In addition, the read number correction unit reads a predetermined fixed value (K) when the interval between pages to be read in the block to be read is less than n pages (n is an integer of 2 or more). The number is added (S33, S34, S36 in FIG. 3). Further, the read number correction unit does not perform addition to the read number when the interval between pages to be read within the block to be read is equal to or larger than n pages (S33, S35, and S36 in FIG. 3). ).

DESCRIPTION OF SYMBOLS 10 Memory cell array 20 Memory controller 22 Error detection part 23 Reading number counter 24 Reading number correction part 27 Priority monitoring object registration part 30 Priority monitoring part SA Priority monitoring list area

Claims (6)

A memory control device for reading or writing data to a semiconductor memory in which a plurality of blocks are arranged and a plurality of blocks are arranged.
A read number counter that counts for each block the number of pages read from a block to be read by reading the data as the number of reads;
A monitoring target registration unit that selects a block to be a monitoring target of an error check from among the plurality of blocks based on the number of times of reading, as a monitoring target block;
A monitoring process is performed to read data from the block to be read or the monitoring target block, and count the number of error bits obtained by performing an error detection process on the read data for each block. The monitoring department,
A refresh unit that performs a refresh process on the monitoring target block when the number of error bits corresponding to the monitoring target block is larger than a predetermined first error threshold;
And a read number correction unit that corrects the read number.
The read number correction unit
When reading is performed sequentially from adjacent pages in the block to be read, a value corresponding to the number of pages to be read is added to the number of readings, and in the block to be read A memory control apparatus characterized in that a predetermined fixed value is added to the number of readings when the interval between the pages to be read is less than n pages (n is an integer of 2 or more). The monitoring target registration unit selects a block corresponding to the number of readings having a value larger than a first monitoring threshold among the plurality of blocks as the monitoring target block.
The monitoring unit is configured to, when the number of readings corresponding to the block to be read out is larger than a second monitoring threshold that is larger than the first monitoring threshold, to the block to be read out. Execute monitoring process,
The read number correction unit becomes the read target when the number of error bits corresponding to the block to be read is larger than a second error threshold smaller than the first error threshold. The memory control device according to claim 1, wherein the value of the number of times of reading corresponding to the block is replaced with the value of the second monitoring threshold. The monitoring target registration unit, from among the plurality of blocks, a first condition that said read count is the first large than superintendent Mi閾 value, the number of the error bits is larger than a third error threshold A block satisfying at least one of the second condition and the third condition in which the number of times of execution of the refresh process is larger than a predetermined number of times of execution threshold is selected as the monitoring target block; Writing information indicating a target block in the semiconductor memory;
Claim wherein the monitoring unit, which reads the information indicating the supervising object block from the semiconductor memory in response to power-on, and characterized by applying the monitoring process to the front Ki監 visual target block indicated by said information The memory control device according to 2 .   The memory control device according to any one of claims 1 to 3, wherein the first error threshold is an upper limit value of the number of error bits capable of error correction.   The memory control device according to any one of claims 1 to 4, wherein the semiconductor memory is a NAND flash memory. A memory control method for reading or writing data to a semiconductor memory in which a plurality of blocks are arranged and a plurality of blocks are arranged.
The number of pages read from the block to be read by reading the data is counted for each block as the number of readings,
Based on the number of times of reading, a block to be monitored for error check is selected from among the plurality of blocks as a monitoring target block,
Reading data from the block to be read or the monitoring target block, counting the number of error bits obtained by performing error detection processing on the read data for each block;
Refresh processing is performed on the monitoring target block if the number of error bits corresponding to the monitoring target block is larger than a predetermined first error threshold;
When reading is performed sequentially from adjacent pages in the block to be read, a value corresponding to the number of pages to be read is added to the number of readings, and in the block to be read A memory control method characterized in that a predetermined fixed value is added to the number of readings when the interval between pages to be read is less than n pages (n is an integer of 2 or more).