TWI764569B - semiconductor memory device - Google Patents
semiconductor memory deviceInfo
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- TWI764569B TWI764569B TW110105325A TW110105325A TWI764569B TW I764569 B TWI764569 B TW I764569B TW 110105325 A TW110105325 A TW 110105325A TW 110105325 A TW110105325 A TW 110105325A TW I764569 B TWI764569 B TW I764569B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
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- Debugging And Monitoring (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
實施方式之半導體記憶裝置具有:記憶胞陣列,其具有複數個非揮發性記憶胞;定序器,其控制基於自記憶胞陣列讀出資料之讀出動作之序列;及行解碼器;且上述定序器控制以下序列:接收讀出指令及位址信號後,將就緒/忙碌信號自就緒變更為忙碌,將就緒/忙碌信號變更為忙碌後,使用感測放大器自記憶胞陣列讀出資料,將資料儲存至資料鎖存電路後,將就緒/忙碌信號自忙碌變更為就緒,將就緒/忙碌信號變更為就緒後,接收資料輸出指令,於第1條件發生之情形時,將包含資料鎖存電路中儲存之資料之日誌資料寫入至記憶胞陣列之記憶區域。The semiconductor memory device of the embodiment has: a memory cell array having a plurality of non-volatile memory cells; a sequencer that controls a sequence of read operations based on reading data from the memory cell array; and a row decoder; The sequencer controls the following sequence: after receiving the read command and address signal, the ready/busy signal is changed from ready to busy, and after the ready/busy signal is changed to busy, the sense amplifier is used to read data from the memory cell array, After storing the data in the data latch circuit, change the ready/busy signal from busy to ready, and after changing the ready/busy signal to ready, receive the data output command, and include data latch when the first condition occurs The log data of the data stored in the circuit is written to the memory area of the memory cell array.
Description
本發明之實施方式係關於一種半導體記憶裝置。Embodiments of the present invention relate to a semiconductor memory device.
由於無法獲得足夠的用於半導體記憶裝置之不良解析之資料,故有時難以進行不良解析。Since sufficient data for failure analysis of semiconductor memory devices cannot be obtained, it is sometimes difficult to perform failure analysis.
實施方式提供一種能夠保存用於不良解析之資料之半導體記憶裝置。Embodiments provide a semiconductor memory device capable of storing data for failure analysis.
實施方式之半導體記憶裝置具有:記憶胞陣列,其包含複數個區塊,能夠儲存第1資料;定序器,其控制基於讀出動作之序列,上述讀出動作係基於自記憶體控制器接收之讀出指令,自上述記憶胞陣列讀出上述第1資料;及行解碼器,其包含感測放大器及資料鎖存電路,上述感測放大器進行自上述記憶胞陣列讀出上述第1資料時所需之感測動作,上述資料鎖存電路儲存上述第1資料;且上述複數個區塊中之至少一個區塊具有第1及第2選擇電晶體、以及串聯連接於上述第1及第2選擇電晶體之間的複數個非揮發性記憶胞,上述定序器控制如下之上述序列:接收上述讀出指令及位址信號,接收上述讀出指令及上述位址信號後,將就緒/忙碌信號自就緒變更為忙碌,將上述就緒/忙碌信號變更為上述忙碌後,使用上述感測放大器自上述記憶胞陣列讀出上述第1資料,將上述第1資料儲存至上述資料鎖存電路,將上述第1資料儲存至上述資料鎖存電路後,將上述就緒/忙碌信號自上述忙碌變更為上述就緒,將上述就緒/忙碌信號變更為上述就緒後,接收資料輸出指令,接收上述資料輸出指令後,將上述資料鎖存電路中儲存之上述第1資料輸出至上述記憶體控制器,於第1條件發生之情形時,將包含上述資料鎖存電路中儲存之上述第1資料的日誌資料寫入至上述記憶胞陣列之記憶區域。The semiconductor memory device of the embodiment has: a memory cell array including a plurality of blocks and capable of storing first data; a sequencer whose control is based on a sequence of read operations based on reception from a memory controller The read command reads the first data from the memory cell array; and a row decoder, which includes a sense amplifier and a data latch circuit, when the sense amplifier reads the first data from the memory cell array For the required sensing operation, the data latch circuit stores the first data; and at least one of the plurality of blocks has first and second selection transistors, and is connected in series to the first and second Selecting a plurality of non-volatile memory cells between transistors, the sequencer controls the sequence as follows: receiving the read command and the address signal, after receiving the read command and the address signal, the sequencer will be ready/busy The signal is changed from ready to busy, after changing the above-mentioned ready/busy signal to the above-mentioned busy, the above-mentioned first data is read out from the above-mentioned memory cell array by using the above-mentioned sense amplifier, and the above-mentioned first data is stored in the above-mentioned data latch circuit. After the first data is stored in the data latch circuit, the ready/busy signal is changed from the busy to the ready, after the ready/busy signal is changed to the ready, a data output command is received, and after receiving the data output command , output the above-mentioned first data stored in the above-mentioned data latch circuit to the above-mentioned memory controller, when the first condition occurs, write the log data including the above-mentioned first data stored in the above-mentioned data latch circuit to the memory region of the above-mentioned memory cell array.
以下,參照圖式對實施方式進行說明。Hereinafter, embodiments will be described with reference to the drawings.
(第1實施方式)(first embodiment)
對第1實施方式之記憶體系統進行說明。以下,列舉具備NAND型快閃記憶體之記憶體系統進行說明。The memory system of the first embodiment will be described. Hereinafter, a memory system including a NAND-type flash memory will be described.
[記憶體系統之整體構成][The overall structure of the memory system]
首先,使用圖1對本實施方式之記憶體系統之大體之整體構成進行說明。First, the general overall configuration of the memory system of the present embodiment will be described with reference to FIG. 1 .
圖1係表示本實施方式之記憶體系統之構成的區塊圖。如圖所示,記憶體系統1具備NAND型快閃記憶體(以下,稱為NAND記憶體)100及記憶體控制器(以下,亦簡稱為控制器)200。NAND記憶體100與控制器200係形成於例如1個基板上。記憶體系統1係用於例如SD(Secure Digital,安全數碼)卡之類之記憶卡或SSD(Solid State Drive,固態硬碟)等。FIG. 1 is a block diagram showing the configuration of the memory system of the present embodiment. As shown in the figure, the
NAND記憶體100係非揮發性記憶體。NAND記憶體100具備複數個記憶胞,非揮發地記憶資料。控制器200藉由NAND匯流排而與NAND記憶體100連接。控制器200藉由主機匯流排而與主機機器300(點線所示)連接。而且,控制器200係對NAND記憶體100進行控制並回應於自主機機器300接收之要求而對NAND記憶體100進行存取之記憶體控制器。主機機器300例如為數位相機或個人電腦等,主機匯流排係遵循例如SD介面之匯流排。NAND匯流排係遵循NAND介面之進行信號收發之匯流排。
經由NAND介面(I/F)電路250而於NAND記憶體100與控制器200間收發各種信號。自控制器200向NAND記憶體100供給晶片賦能信號CEn、指令鎖存賦能信號CLE、位址鎖存賦能信號ALE、寫入賦能信號WEn、讀出賦能信號REn及寫入保護信號WPn。自NAND記憶體100向控制器200供給就緒/忙碌信號RBn。於控制器200與NAND記憶體100之間收發輸入輸出信號I/O及資料選通信號DQS/DQSn。Various signals are sent and received between the
晶片賦能信號CEn係用於使NAND記憶體100啟用之信號,於低位準被生效。指令鎖存賦能信號CLE及位址鎖存賦能信號ALE係向NAND記憶體100通知輸入輸出信號I/O分別為指令及位址之信號。寫入賦能信號WEn於低位準被生效,係向NAND記憶體100通知將輸入輸出信號I/O寫入至NAND記憶體100之信號。讀出賦能信號REn亦於低位準被生效,係用於使來自NAND記憶體100之讀出資料輸出至輸入輸出信號I/O之信號。寫入保護信號WPn係用於向NAND記憶體100指示禁止資料寫入及抹除之信號。資料選通信號DQS/DQSn係用於控制輸入輸出信號I/O之輸入輸出時序之信號。The chip enable signal CEn is a signal for enabling the
就緒/忙碌信號RBn係表示NAND記憶體100為就緒狀態(能夠接收來自控制器200之命令之狀態)或忙碌狀態(無法接收來自控制器200之命令之狀態)之信號,低位準表示忙碌狀態。輸入輸出信號I/O例如為8位元之信號。而且,輸入輸出信號I/O係於NAND記憶體100與控制器200之間收發之資料之實體,為指令、位址、寫入資料及讀出資料等。The ready/busy signal RBn indicates that the
[控制器之構成)[Construction of the controller)
其次,對控制器200之詳細構成進行說明。如圖1所示,控制器200係具備主機介面(I/F)電路210、隨機存取記憶體(以下,稱為RAM)220、具有中央處理裝置(CPU)之處理器230、緩衝記憶體240、NAND介面電路250及ECC(Error Checking and Correcting)電路260的電路。Next, the detailed configuration of the
主機介面電路210經由主機匯流排而與主機機器300連接,將自主機機器300接收之要求及資料分別傳輸至處理器230及緩衝記憶體240。又,回應於處理器230之指令,將緩衝記憶體240內之資料傳輸至主機機器300。The
RAM220例如為DRAM(Dynamic Random Access Memory,動態隨機存取記憶體)或SRAM(Static Random Access Memory,靜態隨機存取記憶體)等半導體記憶體。RAM220係用作處理器230之作業區域。而且,RAM220保持用於管理NAND記憶體100之韌體或管理資訊MI。管理資訊MI係對照表(LUT)、轉換表資訊(TBL)等。轉換表資訊TBL包含轉換資訊。轉換資訊係用於在控制器200執行資料讀出處理時轉換資料讀出位準之資訊。The
處理器230對控制器200整體之動作進行控制。例如,處理器230於自主機機器300接收到資料讀出要求時,回應於資料讀出要求而對NAND介面電路250發出讀出指令。於接收到來自主機機器300之資料寫入要求及資料抹除要求時,處理器230亦同樣地對NAND介面電路250發出與所接收之要求對應之指令。又,處理器230執行耗損平均等用於管理NAND記憶體100之各種處理。The
緩衝記憶體240暫時保持寫入資料或讀出資料。The
NAND介面電路250經由NAND匯流排而與NAND記憶體100連接,管理與NAND記憶體100之通信。而且,NAND介面電路250基於自處理器230接收之指令,將包含指令、資料等之各種信號發送至NAND記憶體100,又,自NAND記憶體100接收各種信號及資料。The
NAND介面電路250基於自處理器230接收之指令,將晶片賦能信號CEn、指令鎖存賦能信號CLE、位址鎖存賦能信號ALE、寫入賦能信號WEn及讀出賦能信號REn輸出至NAND記憶體100。又,於寫入資料時,NAND介面電路250將由處理器230發出之寫入指令及緩衝記憶體240內之寫入資料以輸入輸出信號I/O之形式傳輸至NAND記憶體100。進而,於讀出資料時,NAND介面電路250將由處理器230發出之讀出指令以輸入輸出信號I/O之形式傳輸至NAND記憶體100,進而,以輸入輸出信號I/O之形式接收自NAND記憶體100讀出之資料,並將其傳輸至緩衝記憶體240。The
ECC電路260進行與NAND記憶體100中記憶之資料相關之錯誤檢測及錯誤訂正處理。即,ECC電路260於寫入資料時產生錯誤訂正符號,並將其賦予至寫入資料,於讀出資料時,訂正錯誤,同時解碼資料。ECC電路260於解碼讀出資料失敗時,向處理器230通知ECC錯誤。The
[NAND型快閃記憶體之構成][Constitution of NAND Flash Memory]
其次,對NAND記憶體100之構成進行說明。如圖1所示,NAND記憶體100具備記憶胞陣列110、列解碼器120、驅動電路130、行解碼器140、位址暫存器150、指令暫存器160、定序器170、暫存器單元180及溫度感測器190。Next, the configuration of the
記憶胞陣列110具備複數個區塊BLK,該等複數個區塊BLK包含與列及行建立對應之複數個非揮發性記憶胞。區塊BLK係用作例如資料之抹除單位。於圖1中,圖示4個區塊BLK0~BLK3作為一例。而且,記憶胞陣列110非揮發地記憶由控制器200提供之資料。The
列解碼器120基於位址暫存器150內之區塊位址BA,選擇區塊BLK0~BLK3之任一者,進而,選擇所選區塊BLK中之字元線WL。The
驅動電路130基於位址暫存器150內之頁位址PA,經由列解碼器120對所選區塊BLK供給電壓。The driving
行解碼器140包含資料鎖存電路XDL及感測放大器SA。感測放大器SA包含複數個感測放大器電路。感測放大器SA於讀出資料時,進行感測動作。感測動作係感測自記憶胞陣列110讀出之資料,並進行必要之運算。資料鎖存電路XDL包含用於資料之輸入輸出之複數個鎖存電路。而且,行解碼器140經由其資料鎖存電路XDL而將讀出資料DAT輸出至控制器200。行解碼器140於寫入資料時,於資料鎖存電路XDL已接收自控制器200接收之寫入資料DAT後,執行對記憶胞陣列110之寫入動作。The
讀出資料及寫入資料係用戶資料。資料鎖存電路XDL具有用戶資料儲存部。用戶資料儲存部係能夠儲存用戶資料之電路部分。資料鎖存電路XDL進而具有亦可儲存下述位址資訊等之冗餘部。即,資料鎖存電路XDL中能夠儲存讀出資料及寫入資料以及位址資訊等。Read data and write data are user data. The data latch circuit XDL has a user data storage unit. The user data storage part is a circuit part capable of storing user data. The data latch circuit XDL further has a redundant portion that can also store the following address information and the like. That is, the data latch circuit XDL can store read data, write data, address information, and the like.
再者,於本實施方式及其他實施方式中,對用戶資料儲存部及冗餘部設置於資料鎖存電路XDL之例進行說明,但亦可設置於其他資料鎖存電路,例如資料鎖存電路ADL、BDL。即,亦可使用資料鎖存電路ADL、BDL或CDL作為暫時儲存下述日誌資料之資料鎖存電路。Furthermore, in this embodiment and other embodiments, an example in which the user data storage unit and the redundant unit are provided in the data latch circuit XDL will be described, but they may also be provided in other data latch circuits, such as a data latch circuit. ADL, BDL. That is, the data latch circuit ADL, BDL or CDL can also be used as a data latch circuit for temporarily storing the following log data.
位址暫存器150保持自控制器200接收之位址ADD。該位址ADD中包含上述區塊位址BA及頁位址PA。即,位址暫存器150儲存位址資訊。指令暫存器160保持自控制器200接收之指令CMD。The
定序器170係基於指令暫存器160中保持之指令CMD來控制NAND記憶體100整體之動作的控制電路。The
定序器170基於來自控制器200之指令CMD,執行資料讀出、資料寫入及資料抹除。The
進而,定序器170以如下方式執行日誌資料保存處理。因此,定序器170能夠自位址暫存器150獲取位址。進而,定序器170能夠將資料傳輸至行解碼器140。Furthermore, the
暫存器單元180包含複數個暫存器。暫存器單元180中能夠儲存溫度感測器190之溫度碼等。The
溫度感測器190產生表示NAND記憶體100之溫度之溫度碼。定序器170週期性(例如,以各動作為單位)地獲取溫度碼。溫度碼係NAND記憶體100之溫度資訊。溫度碼係NAND記憶體100之使用狀態資料。The
其次,使用圖2對上述區塊BLK之構成進行說明。圖2係表示本實施方式之記憶胞陣列之構成的電路圖。如圖所示,1個區塊BLK包含例如4個串單元SU(SU0~SU3)。又,各串單元SU包含複數個NAND串6。Next, the configuration of the above-mentioned block BLK will be described with reference to FIG. 2 . FIG. 2 is a circuit diagram showing the configuration of the memory cell array of the present embodiment. As shown in the figure, one block BLK includes, for example, four string units SU (SU0 to SU3). In addition, each string unit SU includes a plurality of NAND strings 6 .
NAND串6之各者包含例如8個記憶胞電晶體MT(MT0~MT7)及2個選擇電晶體ST1、ST2。各記憶胞電晶體MT具備控制閘極及電荷儲存層,非揮發地保持資料。而且,複數個(例如8個)記憶胞電晶體MT串聯連接於選擇電晶體ST1之源極與選擇電晶體ST2之汲極之間。Each of the NAND strings 6 includes, for example, 8 memory cell transistors MT (MT0-MT7) and 2 select transistors ST1, ST2. Each memory cell transistor MT has a control gate and a charge storage layer, and retains data non-volatilely. Furthermore, a plurality of (eg, eight) memory cell transistors MT are connected in series between the source electrode of the selection transistor ST1 and the drain electrode of the selection transistor ST2.
串單元SU0~SU3之各者中的選擇電晶體ST1之閘極分別與選擇閘極線SGD0~SGD3連接。相對於此,串單元SU0~SU3之各者中的選擇電晶體ST2之閘極共通連接於例如選擇閘極線SGS。當然,串單元SU0~SU3之各者中的選擇電晶體ST2之閘極亦可以串單元為單位連接於不同之選擇閘極線SGS0~SGS3。又,位於同一區塊BLK內之記憶胞電晶體MT0~MT7之控制閘極分別共通連接於字元線WL0~WL7。The gates of the selection transistors ST1 in each of the string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. On the other hand, the gates of the selection transistors ST2 in each of the string units SU0 to SU3 are commonly connected to, for example, the selection gate line SGS. Of course, the gates of the selection transistors ST2 in each of the string units SU0 - SU3 may also be connected to different selection gate lines SGS0 - SGS3 in units of string units. In addition, the control gates of the memory cell transistors MT0-MT7 in the same block BLK are respectively connected to the word lines WL0-WL7 in common.
又,記憶胞陣列110內位於同一列之複數個NAND串6之選擇電晶體ST1之汲極共通連接於位元線BL(BL0~BL(K-1),其中,K為2以上之自然數)。即,位元線BL於複數個區塊BLK間將複數個NAND串6共通連接。進而,複數個選擇電晶體ST2之源極共通連接於源極線SL。In addition, the drains of the selection transistors ST1 of the plurality of
即,各串單元SU包含與互不相同之複數個位元線BL連接且與同一選擇閘極線SGD連接的複數個NAND串6。又,各區塊BLK包含複數個串單元SU。而且,記憶胞陣列110係共通連接有各位元線BL之複數個區塊BLK之集合體。That is, each string unit SU includes a plurality of
圖3係表示NAND記憶體100之記憶胞陣列110之記憶區域的記憶體映射。FIG. 3 shows a memory map of the memory regions of the
記憶胞陣列110中,除了供記憶用戶資料之記憶區域以外,還具有不會寫入用戶資料之特定記憶區域PMA。特定記憶區域PMA係與供記憶用戶資料之記憶區域不同之記憶區域。由此,用戶資料不被寫入至特定記憶區域PMA。In the
特定記憶區域PMA包含複數個日誌資料記憶區域PMAp。各日誌資料記憶區域PMAp具有能夠儲存複數個日誌資料LD之資料尺寸。The specific memory area PMA includes a plurality of log data memory areas PMAp. Each log data memory area PMAp has a data size capable of storing a plurality of log data LD.
日誌資料LD具有包含下述錯誤發生資料之資料部分DP及包含位址資訊(包含包括區塊位址BA及頁位址PA之資訊)之冗餘部分RP。包含錯誤發生資料之資料部分DP與資料鎖存電路XDL之用戶資料儲存部對應,包含位址資訊(區塊位址BA及頁位址PA)之冗餘部分RP與資料鎖存電路XDL之冗餘部對應。The log data LD has a data part DP containing the following error occurrence data and a redundant part RP containing address information (including information including a block address BA and a page address PA). The data portion DP including error occurrence data corresponds to the user data storage portion of the data latch circuit XDL, and the redundant portion RP including address information (block address BA and page address PA) corresponds to the redundant portion of the data latch circuit XDL. The remainder corresponds.
於圖3中,特定記憶區域PMA具有複數個日誌資料記憶區域PMAp。各日誌資料記憶區域PMAp包含至少1個區塊BLK。各區塊BLK包含複數個頁。自記憶胞陣列110讀出資料及向記憶胞陣列110寫入資料係以複數位元之資料之集合即頁為單位進行。各頁能夠用頁位址PA指定。各頁中能夠儲存1個日誌資料LD。由此,於特定記憶區域PMA中之1個區塊BLK中之1個頁中儲存1個日誌資料LD。於1個區塊BLK內,日誌資料LD依序儲存於連續之複數個頁中。於各日誌資料記憶區域PMAp包含複數個區塊BLK之情形時,若於1個區塊BLK內之全部頁中儲存日誌資料LD,則於特定記憶區域PMA內之下一區塊BLK儲存日誌資料LD。由此,藉由保存日誌資料LD後逐個增加例如特定記憶區域PMA中之頁位址PA,能夠保存已保存之日誌資料LD,同時記憶下一日誌資料LD。保存下一日誌資料LD之位址係由定序器170所管理之位址指標指定。此處,保存1個日誌資料LD後,逐個增加位址指標所表示之頁位址PA,但亦可以2個為單位或者以3個為單位等以特定數為單位增加位址指標所表示之頁位址PA,而變更表示保存下一日誌資料LD之位址的頁位址PA。In FIG. 3 , the specific memory area PMA has a plurality of log data memory areas PMAp. Each log data memory area PMAp includes at least one block BLK. Each block BLK includes a plurality of pages. Reading data from the
圖4係表示相隔地配置有複數個日誌資料記憶區域PMAp之特定記憶區域PMA之例的記憶體映射。FIG. 4 is a memory map showing an example of a specific memory area PMA in which a plurality of log data memory areas PMAp are arranged at intervals.
於圖4中,2個日誌資料記憶區域PMAp相隔而設置。於日誌資料記憶區域PMAp之各區塊BLK內,於每次儲存日誌資料LD時增加一個頁位址PA,藉此可保存已保存之日誌資料LD,同時儲存下一日誌資料LD。若於1個區塊BLK內之全部頁中儲存日誌資料LD,則於保存日誌資料LD後,逐個增加例如區塊編號,藉此能夠保存已保存之日誌資料LD,同時於下一區塊BLK中記憶下一日誌資料LD。若於1個日誌資料記憶區域PMAp內之全部區塊BLK之全部頁中儲存日誌資料LD,則指定另一日誌資料記憶區域PMAp之區塊位址BA及頁位址PA,將日誌資料LD儲存至另一日誌資料記憶區域PMAp中。In FIG. 4 , two log data memory areas PMAp are set apart from each other. In each block BLK of the log data memory area PMAp, a page address PA is added each time the log data LD is stored, so that the saved log data LD can be saved, and the next log data LD can be stored simultaneously. If the log data LD is stored in all pages in one block BLK, after the log data LD is saved, for example, the block number is incremented one by one, so that the saved log data LD can be saved, and the log data LD can be saved in the next block BLK at the same time. memorize the next log data LD. If the log data LD is stored in all pages of all blocks BLK in one log data memory area PMAp, specify the block address BA and page address PA of another log data memory area PMAp to store the log data LD to another log data memory area PMAp.
[讀出錯誤之情形時之日誌資料保存處理][Log data saving processing in case of reading error]
如上所述,定序器170基於來自控制器200之指令CMD,執行資料讀出、資料寫入及資料抹除。本實施方式係關於發生讀出錯誤之情形時之日誌資料LD之保存。As described above, the
圖5係表示執行資料讀出時於控制器200與NAND記憶體100間收發資料之時序的時序圖。FIG. 5 is a timing chart showing the timing of sending and receiving data between the
自控制器200向NAND記憶體100發出讀出指令後,定序器170執行讀出動作(P1)。即,定序器170根據讀出指令自NAND記憶體100讀出資料,將所讀出之資料儲存至資料鎖存電路XDL。讀出動作(P1)期間,就緒/忙碌信號成為忙碌狀態,且暫存器單元180內之狀態暫存器亦被設定為表示忙碌之狀態。讀出動作結束後,就緒/忙碌信號成為就緒狀態(P1a),且狀態暫存器亦被設定為表示就緒之狀態。控制器200可藉由發出狀態讀出指令而確認狀態暫存器之狀態。控制器200以就緒/忙碌信號或者狀態暫存器之狀態,判斷讀出動作已完成。After the
控制器200將資料輸出指令向NAND記憶體100發出。定序器170根據資料輸出指令,將資料鎖存電路XDL之資料輸出至控制器200。即,定序器170將所讀出之資料輸出至記憶體控制器200。The
於控制器200中,藉由ECC電路260對接收到之資料進行錯誤檢測及錯誤訂正。若於接收到之資料中檢測出錯誤且錯誤訂正失敗之情形時,處理器230向NAND記憶體100發出ECC錯誤發生資訊。In the
處理器230於發生ECC錯誤時,進行將發生ECC錯誤之區塊設為壞塊(不良區塊)之處理。When an ECC error occurs, the
定序器170若接收到ECC錯誤發生資訊,則執行禁止受理特定指令之禁止處理(P2)。此處,特定指令係伴有由記憶體控制器200更新資料鎖存電路XDL中儲存之資料之情況之指令。執行禁止處理P2後,於資料鎖存電路XDL中依然保持所讀出之資料。定序器170執行日誌資料保存處理(P3)。When the
如上所述,定序器170於接收到讀出錯誤之通知時,進行禁止資料鎖存電路XDL之資料更新之處理後,將特定資料寫入至特定記憶區域PMA。As described above, when the
圖6係表示資料之讀出指令序列的圖。於讀出指令序列中,定序器170首先輸出預約指令「c01」。輸出預約指令「c01」後,輸出指令「c02」。指令「c02」係通知執行讀出動作。輸出指令「c01」及「c02」時,指令鎖存賦能信號CLE成為高位準(High)。指令「c01」及「c02」之輸出結束後,指令鎖存賦能信號CLE成為低位準(Low)。輸出指令「c02」後,輸出包含2個行位址「CA1」、「CA2」及3個列位址「RA1」、「RA2」、「RA3」之位址資料。輸出位址資料「CA1」、「CA2」、「RA1」、「RA2」、「RA3」時,位址鎖存賦能信號ALE成為高位準。位址資料之輸出結束後,位址鎖存賦能信號ALE成為低位準。繼位址資料之後,輸出指示執行讀出動作之指令「c03」。輸出指令「c03」時,指令鎖存賦能信號CLE成為高位準。指令「c03」之輸出結束後,指令鎖存賦能信號CLE成為低位準。輸出指令「c03」後,就緒/忙碌信號RBn成為低位準。FIG. 6 is a diagram showing a data read command sequence. In the read command sequence, the
就緒/忙碌信號RBn成為高位準後,控制器200輸出資料輸出指令。首先,先輸出指令「c04」。指令「c04」係通知執行資料輸出動作。輸出指令「c04」時,指令鎖存賦能信號CLE成為高位準。指令「c04」之輸出結束後,指令鎖存賦能信號CLE成為低位準。輸出指令「c04」後,輸出5個位址資料。輸出位址資料時,位址鎖存賦能信號ALE成為高位準。位址資料之輸出結束後,位址鎖存賦能信號ALE成為低位準。繼位址資料之後,輸出指示執行資料輸出動作之指令「c05」。輸出指令「c05」時,指令鎖存賦能信號CLE成為高位準。指令「c05」之輸出結束後,指令鎖存賦能信號CLE成為低位準。輸出指令「c05」後,定序器170輸出資料鎖存電路XDL之資料。After the ready/busy signal RBn becomes a high level, the
以上述方式執行讀出指令,控制器200能夠自NAND記憶體100讀出資料。By executing the read command in the above manner, the
圖7係表示接收到ECC錯誤發生資訊時的定序器170之日誌資料保存處理之一例的流程圖。FIG. 7 is a flowchart showing an example of the log data storage process of the
定序器170判定是否接收到ECC錯誤發生資訊(S1)。若接收到ECC錯誤發生資訊,則定序器170執行S2以下之處理。若未接收到ECC錯誤發生資訊(S1:否),則定序器170不執行S2以下之處理。The
若接收到ECC錯誤發生資訊(S1:是),則定序器170執行特定禁止處理P2(S2)。特定禁止處理P2係禁止受理伴有資料鎖存電路XDL之更新之指令的禁止處理。If the ECC error occurrence information is received ( S1 : YES), the
禁止處理P2例如使就緒/忙碌信號RBn成為低位準,並自NAND記憶體100供給至控制器200。就緒/忙碌信號RBn為低位準時,控制器200不向NAND記憶體100輸出指令。For example, the prohibition process P2 makes the ready/busy signal RBn low, and is supplied from the
S2後,定序器170將發生ECC錯誤之位址資訊寫入至資料鎖存電路XDL之冗餘部(S3)。After S2, the
S3後,定序器170將發生ECC錯誤之資料(即錯誤發生資料)及位址資訊自資料鎖存電路XDL傳輸至特定記憶區域PMA之1個資料記憶區域(S4)。即,定序器170自記憶體控制器200接收讀出錯誤之通知後,將特定資料寫入至特定記憶區域PMA。該特定資料包含讀出資料及讀出指令相關之位址資訊。具體而言,定序器170將資料鎖存電路XDL之資料作為日誌資料LD寫入至特定記憶區域PMA之1個資料記憶區域。After S3, the
定序器170增加特定記憶區域PMA之位址指標之位址(S5)。位址指標之位址資訊記憶於特定記憶區域PMA中。The
如上所述,特定記憶區域PMA具有複數個日誌資料記憶區域PMAp。定序器170管理位址指標。位址指標表示特定記憶區域PMA中記憶下一日誌資料LD之日誌資料記憶區域PMAp之位址。定序器170於將日誌資料LD寫入至日誌資料記憶區域PMAp後,增加日誌資料記憶區域PMAp之位址。位址指標之值(位址)藉由增加1個而變更,於已寫入一次日誌資料LD之日誌資料記憶區域PMAp中,資料不被覆寫。其結果,日誌資料LD得以被保存。As described above, the specific memory area PMA has a plurality of log data memory areas PMAp.
如上所述,定序器170於將特定資料寫入至特定記憶區域PMA後,執行保護寫入至特定記憶區域PMA之特定資料之處理。As described above, after writing the specific data into the specific memory area PMA, the
於日誌資料記憶區域PMAp中記憶錯誤發生資料及位址資訊(區塊位址BA及頁位址PA)。Error occurrence data and address information (block address BA and page address PA) are stored in the log data memory area PMAp.
圖8係表示發生讀出錯誤之情形時向特定記憶區域PMA保存日誌資料之流程的圖。FIG. 8 is a diagram showing a flow of storing log data in the specific memory area PMA when a read error occurs.
控制器200於無法對讀出資料進行ECC訂正時,將ECC錯誤發生資訊輸出至NAND記憶體100。定序器170將資料鎖存電路XDL之日誌資料LD保存至記憶胞陣列110中之特定記憶區域PMA中。When the
日誌資料LD記憶於記憶區域PMA中之位址指標所表示之位址之記憶區域中。The log data LD is stored in the memory area of the address indicated by the address index in the memory area PMA.
如上所述,根據上述第1實施方式,於記憶體系統1中,發生讀出錯誤時,定序器170自主地將日誌資料LD記憶至NAND記憶體100之特定記憶區域PMA中。日誌資料LD包含讀出錯誤相關之錯誤發生資料及其位址資訊(區塊位址BA及頁位址PA)。由此,能夠使用NAND記憶體100中之日誌資料LD進行不良解析。As described above, according to the first embodiment, when a read error occurs in the
(第2實施方式)(Second Embodiment)
於第1實施方式中,於發生讀出錯誤之情形時,保存日誌資料LD,但於第2實施方式中,於發生寫入錯誤之情形時,將日誌資料LD保存至特定記憶區域PMA中。In the first embodiment, when a read error occurs, the log data LD is saved, but in the second embodiment, when a write error occurs, the log data LD is saved in the specific memory area PMA.
第2實施方式之記憶體系統之構成與第1實施方式之記憶體系統1之構成相同,NAND記憶體100之構成及記憶體控制器200之構成亦分別與第1實施方式之NAND記憶體100之構成及記憶體控制器200之構成相同。由此,相同構成要素使用相同符號並省略說明。The configuration of the memory system of the second embodiment is the same as the configuration of the
[寫入錯誤之情形時之日誌資料保存處理][Log data saving processing in case of writing error]
圖9係表示執行資料寫入時於控制器200與NAND記憶體100間收發資料之時序的時序圖。FIG. 9 is a timing chart showing the timing of sending and receiving data between the
自控制器200向NAND記憶體100發出寫入指令後,定序器170執行寫入動作(P11)。寫入動作包含編程動作及驗證動作。編程動作係藉由將電子注入至電荷儲存層而使閾值上升(或禁止注入以維持閾值)之動作。驗證動作係藉由在編程動作後讀出資料來判定記憶胞電晶體MT之閾值是否達到目標位準之動作。After the
寫入動作(P11)期間,就緒/忙碌信號成為忙碌狀態,且暫存器單元180內之狀態暫存器亦設定為表示忙碌之狀態。寫入動作結束後,就緒/忙碌信號成為就緒狀態(P11a),且狀態暫存器亦設定為表示就緒之狀態。控制器200向NAND記憶體100發出狀態讀出指令。定序器170根據狀態讀出指令,執行狀態讀出處理(P12)。狀態讀出處理係讀出表示寫入動作成功或失敗之狀態資料之處理。During the writing operation (P11), the ready/busy signal becomes a busy state, and the status register in the
定序器170於寫入動作失敗(即寫入錯誤)之情形時,執行禁止受理特定指令之禁止處理(P13)。此處,特定指令係伴有記憶體控制器200更新資料鎖存電路XDL中儲存之資料之情況之指令。禁止處理P13後,資料鎖存電路XDL中保持寫入資料(期望值)即發生寫入錯誤之資料不變。The
定序器170向控制器200輸出狀態資料。
定序器170於寫入動作失敗之情形時,於輸出狀態資料後,執行日誌資料保存處理(P14)。When the write operation fails, the
如上所述,定序器170於發生寫入錯誤時,進行禁止資料鎖存電路XDL之資料更新之處理後,將特定資料寫入至特定記憶區域PMA。As described above, when a write error occurs, the
圖10係表示資料之寫入指令序列的圖。於寫入指令序列中,定序器170首先輸出預約指令「c01」。輸出預約指令「c01」後,輸出指令「c11」。指令「c11」係通知執行寫入動作。輸出指令「c01」及「c11」時,指令鎖存賦能信號CLE成為高位準。指令「c01」及「c11」之輸出結束後,指令鎖存賦能信號CLE成為低位準。輸出指令「c11」後,輸出包含2個行位址「CA1」、「CA2」及3個列位址「RA1」、「RA2」、「RA3」之位址資料。輸出位址資料「CA1」、「CA2」、「RA1」、「RA2」、「RA3」時,位址鎖存賦能信號ALE成為高位準。位址資料之輸出結束後,位址鎖存賦能信號ALE成為低位準。繼位址資料之後,輸出寫入資料。定序器170保持寫入至資料鎖存電路XDL資料。繼寫入資料之後,輸出指示執行寫入動作之指令「c12」。輸出指令「c12」時,指令鎖存賦能信號CLE成為高位準。指令「c12」之輸出結束後,指令鎖存賦能信號CLE成為低位準。輸出指令「c12」後,就緒/忙碌信號RBn成為低位準,直至寫入結束為止。FIG. 10 is a diagram showing a data write command sequence. In the write command sequence, the
以上述方式執行寫入指令,控制器200能夠將資料寫入至NAND記憶體100中。By executing the write command in the above manner, the
圖11係表示發生寫入錯誤時的定序器170之日誌資料保存處理之一例的流程圖。FIG. 11 is a flowchart showing an example of the log data storage process of the
定序器170判定是否發生寫入錯誤(S11)。基於狀態資料判定是否發生寫入錯誤。於寫入動作中,於編程動作後之驗證動作中,判定記憶胞電晶體MT之閾值未達到目標位準時,發生寫入錯誤。The
若發生寫入錯誤時,則定序器170執行S12以下之處理。若未發生寫入錯誤,則定序器170不執行S12以下之處理。When a write error occurs, the
若發生寫入錯誤(S11:是),則定序器170執行特定禁止處理P13(S12)。特定禁止處理P13係禁止受理伴有資料鎖存電路XDL之更新之指令的處理。If a write error occurs ( S11 : YES), the
禁止處理P13例如使就緒/忙碌信號RBn成為低位準,並自NAND記憶體100供給至控制器200。就緒/忙碌信號RBn為低位準時,控制器200不向NAND記憶體100輸出指令。For example, the prohibition process P13 makes the ready/busy signal RBn low, and is supplied from the
S12後,定序器170將發生寫入錯誤之位址資訊寫入至資料鎖存電路XDL之冗餘部(S13)。After S12, the
S13後,定序器170將發生寫入錯誤之資料(即錯誤發生資料)及位址資訊自資料鎖存電路XDL傳輸至特定記憶區域PMA之1個資料記憶區域(S14)。即,定序器170根據寫入指令將資料寫入至NAND記憶體100中。定序器170於發生資料寫入錯誤時,將特定資料寫入至特定記憶區域PMA。該特定資料包含寫入資料及寫入指令相關之位址資訊。具體而言,定序器170將資料鎖存電路XDL之資料作為日誌資料LD寫入至特定記憶區域PMA之1個資料記憶區域。After S13, the
定序器170增加特定記憶區域PMA之位址指標之位址(S15)。The
如上所述,特定記憶區域PMA具有複數個日誌資料記憶區域PMAp。定序器170管理表示特定記憶區域PMA中記憶下一日誌資料LD之日誌資料記憶區域PMAp之位址的位址指標。日誌資料LD被寫入至日誌資料記憶區域PMAp後,增加日誌資料記憶區域PMAp之位址。藉由增加1個位址,於已寫入一次日誌資料LD之日誌資料記憶區域PMAp中,資料不被覆寫。其結果,日誌資料LD得以被保存。As described above, the specific memory area PMA has a plurality of log data memory areas PMAp. The
如上所述,定序器170將特定資料寫入至特定記憶區域PMA後,執行保護寫入至特定記憶區域PMA之特定資料之處理。As described above, after the
於日誌資料記憶區域PMAp中記憶錯誤發生資料及位址資訊(區塊位址BA及頁位址PA)。Error occurrence data and address information (block address BA and page address PA) are stored in the log data memory area PMAp.
圖12係表示發生寫入錯誤之情形時向特定記憶區域PMA保存日誌資料LD之流程的圖。FIG. 12 is a diagram showing a flow of storing log data LD in the specific memory area PMA when a write error occurs.
定序器170於存在寫入錯誤時,將資料鎖存電路XDL之日誌資料LD保存至記憶胞陣列110中之特定記憶區域PMA中。The
日誌資料LD記憶於位址指標所表示之位址之記憶區域PMA中。The log data LD is stored in the memory area PMA of the address indicated by the address index.
由此,於NAND記憶體100中,於發生寫入錯誤時,定序器170自主地將日誌資料LD記憶至特定記憶區域PMA。日誌資料LD包含寫入錯誤相關之錯誤發生資料及其位址資訊(區塊位址BA及頁位址PA)。由此,能夠使用NAND記憶體100中之日誌資料LD進行不良解析。Therefore, in the
其次,對變化例進行說明。Next, a modification example will be described.
於上述第2實施方式中,於發生寫入錯誤時,將錯誤發生資料及其位址資訊記憶至特定記憶區域PMA中,但亦可於每次執行寫入時將錯誤發生資料及其位址資訊記憶至特定記憶區域PMA中,於發生寫入錯誤時使特定記憶區域PMA之資料無法更新。In the above-mentioned second embodiment, when a writing error occurs, the error occurrence data and its address information are stored in the specific memory area PMA, but the error occurrence data and its address can also be stored each time writing is performed. The information is stored in the specific memory area PMA, so that the data in the specific memory area PMA cannot be updated when a writing error occurs.
圖13係表示變化例中之執行資料寫入時於控制器200與NAND記憶體100間收發資料之時序的時序圖。FIG. 13 is a timing chart showing the timing of sending and receiving data between the
自控制器200向NAND記憶體100發出寫入指令後,定序器170執行向由控制器200指定之位址之寫入動作(P21)。After the
定序器170執行日誌資料保存處理(P22)。日誌資料保存處理(P22)與日誌資料保存處理(P14)相同。The
寫入動作(P22)期間,就緒/忙碌信號成為忙碌狀態,且暫存器單元180內之狀態暫存器亦設定為表示忙碌之狀態。寫入動作結束後,就緒/忙碌信號成為就緒狀態(P22a),且狀態暫存器亦設定為表示就緒之狀態。控制器200向NAND記憶體100發出狀態讀出指令。定序器170基於狀態資料,判定是否發生寫入錯誤。During the writing operation (P22), the ready/busy signal becomes a busy state, and the status register in the
若發生狀態失敗(P23),則向控制器200輸出寫入失敗之狀態資料。If a status failure occurs (P23), the writing failure status data is output to the
若發生狀態失敗(P23),則定序器170於輸出狀態資料後,執行覆寫禁止處理(P24)。於覆寫禁止處理(P24)中,增加特定記憶區域PMA之位址指標之位址。所謂覆寫禁止,亦包含限制一定期間或者一定次數之覆寫之情形。If a status failure occurs (P23), the
圖14係表示發生寫入錯誤時的定序器170之日誌資料保存處理之一例的流程圖。FIG. 14 is a flowchart showing an example of the log data storage process of the
定序器170執行向由控制器200指定之位址之寫入動作(S21)。The
S21後,定序器170將位址資訊寫入至資料鎖存電路XDL之冗餘部(S22)。After S21, the
S22後,定序器170將錯誤發生資料及位址資訊自資料鎖存電路XDL傳輸至特定記憶區域PMA之1個資料記憶區域(S23)。After S22, the
定序器170判定S21中之寫入動作之執行中是否發生寫入錯誤(S24)。若發生寫入錯誤,則定序器170增加特定記憶區域PMA之位址指標之位址(S25)。若未發生寫入錯誤,則定序器170進入至S21之處理。The
於每次連續執行寫入動作時,若未發生寫入錯誤(S24:否),則對特定記憶區域PMA覆寫新的資料(寫入資料)及位址資訊。若發生寫入錯誤(S24:是),則定序器170增加特定記憶區域PMA之位址(S25)。由此,記憶有資料(即錯誤發生資料)及位址資訊之日誌資料記憶區域PMAp不被覆寫。If no write error occurs ( S24 : No) every time the write operation is performed continuously, the specific memory area PMA is overwritten with new data (written data) and address information. If a write error occurs (S24: YES), the
如上所述,根據上述第2實施方式及變化例,於NAND記憶體100中,於發生寫入錯誤時,於特定記憶區域PMA記憶日誌資料LD。日誌資料LD包含寫入錯誤相關之錯誤發生資料及其位址資訊(區塊位址BA及頁位址PA)。由此,能夠使用日誌資料LD進行不良解析。As described above, according to the second embodiment and the modification, in the
再者,於記憶胞電晶體MT為能夠記憶3位元之資料之TLC(Triple Level Cell,三層單元)、能夠記憶4位元之資料之QLC(Quad Level Cell,四層單元)等之情形時,特定記憶區域PMA較佳為pSLC(pseudo Single Level Cell,偽單層單元)區域。pSLC區域係以SLC模式寫入資料之區域。SLC模式係向如TLC或QLC之能夠記憶多值資料的記憶胞電晶體MT中以1位元資料之形式記憶資料之模式。定序器170於向pSLC區域寫入日誌資料LD時,以SLC模式寫入資料。Furthermore, the memory cell transistor MT is a TLC (Triple Level Cell) capable of storing 3-bit data, a QLC (Quad Level Cell) capable of storing 4-bit data, etc. , the specific memory area PMA is preferably a pSLC (pseudo Single Level Cell, pseudo single level cell) area. The pSLC area is the area where data is written in SLC mode. The SLC mode is a mode for storing data in the form of 1-bit data into a memory cell transistor MT capable of storing multi-value data such as TLC or QLC. When the
例如,於TLC之情形時,如圖2中單點鏈線所示,各字元線WL之複數個記憶胞電晶體MT中能夠保持3頁之資料。於寫入有上位頁之資料時,保存於pSLC之第1日誌資料記憶區域中,於寫入有中位頁之資料時,保存於pSLC之第2日誌資料記憶區域中,於寫入有下位頁之資料時,保存於pSLC之第3日誌資料記憶區域中。For example, in the case of TLC, as shown by the single-dotted chain line in FIG. 2 , the data of 3 pages can be held in the plurality of memory cell transistors MT of each word line WL. When the data of the upper page is written, it is stored in the first log data memory area of pSLC. When the data of the middle page is written, it is saved in the second log data memory area of pSLC. When the data of the page is stored, it is stored in the third log data memory area of pSLC.
(第3實施方式)(third embodiment)
於第1實施方式中,於發生讀出錯誤時,保存日誌資料LD,於第2實施方式中,於寫入錯誤時,保存日誌資料,但於第3實施方式中,於發生某些錯誤時,將NAND記憶體100之使用狀態或動作狀態相關之日誌資料LD保存至特定記憶區域PMA中。In the first embodiment, log data LD is saved when a read error occurs, and in the second embodiment, log data is saved when a write error occurs, but in the third embodiment, when some errors occur , and save the log data LD related to the use state or the action state of the
第3實施方式之記憶體系統之構成與第1實施方式之記憶體系統1之構成相同,NAND記憶體100之構成及記憶體控制器200之構成亦分別與第1實施方式之NAND記憶體100之構成及記憶體控制器200之構成相同。由此,相同構成要素使用相同符號並省略說明。The configuration of the memory system of the third embodiment is the same as the configuration of the
圖15係表示發生錯誤時的定序器170之日誌資料LD之保存處理之一例的流程圖。於本實施方式中,日誌資料LD中包含溫度感測器190之溫度碼。溫度碼係由定序器170獲取,並作為溫度資訊儲存於暫存器單元180中之溫度碼暫存器中。FIG. 15 is a flowchart showing an example of the storage process of the log data LD of the
發生讀出錯誤時,定序器170自控制器200接收ECC錯誤資訊。寫入錯誤或者抹除錯誤於定序器170中被檢測出。When a read error occurs, the
定序器170判定是否發生讀出錯誤等某些錯誤(S31)。The
若檢測出某些錯誤(S31:是),則定序器170執行S32以後之處理。若未檢測出某些錯誤(S31:否),則定序器170不執行S32以後之處理。If some errors are detected (S31: YES), the
若檢測出某些錯誤(S31:是),則定序器170禁止受理特定指令(P32)。此處,特定指令係伴有記憶體控制器200更新資料鎖存電路XDL中儲存之資料之情況之指令。If some errors are detected ( S31 : YES), the
S32後,定序器170將溫度感測器190之溫度資訊作為使用狀態資料寫入至資料鎖存電路XDL之冗餘部(S33)。After S32, the
S33後,定序器170將溫度資訊自資料鎖存電路XDL傳輸至特定記憶區域PMA(S34)。錯誤發生資料及溫度資訊儲存於資料鎖存電路XDL中。定序器170將資料鎖存電路XDL之資料寫入至特定記憶區域PMA。After S33, the
如上所述,定序器170將溫度感測器190之溫度資訊寫入至特定記憶區域PMA。As described above, the
S34後,定序器170增加特定記憶區域PMA之位址指標之位址(S35)。After S34, the
如上所述,根據上述第3實施方式,於記憶體系統1中,若發生某些錯誤,則將溫度資訊作為日誌資料LD記憶至特定記憶區域PMA。由此,能夠使用日誌資料LD進行不良解析。As described above, according to the above-described third embodiment, in the
再者,於上述實施方式中,若發生某些錯誤,則保存包含溫度資訊之日誌資料LD,但亦可於日誌資料LD中包含溫度資訊以外之資訊。例如,亦可將抹除次數或者讀出次數之資訊與溫度資訊一起作為NAND記憶體100之動作狀態資訊包含於日誌資料LD中。抹除次數或者讀出次數之資訊係出貨後至發生某些錯誤之時點為止之累積次數。Furthermore, in the above-mentioned embodiment, if some errors occur, the log data LD including the temperature information is saved, but the log data LD may also include information other than the temperature information. For example, the information of the erasing times or the reading times may be included in the log data LD together with the temperature information as the operation state information of the
進而,再者,亦可使Set Feature指令所含之移位量等動作條件相關之資訊作為動作狀態資訊包含於日誌資料LD中。Furthermore, it is also possible to include in the log data LD information related to operation conditions such as the shift amount included in the Set Feature command as operation state information.
即,亦可使定序器170將NAND記憶體100之動作狀態之資訊寫入至特定記憶區域PMA。That is, the
抹除次數係定序器170根據上述接收到之指令而執行的抹除動作之執行次數。抹除次數係於每次執行抹除指令時由定序器170按區塊計數,並儲存至暫存器單元180中之抹除次數暫存器中。抹除次數之計數亦可包含客戶方所實施之動作測試中之抹除次數。The number of erasing is the number of erasing operations performed by the
讀出次數係定序器170根據接收到之指令而執行的讀出動作之執行次數。讀出次數係於每次執行讀出指令時由定序器170按每一區塊計數,並儲存至暫存器單元180中之讀出次數暫存器。讀出次數之計數亦可包含客戶方所實施之動作測試中之讀出次數。The number of read times is the number of times the
移位量等動作條件相關之資訊係設定用於執行接收到之指令之動作條件的資訊。動作條件相關之資訊儲存於暫存器單元180中。例如,每次接收Set Feature指令時,擷取Set Feature指令相關之移位量等動作條件相關之資料,儲存至Feature暫存器中。The information related to the operation condition such as the shift amount is the information for setting the operation condition for executing the received command. The information related to the action conditions is stored in the
圖16係表示發生某些錯誤時向特定記憶區域PMA保存日誌資料之流程的圖。FIG. 16 is a diagram showing the flow of saving log data to the specific memory area PMA when some error occurs.
發生某些錯誤時,定序器170將溫度碼暫存器、抹除次數暫存器、讀出次數暫存器及Feature暫存器之至少1者中儲存之資料寫入至資料鎖存電路XDL之冗餘部。When some error occurs, the
資料鎖存電路XDL之日誌資料LD被保存於記憶胞陣列110中之特定記憶區域PMA中。The log data LD of the data latch circuit XDL is stored in a specific memory area PMA in the
再者,亦可將表示發生之錯誤為讀出錯誤、寫入錯誤或抹除錯誤之錯誤碼資訊亦包含於日誌資料LD中。Furthermore, error code information indicating that the error occurred is a read error, a write error, or an erase error may also be included in the log data LD.
如上所述,根據上述第3實施方式,於記憶體系統1中,若發生某種錯誤,則定序器170自主地將使用狀態或動作狀態之資料作為日誌資料LD而記憶至特定記憶區域PMA中。由此,能夠使用日誌資料LD進行不良解析。As described above, according to the above-mentioned third embodiment, in the
(第4實施方式)(fourth embodiment)
於第3實施方式中,於記憶體系統1中,若發生某種錯誤,則無論錯誤之種類如何,均將使用狀態或動作狀態相關之日誌資料LD記憶於特定記憶區域PMA。第4實施方式中,當發生讀出錯誤時,將包含錯誤發生資料、位址資訊(區塊位址BA及頁位址PA)、以及與使用狀態及動作狀態之至少一者相關之資訊的日誌資料LD,記憶於特定記憶區域PMA中。In the third embodiment, if a certain error occurs in the
第4實施方式之記憶體系統之構成與第1實施方式之記憶體系統1之構成相同,NAND記憶體100之構成及記憶體控制器200之構成亦分別與第1實施方式之NAND記憶體100之構成及記憶體控制器200之構成相同。由此,對於相同構成要素使用相同符號並省略說明。The configuration of the memory system of the fourth embodiment is the same as that of the
於第1實施方式中,發生讀出錯誤時,日誌資料LD中包含錯誤發生資料及位址資訊(區塊位址BA及頁位址PA)。錯誤發生資料儲存於日誌資料LD中之資料部分DP中。In the first embodiment, when a read error occurs, the log data LD includes error occurrence data and address information (block address BA and page address PA). The error occurrence data is stored in the data part DP in the log data LD.
相對於此,於第4實施方式中,發生讀出錯誤時,向資料鎖存電路XDL之冗餘部寫入位址資訊(區塊位址BA及頁位址PA)及使用狀態或動作狀態之資訊。其結果,位址資訊及溫度資訊等使用狀態或動作狀態之資訊包含於日誌資料LD中之冗餘部分RP中。On the other hand, in the fourth embodiment, when a read error occurs, address information (block address BA and page address PA) and the use state or operation state are written into the redundant portion of the data latch circuit XDL information. As a result, the information of the use state or the operation state, such as address information and temperature information, is included in the redundant part RP in the log data LD.
即,定序器170所接收之指令係來自控制NAND記憶體100之記憶體控制器200之讀出指令。定序器170根據讀出指令而自NAND記憶體100讀出資料。定序器170將所讀出之資料作為讀出資料輸出至記憶體控制器200。定序器170自記憶體控制器200接收讀出錯誤之通知後,將特定資料寫入至特定記憶區域PMA。該特定資料包含讀出資料、讀出指令相關之位址資訊、及NAND記憶體100之使用狀態或動作狀態之資訊。That is, the command received by the
如上所述,根據上述第4實施方式,於記憶體系統1中,發生讀出錯誤時,定序器170自主地將日誌資料LD記憶至NAND記憶體100之特定記憶區域PMA中。該日誌資料LD包含讀出錯誤相關之錯誤發生資料、其位址資訊(區塊位址BA及頁位址PA)、及使用狀態或動作狀態之資訊。由此,能夠使用NAND記憶體100中之日誌資料LD進行不良解析。As described above, according to the fourth embodiment, in the
(第5實施方式)(Fifth Embodiment)
於第3實施方式中,於記憶體系統1中,若發生某些錯誤,則無論錯誤之種類如何,均將使用狀態或動作狀態相關之日誌資料LD記憶至特定記憶區域PMA中。於該第5實施方式中,於發生寫入錯誤時,將包含錯誤發生資料、位址資訊(區塊位址BA及頁位址PA)以及與使用狀態及動作狀態之至少一者相關之資訊的日誌資料LD記憶至特定記憶區域PMA中。In the third embodiment, if some error occurs in the
第5實施方式之記憶體系統之構成與第1實施方式之記憶體系統1之構成相同,NAND記憶體100之構成及記憶體控制器200之構成亦分別與第1實施方式之NAND記憶體100之構成及記憶體控制器200之構成相同。由此,相同構成要素使用相同符號並省略說明。The configuration of the memory system of the fifth embodiment is the same as the configuration of the
於第2實施方式中,於發生寫入錯誤時,日誌資料LD中包含錯誤發生資料及位址資訊。錯誤發生資料儲存於日誌資料LD中之資料部分DP中。In the second embodiment, when a write error occurs, the log data LD includes error occurrence data and address information. The error occurrence data is stored in the data part DP in the log data LD.
相對於此,於第5實施方式中,於發生寫入錯誤時,向資料鎖存電路XDL之冗餘部寫入位址資訊(區塊位址BA及頁位址PA)及使用狀態或動作狀態之資訊。其結果,位址資訊及溫度資訊等使用狀態或動作狀態之資訊包含於日誌資料LD中之冗餘部分RP中。On the other hand, in the fifth embodiment, when a write error occurs, address information (block address BA and page address PA) and use status or operation are written to the redundant portion of the data latch circuit XDL Status information. As a result, the information of the use state or the operation state, such as address information and temperature information, is included in the redundant part RP in the log data LD.
如上所述,根據上述第5實施方式,於記憶體系統1中,於發生寫入錯誤時,定序器170自主地將日誌資料LD記憶至NAND記憶體100之特定記憶區域PMA中。該日誌資料LD包含寫入錯誤相關之錯誤發生資料、其位址資訊(區塊位址BA及頁位址PA)、及使用狀態或動作狀態之資訊。由此,能夠使用NAND記憶體100中之日誌資料LD進行不良解析。As described above, according to the fifth embodiment, in the
即,定序器170所接收之指令係來自控制NAND記憶體100之記憶體控制器200之寫入指令。定序器170根據寫入指令而將資料寫入至NAND記憶體100中。定序器170於發生資料之寫入錯誤時,將特定資料寫入至特定記憶區域PMA。該特定資料包含寫入資料、寫入指令相關之位址資訊、及NAND記憶體100之使用狀態或動作狀態之資訊。That is, the command received by the
再者,第2實施方式之變化例亦可適用於該第5實施方式。即,亦可於每次執行資料之寫入時將包含錯誤發生資料、位址資訊、及與使用狀態或動作狀態之至少一者相關之資訊的日誌資料LD記憶至特定記憶區域PMA中,於發生寫入錯誤時使特定記憶區域PMA之資料無法更新。In addition, the modification of 2nd Embodiment can also be applied to this 5th Embodiment. That is, the log data LD including the error occurrence data, address information, and information related to at least one of the use state or the action state can also be stored in the specific memory area PMA every time the data is written. When a write error occurs, the data of the specific memory area PMA cannot be updated.
如上所述,根據上述各實施方式,定序器170能夠自控制針對NAND記憶體100之資料讀出動作及寫入動作的記憶體控制器200接收指令。定序器170於與所接收之指令相應之動作(讀出動作、寫入動作、抹除動作)發生錯誤時,將特定資料寫入至NAND記憶體100之特定記憶區域PMA。As described above, according to the above-described embodiments, the
由此,根據上述各實施方式,能夠提供一種能夠保存用於不良解析之資料之半導體記憶裝置。Thus, according to the above-described embodiments, it is possible to provide a semiconductor memory device capable of storing data for failure analysis.
上述實施方式及變化例亦可於可能之範圍內相互組合。例如,第2實施方式之變化例可與第3實施方式組合。The above-described embodiments and modifications can also be combined with each other to the extent possible. For example, the modification of the second embodiment can be combined with the third embodiment.
已對本發明之若干實施方式進行了說明,但該等實施方式係作為例所例示者,並不意圖限定發明之範圍。該等新穎之實施方式可以其他各種形態實施,可於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施方式或其變化包含於發明之範圍或主旨中,且包含於專利請求範圍所記載之發明及其均等之範圍內。Several embodiments of the present invention have been described, but these embodiments are illustrated as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or variations thereof are included in the scope or gist of the invention, and are included in the invention described in the scope of the patent claim and its equivalents.
[相關申請] 本申請享受以日本專利申請2020-152510號(申請日:2020年9月11日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。 [Related Application] This application enjoys priority based on Japanese Patent Application No. 2020-152510 (filing date: September 11, 2020). The present application includes the entire contents of the basic application by referring to the basic application.
6: NAND串 100: NAND記憶體 110:記憶胞陣列 120:列解碼器 130:驅動電路 140:行解碼器 150:位址暫存器 160:指令暫存器 170:定序器 180:暫存器單元 190:溫度感測器 200:記憶體控制器 210:主機介面電路 220:隨機存取記憶體 230:處理器 240:緩衝記憶體 250: NAND介面電路 260: ECC電路 300:主機機器 ADD:位址 ALE:位址鎖存賦能信號 BL0:位元線 BL1:位元線 BL(K-1):位元線 BLK0:區塊 BLK1:區塊 BLK2:區塊 BLK3:區塊 c01:指令 c02:指令 c03:指令 c04:指令 c05:指令 c11:指令 c12:指令 CA1:行位址 CA2:行位址 CEn:晶片賦能信號 CLE:指令鎖存賦能信號 CMD:指令 DAT:讀出資料 DQS:資料選通信號 DQS:資料選通信號 I/O:資料選通信號 LD:日誌資料 LUT :對照表 MT0:記憶胞電晶體 MT1:記憶胞電晶體 MT2:記憶胞電晶體 MT3:記憶胞電晶體 MT4:記憶胞電晶體 MT5:記憶胞電晶體 MT6:記憶胞電晶體 MT7:記憶胞電晶體 P1:讀出動作 P1a:就緒狀態 P2:禁止處理 P3:日誌資料保存處理 P11:寫入動作 P11a:就緒狀態 P12:狀態讀出處理 P13:禁止處理 P14:日誌資料保存處理 P21:寫入動作 P22:日誌資料保存處理 P22a:就緒狀態 P23:狀態失敗 P24:禁止處理 PMA:特定記憶區域 PMAp:日誌資料記憶區域 RA1:列位址 RA2:列位址 RA3:列位址 R/B:就緒/忙碌 RBn:就緒/忙碌信號 REn:讀出賦能信號 S1:步驟 S2:步驟 S3:步驟 S4:步驟 S5:步驟 S11:步驟 S12:步驟 S13:步驟 S14:步驟 S15:步驟 S21:步驟 S22:步驟 S23:步驟 S24:步驟 S25:步驟 S31:步驟 S32:步驟 S33:步驟 S34:步驟 S35:步驟 SA:感測放大器 SGD0:選擇閘極線 SGD1:選擇閘極線 SGD2:選擇閘極線 SGD3:選擇閘極線 SGD4:選擇閘極線 SGS:選擇閘極線 ST1:選擇電晶體 ST2:選擇電晶體 SU0:串單元 SU1:串單元 SU2:串單元 SU3:串單元 SL:源極線 TBL:轉換表資訊 WL1:字元線 WL2:字元線 WL3:字元線 WL4:字元線 WL5:字元線 WL6:字元線 WL7:字元線 WEn:寫入賦能信號 WPn:寫入保護信號 XDL:資料鎖存電路 6: NAND string 100: NAND memory 110: Memory Cell Array 120: Column Decoder 130: Drive circuit 140: Line Decoder 150: address scratchpad 160: Instruction scratchpad 170: Sequencer 180: Scratchpad unit 190: Temperature sensor 200: Memory Controller 210: host interface circuit 220: Random Access Memory 230: Processor 240: Buffer memory 250: NAND interface circuit 260: ECC Circuit 300: host machine ADD: address ALE: address latch enable signal BL0: bit line BL1: bit line BL(K-1): bit line BLK0: block BLK1: block BLK2:Block BLK3: Block c01: instruction c02: instruction c03: instruction c04: instruction c05: instruction c11: instruction c12: instruction CA1: row address CA2: row address CEn: chip enable signal CLE: instruction latch enable signal CMD: command DAT: read data DQS: data strobe signal DQS: data strobe signal I/O: Data strobe signal LD: log data LUT : Comparison table MT0: memory cell transistor MT1: Memory Cell Transistor MT2: Memory Cell Transistor MT3: Memory Cell Transistor MT4: Memory Cell Transistor MT5: Memory Cell Transistor MT6: Memory Cell Transistor MT7: Memory Cell Transistor P1: readout action P1a: ready state P2: Prohibition of processing P3: Log data storage processing P11: write action P11a: Ready state P12: Status read processing P13: PROHIBITED PROCESSING P14: Log data storage processing P21: Write Action P22: Log data storage processing P22a: Ready state P23: Status failed P24: PROHIBITED PROCESSING PMA: specific memory area PMap: log data memory area RA1: column address RA2: column address RA3: column address R/B: ready/busy RBn: ready/busy signal REn: read enable signal S1: Step S2: Step S3: Step S4: Steps S5: Steps S11: Steps S12: Steps S13: Steps S14: Steps S15: Steps S21: Steps S22: Step S23: Step S24: Step S25: Steps S31: Step S32: Step S33: Step S34: Step S35: Steps SA: Sense Amplifier SGD0: select gate line SGD1: select gate line SGD2: select gate line SGD3: select gate line SGD4: select gate line SGS: select gate line ST1: select transistor ST2: select transistor SU0: string unit SU1: string unit SU2: string unit SU3: string unit SL: source line TBL: Conversion Table Information WL1: word line WL2: word line WL3: word line WL4: word line WL5: word line WL6: word line WL7: word line WEn: write enable signal WPn: Write Protect Signal XDL: Data Latch Circuit
圖1係表示第1實施方式之記憶體系統之構成的區塊圖。 圖2係表示第1實施方式之記憶胞陣列之構成的電路圖。 圖3係表示第1實施方式之NAND(反及)型快閃記憶體之記憶胞陣列之記憶區域的記憶體映射。 圖4係表示第1實施方式之相隔地配置有複數個日誌資料記憶區域之特定記憶區域之例的記憶體映射。 圖5係表示第1實施方式之執行資料讀出時於記憶體控制器與NAND型快閃記憶體間收發資料之時序的時序圖。 圖6係表示第1實施方式之資料之讀出指令序列的圖。 圖7係表示第1實施方式之接收到ECC(Error Check and Correction,錯誤檢查與校正)錯誤發生資訊時定序器進行之日誌資料保存處理之一例的流程圖。 圖8係表示第1實施方式之發生讀出錯誤之情形時向特定記憶區域保存日誌資料之流程的圖。 圖9係表示第2實施方式之執行資料寫入時於控制器與NAND型快閃記憶體間收發資料之時序的時序圖。 圖10係表示第2實施方式之資料之寫入指令序列的圖。 圖11係表示第2實施方式之發生寫入錯誤時定序器進行之日誌資料保存處理之一例的流程圖。 圖12係表示第2實施方式之發生寫入錯誤之情形時向特定記憶區域保存日誌資料之流程的圖。 圖13係表示第2實施方式之變化例之執行資料寫入時於控制器與NAND型快閃記憶體間收發資料之時序的時序圖。 圖14係表示第2實施方式之變化例之發生寫入錯誤時定序器進行之日誌資料保存處理之一例的流程圖。 圖15係表示第3實施方式之發生錯誤時定序器進行之日誌資料保存處理之一例的流程圖。 圖16係表示第3實施方式之發生某些錯誤時向特定記憶區域保存日誌資料之流程的圖。 FIG. 1 is a block diagram showing the configuration of the memory system according to the first embodiment. FIG. 2 is a circuit diagram showing the configuration of the memory cell array according to the first embodiment. FIG. 3 shows the memory map of the memory area of the memory cell array of the NAND (inversion) type flash memory according to the first embodiment. FIG. 4 is a memory map showing an example of a specific memory area in which a plurality of log data memory areas are arranged at intervals according to the first embodiment. FIG. 5 is a timing chart showing the timing of sending and receiving data between the memory controller and the NAND-type flash memory when data reading is performed according to the first embodiment. FIG. 6 is a diagram showing a data read command sequence according to the first embodiment. 7 is a flowchart showing an example of log data storage processing performed by the sequencer when an ECC (Error Check and Correction) error occurrence information is received according to the first embodiment. 8 is a diagram showing a flow of storing log data in a specific memory area when a read error occurs in the first embodiment. FIG. 9 is a timing chart showing the timing of sending and receiving data between the controller and the NAND-type flash memory when data writing is performed in the second embodiment. FIG. 10 is a diagram showing a data write command sequence according to the second embodiment. FIG. 11 is a flowchart showing an example of log data storage processing performed by the sequencer when a write error occurs in the second embodiment. FIG. 12 is a diagram showing a flow of storing log data in a specific memory area when a write error occurs in the second embodiment. 13 is a timing chart showing the timing of sending and receiving data between the controller and the NAND-type flash memory when data writing is performed in a modification of the second embodiment. FIG. 14 is a flowchart showing an example of log data storage processing performed by the sequencer when a write error occurs in a modification of the second embodiment. FIG. 15 is a flowchart showing an example of log data storage processing performed by the sequencer when an error occurs in the third embodiment. FIG. 16 is a diagram showing a flow of storing log data in a specific memory area when some error occurs in the third embodiment.
S1:步驟 S2:步驟 S3:步驟 S4:步驟 S5:步驟 S1: Step S2: Step S3: Step S4: Steps S5: Steps
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080235442A1 (en) * | 2007-03-19 | 2008-09-25 | Samsung Electronics Co., Ltd. | Flash memory device capable of improving read performance |
US20090241010A1 (en) * | 2008-03-01 | 2009-09-24 | Kabushiki Kaisha Toshiba | Memory system |
WO2013027642A1 (en) * | 2011-08-19 | 2013-02-28 | Kabushiki Kaisha Toshiba | Information processing apparatus, method for controlling information processing apparatus, non-transitory recording medium storing control tool, host device, non-transitory recording medium storing performance evaluation tool, and performance evaluation method for external memory device |
US20200065000A1 (en) * | 2008-06-20 | 2020-02-27 | Toshiba Memory Corporation | Memory system with selective access to first and second memories |
US10643703B2 (en) * | 2017-03-24 | 2020-05-05 | Toshiba Memory Corporation | Semiconductor memory device having a semiconductor chip including a memory cell and a resistance element |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US8027194B2 (en) * | 1988-06-13 | 2011-09-27 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
US8558051B2 (en) | 2007-07-18 | 2013-10-15 | The Procter & Gamble Company | Disposable absorbent article having odor control system |
US10055352B2 (en) | 2014-03-11 | 2018-08-21 | Amazon Technologies, Inc. | Page cache write logging at block-based storage |
US9362000B2 (en) * | 2014-09-05 | 2016-06-07 | Kabushiki Kaisha Toshiba | Memory system and management method thereof |
KR102498223B1 (en) * | 2015-10-13 | 2023-02-09 | 삼성전자주식회사 | Method for operating universal flash stroage (ufs) device, method for operating ufs host, and method for operating ufs systrem having them |
KR102384773B1 (en) | 2017-10-12 | 2022-04-11 | 삼성전자주식회사 | Storage device, computing system and debugging method thereof |
KR20190067370A (en) | 2017-12-07 | 2019-06-17 | 에스케이하이닉스 주식회사 | Data Storage Device and Operation Method Thereof, Storage System Having the Same |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080235442A1 (en) * | 2007-03-19 | 2008-09-25 | Samsung Electronics Co., Ltd. | Flash memory device capable of improving read performance |
US20090241010A1 (en) * | 2008-03-01 | 2009-09-24 | Kabushiki Kaisha Toshiba | Memory system |
US20200065000A1 (en) * | 2008-06-20 | 2020-02-27 | Toshiba Memory Corporation | Memory system with selective access to first and second memories |
WO2013027642A1 (en) * | 2011-08-19 | 2013-02-28 | Kabushiki Kaisha Toshiba | Information processing apparatus, method for controlling information processing apparatus, non-transitory recording medium storing control tool, host device, non-transitory recording medium storing performance evaluation tool, and performance evaluation method for external memory device |
US10643703B2 (en) * | 2017-03-24 | 2020-05-05 | Toshiba Memory Corporation | Semiconductor memory device having a semiconductor chip including a memory cell and a resistance element |
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