JP6510225B2 - Clock data recovery circuit, timing controller, electronic device, clock data recovery method - Google Patents

Description

  The present invention relates to a CDR (Clock Data Recovery) circuit.

  Serial data transmission is used to transmit and receive data between semiconductor integrated circuits via a small number of data transmission lines. The reception of the serial data signal is performed by latching each bit data of the serial data at the timing of a clock signal synchronized therewith.

  Here, the clock signal may be embedded in the serial data signal. In this case, the change point of the serial data signal is monitored by the CDR circuit, the clock signal is regenerated based on the detected change point, and the serial data signal is latched by the regenerated clock signal. The related arts are disclosed in Patent Documents 1 to 3.

JP 2005-5999 A Unexamined-Japanese-Patent No. 2003-204319 JP, 2011-120106, A WO 14/045551 A1 brochure

  There are various types of CDR circuits, and one of the typical ones is a CDR circuit using a PLL (Phase Locked Loop) circuit. When the CDR circuit of the PLL system is used for an application where input data is inputted intermittently, the lock of the PLL circuit is released each time the input data is not inputted. Therefore, there is a problem that each time input data resumes, a delay occurs until the PLL circuit locks.

  This problem can be solved by using an oversampling type CDR circuit (see Patent Document 4). In the oversampling method, data is taken in by a high-speed clock signal that is about three times the frequency (input frequency) of input data, and the clock signal is regenerated by logic processing to extract data. The oversampling CDR circuit is suitable for applications where input data is given intermittently because there is no delay for phase lock, but the operating frequency is higher and power consumption is higher than that of the PLL CDR circuit. The problem arises that In addition, a semiconductor manufacturing process is required to manufacture a device capable of high speed operation, which causes an increase in cost. Furthermore, the accuracy of the clock signal to be reproduced is easily affected by the accuracy of the high-speed clock signal, and the cost is high when using an external crystal oscillator for frequency stabilization.

  The present invention has been made in view of such problems, and one of the exemplary objects of an aspect thereof is to provide a PLL CDR circuit capable of reproducing a clock in a short time.

One aspect of the present invention relates to a clock data recovery circuit. The clock data recovery circuit has a voltage controlled oscillator that generates a multiphase clock signal including a plurality of clock signals having a frequency corresponding to the control voltage and shifted in phase with each other at regular intervals, and a phase of input data compared with a plurality of clock signals each phase, the comparison result and a phase comparator for generating a phase difference signal indicating a frequency of the input data, as compared to the frequency of the multiphase clock signal, the frequency difference signal indicating a comparison result ( Alternatively a frequency comparator for generating also referred) and the phase frequency difference signal, a charge pump circuit for generating a control voltage whose voltage level is adjusted according to the phase difference signal Oyo BiAmane wavenumber difference signal, the multi-phase clock signal A dummy clock signal generator for generating a dummy clock signal having substantially the same frequency as that of the frequency stabilized period; Obtain. In the absence of input data, the frequency comparator compares the frequency of the dummy clock signal with the frequency of the multiphase clock signal instead of the frequency of the input data.

  According to this aspect, the dummy clock signal is used to continue operating the frequency lock loop when no input data is input, thereby substantially reducing the frequency of the input data and the frequency of the multiphase clock signal when the input data is resumed Can be matched. As a result, the time required to adjust the frequency is shortened, and when the phase adjustment is completed, it is possible to immediately acquire serial data included in the input data.

  The dummy clock signal generator receives an oscillator generating a dummy clock signal of a frequency according to the control data, and the dummy clock signal and the multiphase clock signal, and adjusts the control data such that the frequencies thereof coincide. And calibration logic circuitry.

  The calibration logic circuit includes a frequency divider for dividing each of the dummy clock signal and the output clock signal of the clock data recovery circuit, a first counter for counting the dummy clock signal after dividing, and an output clock signal after dividing. According to the first count value and the second count value when one of the second counter for counting the first count value of the first counter and the second count value of the second counter reaches a predetermined first value And a control data adjuster that increases and decreases control data.

  The control data adjuster may increase or decrease the control data according to the magnitude relationship between the first count value and the second count value.

  The control data adjuster may increase or decrease the control data in steps of a predetermined second value.

  The predetermined first value and the predetermined second value may be settable.

  The control data adjuster may increase or decrease the control data according to the difference between the first count value and the second count value.

  Another aspect of the invention relates to a timing controller. The timing controller comprises any of the clock data recovery circuits described above.

  Another aspect of the present invention relates to an electronic device. The electronic device may comprise a timing controller.

  A combination of any of the above components or a conversion of the expression of the present invention among methods, apparatuses, etc. is also effective as an aspect of the present invention.

  According to an aspect of the present invention, a clock signal can be regenerated in a short time.

FIG. 2 is a block diagram showing a configuration of a CDR circuit according to an embodiment. It is a time chart which shows the timing of each signal in the CDR circuit of FIG. FIG. 6 is an operation waveform diagram of the CDR circuit of FIG. 1; FIGS. 4A and 4B are circuit diagrams showing configuration examples of the dummy clock signal generator. It is a circuit diagram which shows the structure of the phase comparator of FIG. 6 (a) and 6 (b) are time charts showing the operation of the phase comparator of FIG. FIGS. 7A and 7B are time charts showing the operation of the phase comparator shown in FIG. It is a block diagram of electronic equipment provided with CDR circuitry.

  Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and duplicating descriptions will be omitted as appropriate. In addition, the embodiments do not limit the invention and are merely examples, and all the features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In the present specification, “the state in which the member A is connected to the member B” means that the members A and B are electrically, in addition to the case where the members A and B are directly physically connected. It also includes the case of indirect connection via other members that do not affect the connection state.
Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, or the electric member It also includes the case of indirect connection via other members that do not affect the connection state.

  FIG. 1 is a block diagram showing the configuration of a CDR circuit 100 according to the embodiment. The CDR circuit 100 includes a phase comparator 10, a frequency comparator 20, a selector 30, a charge pump circuit 40, a loop filter 50, a voltage controlled oscillator (VCO) 60, and a serial / parallel converter 70 as its basic configuration.

CDR circuit 100 receives serial type differential input data D _IN +, D _IN − (hereinafter, referred to simply as input data D _{IN as} needed). A clock signal is embedded in the input data D _IN . CDR circuit 100 extracts and reproducing clock signal from the input data D _IN, by utilizing the clock signal reproduced captures the value of the input data D _IN. The input data D _IN is inputted intermittently.

  CDR circuit 100 regenerates four-phase clock signals CK1 to CK4 (hereinafter collectively referred to as multi-phase clock signal CKm) having a frequency of 1/2 the data rate. The phases of the four-phase clock signals CK1 to CK4 are shifted by 1⁄4 cycle (90 degrees). The four-phase clock signals CK1 to CK4 are generated by a so-called PLL circuit.

The phase comparator 10 uses the first clock signal CK1 and the third clock signal CK3 whose phases are mutually shifted by 180 degrees among the four phase clock signals CK1 to CK4, and generates two phase clock signals per cycle of the clock signal. Data D _OUT 1 and D _OUT 2 are acquired. Specifically, the value of the input data D _IN is latched at the positive edge timing of the first clock signal CK1, and the value is set as data D _OUT 1 and the input data D _IN at the positive edge timing of the third clock signal CK3. Latch the value of D.sub.OUT as data _D.sub.OUT2 . The data D _OUT 1 and D _OUT 2 are supplied to the subsequent serial-to-parallel converter 70. FIG. 2 is a timing chart showing the timing of each signal in the CDR circuit 100 of FIG.

Serial-to-parallel converter 70 receives serial data D _OUT 1 and D _OUT 2 and clock signals CK 1 and CK 3 synchronized therewith, and synchronizes serial data D _OUT 1 and D _OUT 2 to output parallel data D _OUT . Convert. Serial-parallel converter 70, the output parallel data _{D OUT,} the same output to the subsequent processing blocks the clock signal _{CK OUT} synchronized.

  The configuration related to extraction and reproduction of the clock signals CK1 to CK4 in the CDR circuit 100 will be described below.

The phase comparator 10, the charge pump circuit 40, the loop filter 50, and the VCO 60 form a so-called PLL (Phase Locked Loop) circuit. The frequency fm of the clock signals CK1 to CK4 and the timing of the edge of the second clock signal CK2 and the timing of the edge of the fourth clock signal CK4 coincide with the change point of the input data D _IN by this PLL circuit. The phase is feedback controlled.

  The VCO 60 oscillates at a frequency fm according to the input control voltage Vcnt2. The VCO 60 generates four phase clock signals CK1 to CK4. For example, the VCO 60 is a ring oscillator in which four delay elements are connected in a ring. Each delay element is biased by the control voltage Vcnt2, and the delay amount of each is controlled by the control voltage Vcnt2. As a result, the oscillation frequency fm of the ring oscillator corresponds to the control voltage Vcnt2. The four-phase clock signals CK1 to CK4 correspond to input signals (or output signals) of four delay elements.

The phase comparator 10 receives the input data D _IN and the clock signals CK1 to CK4. The phase comparator 10 compares the phase of the input data D _{IN with} the phase of each of the clock signals CK1 to CK4, and generates an up signal UP_A and a down signal DN_A. The up signal UP_A and the down signal DN_A are collectively referred to as a phase difference signal PD_A.

When the phase of the clock signal CK is delayed with respect to the input data D _IN , the up signal UP_A is asserted (high level), and when the phase of the clock signal CK is advanced with respect to the input data D _IN , the down signal DN_A Is asserted.

  The phase difference signal PD_A is input to the charge pump circuit 40 through the selector 30. The charge pump circuit 40 increases the control voltage Vcnt1 when the up signal UP_A is asserted, and decreases the control voltage Vcnt1 when the down signal DN_A is asserted. The loop filter 50 is a lag lead filter, and adjusts the high frequency component of the control voltage Vcnt1 to generate a control voltage Vcnt2. A low pass filter may be used as the loop filter 50.

  The configuration of charge pump circuit 40 is not limited, but includes, for example, a capacitor, a charging circuit for charging the capacitor in response to up signal UP_A, and a discharging circuit for discharging the capacitor in response to down signal DN_A. Be done. The control voltage Vcnt2 is output to the VCO 60.

When the up signal UP_A is asserted after the phase of the clock signal CK is delayed, the control voltage Vcnt2 rises, so that the frequency fm of the multiphase clock signal CKm becomes high, and feedback is applied so that the phase advances. On the contrary, when the phase of the multiphase clock signal CKm advances and the down signal DN_A is asserted, the control voltage Vcnt2 decreases, so that the frequency fm of the multiphase clock signal CKm decreases and feedback is applied to delay the phase. As a result, the frequency fm and the phase of the multiphase clock signal are optimized on the basis of the change point (edge) of the input data D _IN .

  In addition to the PLL circuit described above, the CDR circuit 100 includes a frequency comparator 20, a charge pump circuit 40, a loop filter 50, and an FLL (Frequency Locked Loop) circuit formed by the VCO 60.

Period of the clock signal CK2 and CK4 by FLL circuit (i.e. frequency fm) is the frequency fm and the phase of the clock signal CK1~CK4 to match the data period Td of the input data _{D IN} (ie the input frequency _{f IN)} feedback control Be done.

The first comparator CMP1 compares the input data D _IN + and D _IN − to generate a reference signal Ref. The second comparator CMP2 compares the clock signals CK2 and CK4 to generate a Vco signal. Frequency comparator 20 compares the reference signal Ref and Vco signal to generate a frequency difference signal PFD corresponding to the frequency difference. Frequency difference signal PFD indicates whether against frequency of the reference signal Ref, small or the frequency of the Vco signal is large. The frequency difference signal PFD, similarly to the phase difference signal PD, includes the up signal UP_B and the down signal DN_B. The up signal UP_B is asserted when the frequency of the Vco signal is low , and the down signal DN_B is asserted when the frequency is high .

  The phase frequency difference signal PFD is input to the charge pump circuit 40 through the selector 30. The operations of the charge pump circuit 40, the loop filter 50, and the VCO 60 are as described above. The selector 30 receives the phase difference signal PD and the phase frequency difference signal PFD, and generates a control signal (UP / DN).

By the FLL circuit, the frequency fm of the multiphase clock signal CKm is equal to the input frequency f _IN such that the interval between the positive edge of the clock signal CK2 and the positive edge of the clock signal CK4 matches the cycle of the input data D _IN. The frequencies fm and phases of the multiphase clock signals CK1 to CK4 are feedback controlled so as to coincide with each other.

The above is the basic configuration of the CDR circuit 100. CDR circuit 100 further includes a dummy clock signal generator 80 and a selector 81. Dummy clock signal generator 80 receives substantially the same frequency as frequency fm of the multiphase clock signal during a period in which input data D _IN is input and frequency fm of multiphase clock signal CKm is stabilized. And generates a dummy clock signal CKd. For example, the dummy clock signal generator 80 detects the frequency of the output clock signal CK _OUT as the frequency fm of the multiphase clock signal CKm.

The selector 81 receives the reference signal Ref corresponding to the input data D _IN and the dummy clock signal CKd, selects one of them, and outputs it to the Ref terminal of the frequency comparator 20. The selector 81, in the input state of the input data _{D IN,} selects the output Ref of the first comparator CMP1, in the no-input state of the input data _{D IN,} selects the dummy clock signal CKd. That is, in the non-input state of the input data D _IN , the frequency comparator 20 compares the frequency f d of the dummy clock signal CK d with the frequency f m of the multiphase clock signal CK m instead of the input data D _IN .

The above is the configuration of the dummy clock signal generator 80. Subsequently, the operation will be described.
FIG. 3 is an operation waveform diagram of CDR circuit 100 of FIG. In FIG. 3, CK2 is shown as a representative of multiphase clocks. As shown in FIG. 2, CK2 is a clock signal whose frequency and phase are adjusted so as to have an edge at the transition point of the input data D _IN .

When the input data D _IN is input at time t0, the selector 81 selects the Ref signal, and feedback is applied so that the frequency of the Ref signal and the frequency of the Vco signal corresponding to the multiphase clock signal match. Also, in parallel with that, the phase of each of the plurality of clock signals CK1 to CK4 is adjusted to be appropriately positioned with respect to the change point of the input data D _IN .

While the frequency of the multiphase clock signal is stable, a calibration period CAL is provided. In this calibration period CAL, the frequency of the output clock CK _OUT according to the multiphase clock signal is detected, and a dummy clock signal CKd having a frequency substantially the same as the frequency is generated.

At time t1, the input data D _IN is not input. Then, the selector 81 selects the dummy clock signal CKd instead of the Ref signal. Thus, the frequency of the Vco signal is maintained at the frequency of the dummy clock signal CKd, that is, the frequency of the input data D _IN by the FLL circuit including the frequency comparator 20, the selector 30, the charge pump circuit 40, the loop filter 50, and the VCO 60. Be done.

At time t2, when the input data D _IN is input again, the selector 81 selects the Ref signal again. Since the FLL circuit is operated using the Vco signal and the dummy clock signal CKd from time t1 to t2, the frequency of the Ref signal and the frequency of the Vco signal at time t2 can be substantially the same. After time t2, the phase of the multiphase clock signal is corrected based on the phase of the input data D _IN by the PLL circuit including the phase comparator 10.

The above is the operation of the CDR circuit 100.
In the CDR circuit 100, in the non-input state of the input data D _IN , the frequency lock loop continues to operate using the dummy clock signal CKd. Thus, when the input data D _IN is resumed, the frequency of the input data D _IN can be substantially matched with the frequency of the multiphase clock signal. As a result, the time required to adjust the frequency is shortened, and as soon as the phase adjustment is completed, serial data included in the input data D _IN can be obtained.

More specifically, in the non-input state of the input data D _IN , the control voltage Vcnt2 is kept close to the voltage level of the input data D _{IN in} the input state by continuing the operation of the frequency lock loop using the dummy clock signal CKd. Can be maintained. As a result, when the input data D _IN is input again, the time until the control voltage Vcnt2 returns to the original voltage level can be shortened, and the PLL circuit and the FLL circuit can be locked in a short time.

  Further, since the CDR circuit 100 can be operated at a lower speed as compared with the oversampling method, it is advantageous in terms of power consumption and also has the advantage that an external oscillator is not required.

  The present invention extends to various circuits understood from the block diagram of FIG. 1 and the above description, and is not limited to a specific circuit configuration, but the specific configuration example will be described below.

FIGS. 4A and 4B are circuit diagrams showing configuration examples of the dummy clock signal generator 80. FIG. The dummy clock signal generator 80 includes an oscillator 82 and a calibration logic circuit 84. Oscillator 82 generates a dummy clock signal CKd having a frequency corresponding to the control data _{D CNT.} The calibration logic circuit 84 receives the dummy clock signal CKd and the output clock signal CK _OUT, and adjusts the control data D _CNT so that their frequencies fd and fm coincide with each other.

The calibration logic circuit 84 of FIG. 4B includes a frequency divider 86, a first counter 88, a second counter 90, and a control data adjuster 92. The frequency divider 86 divides each of the dummy clock signal CKd and the output clock signal CK _OUT of the CDR circuit 100 by 1 / n. The first counter 88 counts the frequency-divided dummy clock signal CKd ′. The second counter 90 counts the divided output clock signal CK _OUT '.

The control data adjuster 92 receives the first count value OSC_COUNT of the first counter 88 and the second count value LS_COUNT of the second counter 90. The control data adjuster 92 sets the first count value OSC_COUNT and the second count value LS_COUNT when one of them (in the present embodiment, the second count value LS_COUNT) reaches a predetermined first value X (for example, 1024). In response, the control data _DCNT is increased or decreased.

For example, the control data adjuster 92 according to the magnitude relationship between the first count value OSC_COUNT a second count value LS_COUNT, increases or decreases the control data _{D CNT.} That is, if LS_COUNT> OSC_COUNT, the control data D _CNT is increased and the frequency of the dummy clock signal CKd is increased. If LS_COUNT <OSC_COUNT Conversely, reducing the control data _{D CNT,} to lower the frequency of the dummy clock signal CKd.

The control data adjuster 92 may increase or decrease the control data D _CNT in steps of a predetermined second value Y. Preferably, the first value X and the second value Y can be set externally using a register or the like.

According to the dummy clock signal generator 80, the frequency fm of the multiphase clock signal CKm is measured using the output clock signal CK _OUT, and the dummy clock signal CKd having substantially the same frequency can be generated. it can.

Control data adjuster 92, the first count value OSC_COUNT and according to the difference of the second count value LS_COUNT, may be increased or decreased control data _{D CNT.} That is, the larger the difference is, the larger the increase / decrease step of the control data D _CNT may be.

  Subsequently, a specific configuration of the phase comparator 10 will be described. FIG. 5 is a circuit diagram showing a configuration of phase comparator 10 of FIG. The phase comparator 10 includes flip flops FF1 to FF4, buffers BUF1 to BUF4, and a decoder circuit 12.

The plurality of flip flops FF1 to FF4 are provided for each of the clock signals CK1 to CK4. The i-th flip-flop FFi (1 ≦ i ≦ 4) compares the input signals D _IN + and D _IN − (single-end conversion), and indicates data indicating the comparison result as the timing of the positive edge of the corresponding clock signal CKi. To latch. This flip flop is also referred to as a sense amplifier (SA).

Data q1 latched by the flip-flop FF1 is outputted as data _{D OUT} 1 through the buffer BUF1. Data q2 latched by the flip-flop FF2 similarly is output as data _{D OUT} 2 through the buffer BUF2.

  The data q1 to q4 generated by the flip flops FF1 to FF4 are input to the decoder circuit 12 of the subsequent stage through the buffers BUF1 to BUF4. The decoder circuit 12 generates a phase difference signal PD_A (up signal UP_A, down signal DN_A) based on the data q1 to q4.

  The decoder circuit 12 includes a plurality of first logic gates G1, a plurality of second logic gates G2, a third logic gate G3, and a fourth logic gate G4.

The plurality of first logic gates G1 ₁ and G1 ₂ are provided for each of the odd-numbered flip flops FF1 and FF3. When the number of phases is larger than 4, FF1, FF3, FF5,... Are grasped as odd-numbered flip flops. In other words, the odd-numbered flip-flops refer to flip-flops corresponding to clock signals for latching the data D _OUT 1 and D _OUT 2 and flip-flops alternately arranged therewith.

The i-th (i is a natural number) -th first logic gate G1 _i is the output of the (2 × i−1) -th flip flop FF _{2 × i−1} and the (2 × i) -th flip flop FF _{2 × i} It is configured to generate an internal up signal upi which is asserted (high level) when there is a mismatch between the output and the output.

The plurality of second logic gates G2 ₁ and G2 ₂ are provided for each of the even-numbered flip-flops FF2 and FF4. When the number of phases is larger than 4, FF2, FF4, FF6,... Are grasped as even-numbered flip-flops.

When the j (j is an even number) second logic gate G2 _j does not match the output of the (2 × j) th flip flop FF (2 × j) and the output of the (2 × j + 1) th flip flop It is configured to generate an asserted internal down signal dni.

  For example, the first logic gate G1 and the second logic gate G2 can be configured using an exclusive OR gate EOR.

Specifically, the logic gate EOR0 (G1 ₁ ) compares the data q1 with the data q2 and generates an internal up signal up1 indicating coincidence or noncoincidence. The logic gate EOR1 (G2 ₁ ) compares the data q2 with the data q3 and generates an internal down signal dn1 indicating coincidence or non-coincidence. The logic gate EOR2 (G2 ₂ ) compares the data q4 with the data q1 and generates an internal down signal dn2 indicating coincidence or non-coincidence. Logic gate EOR 3 (G1 ₂₎ compares the data q3 and data q4, matching, and generates an internal up signal up2 indicating a mismatch. The outputs of the logic gates EOR0 to EOR3 become 0 (low level) when the respective two input signals coincide, and become 1 (high level) when they do not coincide.

Third logic gate G3 (AND0) is based on the plurality of first logic gates _G1 1, G1 plurality of internal-up signal generated by the ₂ up1, up2, it generates an up signal UP_A. Specifically, the third logic gate G3 is an AND gate, and asserts the up signal UP_A when all the internal up signals up1 to up2 are asserted.

Fourth logic gate G4 (AND1) is an AND gate, based on the plurality of internal down signals generated by the plurality of second logic gates _G2 1, G2 ₂ dn1, dn2, and generates a down signal DN_A. Specifically, the fourth logic gate G4 is an AND gate, and asserts the down signal DN_A when all the internal down signals dn1 and dn2 are asserted.

The above is the configuration of the phase comparator 10. Subsequently, the operation of the phase comparator 10 will be described. FIGS. 6A and 6B and FIGS. 7A and 7B are time charts showing the operation of the phase comparator 10 of FIG. In FIGS. 6A and 6B, when the input data D _IN changes once, and when the input data D _IN changes twice in a row, each of FIGS. 7A and 7B shows that the input data D _IN is three. The figure shows the operation in the case of two non-continuous changes, in the case of continuous changes.

As shown in FIG. _6A , when the input data D _IN changes once, if the phase of the input data D _IN is advanced, an up signal having a length of one section (1⁄4 cycle of the clock signal) If UP_A is generated and the phase of the input data D _IN is delayed, a down signal DN_A having a length of one period (1⁄4 period of the clock signal) is generated.

Referring to FIG. 6 (b), when the input data D _IN is changed twice in succession, if advances the phase of the input data D _IN, up the length of the three sections (3/4 period of the clock signal) If the signal UP_A is generated and the phase of the input data D _IN is delayed, a down signal DN_A having a length of three sections (3⁄4 cycle of the clock signal) is generated.

Referring to FIG. 7 (a), when the input data D _IN is changed three times in a row, if advances the phase of the input data D _IN, length up of five sections (5/4 period of the clock signal) If the signal UP_A is generated and the phase of the input data D _IN is delayed, a down signal DN_A having a length of 5 sections (5/4 periods of the clock signal) is generated.

Referring to FIG. 7B, when the input data D _IN changes discontinuously, it can be seen that the same operation as that in the case of one change of FIG. 6A is repeated twice.

As described above, according to the phase comparator 10 according to the embodiment, it is possible to generate the up signal UP_A and the down signal DN_A that are asserted for a period corresponding to the number of times the input data D _IN changes continuously. .

The phase comparator 10 is characterized in that the delay is small since the timing synchronization is not taken in the process of generating the up signal UP_A and the down signal DN_A. Therefore, the phase of the clock signal can quickly follow the fluctuation of the input data D _IN .

  Further, it is also an advantage of the phase comparator 10 of FIG. 5 that the minimum width of the assert period of the down signal DN and the up signal UP is one section (1⁄4 period of the clock signal, 90 degrees phase). That is, since the minimum widths of the down signal DN_A and the up signal UP_A are small, the degree of freedom in design of the charge pump circuit 40 can be increased.

In general, charge pump circuit 40 includes a capacitor, a charging circuit that charges the capacitor according to up signal UP, and a discharge circuit that discharges the capacitor according to down signal DN. Then, the voltage generated in the capacitor is output as the control voltage Vcnt1.
Therefore, change amount ΔV of control voltage Vcnt1 is
ΔV = τ × Ichg / C
Given by In other words,
(1) Proportional to the pulse width τ of the up signal UP and the down signal DN,
(2) Proportional to charge / discharge current Ichg,
(3) Inversely proportional to the capacitance value C of the capacitor.

  Therefore, in order to obtain the same change amount ΔV of the control voltage Vcnt1, the charge / discharge current Ichg can be increased or the capacitance value C of the capacitor can be decreased by shortening the pulse width. Since the small capacitor C means that the circuit area can be reduced, it is extremely useful for circuit integration. Further, the ability to increase the charge / discharge current Ichg means that the accuracy thereof can be enhanced, and therefore, it is very useful in enhancing the accuracy of the frequency stabilization of the CDR circuit 100.

  Finally, the application of the CDR circuit 100 will be described. The CDR circuit 100 can be used for the timing controller 204. FIG. 8 is a block diagram of an electronic device 200 including the CDR circuit 100. The electronic device 200 includes an image processor 202, a timing controller 204, a display panel 206, a gate driver 208, and a source driver 210.

The timing controller 204 includes the CDR circuit 100 described above and a frame memory 205. Image data D _IN is transmitted from the image processor 202 to the timing controller 204 in a format compliant with the eDP standard or other standards. For example, the image data D _IN is transmitted as 24-bit serial data of 3 bits each for RGB. The image processor 202 is a graphics processing unit (GPU), an application processor, or a central processing unit (CPU).

CDR circuit 100 receives image data D _IN from image processor 202. The timing controller 204 generates various timing signals based on the data D _IN received by the CDR circuit 100. The gate driver 208 sequentially selects the scanning lines of the display panel 206 in synchronization with the timing signal from the source driver 210. The source driver 210 applies a drive voltage corresponding to the luminance data from the timing controller 204 to the data line of the display panel 206.

  In the electronic device 200, a function called panel self refresh (PSR) may be implemented. In panel self refresh, when displaying a still image, transmission of image data from the image processor 202 to the timing controller 204 is stopped, and display is performed based on the data stored in the frame memory 205 of the timing controller 204. An image is displayed on the panel 206. Therefore, when the panel self-refresh function is set to active, CDR circuit 100 holds the received image data in frame memory 205, and when there is no input from image processor 202, image data in frame memory 205 is displayed. Displayed on the panel 206.

When the panel self refresh function is supported, the input data D _IN from the image processor 202 to the CDR circuit 100 is generated intermittently. The CDR circuit 100 according to the embodiment can be suitably used for such an application.

In this application, when the input data D _IN is input, the CDR circuit 100 may update the frequency of the dummy clock signal CKd by providing the calibration period CAL once per frame.

In the panel self refresh, a control signal for notifying stop of the input data D _IN is supplied from the image processor 202 to the timing controller 204. Therefore, the timing controller 204 can control the selector 81 based on this control signal.

  The embodiment is an exemplification, and it is understood by those skilled in the art that various modifications can be made to the combination of each component and each processing process, and such modifications are also within the scope of the present invention. . Hereinafter, such modified examples will be described.

(First modification)
Although the embodiment has been described by way of example in which the 4-phase clock signal is regenerated, the technical idea disclosed in the embodiment can also be expanded to 8-phase, 16-phase and other clock signals, It is understood by those skilled in the art that they are also included in the scope of the present invention.

(2nd modification)
In the embodiment, the timing controller is described as an application of the CDR circuit 100, but the present invention is not limited thereto. For example, the CDR circuit 100 is available to a bridge chip. Bridge chips are used to bridge different interface standards. For example, an input interface of a bridge chip that converts image data compliant with the eDP standard into serial data of the CMOS format and outputs it, and a bridge converts image data compliant with the eDP standard into serial data of the LVDS format and outputs them The CDR circuit 100 can be used for the input interface of the chip.

(Third modification)
Although the dummy clock signal generator 80 of FIG. 4 detects the frequency fm of the multiphase clock signal CKm using the output clock signal CK _OUT , the present invention is not limited thereto. The calibration logic circuit 84 may receive the output Ref of the comparator CMP1 instead of the output clock signal CK _OUT , may receive the Vco signal which is the output of CMP2, or a plurality of clock signals. One of CK1 to CK4 may be input.

  While the present invention has been described using specific terms based on the embodiments, the embodiments merely show the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement can be made without departing from the concept of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Phase comparator, 12 ... Decoder circuit, 20 ... Frequency comparator, 30 ... Selector, 40 ... Charge pump circuit, 50 ... Loop filter, 60 ... VCO, 70 ... Serial parallel converter, 80 ... Dummy clock signal generator , 81: selector, 82: oscillator, 84: calibration logic circuit, 86: frequency divider, 88: first counter, 90: second counter, 92: control data adjuster, 100: CDR circuit, 200: electronic device, 202 ... image processor, 204 ... timing controller, 205 ... frame memory, 206 ... display panel, 208 ... gate driver, 210 ... source driver.

Claims (10)

A voltage controlled oscillator generating a multiphase clock signal including a plurality of clock signals having a frequency corresponding to the control voltage and shifted in phase with each other at equal intervals;
A phase comparator which compares the phase of input data with the phase of each of the plurality of clock signals and generates a phase difference signal indicating the comparison result;
A frequency comparator that compares the frequency of the input data with the frequency of the multiphase clock signal and generates a frequency difference signal indicating a comparison result;
A charge pump circuit generating the control voltage whose voltage level is adjusted according to the phase difference signal and the frequency difference signal;
A dummy clock signal generator that generates a dummy clock signal having substantially the same frequency as the frequency during a period in which the frequency of the multiphase clock signal is stabilized;
Equipped with
When the input data is not input, the dummy clock signal is input only to the frequency comparator , and the frequency comparator substitutes the frequency of the dummy clock signal for the multiphase clock signal instead of the frequency of the input data. A clock data recovery circuit characterized by comparing with the frequency of the clock. The dummy clock signal generator
An oscillator for generating the dummy clock signal of a frequency corresponding to control data;
A calibration logic circuit that receives the dummy clock signal and the multiphase clock signal, and adjusts the control data such that their frequencies match;
The clock data recovery circuit as claimed in claim 1, comprising: The calibration logic circuit
A divider for dividing each of the dummy clock signal and the output clock signal of the clock data recovery circuit;
A first counter that counts the dummy clock signal after frequency division;
A second counter that counts the output clock signal after frequency division;
The control data according to the first count value and the second count value when one of the first count value of the first counter and the second count value of the second counter reaches a predetermined first value Control data adjuster to increase or decrease
The clock data recovery circuit according to claim 2, further comprising:   4. The clock data recovery circuit according to claim 3, wherein the control data adjuster increases or decreases the control data according to a magnitude relationship between the first count value and the second count value.   5. The clock data recovery circuit according to claim 4, wherein the control data adjuster increases or decreases the control data in steps of a predetermined second value.   6. The clock data recovery circuit according to claim 5, wherein the predetermined first value and the predetermined second value are settable.   4. The clock data recovery circuit according to claim 3, wherein the control data adjuster increases or decreases the control data according to a difference between the first count value and the second count value.   A timing controller comprising the clock data recovery circuit according to any one of claims 1 to 7.   An electronic apparatus comprising the timing controller according to claim 8. Generating a multi-phase clock signal comprising a plurality of clock signals having a frequency corresponding to the control voltage and having phases equidistantly shifted relative to one another;
The phase comparator compares the phase of the input data with the phase of each of the plurality of clock signals and generates a phase difference signal including an up signal and a down signal indicating the comparison result;
The frequency comparator compares the frequency of the input data with the frequency of the multiphase clock signal and generates a frequency difference signal including an up signal and a down signal indicating a comparison result;
A charge pump circuit changes the control voltage such that the frequency of the voltage controlled oscillator increases when the up signal of the phase difference signal is asserted or when the up signal of the frequency difference signal is asserted. Changing the control voltage such that the frequency of the voltage controlled oscillator is lowered when the down signal of the phase difference signal or the down signal of the frequency difference signal is asserted.
Measuring the frequency during a period in which the frequency of the multiphase clock signal is stabilized, and generating a dummy clock signal having the measured frequency;
The step of inputting the dummy clock signal instead of the input data to the frequency comparator in the non-input state of the input data, and not inputting the dummy clock signal to the phase comparator ;
A clock data recovery method comprising:

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