JP2016116126A - Clock data recovery circuit, timing controller, electronic equipment, and clock data recovery method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL-system CDR circuit capable of regenerating a clock in a short time.SOLUTION: A VCO 60 generates a plurality of clock signals CK1 to CK4 (multi-phase clock signal CKm) having a frequency fm according to control voltage Vcnt2. A phase comparator 10 compares a phase of input data Dwith a phase of each of the plurality of clock signals CK1 to CK4. A frequency comparator 20 compares a frequency fof the input data Dwith the frequency fm of the multi-phase clock signal CKm. A charge pump circuit 40 adjusts the control voltage Vcnt2 according to a phase difference signal PD and a phase frequency difference signal PFD. A dummy clock signal generator 80 generates a dummy clock signal CKd having substantially the same frequency as the frequency fm during the period during which the frequency fm is stable. In a state in which the input data Dis not input, the frequency comparator 20 compares a frequency fd of the dummy clock signal CKd with the frequency fm of the multi-phase clock signal CKm.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a CDR (Clock Data Recovery) circuit.

  Serial data transmission is used to transmit and receive data between semiconductor integrated circuits via a small number of data transmission lines. The serial data signal is received by latching each bit data of the serial data at the timing of the clock signal synchronized therewith.

  Here, a clock signal may be embedded in the serial data signal. In this case, the change point of the serial data signal is monitored by the CDR circuit, the clock signal is reproduced based on the detected change point, and the serial data signal is latched by the reproduced clock signal. Patent Documents 1 to 3 disclose related technologies.

JP 2005-5999 A JP 2003-204319 A JP 2011-120106 A International Publication No. 14/045551 A1 Pamphlet

  There are various types of CDR circuits. A typical example is a CDR circuit using a PLL (Phase Locked Loop) circuit. When the PLL system CDR circuit is used in an application in which input data is intermittently input, the PLL circuit is unlocked every time the input data is not input. Therefore, every time input data is restarted, there is a problem that a delay occurs until the PLL circuit is locked.

  This problem can be solved by using an oversampling CDR circuit (see Patent Document 4). In the oversampling method, data is captured by a high-speed clock signal that is about three times the frequency of input data (input frequency), the clock signal is reproduced by logic processing, and data is extracted. An oversampling CDR circuit is suitable for applications in which input data is intermittently supplied because there is no delay due to phase locking. However, the operating frequency is higher than that of a PLL type CDR circuit, and power consumption is increased. The problem that becomes large arises. In addition, a semiconductor manufacturing process for manufacturing a device capable of high-speed operation is required, which causes an increase in cost. Furthermore, the accuracy of the recovered clock signal is easily affected by the accuracy of the high-speed clock signal, and the cost increases when an external crystal oscillator is used to stabilize the frequency.

  SUMMARY An advantage of some aspects of the invention is to provide a PLL type CDR circuit that can regenerate a clock in a short time.

  One embodiment of the present invention relates to a clock data recovery circuit. The clock data recovery circuit has a frequency according to a control voltage, a voltage controlled oscillator that generates a multiphase clock signal including a plurality of clock signals whose phases are shifted at equal intervals, and a phase of input data, A phase comparator that compares the phase of each clock signal and generates a phase difference signal indicating the comparison result, and a phase frequency difference signal that compares the frequency of the input data with the frequency of the multiphase clock signal and indicates the comparison result A frequency comparator that generates a voltage difference, a charge pump circuit that generates a control voltage whose voltage level is adjusted according to the phase difference signal and the phase frequency difference signal, and a frequency phase of the multiphase clock signal that is stabilized A dummy clock signal generator for generating a dummy clock signal having a frequency substantially the same as the frequency. In the non-input state of input data, the frequency comparator compares the frequency of the dummy clock signal with the frequency of the multiphase clock signal instead of the frequency of the input data.

  According to this aspect, when the input data is not input, the frequency lock loop is continuously operated using the dummy clock signal, so that when the input data is resumed, the frequency of the input data and the frequency of the multiphase clock signal are substantially reduced. Can match. As a result, the time required for frequency adjustment is shortened, and when phase adjustment is completed, serial data included in the input data can be immediately acquired.

  The dummy clock signal generator receives an oscillator that generates a dummy clock signal having a frequency corresponding to the control data, the dummy clock signal and the multiphase clock signal, and adjusts the control data so that the frequencies coincide with each other. And a calibration logic circuit.

  The calibration logic circuit includes a frequency divider that divides each of the dummy clock signal and the output clock signal of the clock data recovery circuit, a first counter that counts the divided dummy clock signal, and an output clock signal after the division According to the first count value and the second count value when one of the first count value of the first counter and the second count value of the second counter reaches the predetermined first value. And a control data adjuster for increasing / decreasing the control data.

  The control data adjuster may increase or decrease the control data according to the magnitude relationship between the first count value and the second count value.

  The control data adjuster may increase or decrease the control data in steps of a predetermined second value.

  The predetermined first value and the predetermined second value may be settable.

  The control data adjuster may increase or decrease the control data according to the difference between the first count value and the second count value.

  Another aspect of the present invention relates to a timing controller. The timing controller includes any one of the clock data recovery circuits described above.

  Another embodiment of the present invention relates to an electronic device. The electronic device may include a timing controller.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  According to an aspect of the present invention, a clock signal can be reproduced in a short time.

It is a block diagram which shows the structure of the CDR circuit which concerns on embodiment. 2 is a time chart showing timing of each signal in the CDR circuit of FIG. 1. FIG. 2 is an operation waveform diagram of the CDR circuit of FIG. 1. 4A and 4B are circuit diagrams showing a configuration example of the dummy clock signal generator. It is a circuit diagram which shows the structure of the phase comparator of FIG. 6A and 6B are time charts showing the operation of the phase comparator of FIG. 7A and 7B are time charts showing the operation of the phase comparator of FIG. It is a block diagram of an electronic device provided with a CDR circuit.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 1 is a block diagram showing a configuration of a CDR circuit 100 according to the embodiment. The CDR circuit 100 includes a phase comparator 10, a frequency comparator 20, a selector 30, a charge pump circuit 40, a loop filter 50, a VCO (Voltage Controlled Oscillator) 60, and a serial / parallel converter 70 as its basic configuration.

The CDR circuit 100 receives serial-type differential input data D _IN + and D _IN − (hereinafter simply referred to as input data D _IN as necessary). A clock signal is embedded in the input data _DIN . CDR circuit 100 extracts and reproducing clock signal from the input data D _IN, by utilizing the clock signal reproduced captures the value of the input data D _IN. The input data _DIN is input intermittently.

  The CDR circuit 100 reproduces four-phase clock signals CK1 to CK4 (hereinafter collectively referred to as a multiphase clock signal CKm) having a frequency that is ½ of the data rate. The phases of the four-phase clock signals CK1 to CK4 are shifted from each other by 1/4 period (90 degrees). The four-phase clock signals CK1 to CK4 are generated by a so-called PLL circuit.

The phase comparator 10 uses the first clock signal CK1 and the third clock signal CK3 whose phases are shifted from each other by 180 degrees among the four-phase clock signals CK1 to CK4. Data D _OUT 1 and D _OUT 2 are acquired. Specifically, the value of the input data D _IN at the timing of the positive edge of the first clock signal CK1 latches, its value as data D _{OUT 1,} the input data D _IN at the timing of the positive edge of the third clock signal CK3 Is latched, and the value is used as data D _OUT 2. The data D _OUT 1 and D _OUT 2 are supplied to the subsequent serial-parallel converter 70. FIG. 2 is a time chart showing the timing of each signal in the CDR circuit 100 of FIG.

The serial / parallel converter 70 receives the serial data D _OUT 1 and D _OUT 2 and the clock signals CK 1 and CK 3 synchronized therewith, and synchronizes the timing of the serial data D _OUT 1 and D _OUT 2 to the output parallel data D _OUT . Convert. The serial / parallel converter 70 outputs the output parallel data D _OUT to the subsequent processing block together with the clock signal CK _OUT synchronized therewith.

  Hereinafter, a configuration related to extraction and reproduction of the clock signals CK1 to CK4 in the CDR circuit 100 will be described.

The phase comparator 10, the charge pump circuit 40, the loop filter 50, and the VCO 60 form a so-called PLL (Phase Locked Loop) circuit. This PLL circuit, and the timing of an edge of the second clock signal CK2, so that the timing of the edge of the fourth clock signal CK4, respectively, consistent with the change point of the input data _{D IN,} frequency fm and the clock signal CK1~CK4 The phase is feedback controlled.

  The VCO 60 oscillates at a frequency fm according to the input control voltage Vcnt2. The VCO 60 generates four-phase clock signals CK1 to CK4. For example, the VCO 60 is a ring oscillator in which four stages of delay elements are connected in a ring shape. Each delay element is biased by the control voltage Vcnt2, and the delay amount is controlled by the control voltage Vcnt2. As a result, the oscillation frequency fm of the ring oscillator corresponds to the control voltage Vcnt2. The four-phase clock signals CK1 to CK4 correspond to input signals (or output signals) of the four delay elements.

The phase comparator 10 receives input data _{D IN} and the clock signal CK1 to CK4. The phase comparator 10, the phase of the input data _{D IN} in comparison with the clock signal CK1~CK4 respective phases, the up signal UP_A, generates a down signal DN_A. The up signal UP_A and the down signal DN_A are also collectively referred to as a phase difference signal PD_A.

When the phase of the clock signal CK is delayed with respect to the input data _{D IN} is up signal UP_A is asserted (high level), when the phase of the clock signal CK is advanced with respect to the input data _{D IN} is down signal DN_A Is asserted.

  The phase difference signal PD_A is input to the charge pump circuit 40 via the selector 30. The charge pump circuit 40 increases the control voltage Vcnt1 when the up signal UP_A is asserted, and decreases the control voltage Vcnt1 when the down signal DN_A is asserted. The loop filter 50 is a lag lead filter, and adjusts a high frequency component of the control voltage Vcnt1 to generate a control voltage Vcnt2. A low pass filter may be used as the loop filter 50.

  The configuration of the charge pump circuit 40 is not limited, and includes, for example, a capacitor, a charging circuit that charges the capacitor in response to the up signal UP_A, and a discharging circuit that discharges the capacitor in response to the down signal DN_A. Is done. The control voltage Vcnt2 is output to the VCO 60.

When the phase of the clock signal CK is delayed and the up signal UP_A is asserted, the control voltage Vcnt2 rises, so that the frequency fm of the multiphase clock signal CKm increases, and feedback is applied so that the phase advances. On the other hand, when the phase of the multiphase clock signal CKm advances and the down signal DN_A is asserted, the control voltage Vcnt2 decreases, so that the frequency fm of the multiphase clock signal CKm is lowered and feedback is applied so that the phase is delayed. As a result, the frequency fm and phase of the multiphase clock signal are optimized with reference to the changing point (edge) of the input data _DIN .

  In addition to the PLL circuit described above, the CDR circuit 100 includes a frequency locked loop (FLL) circuit formed by the frequency comparator 20, the charge pump circuit 40, the loop filter 50, and the VCO 60.

Period of the clock signal CK2 and CK4 by FLL circuit (i.e. frequency fm) is the frequency fm and the phase of the clock signal CK1~CK4 to match the data period Td of the input data _{D IN} (ie the input frequency _{f IN)} feedback control Is done.

The first comparator CMP1 compares the input data D _IN + and D _IN − and generates a reference signal Ref. The second comparator CMP2 compares the clock signals CK2 and CK4 and generates a Vco signal. The frequency comparator 20 compares the reference signal Ref and the Vco signal, and generates a phase frequency difference signal PFD corresponding to the phase difference. The phase frequency difference signal PFD indicates whether the phase of the Vco signal is advanced or delayed with respect to the phase of the reference signal Ref. Similarly to the phase difference signal PD, the phase frequency difference signal PFD includes an up signal UP_B and a down signal DN_B. The up signal UP_B is asserted when the phase of the Vco signal is delayed, and the down signal DN_B is asserted when the phase is advanced.

  The phase frequency difference signal PFD is input to the charge pump circuit 40 through the selector 30. The operations of the charge pump circuit 40, the loop filter 50, and the VCO 60 are as described above. The selector 30 receives the phase difference signal PD and the phase frequency difference signal PFD and generates a control signal (UP / DN).

The FLL circuit, the interval between the positive edge and the positive edge of the clock signal CK4 clock signal CK2, to match the period of the input data _{D IN,} and the frequency fm is the input frequency _{f IN} of the multiphase clock signal CKm other words The frequency fm and the phase of the multiphase clock signals CK1 to CK4 are feedback controlled so as to match.

The above is the basic configuration of the CDR circuit 100. The CDR circuit 100 is further provided with a dummy clock signal generator 80 and a selector 81. Dummy clock signal generator 80, the input data D _IN is inputted, in a period in which the frequency fm of the multiphase clock signal CKm is stabilized, the frequency fm substantially the same frequency of the multiphase clock signal A dummy clock signal CKd having the same is generated. For example, the dummy clock signal generator 80 detects the frequency of the output clock signal CK _OUT as the frequency fm of the multiphase clock signal CKm.

The selector 81 includes a reference signal Ref in accordance with the input data _{D IN,} receives the dummy clock signal CKd, selects and outputs one to the Ref terminal of the frequency comparator 20. The selector 81, in the input state of the input data _{D IN,} selects the output Ref of the first comparator CMP1, in the no-input state of the input data _{D IN,} selects the dummy clock signal CKd. That in the no-input state of the input data _{D IN,} frequency comparator 20, the frequency fd of the dummy clock signal CKd instead of the input data _{D IN,} compared with the frequency fm of the multiphase clock signal CKm.

The above is the configuration of the dummy clock signal generator 80. Next, the operation will be described.
FIG. 3 is an operation waveform diagram of the CDR circuit 100 of FIG. FIG. 3 shows CK2 as a representative multiphase clock. As shown in FIG. 2, CK2 is a transition point of the input data D _IN is a clock signal whose frequency and phase are adjusted so as to have an edge.

When the input data D _IN at time t0 is input, the selector 81, the Ref signal is selected, so that the frequency of the Vco signal corresponding to the frequency and the multiphase clock signal Ref signal matches, the feedback is applied. The parallel thereto, a plurality of clock signals CK1~CK4 each phase is adjusted to be positioned appropriately with respect to the change point of the input data D _IN.

While the frequency of the multiphase clock signal is stable, a calibration period CAL is provided. In this calibration period CAL, the frequency of the output clock CK _OUT corresponding to the multiphase clock signal is detected, and a dummy clock signal CKd having substantially the same frequency as that frequency is generated.

At time t1, the input data _DIN is not input. Then, the selector 81 selects the dummy clock signal CKd instead of the Ref signal. Maintained by this, the frequency comparator 20, a selector 30, a charge pump circuit 40, the FLL circuit including a loop filter 50, VCO 60, the frequency of the Vco signal, the frequency of the dummy clock signal CKd, i.e., the frequency of the input data _{D IN} Is done.

When the input data _DIN is input again at time t2, the selector 81 selects the Ref signal again. Since the FLL circuit is operated using the Vco signal and the dummy clock signal CKd between times t1 and t2, the frequency of the Ref signal and the frequency of the Vco signal at time t2 can be made substantially the same. After time t2, the PLL circuit including a phase comparator 10, the phase of the multiphase clock signal is corrected based on the phase of the input data D _IN.

The above is the operation of the CDR circuit 100.
The CDR circuit 100, in the no-input state of the input data _{D IN,} using the dummy clock signal CKd, continuing to operate the frequency locked loop. Thereby, when the input data _DIN is resumed, the frequency of the input data _{DIN and} the frequency of the multiphase clock signal can be substantially matched. As a result, the time required for frequency adjustment is shortened, and when the phase adjustment is completed, the serial data included in the input data _DIN can be acquired immediately.

More particularly, in the no-input state of the input data D _IN, by continuing to operate the frequency-locked loop using a dummy clock signal CKd, near the voltage level of the control voltage Vcnt2, at the input state of the input data D _IN Can be maintained. Accordingly, upon re-input of the input data D _IN, the control voltage Vcnt2 is be short time until the return to the original voltage level, it is possible to lock the PLL circuit and a FLL circuit in a short time.

  Since the CDR circuit 100 can be operated at a lower speed than the oversampling method, it is advantageous from the viewpoint of power consumption, and also has an advantage that an external oscillator is unnecessary.

  The present invention extends to various circuits grasped from the block diagram of FIG. 1 and the above description, and is not limited to a specific circuit configuration, but a specific configuration example will be described below.

4A and 4B are circuit diagrams showing a configuration example of the dummy clock signal generator 80. FIG. The dummy clock signal generator 80 includes an oscillator 82 and a calibration logic circuit 84. Oscillator 82 generates a dummy clock signal CKd having a frequency corresponding to the control data _{D CNT.} Calibration logic circuit 84 receives the dummy clock signal CKd and the output clock signal _{CK OUT,} and their frequency fd, so fm match, modulating the control data _{D CNT.}

The calibration logic circuit 84 in FIG. 4B includes a frequency divider 86, a first counter 88, a second counter 90, and a control data adjuster 92. The frequency divider 86 divides each of the dummy clock signal CKd and the output clock signal CK _OUT of the CDR circuit 100 by 1 / n. The first counter 88 counts the frequency-divided dummy clock signal CKd ′. The second counter 90 counts the divided output clock signal CK _OUT ′.

The control data adjuster 92 receives the first count value OSC_COUNT of the first counter 88 and the second count value LS_COUNT of the second counter 90. The control data adjuster 92 sets the first count value OSC_COUNT and the second count value LS_COUNT when one of them (second count value LS_COUNT in the present embodiment) reaches a predetermined first value X (for example, 1024). In response, the control data _DCNT is increased or decreased.

For example, the control data adjuster 92 according to the magnitude relationship between the first count value OSC_COUNT a second count value LS_COUNT, increases or decreases the control data _{D CNT.} That is, if the LS_COUNT> OSC_COUNT, increases the control data _{D CNT,} increasing the frequency of the dummy clock signal CKd. If LS_COUNT <OSC_COUNT Conversely, reducing the control data _{D CNT,} to lower the frequency of the dummy clock signal CKd.

Control data adjuster 92, the control data D _CNT may be increased or decreased in steps of a predetermined second value Y. It is preferable that the first value X and the second value Y can be set from the outside using a register or the like.

According to the dummy clock signal generator 80, the frequency fm of the multiphase clock signal CKm is measured using the output clock signal CK _OUT, and the dummy clock signal CKd having substantially the same frequency as that is generated. it can.

Control data adjuster 92, the first count value OSC_COUNT and according to the difference of the second count value LS_COUNT, may be increased or decreased control data _{D CNT.} That is, the increase / decrease step of the control data _DCNT may be increased as the difference is increased.

  Next, a specific configuration of the phase comparator 10 will be described. FIG. 5 is a circuit diagram showing a configuration of the phase comparator 10 of FIG. The phase comparator 10 includes flip-flops FF1 to FF4, buffers BUF1 to BUF4, and a decoder circuit 12.

The plurality of flip-flops FF1 to FF4 are provided for the clock signals CK1 to CK4, respectively. The i-th flip-flop FFi (1 ≦ i ≦ 4) compares the input signals D _IN + and D _IN − (single-end conversion) and uses the data indicating the comparison result as the positive edge timing of the corresponding clock signal CKi. Latch with. This flip-flop is also called a sense amplifier (SA).

The data q1 latched by the flip-flop FF1 is output as data D _OUT 1 via the buffer BUF1. Data q2 latched by the flip-flop FF2 similarly is output as data _{D OUT} 2 through the buffer BUF2.

  Data q1 to q4 generated by the flip-flops FF1 to FF4 are input to the subsequent decoder circuit 12 via the buffers BUF1 to BUF4. The decoder circuit 12 generates a phase difference signal PD_A (up signal UP_A, down signal DN_A) based on the data q1 to q4.

  The decoder circuit 12 includes a plurality of first logic gates G1, a plurality of second logic gates G2, a third logic gate G3, and a fourth logic gate G4.

The plurality of first logic gates G1 ₁ and G1 ₂ are provided for each odd-numbered flip-flop FF1 and FF3. When the number of phases is greater than 4, FF1, FF3, FF5... Are recognized as odd-numbered flip-flops. In other words, the odd-numbered flip-flop means a flip-flop corresponding to a clock signal for latching the data D _OUT 1 and D _OUT 2 and a flip-flop arranged every other one.

The i-th (i is a natural number) first logic gate G1 _i is connected to the output of the (2 × i−1) th flip-flop FF _{2 × i−1} and the (2 × i) th flip-flop FF _{2 × i} . It is configured to generate an internal up signal upi that is asserted (high level) when the output does not match.

The plurality of second logic gates G2 ₁ and G2 ₂ are provided for each even-numbered flip-flop FF2 and FF4. When the number of phases is greater than 4, FF2, FF4, FF6... Are recognized as even-numbered flip-flops.

The j-th (j is an even number) second logic gate G2 _j is when the output of the (2 × j) -th flip-flop FF (2 × j) and the output of the (2 × j + 1) -th flip-flop do not match. It is configured to generate an internal down signal dni that is asserted.

  For example, the first logic gate G1 and the second logic gate G2 can be configured using an exclusive OR gate EOR.

Specifically, the logic gate EOR0 (G1 ₁ ) compares the data q1 and the data q2, and generates an internal up signal up1 indicating a match or mismatch. The logic gate EOR1 (G2 ₁ ) compares the data q2 and the data q3, and generates an internal down signal dn1 indicating a match or mismatch. The logic gate EOR2 (G2 ₂ ) compares the data q4 and the data q1, and generates an internal down signal dn2 indicating a match or mismatch. The logic gate EOR3 (G1 ₂ ) compares the data q3 and the data q4, and generates an internal up signal up2 indicating a match or mismatch. The outputs of the logic gates EOR0 to EOR3 are 0 (low level) when the two input signals match, and 1 (high level) when they do not match.

The third logic gate G3 (AND0) generates the up signal UP_A based on the plurality of internal up signals up1 and up2 generated by the plurality of first logic gates G1 ₁ and G1 ₂ . Specifically, the third logic gate G3 is an AND gate, and asserts the up signal UP_A when all the internal up signals up1 and up2 are asserted.

The fourth logic gate G4 (AND1) is an AND gate, and generates a down signal DN_A based on the plurality of internal down signals dn1 and dn2 generated by the plurality of second logic gates G2 ₁ and G2 ₂ . Specifically, the fourth logic gate G4 is an AND gate, and asserts the down signal DN_A when all the internal down signals dn1 and dn2 are asserted.

The above is the configuration of the phase comparator 10. Next, the operation of the phase comparator 10 will be described. FIGS. 6A and 6B and FIGS. 7A and 7B are time charts showing the operation of the phase comparator 10 of FIG. FIGS. 6A and 6B show the case where the input data D _IN changes once, and the case where the input data D _IN changes 3 times. FIGS. 7A and 7B show that the input data D _IN is 3 In the case of changing continuously, the operation in the case of changing continuously twice is shown.

As shown in FIG. 6 (a), when the input data D _IN is changed once, if advances the phase of the input data D _IN, 1 segment length of up signal (1/4 cycle of the clock signal) UP_A is generated, if the delayed phase of the input data _{D iN} Conversely, the length of the down signal DN_A of one interval (1/4 cycle of the clock signal) is generated.

Referring to FIG. 6 (b), when the input data D _IN is changed twice in succession, if advances the phase of the input data D _IN, up the length of the three sections (3/4 period of the clock signal) signal UP_A is generated, if the delayed phase of the input data _{D iN} Conversely, the length of the down signal DN_A of three sections (3/4 period of the clock signal) is generated.

Referring to FIG. 7 (a), when the input data D _IN is changed three times in a row, if advances the phase of the input data D _IN, length up of five sections (5/4 period of the clock signal) signal UP_A is generated, if the delayed phase of the input data _{D iN} Conversely, the length of the down signal DN_A of five sections (5/4 period of the clock signal) is generated.

Referring to FIG. 7 (b), when the input data D _IN is changed discontinuously can be seen to repeated twice when the same operation as the one change in FIG. 6 (a).

According to the phase comparator 10 according to the thus embodiment, it is possible to generate the input data D _IN is the period asserted in response to the number of times changes continuously, up signal UP_A and the down signal DN_A .

The phase comparator 10 has a feature that the delay is small because timing synchronization is not taken in the process of generating the up signal UP_A and the down signal DN_A. Thus the phase of the clock signal it is possible to quickly follow the fluctuations of the input data D _IN.

  It is also an advantage of the phase comparator 10 in FIG. 5 that the minimum width of the assertion period of the down signal DN and the up signal UP is one section (a quarter period of the clock signal, 90 degrees phase). That is, since the minimum widths of the down signal DN_A and the up signal UP_A are small, the degree of freedom in designing the charge pump circuit 40 can be increased.

Generally, the charge pump circuit 40 includes a capacitor, a charging circuit that charges the capacitor in response to the up signal UP, and a discharging circuit that discharges the capacitor in response to the down signal DN. The voltage generated in the capacitor is output as the control voltage Vcnt1.
Therefore, the change amount ΔV of the control voltage Vcnt1 is
ΔV = τ × Ichg / C
Given in. That means
(1) Proportional to the pulse width τ of the up signal UP and down signal DN,
(2) Proportional to charge / discharge current Ichg,
(3) It is inversely proportional to the capacitance value C of the capacitor.

  Therefore, if the change amount ΔV of the same control voltage Vcnt1 is to be obtained, the charge / discharge current Ichg can be increased or the capacitance value C of the capacitor can be decreased due to the short pulse width. The small capacitor C means that the circuit area can be reduced, which is very useful for circuit integration. In addition, the fact that the charge / discharge current Ichg can be increased means that the accuracy can be increased, which is very useful in increasing the accuracy of frequency stabilization of the CDR circuit 100.

  Finally, the use of the CDR circuit 100 will be described. The CDR circuit 100 can be used for the timing controller 204. FIG. 8 is a block diagram of an electronic device 200 that includes the CDR circuit 100. The electronic device 200 includes an image processor 202, a timing controller 204, a display panel 206, a gate driver 208, and a source driver 210.

The timing controller 204 includes the CDR circuit 100 and the frame memory 205 described above. Image data _DIN is transmitted from the image processor 202 to the timing controller 204 in a format compliant with the eDP standard or other standards. For example, the image data _DIN is transmitted as 24-bit serial data of 3 bits for each of RGB. The image processor 202 is a GPU (Graphics Processing Unit), an application processor, a CPU (Central Processing Unit), or the like.

CDR circuit 100 receives the image data _{D IN} from the image processor 202. The timing controller 204 generates various timing signals on the basis of the data _{D IN} to CDR circuit 100 receives. The gate driver 208 sequentially selects the scanning lines of the display panel 206 in synchronization with the timing signal from the source driver 210. The source driver 210 applies a driving voltage corresponding to the luminance data from the timing controller 204 to the data line of the display panel 206.

  The electronic device 200 may be equipped with a function called panel self-refresh (PSR). In the panel self-refresh, transmission of image data from the image processor 202 to the timing controller 204 is stopped when a still image is displayed, and the display is displayed on the basis of the data stored in the frame memory 205 by the timing controller 204. An image is displayed on the panel 206. Therefore, when the panel self-refresh function is set to active, the CDR circuit 100 holds the received image data on the frame memory 205, and in the state of no input from the image processor 202, the image data on the frame memory 205 is displayed. Display on the panel 206.

To support panel self-refresh function, the input data _{D IN} from the image processor 202 to the CDR circuit 100 is intermittently generated. The CDR circuit 100 according to the embodiment can be suitably used for such applications.

In this application, CDR circuit 100, when the input data D _IN is input, at a frequency of once per frame, providing a calibration period CAL, may update the frequency of the dummy clock signal CKd.

The panel self-refresh, the control signal for notifying the stop of the input data D _IN is given from the image processor 202 to the timing controller 204. Therefore, the timing controller 204 can control the selector 81 based on this control signal.

  The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. . Hereinafter, such modifications will be described.

(First modification)
In the embodiment, the case where a four-phase clock signal is reproduced has been described as an example. However, the technical idea disclosed in the embodiment can be expanded to eight-phase, sixteen-phase, and other clock signals, Those skilled in the art will appreciate that they are also within the scope of the present invention.

(Second modification)
In the embodiment, the timing controller has been described as an application of the CDR circuit 100, but the present invention is not limited thereto. For example, the CDR circuit 100 can be used for a bridge chip. Bridge chips are used to bridge different interface standards. For example, an input interface of a bridge chip that converts image data that conforms to the eDP standard to serial data in CMOS format and outputs it, or a bridge that converts image data that conforms to the eDP standard to serial data in LVDS format and outputs it The CDR circuit 100 can be used as the input interface of the chip.

(Third Modification)
In the dummy clock signal generator 80 of FIG. 4, the output clock signal CK _OUT is used to detect the frequency fm of the multiphase clock signal CKm, but the present invention is not limited to this. In place of the output clock signal CK _OUT , the calibration logic circuit 84 may receive the output Ref of the comparator CMP1, the Vco signal that is the output of CMP2, or a plurality of clock signals. Any of CK1 to CK4 may be input.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Phase comparator, 12 ... Decoder circuit, 20 ... Frequency comparator, 30 ... Selector, 40 ... Charge pump circuit, 50 ... Loop filter, 60 ... VCO, 70 ... Serial parallel converter, 80 ... Dummy clock signal generator , 81, selector, 82, oscillator, 84, calibration logic circuit, 86, frequency divider, 88, first counter, 90, second counter, 92, control data adjuster, 100, CDR circuit, 200, electronic device, 202 ... Image processor, 204 ... Timing controller, 205 ... Frame memory, 206 ... Display panel, 208 ... Gate driver, 210 ... Source driver.

Claims (10)

A voltage controlled oscillator that generates a multi-phase clock signal including a plurality of clock signals having a frequency according to a control voltage and having phases shifted from each other at equal intervals;
A phase comparator that compares the phase of the input data with the phase of each of the plurality of clock signals and generates a phase difference signal indicating a comparison result;
A frequency comparator that compares the frequency of the input data with the frequency of the multiphase clock signal and generates a phase frequency difference signal indicating a comparison result;
A charge pump circuit for generating the control voltage whose voltage level is adjusted according to the phase difference signal and the phase frequency difference signal;
A dummy clock signal generator for generating a dummy clock signal having substantially the same frequency as the frequency in a period in which the frequency of the multiphase clock signal is stabilized;
With
In the non-input state of the input data, the frequency comparator compares the frequency of the dummy clock signal with the frequency of the multiphase clock signal instead of the frequency of the input data. . The dummy clock signal generator is
An oscillator that generates the dummy clock signal having a frequency according to control data;
A calibration logic circuit that receives the dummy clock signal and the multiphase clock signal and adjusts the control data so that their frequencies match;
The clock data recovery circuit according to claim 1, comprising: The calibration logic circuit
A frequency divider that divides each of the dummy clock signal and the output clock signal of the clock data recovery circuit;
A first counter that counts the dummy clock signal after frequency division;
A second counter for counting the output clock signal after frequency division;
The control data according to the first count value and the second count value when one of the first count value of the first counter and the second count value of the second counter reaches a predetermined first value. A control data adjuster to increase or decrease
The clock data recovery circuit according to claim 2, comprising:   4. The clock data recovery circuit according to claim 3, wherein the control data adjuster increases or decreases the control data according to a magnitude relationship between the first count value and the second count value.   The clock data recovery circuit according to claim 4, wherein the control data adjuster increases or decreases the control data in a predetermined second value step.   6. The clock data recovery circuit according to claim 5, wherein the predetermined first value and the predetermined second value can be set.   4. The clock data recovery circuit according to claim 3, wherein the control data adjuster increases or decreases the control data according to a difference between the first count value and the second count value.   A timing controller comprising the clock data recovery circuit according to claim 1.   An electronic apparatus comprising the timing controller according to claim 8. A voltage-controlled oscillator generating a multi-phase clock signal including a plurality of clock signals having a frequency corresponding to the control voltage and having phases mutually shifted at equal intervals;
A phase comparator compares the phase of the input data with the phase of each of the plurality of clock signals, and generates a phase difference signal including an up signal and a down signal indicating a comparison result;
A frequency comparator compares the frequency of the input data with the frequency of the multiphase clock signal and generates a phase frequency difference signal including an up signal and a down signal indicating a comparison result;
When the up signal of the phase difference signal is asserted or when the up signal of the phase frequency difference signal is asserted, a charge pump circuit adjusts the control voltage to increase the frequency of the voltage controlled oscillator. Changing the control voltage so that the frequency of the voltage controlled oscillator is lowered when the down signal of the phase difference signal or the down signal of the phase frequency difference signal is asserted;
Measuring the frequency during a period when the frequency of the multiphase clock signal is stabilized, and generating a dummy clock signal having the measured frequency;
In the no-input state of the input data, inputting the dummy clock signal instead of the input data to the frequency comparator;
A clock data recovery method comprising:

Images