JP6495327B2 - メモリコントローラにおける細粒度帯域幅プロビジョニング - Google Patents

メモリコントローラにおける細粒度帯域幅プロビジョニング Download PDF

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JP6495327B2
JP6495327B2 JP2016560970A JP2016560970A JP6495327B2 JP 6495327 B2 JP6495327 B2 JP 6495327B2 JP 2016560970 A JP2016560970 A JP 2016560970A JP 2016560970 A JP2016560970 A JP 2016560970A JP 6495327 B2 JP6495327 B2 JP 6495327B2
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request
dram
memory
master
bandwidth
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JP2017511545A (ja
JP2017511545A5 (enExample
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コーク,ノン,トアイ
カリー,スーザン
アンドリュース,ジェフリー
セル,ジョン
ポー,ケヴィン
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Microsoft Corp
Microsoft Technology Licensing LLC
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Microsoft Corp
Microsoft Technology Licensing LLC
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0613Improving I/O performance in relation to throughput
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629Configuration or reconfiguration of storage systems
    • G06F3/0631Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0674Disk device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Dram (AREA)
  • Bus Control (AREA)
JP2016560970A 2014-04-14 2015-04-06 メモリコントローラにおける細粒度帯域幅プロビジョニング Active JP6495327B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/252,673 US9563369B2 (en) 2014-04-14 2014-04-14 Fine-grained bandwidth provisioning in a memory controller
US14/252,673 2014-04-14
PCT/US2015/024414 WO2015160541A1 (en) 2014-04-14 2015-04-06 Fine-grained bandwidth provisioning in a memory controller

Publications (3)

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JP2017511545A JP2017511545A (ja) 2017-04-20
JP2017511545A5 JP2017511545A5 (enExample) 2018-04-26
JP6495327B2 true JP6495327B2 (ja) 2019-04-03

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JP2016560970A Active JP6495327B2 (ja) 2014-04-14 2015-04-06 メモリコントローラにおける細粒度帯域幅プロビジョニング

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US (1) US9563369B2 (enExample)
EP (1) EP3132355B1 (enExample)
JP (1) JP6495327B2 (enExample)
KR (1) KR102380670B1 (enExample)
CN (1) CN106233269B (enExample)
WO (1) WO2015160541A1 (enExample)

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US10691375B2 (en) * 2015-01-30 2020-06-23 Hewlett Packard Enterprise Development Lp Memory network to prioritize processing of a memory access request
US10158712B2 (en) * 2015-06-04 2018-12-18 Advanced Micro Devices, Inc. Source-side resource request network admission control
US20210182190A1 (en) * 2016-07-22 2021-06-17 Pure Storage, Inc. Intelligent die aware storage device scheduler
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US10437482B2 (en) * 2017-07-25 2019-10-08 Samsung Electronics Co., Ltd. Coordinated near-far memory controller for process-in-HBM
US10481944B2 (en) * 2017-08-09 2019-11-19 Xilinx, Inc. Adaptive quality of service control circuit
US10360832B2 (en) 2017-08-14 2019-07-23 Microsoft Technology Licensing, Llc Post-rendering image transformation using parallel image transformation pipelines
US10678690B2 (en) 2017-08-29 2020-06-09 Qualcomm Incorporated Providing fine-grained quality of service (QoS) control using interpolation for partitioned resources in processor-based systems
US10318301B2 (en) 2017-08-31 2019-06-11 Micron Technology, Inc. Managed multiple die memory QoS
US10372609B2 (en) * 2017-09-14 2019-08-06 Intel Corporation Fast cache warm-up
KR102417977B1 (ko) * 2017-10-19 2022-07-07 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
US10700954B2 (en) * 2017-12-20 2020-06-30 Advanced Micro Devices, Inc. Scheduling memory bandwidth based on quality of service floorbackground
US10296230B1 (en) * 2017-12-22 2019-05-21 Advanced Micro Devices, Inc. Scheduling memory requests with non-uniform latencies
US10275352B1 (en) * 2017-12-28 2019-04-30 Advanced Micro Devices, Inc. Supporting responses for memory types with non-uniform latencies on same channel
US11144457B2 (en) * 2018-02-22 2021-10-12 Netspeed Systems, Inc. Enhanced page locality in network-on-chip (NoC) architectures
US10705985B1 (en) * 2018-03-12 2020-07-07 Amazon Technologies, Inc. Integrated circuit with rate limiting
US11099778B2 (en) 2018-08-08 2021-08-24 Micron Technology, Inc. Controller command scheduling in a memory system to increase command bus utilization
CN109062514B (zh) * 2018-08-16 2021-08-31 郑州云海信息技术有限公司 一种基于命名空间的带宽控制方法、装置和存储介质
US10838884B1 (en) 2018-09-12 2020-11-17 Apple Inc. Memory access quality-of-service reallocation
US10635355B1 (en) * 2018-11-13 2020-04-28 Western Digital Technologies, Inc. Bandwidth limiting in solid state drives
US10860254B2 (en) * 2019-04-17 2020-12-08 Vmware, Inc. Throttling resynchronization operations in a data store cluster based on I/O bandwidth limits
US20210279192A1 (en) * 2020-03-06 2021-09-09 Infineon Technologies Ag Distribution of interconnect bandwidth among master agents
US12223174B2 (en) 2020-10-26 2025-02-11 Google Llc Modulating credit allocations in memory subsystems
US20220357879A1 (en) * 2021-05-06 2022-11-10 Apple Inc. Memory Bank Hotspotting
EP4281876A1 (en) * 2021-09-30 2023-11-29 Huawei Technologies Co., Ltd. Memory controller and data processing system with memory controller
WO2023128479A1 (ko) * 2021-12-30 2023-07-06 주식회사 엘엑스세미콘 메모리 제어 시스템 및 메모리 제어 기능을 갖는 디스플레이 디바이스
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Also Published As

Publication number Publication date
WO2015160541A1 (en) 2015-10-22
US20150293709A1 (en) 2015-10-15
EP3132355B1 (en) 2019-09-04
KR102380670B1 (ko) 2022-03-29
CN106233269A (zh) 2016-12-14
EP3132355A1 (en) 2017-02-22
US9563369B2 (en) 2017-02-07
KR20160144482A (ko) 2016-12-16
JP2017511545A (ja) 2017-04-20
CN106233269B (zh) 2019-12-10

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