JP6491655B2 - 即値ハンドリング及びフラグハンドリングのためのプロセッサ及び方法 - Google Patents

即値ハンドリング及びフラグハンドリングのためのプロセッサ及び方法 Download PDF

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JP6491655B2
JP6491655B2 JP2016525922A JP2016525922A JP6491655B2 JP 6491655 B2 JP6491655 B2 JP 6491655B2 JP 2016525922 A JP2016525922 A JP 2016525922A JP 2016525922 A JP2016525922 A JP 2016525922A JP 6491655 B2 JP6491655 B2 JP 6491655B2
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flag
order
mapping table
bit
instruction
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JP2016534430A5 (enExample
JP2016534430A (ja
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ベンカタチャー アショク
ベンカタチャー アショク
パヌコルー カルティック
パヌコルー カルティック
アレカプディ スリカンス
アレカプディ スリカンス
エイ． チットニス サミール
エイ． チットニス サミール
テルぺス エミール
テルぺス エミール
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP2016525922A 2013-10-25 2014-10-24 即値ハンドリング及びフラグハンドリングのためのプロセッサ及び方法 Active JP6491655B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361895715P 2013-10-25 2013-10-25
US61/895,715 2013-10-25
PCT/US2014/062180 WO2015061687A1 (en) 2013-10-25 2014-10-24 Processor and methods for immediate handling and flag handling

Publications (3)

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JP2016534430A JP2016534430A (ja) 2016-11-04
JP2016534430A5 JP2016534430A5 (enExample) 2017-11-30
JP6491655B2 true JP6491655B2 (ja) 2019-03-27

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JP2016525922A Active JP6491655B2 (ja) 2013-10-25 2014-10-24 即値ハンドリング及びフラグハンドリングのためのプロセッサ及び方法

Country Status (6)

Country Link
US (1) US20150121041A1 (enExample)
EP (1) EP3060979B1 (enExample)
JP (1) JP6491655B2 (enExample)
KR (1) KR102161682B1 (enExample)
CN (1) CN105765522B (enExample)
WO (1) WO2015061687A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9798593B1 (en) * 2016-07-06 2017-10-24 Workday, Inc. Synchronization of code execution
US10761849B2 (en) * 2016-09-22 2020-09-01 Intel Corporation Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction
US10713213B2 (en) * 2016-12-21 2020-07-14 Intel Corporation Systems and methods for multi-architecture computing
US11275709B2 (en) 2017-05-02 2022-03-15 Intel Corporation Systems and methods for multi-architecture computing
US10318298B2 (en) * 2017-09-29 2019-06-11 Intel Corporation Apparatus and method for shifting quadwords and extracting packed words
US10481910B2 (en) * 2017-09-29 2019-11-19 Intel Corporation Apparatus and method for shifting quadwords and extracting packed words
CN112114874B (zh) * 2020-08-20 2021-10-15 北京百度网讯科技有限公司 数据处理方法、装置、电子设备和存储介质

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6047369A (en) * 1994-02-28 2000-04-04 Intel Corporation Flag renaming and flag masks within register alias table
US5632023A (en) * 1994-06-01 1997-05-20 Advanced Micro Devices, Inc. Superscalar microprocessor including flag operand renaming and forwarding apparatus
US5649225A (en) * 1994-06-01 1997-07-15 Advanced Micro Devices, Inc. Resynchronization of a superscalar processor
US5933618A (en) * 1995-10-30 1999-08-03 Advanced Micro Devices, Inc. Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction
US6338132B1 (en) * 1998-12-30 2002-01-08 Intel Corporation System and method for storing immediate data
US20050071518A1 (en) * 2003-09-30 2005-03-31 Intel Corporation Flag value renaming
US7587585B1 (en) * 2005-10-26 2009-09-08 Sun Microsystems, Inc. Flag management in processors enabled for speculative execution of micro-operation traces
US7421529B2 (en) * 2005-10-20 2008-09-02 Qualcomm Incorporated Method and apparatus to clear semaphore reservation for exclusive access to shared memory
US7822948B2 (en) * 2008-01-03 2010-10-26 International Business Machines Corporation Apparatus, system, and method for discontiguous multiple issue of instructions
US8250346B2 (en) * 2009-06-04 2012-08-21 Arm Limited Register renaming of a partially updated data granule
US9088594B2 (en) * 2011-02-07 2015-07-21 International Business Machines Corporation Providing to a parser and processors in a network processor access to an external coprocessor
US8924695B2 (en) * 2011-04-07 2014-12-30 Via Technologies, Inc. Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
EP2508980B1 (en) * 2011-04-07 2018-02-28 VIA Technologies, Inc. Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor
US8972701B2 (en) * 2011-12-06 2015-03-03 Arm Limited Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register
US9189236B2 (en) * 2012-12-21 2015-11-17 Intel Corporation Speculative non-faulting loads and gathers

Also Published As

Publication number Publication date
EP3060979A4 (en) 2017-07-05
EP3060979A1 (en) 2016-08-31
CN105765522B (zh) 2020-05-19
WO2015061687A1 (en) 2015-04-30
EP3060979B1 (en) 2020-08-05
US20150121041A1 (en) 2015-04-30
JP2016534430A (ja) 2016-11-04
KR102161682B1 (ko) 2020-10-05
KR20160075639A (ko) 2016-06-29
CN105765522A (zh) 2016-07-13

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