JP2016534430A5 - - Google Patents
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- JP2016534430A5 JP2016534430A5 JP2016525922A JP2016525922A JP2016534430A5 JP 2016534430 A5 JP2016534430 A5 JP 2016534430A5 JP 2016525922 A JP2016525922 A JP 2016525922A JP 2016525922 A JP2016525922 A JP 2016525922A JP 2016534430 A5 JP2016534430 A5 JP 2016534430A5
- Authority
- JP
- Japan
- Prior art keywords
- flag
- mapping table
- order
- write
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361895715P | 2013-10-25 | 2013-10-25 | |
| US61/895,715 | 2013-10-25 | ||
| PCT/US2014/062180 WO2015061687A1 (en) | 2013-10-25 | 2014-10-24 | Processor and methods for immediate handling and flag handling |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016534430A JP2016534430A (ja) | 2016-11-04 |
| JP2016534430A5 true JP2016534430A5 (enExample) | 2017-11-30 |
| JP6491655B2 JP6491655B2 (ja) | 2019-03-27 |
Family
ID=52993620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016525922A Active JP6491655B2 (ja) | 2013-10-25 | 2014-10-24 | 即値ハンドリング及びフラグハンドリングのためのプロセッサ及び方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20150121041A1 (enExample) |
| EP (1) | EP3060979B1 (enExample) |
| JP (1) | JP6491655B2 (enExample) |
| KR (1) | KR102161682B1 (enExample) |
| CN (1) | CN105765522B (enExample) |
| WO (1) | WO2015061687A1 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9798593B1 (en) * | 2016-07-06 | 2017-10-24 | Workday, Inc. | Synchronization of code execution |
| US10761849B2 (en) * | 2016-09-22 | 2020-09-01 | Intel Corporation | Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction |
| US10713213B2 (en) * | 2016-12-21 | 2020-07-14 | Intel Corporation | Systems and methods for multi-architecture computing |
| US11275709B2 (en) | 2017-05-02 | 2022-03-15 | Intel Corporation | Systems and methods for multi-architecture computing |
| US10318298B2 (en) * | 2017-09-29 | 2019-06-11 | Intel Corporation | Apparatus and method for shifting quadwords and extracting packed words |
| US10481910B2 (en) * | 2017-09-29 | 2019-11-19 | Intel Corporation | Apparatus and method for shifting quadwords and extracting packed words |
| CN112114874B (zh) * | 2020-08-20 | 2021-10-15 | 北京百度网讯科技有限公司 | 数据处理方法、装置、电子设备和存储介质 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6047369A (en) * | 1994-02-28 | 2000-04-04 | Intel Corporation | Flag renaming and flag masks within register alias table |
| US5632023A (en) * | 1994-06-01 | 1997-05-20 | Advanced Micro Devices, Inc. | Superscalar microprocessor including flag operand renaming and forwarding apparatus |
| US5649225A (en) * | 1994-06-01 | 1997-07-15 | Advanced Micro Devices, Inc. | Resynchronization of a superscalar processor |
| US5933618A (en) * | 1995-10-30 | 1999-08-03 | Advanced Micro Devices, Inc. | Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction |
| US6338132B1 (en) * | 1998-12-30 | 2002-01-08 | Intel Corporation | System and method for storing immediate data |
| US20050071518A1 (en) * | 2003-09-30 | 2005-03-31 | Intel Corporation | Flag value renaming |
| US7587585B1 (en) * | 2005-10-26 | 2009-09-08 | Sun Microsystems, Inc. | Flag management in processors enabled for speculative execution of micro-operation traces |
| US7421529B2 (en) * | 2005-10-20 | 2008-09-02 | Qualcomm Incorporated | Method and apparatus to clear semaphore reservation for exclusive access to shared memory |
| US7822948B2 (en) * | 2008-01-03 | 2010-10-26 | International Business Machines Corporation | Apparatus, system, and method for discontiguous multiple issue of instructions |
| US8250346B2 (en) * | 2009-06-04 | 2012-08-21 | Arm Limited | Register renaming of a partially updated data granule |
| US9088594B2 (en) * | 2011-02-07 | 2015-07-21 | International Business Machines Corporation | Providing to a parser and processors in a network processor access to an external coprocessor |
| US8924695B2 (en) * | 2011-04-07 | 2014-12-30 | Via Technologies, Inc. | Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor |
| EP2508980B1 (en) * | 2011-04-07 | 2018-02-28 | VIA Technologies, Inc. | Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor |
| US8972701B2 (en) * | 2011-12-06 | 2015-03-03 | Arm Limited | Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register |
| US9189236B2 (en) * | 2012-12-21 | 2015-11-17 | Intel Corporation | Speculative non-faulting loads and gathers |
-
2014
- 2014-10-24 KR KR1020167013469A patent/KR102161682B1/ko active Active
- 2014-10-24 WO PCT/US2014/062180 patent/WO2015061687A1/en not_active Ceased
- 2014-10-24 US US14/523,718 patent/US20150121041A1/en not_active Abandoned
- 2014-10-24 JP JP2016525922A patent/JP6491655B2/ja active Active
- 2014-10-24 EP EP14855674.9A patent/EP3060979B1/en active Active
- 2014-10-24 CN CN201480064146.0A patent/CN105765522B/zh active Active
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