JP6458826B2 - Gate drive circuit - Google Patents

Description

  The present invention relates to a gate drive circuit that alternately turns on and off a high-side switching element and a low-side switching element and suppresses an increase in gate potential due to a capacitance between the drain and the gate of the low-side switching element.

  As a conventional gate drive circuit, a gate drive circuit described in Patent Document 1 is known. This gate drive circuit prevents the through current by adjusting the dead time of the high-side switching element and the low-side switching element and preventing the high-side switching element and the low-side switching element from being simultaneously turned on. .

  7 includes a DC power source Vin, a high-side switching element SW1, a PN-junction diode Di1, a low-side switching element SW2, a freewheeling diode Di2, a reactor L, a capacitor C1, and an electronic control unit (ECU) 11. The control circuit 12 is provided. The switching elements SW1 and SW2 are N-type MOSFETs.

  A series circuit of a switching element SW1, a diode Di1, and a switching element SW2 is connected to both ends of the DC power supply Vin, and one end of the reactor L and a cathode of a free-wheeling diode Di2 are connected to the source of the switching element SW1 and the anode of the diode Di1. Has been. The other end of the reactor L is connected to one end of the capacitor C1, and the anode of the free-wheeling diode Di2 and the other end of the capacitor are grounded.

JP 2006-34030 A

  However, the midpoint potential V1 connected to the load may oscillate at high frequency due to the resonance operation. This high-frequency oscillation phenomenon will be described with reference to a timing chart shown in FIG. Here, V1 represents the anode potential of the diode Di1, and V2 represents the cathode potential of the diode Di1.

  First, when the switching element SW1 is turned on at time t10, a current flows through Vin → SW1 → L → C1. For this reason, the voltages V1 and V2 are predetermined voltages. When the switching element SW2 is turned on at time t11, a current flows in the order of C1, L, Di1, and SW2. For this reason, the voltages V1 and V2 are zero voltages.

  Next, when the switching element SW1 is turned on at time t12, current flows through Vin → SW1 → L → C1, but at time t13 to t14, the midpoint potential V1 to which the load is connected reaches the oscillation operation due to the resonance phenomenon. .

  Due to the drain and gate voltage of the switching element SW2 and the parasitic capacitance Cds, a current iG + flowing from the drain to the gate of the switching element SW2 and a current iG- flowing from the gate to the drain are generated via the parasitic capacitance Cds.

  Since the diode Di1 which is a reverse current blocking element is connected to the drain, there is no path through which the current iG− flows first from the potential V2. For this reason, the relationship of iG + = iG− cannot be maintained due to the oscillation operation due to the resonance phenomenon, and iG +> iG−.

  For this reason, the gate voltage of the switching element SW2 increases, and at time t17, the gate voltage of the switching element SW2 exceeds the threshold voltage Vth, so that the switching element SW2 is turned on. For this reason, since the switching elements SW1 and SW2 are simultaneously turned on, a through current flows.

  An object of the present invention is to provide a gate drive circuit that suppresses an increase in gate potential due to a capacitance between a drain and a gate of a low-side switching element and eliminates an unintended switching element on operation.

  The gate drive circuit according to the present invention includes a series circuit in which a high-side first switching element, a first diode, and a low-side second switching element are connected in series to both ends of a DC power supply, and one end of the first switching element. A reactor connected to the first main electrode and the anode of the first diode and having the other end connected to the load; a freewheeling diode having a cathode connected to one end of the reactor and an anode connected to a reference potential; and one end An impedance element connected to one end of the DC power source and the second main electrode of the first switching element, and the other end connected to the cathode of the first diode and the second main electrode of the second switching element; A control circuit for alternately turning on and off the switching element and the second switching element by providing a predetermined dead time. The features.

  The present invention also provides a series circuit in which a high-side first switching element, a first diode, and a low-side second switching element are connected in series to both ends of a DC power supply, and one end of the first switching element is a first of the first switching element. A reactor connected to the main electrode and the anode of the first diode and having the other end connected to a load; a freewheeling diode having a cathode connected to one end of the reactor and an anode connected to a reference potential; and the first switching element And a control circuit for alternately turning on and off the second switching element with a predetermined dead time, and the first diode includes the reactor, a capacitor included in the load, and the second main element of the second switching element. The forward impedance increases at high frequencies in the resonance phenomenon due to the parasitic capacitance between the electrode and the control electrode. Characterized in that it.

  According to the present invention, there is provided an impedance element having one end connected to one end of the DC power source and the second main electrode of the first switching element and the other end connected to the cathode of the first diode and the second main electrode of the second switching element. Since it is provided, the potential of the second main electrode of the second switching element is held at the potential of the DC power supply.

  For this reason, the current iG− from the control electrode of the second switching element to the second main electrode for the first time is suppressed. Since the first current iG− does not flow, the second and subsequent current iG + flows are suppressed, and the potential of the control electrode of the second switching element is not increased. This operation eliminates an unintended ON operation of the second switching element.

  In the present invention, since the first diode increases the forward impedance at a high frequency in the resonance phenomenon caused by the reactor and the capacitor included in the load and the parasitic capacitance between the second main electrode and the control electrode of the second switching element, Oscillation operation generated in the second main electrode of the second switching element is suppressed.

  For this reason, the current iG− from the control electrode of the second switching element to the second main electrode for the first time is suppressed. Since the first current iG− does not flow, the second and subsequent current iG + flows are suppressed, and the potential of the control electrode of the second switching element is not increased. This operation eliminates an unintended ON operation of the second switching element.

1 is a circuit configuration diagram of a gate drive circuit according to Embodiment 1 of the present invention. FIG. 4 is a timing chart for explaining the operation of each part of the gate drive circuit according to the first embodiment of the invention. It is a circuit block diagram of the 1st modification of the gate drive circuit which concerns on Example 1 of this invention. It is a circuit block diagram of the 2nd modification of the gate drive circuit based on Example 1 of this invention. It is a circuit block diagram of the gate drive circuit which concerns on Example 2 of this invention. It is a figure which shows the characteristic of the forward current with respect to the forward voltage of the high frequency signal of the fast recovery diode of the gate drive circuit which concerns on Example 2 of this invention. It is a circuit block diagram of the conventional gate drive circuit. It is a timing chart for demonstrating operation | movement of each part of the conventional gate drive circuit.

  Hereinafter, a gate drive circuit according to an embodiment of the present invention will be described in detail with reference to the drawings.

Example 1
1 is a circuit configuration diagram of a gate drive circuit according to a first embodiment of the present invention. The gate drive circuit according to the first embodiment shown in FIG. 1 is further connected to the drain of the switching element SW2 and the cathode of the diode Di1 and has the other end connected to the direct current with respect to the conventional gate drive circuit shown in FIG. A resistor R connected to the positive electrode of the power source Vin and the drain of the switching element SW2 is provided.

  The switching element SW1 corresponds to the first switching element of the present invention. The source of the switching element SW1 corresponds to the first main electrode of the present invention, and the drain of the switching element SW1 corresponds to the second main electrode of the present invention.

  The switching element SW2 corresponds to the second switching element of the present invention. The source of the switching element SW2 corresponds to the first main electrode of the present invention, and the drain of the switching element SW2 corresponds to the second main electrode of the present invention.

  The diode Di1 corresponds to the first diode of the present invention, is a PN junction diode, and has a function of blocking reverse current. The resistor R is the impedance element of the present invention and corresponds to the first resistor. The capacitor C1 is a load and corresponds to the first capacitor of the present invention. The ground corresponds to the reference potential of the present invention. The reference potential may be a fixed potential that is not ground.

  The control circuit 12 turns on and off the switching elements SW1 and SW2 alternately with a predetermined dead time.

  The other configuration of the gate driving circuit according to the first embodiment shown in FIG. 1 is the same as that of the conventional gate driving circuit shown in FIG. To do.

  Next, the operation of the thus configured gate drive circuit according to the first embodiment will be described with reference to the timing chart shown in FIG. Note that the frequency of the gate signal of the switching elements SW1 and SW2 shown in FIG. 2 is, for example, 300 kHz, and the high frequency for oscillating operation is, for example, 5 MHz.

  First, when the switching element SW1 is turned on at time to, a current flows through Vin → SW1 → L → C1. For this reason, the voltages V1 and V2 are substantially the same voltage as the voltage of the DC power supply Vin.

  Next, when the switching element SW2 is turned on at time t1, a current flows through Vin → R → SW2. Then, the resistor R is connected to the positive electrode of the DC power source Vin and the drain of the switching element SW2, and the drain and the source are short-circuited, so that the potential V2 becomes almost zero voltage.

  At this time, a current flows from L → C1 → Di, and the capacitor C1 is discharged. For this reason, the energy of the reactor L and the capacitor | condenser C1 is lose | eliminated, and the voltage V1 becomes a zero voltage. At this time, the diode Di1 is turned off.

  Next, when the switching element SW1 is turned on at time t2, a current flows through Vin → SW1 → L → C1, and at time t3, the switching element SW1 is turned off. That is, both the switching element SW1 and the switching element SW2 are off. Then, since the resistor R is connected to the positive electrode of the DC power supply Vin and the drain of the switching element SW2, the voltage of the DC power supply Vin is applied to the drain of the switching element SW2 via the resistor R. For this reason, the potential V2 is held at Vin.

  Therefore, the current iG− from the gate to the drain of the first switching element SW2 is suppressed. Since the first current iG− does not flow, the second and subsequent current iG + flows are suppressed, and the gate potential of the switching element SW2 is not increased.

  For this reason, the gate voltage of the switching element SW2 does not reach the threshold value Vth also at times t3 to t4 and t6 to t7. As a result, the unintended ON operation of the switching element SW2 is eliminated.

(First Modification of Example 1)
FIG. 3 is a circuit configuration diagram of a first modification of the gate drive circuit according to the first embodiment of the present invention. In the first modification, as shown in FIG. 3, one end is connected to the drain of the switching element SW2 and the cathode of the diode Di1, and the other end is connected to the positive electrode of the DC power supply Vin and the drain of the switching element SW2. A series circuit of a resistor R and a capacitor C2 is provided.

  As described above, even when a series circuit of the resistor R and the capacitor C2 is connected between the positive electrode of the DC power supply Vin and the drain of the switching element SW2, as in the first modification, the positive electrode of the DC power supply Vin The same effect as when the resistor R is connected between the drain of the switching element SW2 can be obtained.

(Second Modification of Example 1)
FIG. 4 is a circuit configuration diagram of a second modification of the gate drive circuit according to the first embodiment of the present invention. In the second modification, as shown in FIG. 4, one end is connected to the drain of the switching element SW2 and the cathode of the diode Di1, and the other end is connected to the positive electrode of the DC power supply Vin and the drain of the switching element SW2. A parallel circuit of a resistor R and a capacitor C2 is provided.

  Thus, even if a parallel circuit of the resistor R and the capacitor C3 is connected between the positive electrode of the DC power supply Vin and the drain of the switching element SW2, as in the second modification, the positive electrode of the DC power supply Vin The same effect as when the resistor R is connected between the drain of the switching element SW2 can be obtained.

(Example 2)
FIG. 5 is a circuit configuration diagram of a gate drive circuit according to the second embodiment of the present invention. The gate drive circuit according to the second embodiment is characterized in that a fast recovery diode FRD is used instead of the diode Di1 of the conventional gate drive circuit shown in FIG.

  FIG. 6 is a diagram illustrating the forward current characteristic with respect to the forward voltage of the high-frequency signal of the fast recovery diode of the gate drive circuit according to the second embodiment of the present invention.

  As shown in FIG. 6, in a normal diode, a forward current with respect to a forward voltage increases like a quadratic curve at a low frequency. As shown in FIG. 6, the diode Di1 of the reverse current block described in the first embodiment maintains a constant value in the forward impedance even in the high frequency operation.

  Here, the high frequency is the frequency of the oscillation operation of the voltage V1 at times t3 to t4 and t6 to t7 shown in FIG. This frequency is a high frequency in a resonance phenomenon caused by the reactor L, the capacitor C1, and the capacitance Ddg between the drain and gate of the switching element SW2.

  On the other hand, the fast recovery diode FRD used in the gate drive circuit according to the second embodiment has a high frequency in a resonance phenomenon caused by the reactor L, the capacitor C1, and the capacitance Ddg between the drain and gate of the switching element SW2, as shown in FIG. As shown, the forward impedance increases.

  For this reason, the oscillation operation generated at the drain of the switching element SW2 can be suppressed. Therefore, the current iG− from the gate to the drain of the first switching element SW2 is suppressed. Since the first current iG− does not flow, the second and subsequent current iG + flows are suppressed, and the gate potential of the switching element SW2 is not increased. By this operation, the unintended switching element SW2 is turned off.

  In the gate drive circuit according to the second embodiment, the fast recovery diode FRD is illustrated. However, the forward impedance is high at a high frequency in the resonance phenomenon caused by the reactor L, the capacitor C1, the drain and gate capacitance Ddg between the switching element SW2. Other elements may be used as long as they increase.

11 ECU
12 control circuit Vin DC power supply SW1, SW2 switching element Di1 diode Di2 freewheeling diode FRD fast recovery diode L reactor C1, C2, C3 capacitor R, R1 resistance Cds parasitic capacitance Vth threshold

Claims (4)

A series circuit in which a high-side first switching element, a first diode, and a low-side second switching element are connected in series to both ends of a DC power supply;
A reactor having one end connected to the first main electrode of the first switching element and the anode of the first diode and the other end connected to a load;
A freewheeling diode having a cathode connected to one end of the reactor and an anode connected to a reference potential;
An impedance element having one end connected to one end of the DC power source and the second main electrode of the first switching element and the other end connected to the cathode of the first diode and the second main electrode of the second switching element;
A control circuit for alternately turning on and off the first switching element and the second switching element by providing a predetermined dead time;
A gate drive circuit comprising: The load includes a first capacitor;
2. The gate drive circuit according to claim 1, wherein the impedance element is a first resistor or a series circuit of the first resistor and a second capacitor or a parallel circuit of the first resistor and the second capacitor. . A series circuit in which a high-side first switching element, a first diode, and a low-side second switching element are connected in series to both ends of a DC power supply;
A reactor having one end connected to the first main electrode of the first switching element and the anode of the first diode and the other end connected to a load;
A freewheeling diode having a cathode connected to one end of the reactor and an anode connected to a reference potential;
A control circuit for alternately turning on and off the first switching element and the second switching element by providing a predetermined dead time;
With
The first diode has an increased forward impedance at a high frequency in a resonance phenomenon caused by the reactor, a capacitor included in the load, and a parasitic capacitance between the second main electrode and the control electrode of the second switching element. A gate drive circuit.   4. The gate driving circuit according to claim 3, wherein the first diode is a fast recovery diode.

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