JP6455998B2 - Fan-out semiconductor package - Google Patents

Description

  The present invention relates to a semiconductor package, for example, a fan-out semiconductor package in which connection terminals can be extended outside a region where a semiconductor chip is disposed.

  In general, a silicon-based interposer substrate is used as a package including a plurality of semiconductor chips. For example, a structure in which a first semiconductor chip is mounted on a silicon-based interposer substrate, and a second semiconductor chip is mounted side by side to electrically connect wirings formed on the interposer substrate. Was developed.

  However, the silicon-based interposer substrate has a problem of cost because it is required to form a TSV inside the silicon and form an ultrafine circuit. Further, since the overall thickness of the package is large, there is a limit to downsizing and thinning. As a method for solving this, a method of connecting a plurality of semiconductor chips by incorporating a silicon bridge in a printed circuit board has been developed, but there is a problem that the process becomes complicated and the yield is lowered.

  One of the various objects of the present invention is that it can be thinned and miniaturized despite the inclusion of a plurality of semiconductor chips, and it is possible to minimize noise by shortening the connecting distance between the chips. An object of the present invention is to provide a fan-out semiconductor package that can be manufactured at low cost and high yield.

  One of the various solutions proposed by the present invention is to provide a fan-out semiconductor package that satisfies the following configuration.

  For example, a fan-out semiconductor package according to an example of the present invention includes a first connection member having a through hole, an active surface disposed in the through hole of the first connection member, and a connection pad disposed opposite to the active surface. A first chip package including a first semiconductor chip having an inactive surface disposed on the side, a sealing material for sealing at least a part of the first connecting member and the first chip package, and the sealing A first connecting member including a second connecting member disposed on the stopper and facing the active surface; and a second chip package disposed on the second connecting member and including a second semiconductor chip. Each member includes a redistribution layer electrically connected to the connection pad, and the first and second chip packages are electrically connected via the second connection member.

  One of the various effects of the present invention is that it is possible to reduce the thickness and size even though it includes a plurality of semiconductor chips, and to reduce noise by minimizing the connection distance between the chips. It is possible to provide a fan-out semiconductor package that can be manufactured at low cost and high yield.

It is a block diagram which shows the example of an electronic device system roughly. It is the perspective view which showed an example of the electronic device schematically. It is sectional drawing which showed roughly before and after packaging of a fan-in semiconductor package. It is sectional drawing which showed the packaging process of the fan-in semiconductor package roughly. It is sectional drawing which showed schematically the case where a fan-in semiconductor package was mounted on the interposer board | substrate, and was finally mounted in the main board of an electronic device. It is sectional drawing which showed schematically the case where a fan-in semiconductor package was incorporated in the interposer board | substrate and was finally mounted in the main board of an electronic device. It is sectional drawing which showed the schematic form of the fan-out semiconductor package. It is sectional drawing which showed roughly the case where a fan-out semiconductor package is mounted in the main board of an electronic device. It is sectional drawing which showed schematically an example of the fan-out semiconductor package. FIG. 10 is a schematic cross-sectional view of the fan-out semiconductor package of FIG. 9 viewed along the line II ′. 10 is a schematic manufacturing example of the first chip package of FIG. 9; 10 is a schematic manufacturing example of the first chip package of FIG. 9; 10 is a schematic manufacturing example of the fan-out semiconductor package of FIG. 9. 10 is a schematic manufacturing example of the fan-out semiconductor package of FIG. 9. 10 is a schematic manufacturing example of the fan-out semiconductor package of FIG. 9. 10 is a schematic manufacturing example of the fan-out semiconductor package of FIG. 9. It is sectional drawing which showed schematically another example of the fan-out semiconductor package. It is sectional drawing which showed schematically another example of the fan-out semiconductor package. It is sectional drawing which showed schematically another example of the fan-out semiconductor package.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for a clearer description.

Electronic Device FIG. 1 is a block diagram schematically showing an example of an electronic device system.

  Referring to the drawing, the electronic device 1000 houses a main board 1010. The main board 1010 is physically and / or electrically connected to a chip-related component 1020, a network-related component 1030, and other components 1040. These are also combined with other components described below to form various signal lines 1090.

  Chip-related components 1020 include memory chips such as volatile memory (for example, DRAM), nonvolatile memory (for example, ROM), flash memory, etc .; central processor (for example, CPU), graphic processor (for example, GPU), digital signal Application processor chips such as processors, cryptographic processors, microprocessors and microcontrollers; including but not limited to logic chips such as analog-to-digital converters and application-specific ICs (ASICs) Needless to say, other types of chip-related components may be included. Needless to say, these components 1020 may be combined with each other.

  Network-related components 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA +, HSDPA +, HSUPA + , EDGE, GSM (registered trademark), GPS, GPRS, CDMA, TDMA, DECT, Bluetooth (registered trademark), 3G, 4G, 5G, and any other specified as follows In addition to, but not limited to, any of a number of other wireless or wired standards and protocols may be included. Needless to say, the network-related component 1030 may be combined with the chip-related component 1020.

  Other components 1040 include high frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (Low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interface) filters, MLCCs (Multi-Layer Ceramic Condensers), and the like. However, the present invention is not limited thereto, and besides these, passive components used for various other purposes may be included. It goes without saying that other components 1040 may be combined with each other together with the chip-related component 1020 and / or the network-related component 1030.

  Depending on the type of electronic device 1000, the electronic device 1000 may include other components that are physically and / or electrically connected to the main board 1010. Other components include, for example, camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), compass (not shown), accelerometer ( (Not shown), gyroscope (not shown), speaker (not shown), mass storage device (for example, hard disk drive) (not shown), CD (compact disk) (not shown), and DVD (digital versatile disk) ( (Not shown). However, the present invention is not limited to these, and it goes without saying that other components used for various purposes may be included depending on the type of electronic device 1000.

  The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer. A monitor, a tablet, a laptop, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. Can do. However, the present invention is not limited thereto, and it goes without saying that any other electronic device that processes data may be used.

  FIG. 2 is a perspective view schematically showing an example of an electronic device.

  Referring to the drawings, the semiconductor package is applied to various uses in various electronic devices as described above. For example, a main board 1110 is accommodated in the main body 1101 of the smartphone 1100, and various components 1120 are physically and / or electrically connected to the main board 1110. Further, like the camera 1130, other components that are physically and / or electrically connected to the main board 1110 or not connected are accommodated in the main body 1101. A part of the component 1120 can be a chip-related component, and the semiconductor package 100 can be an application processor, for example, but is not limited thereto. Needless to say, the electronic device is not necessarily limited to the smartphone 1100 and may be another electronic device as described above.

Semiconductor package In general, a semiconductor chip has a large number of fine electric circuits integrated therein. However, the semiconductor chip itself cannot serve as a finished semiconductor product, and can be damaged by external physical or chemical impact. There is sex. Therefore, the semiconductor chip itself is not used as it is, but the semiconductor chip is packaged and used in an electronic device or the like in a packaged state.

  The reason why semiconductor packaging is necessary is that the circuit widths of the semiconductor chip and the main board of the electronic device are different from the viewpoint of electrical connection. Specifically, in the semiconductor chip, the size of the connection pads and the interval between the connection pads are very fine, whereas the main board used in the electronic device has the size of the component mounting pads and the interval between the component mounting pads. It is significantly larger than the scale of a semiconductor chip. Therefore, it is difficult to mount the semiconductor chip on such a main board as it is, and a packaging technique that can alleviate the difference in circuit width between them is required.

  A semiconductor package manufactured by such packaging technology is classified into a fan-in semiconductor package and a fan-out semiconductor package according to the structure and application. Can do.

  Hereinafter, the fan-in semiconductor package and the fan-out semiconductor package will be described in more detail with reference to the drawings.

(Fan-in semiconductor package)
FIG. 3 is a cross-sectional view schematically showing before and after packaging of the fan-in semiconductor package.

  FIG. 4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.

  Referring to the drawing, a semiconductor chip 2220 includes a main body 2221 containing silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like, and a conductive material such as aluminum (Al) formed on one surface of the main body 2221. A connection pad 2222 containing a substance and a passivation film 2223 such as an oxide film or a nitride film formed on one surface of the main body 2221 and covering at least a part of the connection pad 2222, for example, integration in a bare state It can be a circuit (IC). At this time, since the connection pads 2222 are very small, the integrated circuit (IC) is not only a main board of an electronic device having a large difference in circuit width, but also an intermediate level printed circuit board in which the difference in circuit width is smaller than that of the main board. It is difficult to mount on (PCB).

  Therefore, in order to redistribute the connection pads 2222, a connecting member 2240 is formed on the semiconductor chip 2220 according to the size of the semiconductor chip 2220. The connecting member 2240 forms an insulating layer 2241 with an insulating material such as a photosensitive insulating resin (PID) on the semiconductor chip 2220, forms a via hole 2243h for opening the connection pad 2222, and then forms the rewiring layer 2242 and the via 2243. It can be formed by forming. Thereafter, a passivation layer 2250 that protects the connecting member 2240 is formed, an opening 2251 is formed, and then an under bump metal layer 2260 and the like are formed. That is, through a series of processes, for example, the fan-in semiconductor package 2200 including the semiconductor chip 2220, the connecting member 2240, the passivation layer 2250, and the under bump metal layer 2260 is manufactured.

  As described above, the fan-in semiconductor package is a package form in which all the connection pads of the semiconductor chip, for example, I / O (Input / Output) terminals are arranged inside the element. The fan-in semiconductor package has excellent electrical characteristics and can be produced at low cost. Therefore, many elements built in a smartphone are manufactured in the form of a fan-in semiconductor package, and specifically, development is performed so as to realize a small and fast signal transmission.

  However, the fan-in semiconductor package has many spatial restrictions because all of the I / O terminals must be arranged inside the semiconductor chip. Therefore, such a structure is difficult to apply to a semiconductor chip having a large number of I / O terminals or a semiconductor chip having a small size. Further, due to such drawbacks, the fan-in semiconductor package cannot be directly mounted on the main board of the electronic device. This is because even if the size and interval of the I / O terminal of the semiconductor chip is increased by the rewiring process, it cannot be increased to a size and interval that can be directly mounted on the main board of the electronic device. is there.

  FIG. 5 is a cross-sectional view schematically showing a case where the fan-in semiconductor package is mounted on the interposer substrate and finally mounted on the main board of the electronic device.

  FIG. 6 is a cross-sectional view schematically showing a case where the fan-in semiconductor package is built in the interposer substrate and finally mounted on the main board of the electronic device.

  Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222 of the semiconductor chip 2220, that is, the I / O terminals are further redistributed by the interposer substrate 2301. The in-semiconductor package 2200 can be mounted on the main board 2500 of the electronic device in a state where it is mounted. At this time, the solder balls 2270 and the like can be fixed by the underfill resin 2280 and the outside can be covered with the molding material 2290 and the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in another interposer substrate 2302 (Embedded). In that case, the connection pads 2222 of the semiconductor chip 2220 in the state incorporated in the interposer substrate 2302, that is, the I / O terminals are further rewired by the interposer substrate 2302, so that they are finally connected to the main board 2500 of the electronic device. Can be implemented.

  As described above, since the fan-in semiconductor package is difficult to be used by being directly mounted on the main board of the electronic device, after being mounted on another interposer substrate, the main package of the electronic device is further subjected to a packaging process. It is mounted on a board or mounted on a main board of an electronic device in a state of being built in an interposer substrate.

(Fan-out semiconductor package)
FIG. 7 is a cross-sectional view showing a schematic form of a fan-out semiconductor package.

  Referring to the drawing, in the fan-out semiconductor package 2100, for example, the outside of the semiconductor chip 2120 is protected by the sealing material 2130, and the connection pads 2122 of the semiconductor chip 2120 are reconnected to the outside of the semiconductor chip 2120 by the connecting member 2140. Wired. At this time, a passivation layer 2150 can be further formed on the connecting member 2140, and an under bump metal layer 2160 can be further formed in the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 can be an integrated circuit (IC) including a main body 2121, connection pads 2122, a passivation film (not shown), and the like. The connection member 2140 may include an insulating layer 2141, a rewiring layer 2142 formed on the insulating layer 2141, and a via 2143 that electrically connects the connection pad 2122 and the rewiring layer 2142.

  As described above, the fan-out semiconductor package has a form in which the I / O terminals are redistributed to the outside of the semiconductor chip by the connecting member formed on the semiconductor chip. As described above, the fan-in semiconductor package requires that all of the I / O terminals of the semiconductor chip be placed inside the semiconductor chip, so that as the element size is reduced, the ball size and pitch are reduced. Standard ball layout cannot be used. On the other hand, the fan-out semiconductor package has a configuration in which the I / O terminals are redistributed and arranged to the outside of the semiconductor chip by the connecting member formed on the semiconductor chip in this way. Even if the size is reduced, the standardized ball layout can be used as it is. Therefore, as described later, a semiconductor chip can be mounted on a main board of an electronic device without using another interposer substrate as described above.

  FIG. 8 is a cross-sectional view schematically showing a case where the fan-out semiconductor package is mounted on the main board of the electronic device.

  Referring to the drawing, the fan-out semiconductor package 2100 can be mounted on a main board 2500 of an electronic device via solder balls 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 has been standardized to form the connecting member 2140 on the semiconductor chip 2120 that can redistribute the connection pads 2122 up to the fan-out region exceeding the size of the semiconductor chip 2120. The ball layout can be used as it is. As a result, the semiconductor chip 2120 can be mounted on the main board 2500 of the electronic device without a separate interposer substrate.

  As described above, since the fan-out semiconductor package can be mounted on the main board of the electronic device without a separate interposer substrate, the package is smaller in thickness than the fan-in semiconductor package using the interposer substrate. The dimensions can be realized, and the size and thickness can be reduced. Moreover, since it is excellent in thermal characteristics and electrical characteristics, it is particularly suitable for mobile products. Further, it can be realized more compactly than a general POP (Package on Package) type using a printed circuit board (PCB), and the problem caused by the warping phenomenon can be solved.

  On the other hand, the fan-out semiconductor package means a packaging technique for mounting a semiconductor chip on a main board of an electronic device as described above and for protecting the semiconductor chip from an external shock. On the other hand, a mounting method using a printed circuit board (PCB) such as an interposer substrate in which a fan-in semiconductor package is built is a mounting method that differs in scale, application, and the like from a mounting method based on a fan-out semiconductor package.

  In the following, despite the inclusion of a plurality of semiconductor chips, it is possible to reduce the thickness and size, and to reduce noise by minimizing the connection distance between the chips, low cost and high yield A fan-out semiconductor package that can be manufactured in the manufacturing process will be described with reference to the drawings.

  FIG. 9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.

  FIG. 10 is a schematic cross-sectional view of the fan-out semiconductor package of FIG. 9 taken along the line II ′.

  Referring to the drawing, a fan-out semiconductor package 100A according to an example includes a first coupling member 110 having a through hole 110H, an active surface disposed in the through hole 110H of the first coupling member 110, and a connection pad 122P. A first chip package 120 containing a first semiconductor chip 122 having a non-active surface disposed on the opposite side of the active surface, and a seal for sealing at least a part of the first connecting member 110 and the first chip package 120. The second chip package including the second semiconductor chip 181 disposed on the stoppers 130a and 130b, the second coupling member 140 disposed on the sealing materials 130a and 130b and facing the active surface, and the second coupling member 140. 180, and a third chip package 190 disposed on the second connecting member 140 and including the third semiconductor chip 191. No. The first connecting member 110 includes rewiring layers 112a and 112b that are electrically connected to the connection pads 122P. The second connecting member 140 includes a rewiring layer 142 that is electrically connected to the connection pad 122P. The first chip package 120, the second chip package 180, and the third chip package 190 are electrically connected to each other through a rewiring layer 142 included in the second connection member 140.

  As described above, the fan-out semiconductor package 100A according to the example can first rewire the first semiconductor chip 122 by introducing the first chip package 120. In addition, by introducing the first connecting member 110 having the rewiring layers 112a and 112b and the second connecting member 140 having the rewiring layer 142, the wiring can be designed compactly. As a result, the thickness or size of the fan-out semiconductor package 100A can be minimized, the connection distance between chips can be shortened, and the fan-out semiconductor package 100A can be manufactured at low cost and high yield. In particular, by introducing the first semiconductor chip 122 in the form of the first chip package 120, the thickness of the sealing materials 130a and 130b that may occur when the first semiconductor chip 122 is disposed in the through hole 110H of the first connecting member 110. Unevenness can be minimized. Further, an insulating material such as ABF can be used as the material of the sealing materials 130a and 130b, and the cost can be further reduced as compared with the case where an insulating material such as PID resin is used.

  Hereinafter, each configuration included in the fan-out semiconductor package 100A according to an example will be described in more detail.

  The first connecting member 110 includes the rewiring layers 112a and 112b for rewiring the connection pads 122P of the first semiconductor chip 122, so that the number of the rewiring layers 142 of the second connecting member 140 can be reduced. . If necessary, the rigidity of the package 100A can be further improved in accordance with a specific material, and the role of ensuring the thickness uniformity of the sealing materials 130a and 130b can be achieved. The first connection member 110 allows the fan-out semiconductor package 100A according to an example to be used as a part of a package on package. The first connecting member 110 has a through hole 110H. The first chip package 120 is disposed in the through hole 110H so as to be separated from the first connecting member 110 by a predetermined distance. The periphery of the side surface of the first chip package 120 may be surrounded by the first connection member 110. However, this is merely an example, and various modifications can be made to other forms, and other functions can be performed depending on the form.

  The first connecting member 110 passes through the insulating layer 111, the first rewiring layer 112a formed on the lower surface of the insulating layer, the second rewiring layer 112b formed on the upper surface of the insulating layer, A via 113 electrically connecting the first rewiring layer 112a and the second rewiring layer 112b and a metal layer 115 disposed on the wall surface of the through hole 110H are included.

  The material of the insulating layer 111 is not particularly limited, and for example, an insulating substance can be used. At this time, as the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or such a resin is impregnated in a core material such as glass fiber (Glass Fiber, Glass Close, Glass Fabric) together with an inorganic filler. Resin such as prepreg or unclad copper clad laminate (Uncladd CCL) may be used.

  As a material for forming the rewiring layers 112a and 112b, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) ), Or conductive materials such as alloys thereof. The redistribution layers 112a and 112b can perform various functions. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (Signal: S) pattern, and the like can be included. Here, the signal (S) pattern includes various signals excluding a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. In addition, a via pad, a wire pad, a connection terminal pad, and the like can be included.

  The rewiring layers 112a and 112b may be thicker than the rewiring layer 142 of the second connecting member 140. Since the first connecting member 110 can have a thickness equal to or greater than that of the first semiconductor chip 122, the redistribution layers 112a and 112b can be formed in a larger size according to the scale. On the other hand, the rewiring layer 142 of the second connecting member 140 can be formed relatively small in order to reduce the thickness.

  The via 113 electrically connects the redistribution layers 112 a and 112 b formed in different layers, and as a result, forms an electrical path in the first connection member 110. As the formation material of the via 113, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or these A conductive substance such as an alloy of the above can be used. The via 113 may be completely filled with a conductive material, or the conductive material may be formed along the wall surface of the via hole. Further, not only a cylindrical shape but also all known shapes such as an hourglass shape can be applied.

  The metal layer 115 has an additional configuration and can effectively release heat generated from the first chip package 120, and can effectively block electromagnetic waves generated from the first chip package 120. Can do. The metal layer 115 is made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The conductive material may be included. The metal layer 115 is disposed on the wall surface of the through hole 110H, and can surround the side surface of the first chip package 120 without being cut off. The metal layer 115 may be connected to a ground (GND) pattern as necessary to perform a ground function.

  The first chip package 120 is disposed on the active surface of the first semiconductor chip 122, the resin layer 123 surrounding at least a part of the first semiconductor chip 122, and the first semiconductor chip 122, and electrically connected to the connection pads 122P. The interconnect layer 124b is connected to the resin layer 123. The metal layer 125 is disposed on the resin layer 123 and faces the inactive surface of the first semiconductor chip 122. The wiring layer 124b is disposed on the insulating layer 124a disposed on the active surface of the first semiconductor chip 122, and is connected to the connection pad 122P through the via 124c penetrating the insulating layer 124a.

  The first semiconductor chip 122 may be an integrated circuit (IC) in which several hundred to several million elements or more are integrated in one chip. The integrated circuit includes, for example, a central processor (eg, CPU), a graphic processor (eg, GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an application processor chip such as a microcontroller, Specifically, it may be an application processor chip (Application Processor: AP), or an analog-digital converter, an ASIC (Application-Specific IC) logic chip, but is not limited thereto.

  The first semiconductor chip 122 may be an integrated circuit (IC) formed using an active wafer as a base. In this case, as a base material constituting the main body, silicon (Si), germanium (Ge), gallium are used. Arsenic (GaAs) or the like can be used. Various circuits can be formed on the main body. The connection pad 122P is for electrically connecting the first semiconductor chip 122 to other components, and a conductive material such as aluminum (Al) is used without particular limitation as a forming material thereof. be able to. A passivation film exposing the connection pads 122P can be formed on the main body. The passivation film may be an oxide film or a nitride film, or may be a double layer of an oxide film and a nitride film. Further, other insulating films may be disposed.

  The resin layer 123 includes an insulating material. In this case, the insulating substance includes a material containing an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or an inorganic filler such as silica or alumina. A resin containing a reinforcing material, specifically, ABF (Ajinomoto Build-up Film) or the like can be used.

  The insulating layer 124a includes an insulating material. At this time, a photosensitive insulating material such as a PID resin can be used as the insulating material. That is, the insulating layer 124a can be a photosensitive insulating layer. When the insulating layer 124a is composed of multiple layers, the materials of the respective insulating layers may be the same as each other or may be different from each other as necessary. When the insulating layer 124a is composed of multiple layers, they may be integrated by a process, and the boundary may be unclear.

  The wiring layer 124b primarily rewires the connection pads 122P. Forming substances include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The conductive material can be used. The wiring layer 124b can have various functions. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (Signal: S) pattern, and the like can be included. Here, the signal (S) pattern includes various signals excluding a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. In addition, a via pad or the like can be included.

  The via 124c electrically connects the wiring layer 124b formed in different layers and the connection pad 122P. As a material for forming the via 124c, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or these A conductive substance such as an alloy of the above can be used. The via 124c may be completely filled with a conductive material, or the conductive material may be formed along the wall surface of the via hole. Moreover, not only a taper shape but all shapes well-known in the said technical field, such as a cylindrical shape, can be applied.

  The metal layer 125 has an additional structure and releases heat generated from the inactive surface of the first semiconductor chip 122 to the lower portion of the package 100A. In addition, electromagnetic waves generated from the first semiconductor chip 122 can be effectively blocked. The metal layer 125 is made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The conductive material may be included. The metal layer 125 is disposed on the resin layer 123 and covers the inactive surface of the first semiconductor chip 122. The metal layer 125 may be connected to a front side via 133b described later and electrically connected to the front side rewiring layer 132b. Similarly, the metal layer 125 may be connected to a ground (GND) pattern to perform a ground function.

  The sealing materials 130a and 130b can protect the first connecting member 110, the first chip package 120, and the like. The sealing form is not particularly limited, and may be a form surrounding at least a part of the first connecting member 110, the first chip package 120, and the like. For example, the first sealing member 130 a can cover the first connecting member and the upper side of the first chip package 120, and fills the space between the wall surface of the through hole 110 </ b> H and the side surface of the first chip package 120. it can. In addition, the second sealing material 130 b may cover the lower side of the first connecting member 110 and the first chip package 120.

  The sealing materials 130a and 130b include an insulating material. In this case, the insulating substance includes a material containing an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a reinforcing material such as an inorganic filler. Resin, specifically, ABF or the like can be used. When ABF, which is a non-photosensitive insulating material, is used as the sealing materials 130a and 130b, laser hole machining is possible when forming the back side via 133a or the front side via 133b, so compared with the case where PID resin is used. Costs can be reduced, and further excellent fluidity can be more effective in ensuring thickness uniformity.

  The backside rewiring layer 132a is disposed on the first sealing material 130a. The backside redistribution layer 132a can redistribute the connection pads 122P together with the redistribution layer 142, and can electrically connect the first to third chip packages 120, 180, and 190. As a material for forming the backside rewiring layer 132a, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) ), Or conductive materials such as alloys thereof. The backside rewiring layer 132a can perform various functions according to the design design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (Signal: S) pattern, and the like can be included. Here, the signal (S) pattern includes various signals excluding a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. In addition, a via pad, a connection terminal pad, and the like can be included.

  The backside via 133a penetrates the first sealing material 130a and electrically connects the backside rewiring layer 132a to the first chip package 120 and the second rewiring layer 112b of the first connecting member 110. Since the back side via 133a may be a laser via, it can be formed at a relatively low cost. As the material for forming the backside via 133a, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), Alternatively, a conductive material such as an alloy of these can be used. The backside via 133a may be completely filled with a conductive material, or the conductive material may be formed along the wall surface of the via hole. Various shapes such as a tapered shape and a cylindrical shape can be applied.

  The front side rewiring layer 132b is disposed on the second sealing material 130b. Due to the presence of the front side rewiring layer 132b, an electrical path can be formed in the lower portion of the package 100A, and electrical connection to the outside is also possible. As a material for forming the front side rewiring layer 132b, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) ), Or conductive materials such as alloys thereof. The backside rewiring layer 132a can perform various functions according to the design design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (Signal: S) pattern, and the like can be included. Here, the signal (S) pattern includes various signals excluding a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. In addition, a via pad, a connection terminal pad, and the like can be included.

  The front side via 133 b penetrates the second sealing material 130 b and electrically connects the front side rewiring layer 132 b to the first rewiring layer 112 a of the first connecting member 110. When the first chip package 120 includes the metal layer 125, the front side rewiring layer 132 b can be electrically connected to the metal layer 125 of the first chip package 120. Since the front side via 133b may be a laser via, it can be formed at a relatively low cost. As a material for forming the front side via 133b, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), Alternatively, a conductive material such as an alloy of these can be used. The front side via 133b may be completely filled with a conductive material, or the conductive material may be formed along the wall surface of the via hole. Various shapes such as a tapered shape and a cylindrical shape can be applied.

  The second connecting member 140 can rewiring the connection pads 122P of the first semiconductor chip 122. In addition, the first chip package 120, the second chip package 180, and the third chip package 190 can be electrically connected through a short path by the second connection member 140. The second connecting member 140 includes an insulating layer 141, a rewiring layer 142 disposed on the insulating layer 141, and a via 143 that penetrates the insulating layer 141 and connects the rewiring layer 142. The second connecting member 140 may be formed of a single layer, or may be designed with a plurality of layers having a larger number than the drawing.

  An insulating material can be used as the material of the insulating layer 141. At this time, a photosensitive insulating material such as a PID resin can be used as the insulating material in addition to the insulating material as described above. That is, the insulating layer 141 may be a photosensitive insulating layer. When the insulating layer 141 has photosensitivity, the insulating layer 141 can be formed thinner, and the fine pitch of the vias 143 can be achieved more easily. The insulating layer 141 may be a photosensitive insulating layer containing an insulating resin and an inorganic filler. When the insulating layer 141 is composed of multiple layers, the materials of the respective insulating layers may be the same as each other, or may be different from each other as necessary. When the insulating layer 141 is composed of multiple layers, they may be integrated by a process, and the boundary may be unclear.

  The rewiring layer 142 can rewiring the connection pads 122P. In addition, the first to third chip packages 120, 180, and 190 can be electrically connected. As a material for forming the rewiring layer 142, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), Alternatively, a conductive material such as an alloy of these can be used. The rewiring layer 142 can perform various functions according to the design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (Signal: S) pattern, and the like can be included. Here, the signal (S) pattern includes various signals excluding a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal. In addition, a via pad, a connection terminal pad, and the like can be included.

  A surface treatment layer (not shown) can be further formed on the exposed surface of the redistribution layer 142 as necessary. The surface treatment layer (not shown) is formed by, for example, electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / displacement gold plating, DIG plating, HASL, etc. However, it is not particularly limited.

  The via 143 electrically connects the rewiring layer 142 and the backside rewiring layer 132a formed in different layers. As a material for forming the via 143, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or these A conductive substance such as an alloy of the above can be used. The via 143 may be completely filled with a conductive material, or the conductive material may be formed along the wall surface of the via hole. Various shapes such as a tapered shape and a cylindrical shape can be applied.

  The first passivation layer 150 is an additional structure that protects the lower part of the package 100A from physical damage or chemical erosion from the outside. The first passivation layer 150 may have an opening that exposes at least a portion of the front side rewiring layer 132b. Several tens to thousands of such openings can be formed in the first passivation layer 150. The first passivation layer 150 includes an insulating resin and an inorganic filler, but may not include glass fibers. For example, the first passivation layer 150 may be ABF, but is not limited thereto, and may be an insulating material including a photosensitive material, for example, a solder resist.

  The under bump metal layer 160 is an additional configuration that improves the connection reliability of the connection terminal 170 and, as a result, improves the board level reliability of the package 100A. . The under bump metal layer 160 is connected to the front side rewiring layer 132 b exposed through the opening of the passivation layer 150. The under bump metal layer 160 can be formed by metallizing the opening of the first passivation layer 150 using a metal such as copper (Cu).

  The connection terminal 170 is an additional configuration for physically and / or electrically connecting the fan-out semiconductor package 100A to the outside. For example, the fan-out semiconductor package 100A can be mounted on the main board of the electronic device via the connection terminal 170. The connection terminal 170 can be formed of a conductive material such as solder, but this is only an example, and the material is not particularly limited thereto. The connection terminal 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be composed of multiple layers or a single layer. In the case of multiple layers, it can include copper pillars and solder, and in the case of a single layer, it can include tin-silver solder and copper. It is not limited to.

  The number, interval, arrangement form, and the like of the connection terminals 170 are not particularly limited, and can be sufficiently deformed by a normal engineer according to design matters. For example, the number of connection terminals 170 may be several tens to several thousand, depending on the number of connection pads 122P of the first semiconductor chip 122, and may have a number greater than or less than that. When the connection terminal 170 is a solder ball, the connection terminal 170 can cover the side surface of the under bump metal layer 160 that is formed by extending on the one surface of the first passivation layer 150, thereby further improving the connection reliability. it can.

  At least one of the connection terminals 170 is disposed in a fan-out region. The fan-out area means a redistribution area extending outside the area where the first semiconductor chip 122 is disposed. That is, the semiconductor package 100A according to an example is a fan-out package. The fan-out package has higher reliability than the fan-in package, can realize a large number of I / O terminals, and has a 3D connection. Is easy. Further, compared to a BGA (Ball Grid Array) package, an LGA (Land Grid Array) package, etc., the thickness of the package can be reduced, and the price competitiveness is excellent.

  The second passivation layer 155 is an additional structure for protecting the upper portion of the package 100A from physical damage or chemical erosion from the outside. The second passivation layer 155 may have an opening that exposes at least part of the backside redistribution layer 132a. Several tens to thousands of such openings can be formed in the second passivation layer 155. The second passivation layer 155 includes an insulating resin and an inorganic filler, but may not include glass fibers. For example, the second passivation layer 155 may be ABF, but is not limited thereto, and may be an insulating material including a photosensitive material, for example, a solder resist.

  Each of the second chip package 180 and the third chip package 190 may be a stacked package in which a plurality of second semiconductor chips 181 and a plurality of third semiconductor chips 191 are stacked. The plurality of second semiconductor chips 181 and the plurality of third semiconductor chips 191 are each a memory such as a volatile memory (for example, DRAM), a nonvolatile memory (for example, ROM), and a flash memory (for example, Nand Flash). Can be. That is, the second chip package 180 and the third chip package 190 may be HBM (High Bandwidth Memory), WIO (Wide I / O), etc., but are not limited thereto. The plurality of second semiconductor chips 181 stacked one above the other can be connected via the first connection member 182. Similarly, the plurality of third semiconductor chips 191 stacked one above the other can be connected via the second connecting member 192. The first connecting member 182 and the second connecting member 192 may each be a through silicon via (TSV) or a bump formed of a conductive material, but are not limited thereto. It is not something. The second chip package 180 and the third chip package 190 may be connected to the exposed redistribution layer of the second connection member 140 through the first connection terminal 183 and the second connection terminal 193, respectively. The first connection terminal 183 and the second connection terminal 193 may be solder balls or solder bumps, respectively, but are not limited thereto.

  FIGS. 11a and 11b show a schematic example of manufacturing the first chip package of FIG.

  Referring to FIG. 11a, first, a substrate 121 having a cavity 121H is prepared. The substrate 121 includes an insulating material, and may be, for example, a prepreg, an unclad copper clad laminate (Uncladd CCL), or the like. The cavity 121H penetrates the substrate 121 and can be formed by a laser drill or a mechanical drill. Next, the substrate 121 is attached to the adhesive film 201. The adhesive film 201 can be a known tape. Next, the first semiconductor chip 122 is attached on one surface of the adhesive film 201 exposed through the cavity 121H of the substrate 121. The first semiconductor chip 122 may be attached in a face-down manner such that the active surface is in contact with the adhesive film 201.

  Referring to FIG. 11b, the resin layer 123 is subsequently formed. The resin layer 123 may be ABF or the like, and can be formed by laminating or applying the precursor of the resin layer 123 and then curing. In addition, the adhesive film 201 is peeled, and the insulating layer 124a is formed by laminating PID on the active surface of the first semiconductor chip 122 from which the adhesive film 201 has been peeled, or by applying and curing. Thereafter, a hole penetrating the insulating layer 124a is formed by photolithography. Next, after forming a pattern with a dry film or the like, the wiring layer 124b and the via 124c are formed by a process of filling the hole and pattern with plating and etching the seed layer. A plurality of first chip packages 120 are manufactured through a series of processes. Next, the metal layer 125 is formed on the resin layer 123 by sputtering or the like. Next, a plurality of first chip packages 120 are sawed by performing a sawing process. The substrate 121 can be removed by adjusting the width of dicing in the sawing process, but the substrate 121 can be left as described later.

  12a to 12d are schematic diagrams showing an example of manufacturing the fan-out semiconductor package of FIG.

  Referring to FIG. 12a, first, an insulating layer 111 is prepared. Metal films 111c and 111d can be formed on both surfaces of the insulating layer 111 for the convenience of a plating process or the like. Such an insulating layer 111 may be, for example, a copper clad laminate (CCL), but is not limited thereto. Next, a through hole 110H that penetrates the insulating layer 111 is formed. At the same time or separately, a hole for the via 113 is formed. Then, after forming a pattern with a dry film or the like, the rewiring layers 112a and 112b, the via 113, and the metal layer 115 are formed through a process of filling the holes and the pattern with plating and etching the seed layer. The first connecting member 110 is manufactured through a series of processes. Next, the first connecting member 110 is attached to the adhesive film 202. The adhesive film 202 can be a known tape.

  Referring to FIG. 12b, the first chip package 120 manufactured previously is attached on one surface of the adhesive film 202 exposed through the through hole 110H of the first connecting member 110. The first chip package 120 may be attached in a face-up manner so that the inactive surface of the first semiconductor chip 122 faces the adhesive film 202. Next, a first sealing material 130 a that seals at least a part of the first connecting member 110 and the first chip package 120 is formed. The first sealing material 130a may be ABF or the like, and can be formed by laminating or applying a precursor of the first sealing material 130a and then curing. Since ABF has easy resin fluidity, when it is used as the material of the first sealing material 130a, the space between the wall surface of the through hole 110H of the first connecting member 110 and the side surface of the first chip package 120 is used. Can be easily met. Next, the adhesive film 202 is peeled off. Next, at least a part of the first connection member 110 and the first chip package 120 is formed on the first rewiring layer 112a of the first connection member 110 and the metal layer 125 of the first chip package 120 from which the adhesive film 202 has been peeled off. A second sealing material 130b to be sealed is formed. The second sealing material 130b may be ABF or the like, and can be formed by laminating or applying a precursor of the second sealing material 130b and then curing.

  Referring to FIG. 12c, in order to form the back side via 133a and the front side via 133b, holes are formed through the first sealing material 130a and the second sealing material 130b, respectively. At this time, since the first sealing material 130a and the second sealing material 130b can include a non-photosensitive insulating material, a hole can be formed using a laser drill or a mechanical drill. As a result, process costs can be reduced. Then, after forming a pattern on each of the first sealing material 130a and the second sealing material 130b with a dry film or the like, the backside rewiring is performed through a process of filling the hole and the pattern with plating and etching the seed layer. A layer 132a, a back side via 133a, a front side rewiring layer 132b, and a front side via 133b are formed. Next, the first passivation layer 150 having an opening exposing at least a part of the front side rewiring layer 132b is formed on the second sealing material 130b. The first passivation layer 150 can be formed by a method in which a solder resist precursor or the like is laminated or applied and then cured. On the other hand, the first passivation layer 150 may be formed after a second connecting member 140 described later is formed. That is, the order of steps may be different.

  Referring to FIG. 12d, next, the second connecting member 140 is formed on the first sealing material 130a. The second connecting member 140 forms an insulating layer 141 that embeds the backside rewiring layer 132a on the first sealing material 130a, and has a hole for forming the via 143 in the insulating layer 141 by using a photolithography method or the like. Then, a pattern is formed using a dry film or the like on the insulating layer 141, the rewiring layer 142 and the via 143 are formed by a method that fills the hole and the pattern by plating or the like, and the above process is repeated. be able to. Next, a second passivation layer 155 having an opening exposing at least a part of the rewiring layer 142 of the second connecting member 140 is formed on the second connecting member 140. The second passivation layer 155 can be formed by a method of laminating a solder resist precursor or the like, or applying and curing. On the other hand, the second passivation layer 155 can be formed together when the first passivation layer 150 is formed after the second connecting member 140 is formed. Next, the second chip package 180 and the third chip package 190 prepared in advance are mounted on the second passivation layer 155. Further, the under bump metal layer 160 and the connection terminal 170 are formed on the first passivation layer 150 using a known method. The fan-out semiconductor package 100A according to the above example can be manufactured through a series of processes.

  FIG. 13 is a cross-sectional view schematically showing another example of a fan-out semiconductor package.

  Referring to the drawing, a fan-out semiconductor package 100B according to another example further includes a substrate 121 in which the first chip package 120 has a cavity 121H in the above-described fan-out semiconductor package 100A. That is, the substrate 121 can be left in the first chip package 120 by adjusting the dicing width in the manufacturing process of the first chip package 120. In this case, it can be effective for warpage control and the like. The first semiconductor chip 122 may be disposed in the cavity 121 </ b> H, and the substrate 121 may remain so as to surround the periphery of the side surface of the first semiconductor chip 122.

  Other configurations not described are substantially the same as the description of the fan-out semiconductor package 100A according to an example, and thus detailed description thereof is omitted.

  FIG. 14 is a cross-sectional view schematically showing another example of a fan-out semiconductor package.

  Referring to FIG. 14, a fan-out semiconductor package 100C according to another example includes a first connecting member 110 that is in contact with a second sealing material 130b, a first insulating layer 111a that is in contact with the second sealing material 130b, and a second sealing material 130b. A first redistribution layer 112a embedded in the first insulation layer 111a, a second redistribution layer 112b disposed on the opposite side of the first insulation layer 111a from the side where the first redistribution layer 112a is embedded, A second insulating layer 111b disposed on the first insulating layer 111a and covering the second rewiring layer 112b; and a third rewiring layer 112c disposed on the second insulating layer 111b. The first to third redistribution layers 112a, 112b, and 112c are electrically connected to the connection pad 122P. The first and second redistribution layers 112a and 112b and the second and third redistribution layers 112b and 112c are respectively connected via first and second vias 113a and 113b that penetrate the first and second insulating layers 111a and 111b. Are electrically connected.

  When the first redistribution layer 112a is embedded in the first insulating layer 111a, a step generated due to the thickness of the first redistribution layer 112a can be minimized. The first redistribution layer 112a may be recessed inside the first insulating layer 111a. As a result, the lower surface of the first insulating layer 111a and the lower surface of the first redistribution layer 112a can have a step. Accordingly, it is possible to prevent the material forming the first sealing material 130a from bleeding and contaminating the first rewiring layer 112a.

  The rewiring layers 112a, 112b, and 112c of the first connecting member 110 may be thicker than the rewiring layer 142 of the second connecting member 140. Since the first connecting member 110 can have a thickness equal to or greater than that of the first semiconductor chip 122, the redistribution layers 112a, 112b, and 112c can be formed in a larger size according to the scale. On the other hand, the rewiring layer 142 of the second connecting member 140 can be formed in a relatively small size for thinning.

  The other configuration or manufacturing method is substantially the same as the description of the fan-out semiconductor package 100A according to the example, and thus the detailed description is omitted. On the other hand, it goes without saying that the feature of the fan-out semiconductor package 100B according to another example can be applied to the fan-out semiconductor package 100C according to another example.

  FIG. 15 is a cross-sectional view schematically showing another example of a fan-out semiconductor package.

  Referring to FIG. 15, a fan-out semiconductor package 100D according to another example includes a first connection member 110 having a first insulating layer 111a and first redistribution layers 112a disposed on both surfaces of the first insulating layer 111a. A second redistribution layer 112b, a second insulation layer 111b disposed on the first insulation layer 112a and covering the first redistribution layer 112a, and a third redistribution layer 112c disposed on the second insulation layer 111b A third insulating layer 111c disposed on the first insulating layer 111a and covering the second rewiring layer 112b, and a fourth rewiring layer 112d disposed on the third insulating layer 111c. The first to fourth redistribution layers 112a, 112b, 112c, and 112d are electrically connected to the connection pad 122P. Since the first connecting member 110 includes a larger number of rewiring layers 112a, 112b, 112c, and 112d, the second connecting member 140 can be further simplified. Accordingly, it is possible to improve a decrease in yield due to a defect that occurs in the process of forming the second connecting member 140. On the other hand, the first to fourth redistribution layers 112a, 112b, 112c, and 112d are electrically connected via the first to third vias 113a, 113b, and 113c that penetrate the first to third insulating layers 111a, 111b, and 111c, respectively. Can be linked together.

  The first insulating layer 111a may be thicker than the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a basically needs to be relatively thick in order to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c form a larger number of redistribution layers 112c and 112d. It may be introduced to do so. The first insulating layer 111a may include an insulating material different from the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may include a glass fiber, an inorganic filler, and an insulating resin. For example, the first insulating layer 111a may be a prepreg, and the second insulating layer 111c and the third insulating layer 111c include an inorganic filler and an insulating resin. Although it may be an ABF film or a PID film, it is not limited to this. From the same viewpoint, the first via 113a that penetrates the first insulating layer 111a only needs to have a larger diameter than the second and third vias 113b and 113c that penetrate the second and third insulating layers 111b and 111c.

  The rewiring layers 112a, 112b, 112c, and 112d of the first connecting member 110 may be thicker than the rewiring layer 142 of the second connecting member 140. Since the first connecting member 110 can have a thickness equal to or greater than that of the first semiconductor chip 122, the rewiring layers 112a, 112b, 112c, and 112d can also be formed to a larger size. On the other hand, the rewiring layer 142 of the second connecting member 140 can be formed in a relatively small size for thinning.

  The other configuration or manufacturing method is substantially the same as the description of the fan-out semiconductor package 100A according to the example, and thus the detailed description is omitted. On the other hand, it goes without saying that the feature of the fan-out semiconductor package 100B according to another example can be applied to the fan-out semiconductor package 100D according to another example.

  In the present invention, “lower, lower, lower surface” and the like mean directions toward the mounting surface of the fan-out semiconductor package with reference to the cross section of the attached drawings, and “upper, upper, upper surface” and the like It means the opposite direction. However, this defines a direction for convenience of explanation, and it is needless to say that the scope of claims is not limited thereto.

  In the present invention, “connected” is a concept that includes not only a direct connection but also an indirect connection. Further, “electrically connected” is a concept that includes both a case where they are physically connected and a case where they are not connected. The first and second expressions are used to distinguish one component from another component, and do not limit the order and / or importance of the corresponding component. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component without departing from the scope of the present invention.

  The expression “one example” or “another example” as used in the present invention does not mean the same embodiment as each other, but is provided to emphasize and explain different and unique features. However, the presented example does not exclude being realized in combination with other example features. For example, even if a matter described in a specific example is not explained in another example, the explanation is related to the other example as long as there is no explanation contrary to or contradicting the matter in another example. Can be understood.

  Note that the terms used in the present invention are merely used to describe an example, and are not intended to limit the present invention. At this time, the singular includes the plural unless the context clearly indicates otherwise.

1000 Electronic equipment 1010 Main board 1020 Chip related parts 1030 Network related parts 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 Signal line 1100 Smartphone 1101 Main body 1110 Main board 1120 Parts 1130 Camera 2200 Fan-in semiconductor package 2220 Semiconductor chip 2221 Body 2222 Connection pad 2223 Passivation film 2240 Connecting member 2241 Insulating layer 2242 Rewiring layer 2243 Via 2250 Passivation layer 2260 Under bump metal layer 2270 Solder ball 2280 Underfill resin 2290 Molding material 2500 Main board 2301 Interposer substrate 2302 Interposer Substrate 2100 Fan-out semiconductor package 2120 Semiconductor chip 2121 Main body 2122 Connection pad 2140 Connecting member 2141 Insulating layer 2142 Redistribution layer 2143 Via 2150 Passivation layer 2160 Under bump metal layer 2170 Solder ball 100 Semiconductor package 100A to 100D Fan-out semiconductor package 110 First connecting member 111, 111a, 111b, 111c Insulating layer 112a, 112b, 112c, 112d Redistribution layer 113, 113a, 113b, 113c Via 120 First chip package 121 Substrate 122 First semiconductor chip 122P Connection pad 123 Resin layer 124a Insulating layer 124b Wiring layer 124c Via 125 Metal layer 130a, 130b Sealing material 140 Second connecting member 141 Edge layer 142 Redistribution layer 143 Via 132a Backside redistribution layer 133a Backside via 132b Front side redistribution layer 133b Front side via 150, 155 Passivation layer 160 Under bump metal layer 170 Connection terminal 180 Second chip package 181 Second semiconductor Chip 182 First connection member 183 First connection terminal 190 Third chip package 191 Third semiconductor chip 192 Second connection member 193 Second connection terminal 201, 202 Adhesive film

Claims (14)

Have a through-hole, a first connecting member including a first redistribution layer of one or more layers,
A first semiconductor chip disposed in a through-hole of the first connecting member and having an active surface on which a connection pad is disposed and a non-active surface disposed on the opposite side of the active surface ; at least a portion of the first semiconductor chip A resin layer covering the first insulating layer, a first insulating layer disposed on the active surface of the first semiconductor chip, a wiring layer disposed on the first insulating layer, the connection pad penetrating through the first insulating layer, and A first chip package including a first via for electrically connecting the wiring layers ;
A sealing material for sealing at least a part of the first connecting member and the first chip package;
A backside rewiring layer disposed on the encapsulant and facing the active surface of the first semiconductor chip;
A backside via that penetrates the sealing material and electrically connects the backside rewiring layer to the first rewiring layer of the first connecting member and the wiring layer of the first chip package;
A second insulating layer disposed on the sealing material and covering the backside rewiring layer; a second rewiring layer disposed on the second insulating layer; and the second insulating layer; A second connecting member including a second via that electrically connects the two rewiring layers to the backside rewiring layer ;
A second semiconductor chip disposed on the second connection member and electrically connected to the first semiconductor chip through the second connection member ;
The first insulating layer includes a photosensitive insulating material;
The encapsulant includes a non-photosensitive insulating material;
The fan-out semiconductor package , wherein the second insulating layer includes a photosensitive insulating material . The wiring layer is a fan of the first semiconductor chip - is extended to out area, the fan according to claim 1 - out semiconductor package. The first chip package further includes a substrate having a cavity,
Wherein the first semiconductor chip is disposed in the cavity, the fan according to claim 1 or claim 2 - out semiconductor package. Wherein the first chip package, the disposed on the resin layer, wherein the first further comprising a metal layer facing the non-active surface of the semiconductor chip, the fan according to any one of claims 1 to 3 - Out Semiconductor package. A front side rewiring layer disposed on the encapsulant and facing the inactive surface of the first semiconductor chip ;
The fan-out semiconductor package according to claim 4 , further comprising a front side via that penetrates the sealing material and electrically connects the front side rewiring layer to the metal layer. The sealing material covers the upper side of the first connecting member and the first chip package, and fills a space between the wall surface of the through hole and the side surface of the first chip package; The fan-out semiconductor package according to any one of claims 1 to 5 , further comprising: a first connecting member and a second sealing material that covers a lower side of the first chip package. The backside rewiring layer is disposed on the first sealing material so as to face the active surface of the first semiconductor chip,
The backside via penetrates the first sealing material and electrically connects the backside rewiring layer to the first rewiring layer of the first connecting member and the wiring layer of the first chip package ; The fan-out semiconductor package according to claim 6 . A front side rewiring layer disposed on the second encapsulant and facing the inactive surface of the first semiconductor chip ;
Through the second sealing member, further comprising a front side via the front side rewiring layer is first redistribution layer electrically connected in the first connection member, according to claim 6 or claim 7 A fan-out semiconductor package according to claim 1. A passivation layer disposed on the front side redistribution layer and having a first opening exposing at least a portion of the front side redistribution layer;
An under bump metal layer disposed on the first opening;
The fan-out semiconductor package according to claim 8 , further comprising a connection terminal disposed on the under bump metal layer. Said second semiconductor chip before SL on the second coupling member and the second chip package of a plurality laminated structure are disposed, fan according to any one of claims 1 to 9 - out semiconductor package . The first connection member has a first -1 insulating layer, the sealing material and in contact with, the first -1 redistribution layer embedded in the first -1 insulating layer, the first -1 insulating layer wherein including a first-second redistribution layer first -1 redistribution layer is disposed on the opposite side of the embedded side, a fan according to any one of claims 1 to 10 - Out semiconductor package. The first coupling member may be disposed on the first -1 insulating layer, and the first-second insulating layer covering the first-second redistribution layer, disposed on the first-second insulating layer 1 further includes 3 rewiring layer, the fan according to claim 11 - out semiconductor package. The first connection member has a second-first insulating layer, a second-first redistribution layer and the 2-second redistribution layer disposed on both surfaces of the second-first insulating layer, the second-1 disposed on the insulating layer includes a second-second insulating layer covering the second-first redistribution layer, and the 2-3 redistribution layer disposed on the second-second insulating layer, and wherein The fan-out semiconductor package according to any one of claims 1 to 10 . The first coupling member may be disposed on the second-first insulating layer, a second-third insulating layer covering the second-second redistribution layer, disposed on the second-third insulating layer The fan-out semiconductor package according to claim 13 , further comprising a 2-4 redistribution layer.