KR102620892B1 - Fan-out semiconductor package - Google Patents

Abstract

The present disclosure relates to a frame including one or more insulating layers and one or more wiring layers and having a through portion penetrating the one or more insulating layers, a semiconductor chip disposed in the through portion of the frame and having a connection pad, and a lower side of the frame and the semiconductor chip. A connection structure disposed in and including a redistribution layer electrically connected to the connection pad, and at least a portion of the upper surface of the semiconductor chip and at least a portion of the uppermost insulating layer of one or more insulating layers of the frame and one layer of the frame Among the above wiring layers, it includes a first encapsulating material that covers at least a portion of the side surface of the uppermost wiring layer, wherein the upper surface of the first encapsulating material is located lower than the upper surface of the uppermost wiring layer and has a step from the upper surface of the uppermost wiring layer, It concerns fan-out semiconductor packages.

Description

Fan-out semiconductor package {FAN-OUT SEMICONDUCTOR PACKAGE}

This disclosure relates to semiconductor packages, such as fan-out semiconductor packages.

One of the major trends in recent semiconductor chip technology development is to reduce the size of components, and as demand for small semiconductor chips increases in the package field, there is a demand for small size and multiple pins. . One of the semiconductor package technologies proposed to comply with this is the fan-out semiconductor package. The fan-out package rewires the electrical connection structure outside the area where the semiconductor chip is placed, making it possible to implement a large number of pins while having a small size.

Meanwhile, in order to improve the electrical characteristics and efficient use of space in recent premium smartphone products, and to apply package on package (POP) to semiconductor packages containing different semiconductor chips, the backside circuit is used in the semiconductor package structure. It is required to form a , and the requirements for the lines and spaces of the backside circuit are increasing in line with the demands for advancement of chip characteristics and reduction of area.

One of the many purposes of the present disclosure is to provide a fan-out semiconductor package that can reduce the thickness of the product and apply a backside circuit with a fine pitch.

One of several solutions proposed through the present disclosure is to introduce a frame that includes one or more wiring layers and have a penetrating portion, and to place a semiconductor chip in the penetrating portion of the frame, wherein the upper surface of the first encapsulant covering the frame and the semiconductor chip is provided. The first encapsulating material is formed to have a level difference with the upper surface of the uppermost wiring layer of the frame.

For example, a semiconductor package according to an example proposed in the present disclosure includes a frame including one or more insulating layers and one or more wiring layers, and having a penetrating portion penetrating the one or more insulating layers; a semiconductor chip disposed in a penetrating portion of the frame and having a connection pad; a connection structure disposed below the frame and the semiconductor chip and including a redistribution layer electrically connected to the connection pad; and a first encapsulating material covering at least a portion of the upper surface of the semiconductor chip, at least a portion of the upper surface of the uppermost insulating layer among one or more layers of insulating layers of the frame, and at least a portion of a side surface of the uppermost wiring layer among one or more layers of insulating layers of the frame. ; It includes, wherein the upper surface of the first encapsulant may be located lower than the upper surface of the uppermost wiring layer and have a level difference with the upper surface of the uppermost wiring layer.

Alternatively, a semiconductor package according to an example proposed in the present disclosure includes a frame including one or more wiring layers and having a through portion; a semiconductor chip disposed in a penetrating portion of the frame and having a connection pad; a connection structure disposed below the frame and the semiconductor chip and including a redistribution layer electrically connected to the connection pad; a first encapsulant that covers at least a portion of each of the frame and the semiconductor chip and fills at least a portion of the penetrating portion; And a second sealant disposed on the first sealant; It includes, and the boundary between the first and second encapsulants may be located at a level between the upper and lower surfaces of the uppermost wiring layer among one or more wiring layers of the frame.

As one of the many effects of the present disclosure, it is possible to provide a fan-out semiconductor package that can apply a backside circuit with a fine pitch while reducing the thickness of the product.

1 is a block diagram schematically showing an example of an electronic device system.
Figure 2 is a perspective view schematically showing an example of an electronic device.
3A and 3B are cross-sectional views schematically showing before and after packaging a fan-in semiconductor package.
Figure 4 is a cross-sectional view schematically showing the packaging process of a fan-in semiconductor package.
Figure 5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device.
Figure 6 is a cross-sectional view schematically showing the case where the fan-in semiconductor package is embedded in a printed circuit board and finally mounted on the main board of an electronic device.
Figure 7 is a cross-sectional view schematically showing a fan-out semiconductor package.
Figure 8 is a cross-sectional view schematically showing a case where a fan-out semiconductor package is mounted on the main board of an electronic device.
Figure 9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.
FIG. 10 is a schematic plan view taken along line I-I' of the fan-out semiconductor package of FIG. 9.
11 to 13 are process diagrams schematically showing an example of manufacturing the fan-out semiconductor package of FIG. 9.
Figure 14 schematically shows another example of a fan-out semiconductor package.

Hereinafter, the present disclosure will be described with reference to the attached drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clearer explanation.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawing, the electronic device 1000 accommodates the main board 1010. The main board 1010 is physically and/or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040. These are combined with other components described later to form various signal lines 1090.

Chip-related components 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as central processors (eg, CPU), graphics processors (eg, GPU), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; Logic chips such as analog-digital converters and ASICs (application-specific ICs) are included, but are not limited to these, and of course other types of chip-related components may also be included. Additionally, of course, these components 1020 can be combined with each other.

Network-related parts (1030) include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM. , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated as such, but are not limited to, and many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, of course, the network-related components 1030 can be combined with the chip-related components 1020.

Other parts (1040) include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (Electro Magnetic Interference) filter, MLCC (Multi-Layer Ceramic Condenser), etc. , but is not limited to this, and may include passive parts used for various other purposes. In addition, of course, the other components 1040 can be combined with the chip-related components 1020 and/or the network-related components 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and/or electrically connected to the main board 1010. Examples of other components include camera 1050, antenna 1060, display 1070, battery 1080, audio codec, video codec, power amplifier, compass, accelerometer, gyroscope, speaker, mass storage device (e.g. , hard disk drives), CDs (compact disks), and DVDs (digital versatile disks), etc., but are not limited thereto, and other components used for various purposes depending on the type of electronic device 1000. Of course, etc. may be included.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( It may be a computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited to this, and of course, it can be any other electronic device that processes data.

Figure 2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, semiconductor packages are applied to various electronic devices as described above for various purposes. For example, inside the body 1101 of the smart phone 1100, a printed circuit board 1110 such as a motherboard is accommodated, and various components 1120 are physically and/or electrically installed on the printed circuit board 1110. It is connected to. Additionally, other components, such as the camera 1130, which may or may not be physically and/or electrically connected to the printed circuit board 1110, are accommodated within the body 1101. Some of the components 1120 may be chip-related components, for example, the semiconductor package 1121, but are not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, and of course, it may be other electronic devices as described above.

semiconductor package

In general, a semiconductor chip integrates numerous microscopic electrical circuits, but it cannot function as a finished semiconductor product by itself, and there is a possibility that it may be damaged by external physical or chemical shock. Therefore, rather than using the semiconductor chip itself, the semiconductor chip is packaged and used in electronic devices as a package.

The reason why semiconductor packaging is necessary is because, from the perspective of electrical connection, there is a difference in circuit width between the semiconductor chip and the main board of electronic devices. Specifically, in the case of semiconductor chips, the size of the connection pads and the spacing between the connection pads are very small, whereas in the case of motherboards used in electronic devices, the size of the component mounting pads and the spacing between the component mounting pads are much larger than the scale of the semiconductor chip. . Therefore, it is difficult to directly mount a semiconductor chip on such a motherboard, and packaging technology that can buffer the difference in circuit width between them is required.

Semiconductor packages manufactured using this packaging technology can be divided into fan-in semiconductor packages and fan-out semiconductor packages depending on their structure and use.

Below, we will look at the fan-in semiconductor package and fan-out semiconductor package in more detail with reference to the drawings.

(Fan-in semiconductor package)

3A and 3B are cross-sectional views schematically showing before and after packaging a fan-in semiconductor package.

Figure 4 is a cross-sectional view schematically showing the packaging process of a fan-in semiconductor package.

Referring to the drawing, the semiconductor chip 2220 includes a body 2221 containing silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc., and aluminum (Al) formed on one surface of the body 2221. A connection pad 2222 containing a metal material, and a passivation film 2223 such as an oxide or nitride film formed on one surface of the body 2221 and covering at least a portion of the connection pad 2222, for example, It may be an integrated circuit (IC) in a bare state. At this time, because the connection pad 2222 is very small, it is difficult for an integrated circuit (IC) to be mounted on a mid-level printed circuit board (PCB) as well as a main board of an electronic device.

Accordingly, in order to rewire the connection pad 2222, a connection structure 2240 is formed on the semiconductor chip 2220 according to the size of the semiconductor chip 2220. The connection structure 2240 forms an insulating layer 2241 on the semiconductor chip 2220 with an insulating material such as photosensitive insulating resin (PID: Photo Image-able Dielectric), and has a via hole 2243h exposing the connection pad 2222. ) can be formed by forming the wiring pattern 2242 and the via 2243. After that, a passivation layer 2250 is formed to protect the connection structure 2240, an opening 2251 is formed, and then an underbump metal 2260 and the like are formed. That is, through a series of processes, for example, a fan-in semiconductor package 2200 including a semiconductor chip 2220, a connection structure 2240, a passivation layer 2250, and an underbump metal 2260 is manufactured. do.

As such, the fan-in semiconductor package is a package type in which the connection pads of the semiconductor chip, such as I/O (Input/Output) terminals, are all placed inside the device. The fan-in semiconductor package has good electrical characteristics and can be produced inexpensively. there is. Accordingly, many devices used in smartphones are manufactured in the form of fan-in semiconductor packages, and specifically, development is being carried out in the direction of realizing small size and fast signal transmission.

However, fan-in semiconductor packages have many space limitations as all I/O terminals must be placed inside the semiconductor chip. Therefore, it is difficult to apply this structure to semiconductor chips with a large number of I/O terminals or to semiconductor chips of small size. Additionally, due to this vulnerability, the fan-in semiconductor package cannot be directly mounted and used on the main board of an electronic device. Even if the size and spacing of the I/O terminals of a semiconductor chip are expanded through a rewiring process, the size and spacing are not large enough to be directly mounted on the main board of an electronic device.

Figure 5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device.

Figure 6 is a cross-sectional view schematically showing the case where the fan-in semiconductor package is embedded in a printed circuit board and finally mounted on the main board of an electronic device.

Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222 of the semiconductor chip 2220, that is, the I/O terminals, are rewired again through the printed circuit board 2301, and finally, Can be mounted on the main board 2500 of an electronic device with the fan-in semiconductor package 2200 mounted on the printed circuit board 2301. At this time, the solder ball 2270, etc. may be fixed with an underfill resin 2280, etc., and the outside may be covered with a molding material 2290, etc. Alternatively, the fan-in semiconductor package 2200 may be embedded within a separate printed circuit board 2302, and the connection pads of the semiconductor chip 2220 may be connected by the printed circuit board 2302 in an embedded state. (2222), that is, the I/O terminals can be rewired once again and finally mounted on the main board 2500 of the electronic device.

As such, since it is difficult to use the fan-in semiconductor package by directly mounting it on the main board of an electronic device, it is mounted on a separate printed circuit board and then goes through a packaging process and is then mounted on the main board of the electronic device, or as a printed circuit board. It is used by being embedded within a circuit board and mounted on the main board of an electronic device.

(Fan-out semiconductor package)

Figure 7 is a cross-sectional view schematically showing a fan-out semiconductor package.

Referring to the drawing, in the fan-out semiconductor package 2100, for example, the outside of the semiconductor chip 2120 is protected with an encapsulant 2130, and the connection pad 2122 of the semiconductor chip 2120 is a connection structure. By 2140, the wiring is rewired to the outside of the semiconductor chip 2120. At this time, a passivation layer 2150 may be further formed on the connection structure 2140, and an underbump metal 2160 may be further formed in the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the underbump metal 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121 and a connection pad 2122. The connection structure 2140 may include an insulating layer 2141, a wiring layer 2142 formed on the insulating layer 2241, and a via 2143 that electrically connects the connection pad 2122 and the wiring layer 2142. .

In this way, the fan-out semiconductor package is a type in which I/O terminals are rewired and arranged to the outside of the semiconductor chip through a connection structure formed on the semiconductor chip. As described above, the fan-in semiconductor package requires all I/O terminals of the semiconductor chip to be placed inside the semiconductor chip, and as the device size decreases, the ball size and pitch must be reduced, so a standardized ball layout cannot be used. On the other hand, the fan-out semiconductor package is a type in which the I/O terminals are rewired and arranged to the outside of the semiconductor chip through the connection structure formed on the semiconductor chip, so even if the size of the semiconductor chip becomes smaller, a standardized ball layout is maintained. It can be used as is, and as described later, it can be mounted on the main board of an electronic device without a separate printed circuit board.

Figure 8 is a cross-sectional view schematically showing a case where a fan-out semiconductor package is mounted on the main board of an electronic device.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on the main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 is a connection structure that can rewire the connection pad 2122 on the semiconductor chip 2120 to a fan-out area that exceeds the size of the semiconductor chip 2120. Since it forms (2140), a standardized ball layout can be used as is, and as a result, it can be mounted on the main board 2500 of an electronic device without a separate printed circuit board.

In this way, since the fan-out semiconductor package can be mounted on the main board of an electronic device without a separate printed circuit board, it can be implemented with a thinner thickness than the fan-in semiconductor package using a printed circuit board, enabling miniaturization and thinning. do. Additionally, it has excellent thermal and electrical properties, making it particularly suitable for mobile products. In addition, it can be implemented more compactly than the typical POP (Package on Package) type that uses a printed circuit board (PCB), and problems caused by bending can be solved.

Meanwhile, the fan-out semiconductor package refers to a package technology for mounting a semiconductor chip on the motherboard of an electronic device, etc., and for protecting the semiconductor chip from external shock. It is different from this in scale, purpose, etc. It is a different concept from a printed circuit board (PCB), such as a printed circuit board in which a fan-in semiconductor package is built.

Hereinafter, a fan-out semiconductor package that can reduce the thickness of the product and apply a backside circuit with a fine pitch will be described with reference to the drawings.

Figure 9 is a cross-sectional view schematically showing an example of a fan-out semiconductor package.

FIG. 10 is a schematic plan view taken along line I-I' of the fan-out semiconductor package of FIG. 9.

Referring to the drawings, a fan-out semiconductor package (100A) according to an example includes one or more insulating layers (111a, 111b) and one or more wiring layers (112a, 112b, 112c), and one or more insulating layers (111a, 111b). A frame 110 having a penetrating portion 110H, a semiconductor chip 120 disposed in the penetrating portion 110H of the frame 110 and having a connection pad 122, the frame 110 and the semiconductor chip 120. A connection structure 140 disposed on the lower side and including a redistribution layer 142 electrically connected to the connection pad 122, and at least a portion of the upper surface of the semiconductor chip 120 and one or more insulating layers of the frame 110 ( A first suture covering at least a portion of the upper surface of the uppermost insulating layer 111b among 111a and 111b and at least a portion of the side surface of the uppermost wiring layer 112c among one or more wiring layers 112a, 112b and 112c of the frame 110. Includes ash (130). At this time, the upper surface of the first encapsulant 130a has a level difference from the upper surface of the uppermost wiring layer 112c. For example, the upper surface of the first encapsulant 130a is located lower than the upper surface of the uppermost wiring layer 112c, and may be located at a level between the uppermost insulating layer 111b and the uppermost wiring layer 112c. .

Meanwhile, as mentioned above, in order to improve the electrical characteristics of recent premium smartphone products and utilize space efficiently, and to apply package-on-package (POP) to semiconductor packages containing different semiconductor chips, the backside circuit is used in the semiconductor package structure. It is required to form a , and the requirements for the lines and spaces of the backside circuit are increasing in line with the demands for advancement of chip characteristics and reduction of area. For example, a package-on-package structure in which a memory package is stacked on an application processor package is required, and for this purpose, the introduction of a finely designed backside circuit of the application processor is required. Accordingly, a technology for forming a backside circuit by plating on the upper surface of the molding material that seals the semiconductor chip has been proposed. However, since the molding material that generally seals the semiconductor chip contains a non-photosensitive insulating material, the photolithography method cannot be used, which limits the fine pitch of the backside circuit.

On the other hand, the fan-out semiconductor package 100A according to one example is formed to completely cover the uppermost wiring layer 112c of the frame 110, such as by introducing the first encapsulant 130a to have the above-described step structure. Rather, it is formed to cover at least a portion of the side surface of the uppermost wiring layer 112c. In this case, as will be described later, the second encapsulant 130b may be formed on the first encapsulant 130a to cover at least another part of the side surface and at least part of the top surface of the uppermost wiring layer 112c. At this time, when the second encapsulant 130b includes a photosensitive insulating material, a backside circuit and a via connected to the uppermost wiring layer 112c can be introduced through a photolithography process, thereby achieving fine pitch. . In addition, since backside vias are formed by forming photo vias, the thickness of the product can be made thinner by reducing the size of the via and the plating thickness.

Meanwhile, the step between the top surface of the first encapsulant 130a and the top surface of the top wiring layer 112c may be 10 μm or less. If the top surface of the first encapsulant 130a is lower than the top surface of the uppermost wiring layer 112c by more than 10㎛, an undulation problem occurs when forming the second encapsulant 130b on the first encapsulant 130a. It can happen.

Meanwhile, the first and second encapsulants 130a and 130b may each include a photosensitive insulating material. For example, the first and second encapsulants 130a and 130b may include a PID. As such, when the first encapsulant 130a contains a photosensitive insulating material, the above-described step can be formed through a photolithography process, and when the second encapsulant 130b contains a photosensitive insulating material, the laser Since the photolithography process can be used instead of drilling, etc., it can be effective in improving product yield.

Meanwhile, a metal pattern layer 132 may be disposed on the second encapsulant 130b as a backside circuit, and the metal pattern layer 132 may be formed through a metal via 133 penetrating the second encapsulant 130b as a backside via. ) can be electrically connected to the top wiring layer 112c. As described above, the metal pattern layer 132 and the metal via 133 can have a fine pitch because the second encapsulant 130b may include a photosensitive insulating material, and the size of the via and the plating thickness can be reduced. It is also possible to achieve thinner products. If necessary, a third encapsulant 130c covering the metal pattern layer 132 may be further disposed on the second encapsulant 130b, and the third encapsulant 130c may include a metal pattern layer 132. An opening 130h may be formed to expose at least a portion of the . The third encapsulant 130c may also include PID, and in this case, it may be effective in improving product yield as described above.

Meanwhile, a passivation layer 150 having an opening exposing at least a portion of the redistribution layer 142 may be disposed below the connection structure 140, and may be electrically connected to the exposed redistribution layer on the opening of the passivation layer 150. A connected underbump metal 160 may be disposed, and an electrical connection metal 170 electrically connected to the exposed redistribution layer 142 through the underbump metal 160 may be disposed on the lower side of the passivation layer 150. there is.

Hereinafter, each component included in the fan-out semiconductor package 100A according to an example will be described in more detail with reference to the drawings.

The frame 110 can further improve the rigidity of the package 100A depending on the specific material of the insulating layers 111a and 111b, and can play a role such as ensuring thickness uniformity of the first encapsulant 130a. . The frame 110 may have a penetrating portion 110H that penetrates the insulating layers 111a and 111b. A semiconductor chip 120 is disposed in the penetrating portion 110H, and if necessary, passive components may be disposed together. The penetrating portion 110H may have a wall that surrounds the semiconductor chip 120, but is not limited thereto. For example, the frame 110 may be composed of a plurality of units, and in this case, the penetrating portion 110H may extend between the plurality of units. The frame 110 includes wiring layers 112a, 112b, 112c and wiring vias 113a, 113b in addition to the insulating layers 111a and 111b, and therefore can function as an electrical connection member that provides an upper and lower electrical connection path.

The frame 110 is embedded in the first insulating layer 111a, the lower surface of which is in contact with the connection structure 140, and the first wiring layer 112a, the first wiring layer 112a, whose lower surface is in contact with the connection structure 140. A second wiring layer 112b disposed on the upper surface of the insulating layer 111a, a second insulating layer 111b disposed on the upper surface of the first insulating layer 111a and covering at least a portion of the second wiring layer 112b, and a third wiring layer 112c disposed on the upper surface of the second insulating layer 111b. The first and second wiring layers (112a, 112b) and the second and third wiring layers (112b, 112c) have first and second wiring vias (113a, 113a) penetrating the first and second insulating layers (111a, 111b), respectively. It is electrically connected through 113b). The first to third wiring layers 112a, 112b, and 112c may be electrically connected to the connection pad 122 according to their functions through the redistribution layer 142 and the connection via 143 of the connection structure 140.

The material of the insulating layers 111a and 111b is not particularly limited. For example, an insulating material may be used, in which case the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler, for example, ABF (Ajinomoto Build-ABF). up Film), etc. may be used. Alternatively, a material in which the core material such as glass fiber (glass fiber, glass cloth, glass fabric) is impregnated with the above-described resin along with an inorganic filler, for example, prepreg, etc. may be used.

The wiring layers 112a, 112b, and 112c, together with the wiring vias 113a and 113b, may provide an electrical connection path for the top and bottom of the package, and may serve to rewire the connection pad 122. Materials forming the wiring layers 112a, 112b, and 112c include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium ( Metal materials such as Ti) or alloys thereof can be used. The wiring layers 112a, 112b, and 112c can perform various functions depending on the design of the corresponding layer. For example, it may include a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S') pattern, etc. Here, the signal (S) pattern includes various signals, for example, data signals, etc., excluding the ground (GND) pattern, power (PWR) pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. Additionally, the wiring layers 112a, 112b, and 112c may each include various types of via pads. The wiring layers 112a, 112b, and 112c may be formed using a known plating process and may each include a seed layer and a plating layer.

The thickness of each of the wiring layers 112a, 112b, and 112c may be thicker than the thickness of each of the redistribution layers 142. Additionally, it may be thicker than the thickness of the metal pattern layer 132. The frame 110 may have a thickness equal to or greater than that of the semiconductor chip 120. In order to maintain rigidity, prepreg or the like is selected as the material for the insulating layers 111a and 111b, and the wiring layers 112a, 112b, and 112c formed thereby. The thickness may also be relatively thick. On the other hand, the connection structure 140 requires a fine circuit and high-density design, and therefore, the material of the insulating layer 141 is selected as a photosensitive insulating material, and the thickness of the redistribution layer 142 formed therefrom can also be relatively thin. there is. As will be described later, the same applies to the metal pattern layer 132.

The lower surface of the first wiring layer 112a may have a level difference from the lower surface of the first insulating layer 111a. That is, the lower surface of the first wiring layer 112a may be recessed into the inside of the first insulating layer 111a. In this way, the first wiring layer 112a is recessed into the first insulating layer 111a, and the surface in contact with the connection structure 140 of the first insulating layer 111a and the connection structure 140 of the first wiring layer 112a are formed. ) When the surface in contact with the surface has a step, when encapsulating the semiconductor chip 120 and the frame 110 with the encapsulant 130a, it is possible to prevent the forming material from bleeding and contaminating the first wiring layer 112a. .

The wiring vias 113a and 113b electrically connect the wiring layers 112a, 112b, and 112c formed in different layers, and as a result, form an electrical path within the frame 110. Forming materials for the wiring vias 113a and 113b include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). ), or metal materials such as alloys thereof can be used. The wiring vias 113a and 113b may include a signal via, a power via, a ground via, etc., and the power via and the ground via may be the same via. The wiring vias 113a and 113b may each be a field-type via filled with a metal material, or may be a conformal-type via in which a metal material is formed along the wall of the via hole. Additionally, each may have a tapered shape. The wiring vias 113a and 113b may also be formed through a plating process and may be composed of a seed layer and a conductor layer.

When forming a hole for the first wiring via 113a, some pads of the first wiring layer 112a can serve as a stopper, and the width of the upper surface of the first wiring via 113a is less than that of the lower surface. It may be advantageous in the process to have a tapered shape that is larger than the width. In this case, the first wiring via 113a may be integrated with the pad pattern of the second wiring layer 112b. In addition, when forming a hole for the second wiring via 113b, some pads of the second wiring layer 112b can serve as a stopper, and the width of the upper surface of the second wiring via 113b is the width of the lower surface. A larger tapered shape may be advantageous in terms of processing. In this case, the second wiring via 113b may be integrated with the pad pattern of the third wiring layer 112c.

The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of elements are integrated into one chip. At this time, the integrated circuit may be, for example, an application processor chip such as a central processor (e.g., CPU), graphics processor (e.g., GPU), digital signal processor, encryption processor, microprocessor, or microcontroller, but is not limited thereto. No, memory chips such as power management integrated circuit (PMIC: Power Management IC), volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, or analog-to-digital converter, ASIC (application- It may be a logic chip such as a specific IC).

The semiconductor chip 120 may be a bare integrated circuit in which no separate bumps or wiring layers are formed. However, it is not limited to this, and may be a packaged type integrated circuit if necessary. Integrated circuits can be formed based on active wafers. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material forming the body 121 of the semiconductor chip 120. Various circuits may be formed in the body 121. The connection pad 122 is used to electrically connect the semiconductor chip 120 to other components, and metal materials such as aluminum (Al) can be used as forming materials without particular restrictions. A passivation film 123 exposing the connection pad 122 may be formed on the body 121. The passivation film 123 may be an oxide film, a nitride film, or a double layer of an oxide film and a nitride film. Additional insulating films, etc. may be disposed at other necessary positions. Meanwhile, the side of the semiconductor chip 120 where the connection pad 122 is placed becomes the active side, and the back side on the opposite side becomes the inactive side. However, since the connection pad is disposed on the back side, both sides may be active sides.

The first encapsulant 130a covers at least a portion of each of the frame 110 and the semiconductor chip 120 and fills at least a portion of the penetrating portion 110H. The first encapsulant 130a includes an insulating material, and the insulating material may include a photosensitive insulating material. The first encapsulant 130a may include a PID. Through this, effects such as improved yield and reduced thickness can be achieved.

The second encapsulant 130b is disposed on the first encapsulant 130a and covers at least a portion of the third wiring layer 112c, which is the uppermost wiring layer 112c. The second encapsulant 130b also includes an insulating material, and a photosensitive insulating material such as PID may be used as the insulating material. The second encapsulant 130b provides an insulating area where the metal pattern layer 132 and metal via 133, which are backside circuits and vias, can be formed, and may be a PID or the like, allowing the photolithography process to proceed. . Therefore, it can further have effects such as fine pitch.

The third encapsulant 130c is disposed on the second encapsulant 130b and covers at least a portion of the metal pattern layer 132. The third encapsulant 130c also includes an insulating material, and a photosensitive insulating material such as PID may be used as the insulating material. The third encapsulant 130c can be used as the outermost layer of the package. The third encapsulant 130c may have a plurality of openings 130h each exposing at least a portion of the metal pattern layer 132. The third encapsulant 130c may also be a PID, and may further have the effects of improving yield and reducing thickness as described above.

The metal pattern layer 132 is disposed on the second encapsulant 130b and provides a backside circuit to the package together with the metal via 133. The metal pattern layer 132 is also made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or these. It may contain metal substances such as alloys. The metal pattern layer 132 can perform various functions in design. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern includes various signals, for example, data signals, etc., excluding the ground (GND) pattern, power (PWR) pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. The metal pattern layer 132 may also be formed through a known plating process and may be composed of a seed layer and a conductor layer. Since the metal pattern layer 132 is formed on the second encapsulant 130b, fine pitch is possible.

The metal via 133 penetrates the second encapsulant 130b and electrically connects the metal pattern layer 132 to the third wiring layer 112c, which is the uppermost wiring layer 112c. The metal via 133 is also made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. It may include metal substances such as: The metal via 133 may also be a field-type via filled with a metal material, or a conformal-type via in which a metal material is formed along the wall of the via hole. Additionally, it may have a tapered shape in the same direction as the wiring vias 113a and 113b. The metal via 133 may also include a signal via, a ground via, a power via, etc., and the power via and the ground via may be the same via. The metal via 133 may also be formed through a known plating process and may be composed of a seed layer and a conductor layer. The metal via 133 can be formed by filling a via hole formed by photolithography in the second encapsulant 130b with plating, and as a result, fine pitch through the photo via is possible.

The connection structure 140 can rewire the connection pad 122 of the semiconductor chip 120. Through the connection structure 140, the connection pads 122 of tens or hundreds of semiconductor chips 120 with various functions can each be rewired, and through the electrical connection metal 170, they can be physically and/or externally connected according to their functions. Alternatively, they may be electrically connected. The connection structure 140 penetrates the insulating layer 141, the redistribution layer 142 disposed on the insulating layer 141, and the insulating layer 141, and includes the connection pad 122, the redistribution layer 142, and the frame 110. ) includes a connection via 143 that electrically connects the first wiring layer 112a, which is the lowest wiring layer 112a, among the wiring layers 112a, 112b, and 112c, and the redistribution layer 142. The number of insulating layers 141, redistribution layers 142, and connection vias 143 may be more or less than those shown in the drawing.

An insulating material may be used as the material of the insulating layer 141. In this case, a photosensitive insulating material (PID) may be used as the insulating material. In this case, it is possible to introduce a fine pitch through a photo via, thereby forming a fine circuit and It is advantageous for high-density design, and tens to millions of connection pads 122 of the semiconductor chip 120 can be rewired very effectively. The boundaries of the insulating layers 141 may be distinct from each other, or the boundaries may be unclear.

The rewiring layer 142 can be electrically connected to the electrical connection metal 170 by rewiring the connection pad 122 of the semiconductor chip 120. The forming material of the redistribution layer 142 may also be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or Metal materials such as alloys thereof can be used. The redistribution layer 142 can also perform various functions depending on the design. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. Additionally, the redistribution layer 142 may include various types of via pads, electrical connection metal pads, etc. The redistribution layer 142 may also be formed through a plating process and may be composed of a seed layer and a conductor layer.

The connection via 143 electrically connects the redistribution layers 142 formed on different layers, and also connects the connection pad 122 of the semiconductor chip 120 and the first wiring layer, which is the lowest wiring layer 112a of the frame 110. (112a) is electrically connected to the redistribution layer 142. The connection via 143 may be in physical contact with the connection pad 122 when the semiconductor chip 120 is a bare die. Forming materials for the connection vias 143 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). Metal materials such as , or alloys thereof can be used. The connection via 143 may include a signal via, a power via, a ground via, etc., and the power via and the ground via may be the same via. The connection vias 143 may also be field-type vias each filled with a metal material, or may be conformal-type vias in which a metal material is formed along the wall of the via hole. Additionally, it may have a tapered shape in the opposite direction to the wiring vias 113a and 113b. The connection via 143 may also be formed through a plating process and may be composed of a seed layer and a conductor layer.

The passivation layer 150 is an additional component to protect the connection structure 140 from external physical and chemical damage. The passivation layer 150 may include a thermosetting resin. For example, the passivation layer 150 may be ABF, but is not limited thereto. The passivation layer 150 may have a plurality of openings each exposing at least a portion of the lowest redistribution layer 142 among the redistribution layers 142 . There may be tens to tens of thousands of openings, or there may be more or fewer openings. Each opening may be composed of a plurality of holes. If necessary, surface-mounted components such as capacitors may be placed on the lower surface of the passivation layer 150 to be electrically connected to the redistribution layer 142 and, as a result, to the semiconductor chip 120.

The underbump metal 160 is also an additional component and improves the connection reliability of the electrical connection metal 170, and as a result, the board level reliability of the fan-out semiconductor package 100A according to an example can be improved. There may be tens to tens of thousands of underbump metals 160, and the number may be more or less. Each underbump metal 160 may be formed in an opening of the passivation layer 150 and electrically connected to the open lowermost redistribution layer 142 . The underbump metal 160 may be formed using a metal using a known metallization method, but is not limited thereto.

The electrical connection metal 170 is also an additional component, and is configured to physically and/or electrically connect the semiconductor package 100A according to one example to the outside. For example, the semiconductor package 100A according to one example may be mounted on the main board of an electronic device through the electrical connection metal 170. The electrical connection metal 170 is disposed on the passivation layer 150 and may be electrically connected to the underbump metal 160, respectively. Each of the electrical connection metals 170 may be made of a low melting point metal, for example, tin (Sn) or an alloy containing tin (Sn). More specifically, it may be formed of solder, etc., but this is only an example and the material is not particularly limited thereto.

The electrical connection metal 170 may be a land, ball, pin, etc. The electrical connection metal 170 may be formed as a multi-layer or a single layer. If formed as a multi-layer, it may contain copper pillar and solder, and if formed as a single layer, it may contain tin-silver solder or copper, but this is only an example and is not limited thereto. . The number, spacing, arrangement form, etc. of the electrical connection metals 170 are not particularly limited, and can be sufficiently modified according to design details by a person skilled in the art. For example, the number of electrical connection metals 170 may be tens to tens of thousands depending on the number of connection pads 122, or may be more or less.

At least one of the electrical connection metals 170 is disposed in the fan-out area. The fan-out area refers to an area outside the area where the semiconductor chip 120 is placed. Fan-out packages have superior reliability compared to fan-in packages, enable the implementation of multiple I/O terminals, and facilitate 3D interconnection. In addition, compared to BGA (Ball Grid Array) packages and LGA (Land Grid Array) packages, the package thickness can be manufactured thinner and its price competitiveness is excellent.

11 to 13 are process diagrams schematically showing an example of manufacturing the fan-out semiconductor package of FIG. 9.

Referring to FIG. 11, first, prepare the frame 110. Thereafter, a penetrating portion 110H is formed in the frame 110 using a laser drill, etc., and the frame 110 is attached to a tape, etc., and then the semiconductor chip 120 is placed on the tape exposed by the penetrating portion 110H. -It is placed in a down form, and then the first encapsulant 130a is formed to seal the frame 110 and the semiconductor chip 120 by methods such as PID application and curing. Next, a photolithography process, such as a development process, is performed so that the top surface of the first encapsulant 130a has a level difference with the top surface of the uppermost wiring layer 112c. Next, the first bonding sheet 210 is attached to the first encapsulant 130a. The first bonding sheet 210 is not directly attached to the product area shown in the drawing, but is only attached to the dummy area between product areas, and can serve as a detach core.

Referring to FIG. 12, an insulating layer 141 is formed on the lower side of the frame 110 and the semiconductor chip 120 by PID coating and curing, a photo via hole is formed, and AP (Additive Process) and SAP (Semi AP) are formed. ), MSAP (Modified SAP), tenting, etc. plating processes are used to form the redistribution layer 142 and the connection via 143, and this is repeated as necessary to form the connection structure 140. Additionally, a passivation layer 150 and an underbump metal 160 are formed as needed. Next, the second bonding sheet 220 is attached on the passivation layer 150. The first bonding sheet 210 is detached. The second bonding sheet 220 is also not directly attached to the product area shown in the drawing, but is only attached to the dummy area between product areas, and can serve as a detach core.

Referring to FIG. 13, next, PID is applied and cured on the first encapsulant 130a to cover at least a portion of the uppermost wiring layer 112c to form a second encapsulant 130b, and the second encapsulant 130b is formed using a photo via. After forming the via hole, the metal pattern layer 132 and the metal via 133 are formed through the plating process described above. Next, PID is applied and cured as needed to further form a third encapsulant 130c, and an opening 130h is formed using a photolithography method. Thereafter, by detaching the second bonding sheet 220 and forming the electrical connection metal 170 as necessary, a fan-out semiconductor package according to the above-described example is manufactured.

Figure 14 schematically shows another example of a fan-out semiconductor package.

Referring to the drawings, the fan-out semiconductor package 100B according to another example has a frame 110 of a different shape from the fan-out semiconductor package 100A according to the above-described example. Specifically, the frame 110 includes a first insulating layer 111a, a first wiring layer 112a, a second wiring layer 112b, and a first insulating layer 111a disposed on both sides of the first insulating layer 111a, respectively. A second insulating layer 111b and a third insulating layer 111c are disposed on both sides and cover the first and second wiring layers 112a and 112b, respectively, and a first wiring layer 112a of the second insulating layer 111b. A third wiring layer 112c disposed on the opposite side of the buried side, a fourth wiring layer 112d disposed on the opposite side of the side where the second wiring layer 112b of the third insulating layer 111c is buried, and a first wiring layer 112d. A first wiring via (113a) that penetrates the insulating layer (111a) and electrically connects the first and second wiring layers (112a, 112b), and a first wiring via (113a) that penetrates the second insulating layer (111b) and electrically connects the first and third wiring layers (112a). , 113c), and a third wiring via 113c that penetrates the third insulating layer 111c and electrically connects the second and fourth wiring layers 112b and 112d. Includes. Since the frame 110 has a greater number of wiring layers 112a, 112b, 112c, and 112d, the connection structure 140 can be further simplified.

The first insulating layer 111a may be thicker than the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a can be relatively thick to maintain rigidity, and the second insulating layer 111b and third insulating layer 111c are used to form a larger number of wiring layers 112c and 112d. It may have been introduced. From a similar perspective, the first wiring via (113a) penetrating the first insulating layer (111a) is larger than the second and third wiring vias (113b, 113c) penetrating the second and third build-up layers (111b, 111c). The height and average diameter can be large. Additionally, the first wiring via 113a may have an hourglass or cylindrical shape, while the second and third wiring vias 113b and 113c may have a tapered shape in opposite directions. The thickness of each of the wiring layers 112a, 112b, 112c, and 112d may be thicker than the thickness of the redistribution layer 142.

Other than that, other contents are substantially the same as those of the fan-out semiconductor package 100A according to the above-described example, and detailed description will be omitted.

In the present disclosure, lower, lower, bottom, etc. are used for convenience to mean a downward direction based on the cross section of the drawing, and upper, upper, upper, etc. are used to mean the opposite direction. However, this direction is defined for convenience of explanation, and the scope of the patent claims is not particularly limited by the description of this direction, and the concept of top/bottom can change at any time.

In the present disclosure, the meaning of connected is a concept that includes not only directly connected, but also indirectly connected through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept that includes both cases where it is physically connected and cases where it is not connected. Additionally, expressions such as first, second, etc. are used to distinguish one component from another component and do not limit the order and/or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component without departing from the scope of rights.

The expression 'example' used in the present disclosure does not mean identical embodiments, but is provided to emphasize and explain different unique features. However, the examples presented above do not exclude being implemented in combination with features of other examples. For example, even if a matter explained in a specific example is not explained in another example, it can be understood as an explanation related to the other example, as long as there is no explanation contrary to or contradictory to the matter in the other example.

The terminology used in this disclosure is used to describe examples only and is not intended to limit the disclosure. At this time, singular expressions include plural expressions, unless the context clearly indicates otherwise.

Claims (14)

A frame including one or more insulating layers and one or more wiring layers, and having a penetrating portion penetrating the one or more insulating layers;
a semiconductor chip disposed in a penetrating portion of the frame and having a connection pad;
a connection structure disposed below the frame and the semiconductor chip and including a redistribution layer electrically connected to the connection pad; and
A first seal covering at least a portion of the upper surface of the semiconductor chip, at least a portion of the upper surface of the uppermost insulating layer among the one or more layers of the insulating layer of the frame, and at least a portion of a side surface of the uppermost wiring layer among the one or more layers of the insulating layer of the frame. re; Includes,
The upper surface of the first encapsulant is located lower than the upper surface of the uppermost wiring layer and has a step difference from the upper surface of the uppermost wiring layer,
Fan-out semiconductor package.
According to claim 1,
The upper surface of the first encapsulant is located at a level between the upper surface of the uppermost insulating layer and the upper surface of the uppermost wiring layer,
Fan-out semiconductor package.
According to claim 1,
The step is 10㎛ or less,
Fan-out semiconductor package.
According to claim 1,
a second encapsulant disposed on the first encapsulant and covering at least a portion of the upper surface and at least another portion of a side surface of the uppermost wiring layer; Containing more,
Fan-out semiconductor package.
According to claim 4,
The first and second encapsulants each include a photosensitive insulating material,
Fan-out semiconductor package.
According to claim 4,
A metal pattern layer disposed on the second encapsulant; and
a metal via penetrating the second encapsulant and electrically connecting the metal pattern layer to the uppermost wiring layer; Containing more,
Fan-out semiconductor package.
According to claim 6,
a third encapsulant disposed on the second encapsulant, covering the metal pattern layer, and having an opening exposing at least a portion of the metal pattern layer; Containing more,
Fan-out semiconductor package.
According to claim 1,
The frame includes a first insulating layer whose lower surface is in contact with the connecting structure, a first wiring layer embedded in the first insulating layer and whose lower surface is in contact with the connecting structure, a second wiring layer disposed on the upper surface of the first insulating layer, A second insulating layer disposed on the upper surface of the first insulating layer and covering the second wiring layer, and a third wiring layer disposed on the upper surface of the second insulating layer,
The one or more insulating layers include the first and second insulating layers,
The one or more wiring layers include the first to third wiring layers,
The first to third wiring layers are electrically connected to the connection pad,
Fan-out semiconductor package. According to claim 1,
The frame includes a first insulating layer, first and second wiring layers respectively disposed on the lower and upper surfaces of the first insulating layer, and the first and second wiring layers respectively disposed on the lower and upper surfaces of the first insulating layer. It includes second and third insulating layers respectively covering the wiring layer, a third wiring layer disposed on the lower surface of the second insulating layer, and a fourth wiring layer disposed on the upper surface of the third insulating layer,
The one or more insulating layers include the first to third insulating layers,
The one or more wiring layers include the first to fourth wiring layers,
The first to fourth wiring layers are electrically connected to the connection pad,
Fan-out semiconductor package. According to claim 1,
a passivation layer disposed below the connection structure and having an opening exposing at least a portion of the redistribution layer;
an underbump metal disposed on the opening of the passivation layer and electrically connected to the exposed redistribution layer; and
an electrical connection metal disposed below the passivation layer and electrically connected to the exposed redistribution layer through the underbump metal; Containing more,
Fan-out semiconductor package.
A frame including one or more wiring layers and having a penetrating portion;
a semiconductor chip disposed in a penetrating portion of the frame and having a connection pad;
a connection structure disposed below the frame and the semiconductor chip and including a redistribution layer electrically connected to the connection pad;
a first encapsulant that covers at least a portion of each of the frame and the semiconductor chip and fills at least a portion of the penetrating portion; and
A second sealant disposed on the first sealant; Includes,
The boundary between the first and second encapsulants is located at a level between the upper and lower surfaces of the uppermost wiring layer among the one or more wiring layers of the frame,
Fan-out semiconductor package.
According to claim 11,
At least a portion of a side surface of the uppermost wiring layer is covered with the first encapsulant,
At least another part of the side surface of the uppermost wiring layer is covered with the second encapsulant,
At least a portion of the upper surface of the uppermost wiring layer is covered with the second encapsulant,
Fan-out semiconductor package.
According to claim 11,
The first and second encapsulants each include a photosensitive insulating material,
Fan-out semiconductor package.
According to claim 11,
A metal pattern layer disposed on the second encapsulant;
a metal via penetrating the second encapsulant and electrically connecting the metal pattern layer to the uppermost wiring layer; and
a third encapsulant disposed on the second encapsulant and covering at least a portion of the metal pattern layer; Containing more,
Fan-out semiconductor package.

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