JP6454800B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device that uses an environmental radio wave as an AC power source and generates a DC power source from the AC power source.

  In recent years, there has been an increasing demand for improvement in energy utilization efficiency. As one method of improving the energy utilization efficiency, there is an energy recovery method in which environmental radio waves are received by an antenna and a charge pump type rectifier circuit is operated by the received environmental radio waves to obtain electric power. An example of an energy recovery technique using a charge pump rectifier circuit is disclosed in Patent Document 1.

  In the charge pump type rectifier circuit of Patent Document 1, the gate electrode of a diode-connected MOS transistor is connected to an AC signal node having a phase opposite to that of an AC signal applied to its own source electrode or drain electrode. In this charge pump type rectifier circuit, a DC bias voltage is superimposed on an AC signal and applied to the gate electrode. As a result, in this charge pump type rectifier circuit, a technique for performing high-efficiency AC / DC power conversion by reducing ON voltage and ON resistance during forward operation of the diode circuit and reducing reverse leakage current is disclosed. ing.

JP 2008-11584 A

  However, the technique described in Patent Document 1 has a problem in that the leakage current cannot be sufficiently reduced and the conversion efficiency of the AC signal is lowered. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes first and second transistor arrays each including an NMOS transistor and a PMOS transistor connected in series between a first power supply line and a second power supply line. . Then, the gate of the PMOS transistor in one transistor row is connected to a wiring connecting the NMOS transistor and the PMOS transistor in the other transistor row. Further, an alternating current signal superimposed on a bias voltage having a lower voltage than the gate of the PMOS transistor included in the same transistor transistor array is applied to the gate of the NMOS transistor included in the transistor array.

  According to the embodiment, the leakage current can be reduced and the conversion efficiency of the AC signal can be improved.

1 is a block diagram of a semiconductor device according to a first embodiment; FIG. 3 is a circuit diagram of a bias circuit according to the first exemplary embodiment. 3 is a timing chart illustrating an operation of the semiconductor device according to the first embodiment; 3 is a timing chart showing changes in current during operation of the semiconductor device according to the first embodiment; It is a block diagram of the semiconductor device concerning a comparative example. It is a timing chart which shows change of current at the time of operation in a semiconductor device concerning a comparative example. FIG. 3 is a block diagram of a semiconductor device according to a second embodiment. FIG. 6 is a circuit diagram of a bias circuit according to a second embodiment. FIG. 6 is a block diagram of a semiconductor device according to a third embodiment. FIG. 6 is a block diagram of a semiconductor device according to a fourth embodiment. FIG. 9 is a block diagram of a semiconductor device according to a fifth embodiment. FIG. 9 is a block diagram of a semiconductor device according to a sixth embodiment. FIG. 10 is a block diagram of a semiconductor device according to a seventh embodiment. 12 is a timing chart illustrating an operation of the semiconductor device according to the seventh embodiment; FIG. 10 is a diagram for explaining a simulation condition of a leakage current amount in a semiconductor device according to a seventh embodiment; 12 is a graph showing a simulation result of leakage current of the semiconductor device according to the seventh embodiment; FIG. 10 is a block diagram of a semiconductor device according to an eighth embodiment; FIG. 10 is a block diagram of a semiconductor device according to a ninth embodiment.

Embodiment 1
Hereinafter, embodiments will be described with reference to the drawings. First, the semiconductor device 1 according to the first embodiment includes a charge pump rectifier circuit (hereinafter simply referred to as a rectifier circuit). Further, in the semiconductor device 1 according to the first embodiment, an AC signal based on environmental radio waves is received as an input signal by an antenna provided outside. The semiconductor device 1 supplies the load circuit with the power supply voltage VDD generated based on the AC signal. It does not matter whether the load circuit is formed on the same semiconductor chip as the rectifier circuit.

  In the following description, the first conductivity type is N-type, and the second conductivity type is P-type. However, when one of the N-type and P-type conductivity is the first conductivity type and the other conductivity type is the second conductivity type, the first conductivity type is P-type and the second conductivity type is N-type. You can also.

  Furthermore, in the following description, one of a source and a drain of a transistor is referred to as a first transistor terminal, and the other of the source and the drain is referred to as a second transistor terminal. In the following description, of the source and drain of the PMOS transistor, the terminal connected to the second power supply wiring Lp2 side wiring is the first transistor terminal, and the terminal connected to the first power supply wiring Lp1 side wiring is the first. This will be referred to as a transistor terminal 2. Of the source and drain of the NMOS transistor, the terminal connected to the wiring on the first power supply wiring Lp1 side is the first transistor terminal, and the terminal connected to the wiring on the second power supply wiring Lp2 side is the second. This will be referred to as a transistor terminal.

  FIG. 1 shows a block diagram of a semiconductor device 1 according to the first embodiment. As illustrated in FIG. 1, the semiconductor device 1 according to the first embodiment includes a rectifier circuit 10, a bias circuit 12, and a load 13. In FIG. 1, the AC signal source 11 is shown. The AC signal source 11 is an antenna, for example, and receives an environmental radio wave and generates a differential AC signal. It does not matter whether the bias circuit 12 is provided on the same semiconductor chip as the rectifier circuit 10 or not.

  The bias circuit 12 generates a bias voltage Vb, and superimposes and outputs an AC signal output from the AC signal source 11 on the bias voltage Vb. The load 13 is a circuit that performs actual arithmetic processing such as a functional circuit, for example, and uses the power supply voltage VDD output from the rectifier circuit 10 as an operation power supply.

  The rectifier circuit 10 includes a first transistor (for example, NMOS transistor MN1), a second transistor (for example, NMOS transistor MN2), a third transistor (for example, PMOS transistor MP1), and a fourth transistor (for example, PMOS transistor). MP2), a first capacitor C1, a second capacitor C2, and a third capacitor C3. In the rectifier circuit 10, the first power supply line Lp1, the second power supply line Lp2, the first input line Li1, the second input line Li2, the first inter-element line L1, and the second inter-element line L2 are provided. Have

  In FIG. 1, the first input terminal IN1, the second input terminal IN2, the first output terminal OUT1, and the second output terminal OUT2 are illustrated as the terminals of the rectifier circuit 10. These terminals are shown in the description of the rectifier circuit 10 and are not clearly provided when the rectifier circuit 10 and other circuit blocks are formed on the semiconductor chip. The first input terminal IN1 is provided on the first input line Li1, the second input terminal IN2 is provided on the second input line Li2, and the first output terminal OUT1 is on the second power supply line Lp2. The second output terminal OUT2 is provided on the first power supply line Lp1.

  AC signals whose phases are inverted from each other are transmitted to the first input wiring Li1 and the second input wiring Li2. In the example illustrated in FIG. 1, the first input wiring Li1 and the second input wiring Li2 are connected to the AC signal superimposed on the bias voltage Vb by the bias circuit 12 (for example, the voltage value is Vb + vin or Vb−vin). Signal) is transmitted.

  In the NMOS transistor MN1, a first transistor terminal is connected to a first power supply wiring (for example, a ground wiring to which the ground voltage GND is supplied), and a first input wiring Li1 is connected to a gate. In the NMOS transistor MN2, the first transistor terminal is connected to the first power supply line Lp1, and the second input line Li2 is connected to the gate.

  One end of the first capacitor C1 is connected to the first input wiring Li1. One end of the second capacitor C2 is connected to the second input wiring Li2.

  In the PMOS transistor MP1, a first transistor terminal is connected to a second power supply line Lp2 (for example, a power supply line that generates the power supply voltage VDD), and the other end of the first capacitor C1 is connected to a gate. In the PMOS transistor MP2, the first transistor terminal is connected to the second power supply line Lp2, and the other end of the second capacitor C2 is connected to the gate.

  In the rectifier circuit 10, the first inter-element wiring L1 connects the second transistor terminal of the NMOS transistor MN2, the second transistor terminal of the PMOS transistor MP2, and the gate of the PMOS transistor MP1. The second inter-element wiring L2 connects the second transistor terminal of the NMOS transistor MN1, the second transistor terminal of the PMOS transistor MP1, and the gate of the PMOS transistor MP2. In the rectifier circuit 10, the third capacitor C3 is connected between the first power supply line Lp1 and the second power supply line Lp2.

  Here, an example of the circuit configuration of the bias circuit 12 will be described. A circuit diagram showing an example of the bias circuit 12 is shown in FIG. As shown in FIG. 2, the bias circuit 12 has resistors R1 to R4. In FIG. 2, the first terminal T <b> 1 to the fourth terminal T <b> 4 are shown as terminals of the bias circuit 12.

  The resistors R3 and R4 are connected in series between a power supply wiring to which the power supply voltage VDD is supplied and a ground wiring to which the ground voltage GND is supplied. A bias voltage Vb having a voltage value obtained by dividing the power supply voltage VDD by the resistance ratio of the resistors R3 and R4 is generated at the contact point connecting the resistors R3 and R4.

  The resistors R1 and R2 are connected in series between the wiring that connects the first terminal T1 and the third terminal T3 and the wiring that connects the second terminal T2 and the fourth terminal T4. . And the contact which connects resistance R1, R2 and the contact which connects resistance R3, R4 are mutually connected. As a result, the bias voltage Vb is applied to the contact connecting the resistors R1 and R2, and the AC signal vin is superimposed on the bias voltage Vb.

  Next, the operation of the semiconductor device 1 according to the first embodiment will be described. FIG. 3 shows a timing chart showing the operation of the semiconductor device 1 according to the first embodiment. In the semiconductor device 1, the NMOS transistor MN1 and the PMOS transistor MP1 function as a first charge pump circuit, and the NMOS transistor MN2 and the PMOS transistor MP2 function as a second charge pump circuit. In the semiconductor device 1, the first charge pump circuit and the second charge pump circuit operate complementarily. Therefore, FIG. 3 shows only the operations of the NMOS transistor MN1 and the PMOS transistor MP2 among the operations of the semiconductor device 1. In the example shown in FIG. 3, the bias voltage Vb is 0V.

  As shown in FIG. 3, in the semiconductor device 1, alternating current signals whose phases are inverted are input to the NMOS transistor MN1 and the PMOS transistor MP2. Further, the signal input to the gate of the PMOS transistor MP2 is input with the common voltage Vcm as the center of amplitude. On the other hand, the AC signal input to the gate of the NMOS transistor MN1 is a signal centered on the amplitude of the bias voltage Vb having a voltage value lower than the common voltage Vcm. The example shown in FIG. 3 is an example in which the bias voltage Vb is set to 0V.

  The voltage of the second transistor terminal of the NMOS transistor MN1 has a waveform whose center is the amplitude of the common voltage Vcm and whose phase is inverted from that of the AC signal input to the gate. Further, since the voltage of the first transistor terminal of the NMOS transistor MN1 is connected to the ground wiring, the ground voltage (for example, 0 V) is maintained.

  On the other hand, the voltage of the second transistor terminal of the PMOS transistor MP2 has a waveform whose center is the amplitude of the common voltage Vcm and whose phase is inverted from that of the AC signal input to the gate. The voltage of the first transistor terminal of the PMOS transistor MP2 has a waveform that rises to a constant voltage value in accordance with the signal period.

  More specifically, the operation of the semiconductor device 1 is as follows. When a voltage equal to or higher than the threshold value of the NMOS transistor MN1 is applied between the second transistor terminal and the gate of the NMOS transistor MN1, the NMOS transistor MN1 is turned on. A drain current ID1 flows from the first transistor terminal of the NMOS transistor MN1 to the second transistor terminal. During a period in which a voltage equal to or higher than the threshold voltage of the NMOS transistor MN1 is applied to the gate of the NMOS transistor MN1, a low voltage level AC signal (a voltage applied to the gate of the NMOS transistor MN1) is applied to one end of the second capacitor C2. (Inverted signal). Therefore, the second capacitor C2 is charged by this drain current ID1.

  On the other hand, during a period when the gate of the NMOS transistor MN1 is supplied with a voltage equal to or higher than the threshold voltage of the NMOS transistor MN1, a voltage higher than the threshold voltage of the PMOS transistor MP2 is provided between the first transistor terminal and the control terminal of the PMOS transistor MP2. Is given. Therefore, the PMOS transistor MP2 is turned on, and the drain current ID2 flows. At this time, a high voltage AC signal (a signal given to the gate of the NMOS transistor MN1) is given to one end of the first capacitor C1. Therefore, the third capacitor C3 is charged via the PMOS transistor MP2 by the charge charged in the first capacitor C1 in the previous AC signal cycle. The charging current for the third capacitor C3 is the drain current ID2.

  With the operation as described above, in the semiconductor device 1, during the period indicated by hatching in FIG. 3, the second capacitor C2 is charged by the drain current ID1 and the third capacitor C3 is charged by the drain current ID2. Done. During the periods indicated by hatching in FIG. 3, the first capacitor C1 is charged by the drain current ID3 (not shown in FIG. 1) flowing in the NMOS transistor MN2, and the drain current ID4 flowing in the PMOS transistor MP1. The third capacitor C3 is charged by (not shown in FIG. 1).

  In the semiconductor device 1 according to the first embodiment, when performing the above-described operation, it is possible to reduce the leakage current that occurs in the vicinity of the switching of the polarity of the AC signal. This leakage current is generated during a period in which an AC signal is input to the semiconductor device 1 and is hereinafter referred to as a dynamic leakage current. Therefore, the dynamic leak current will be described below.

  FIG. 4 is a timing chart showing changes in current during operation of the semiconductor device according to the first embodiment. This timing chart is a result obtained by simulation. In FIG. 4, in the upper timing chart, the AC signal V01 input to the gate of the NMOS transistor MN1 and the voltage V02 of the second transistor terminal of the NMOS transistor MN1 (or the AC signal input to the gate of the PMOS transistor MP2). And showed. The lower timing chart of FIG. 4 is a timing chart showing changes in the drain current ID1.

  As shown in FIG. 4, in the semiconductor device 1 according to the first embodiment, the AC signal V01 input to the gate of the MOS transistor MN1 is applied to the gate of the MOS transistor MN1, and the second transistor terminal of the MOS transistor MN1 The drain current ID1 flows during a period in which the voltage between the gate and the NMOS transistor MN1 is equal to or higher than the threshold voltage. However, in the NMOS transistor MN1, the direction in which the drain current ID1 flows changes depending on the voltage relationship between the first transistor terminal and the second transistor terminal. More specifically, the voltage between the second transistor terminal and the gate of the NMOS transistor MN1 is higher than the threshold voltage of the NMOS transistor MN1, and the voltage at the first transistor terminal is higher than the voltage at the second transistor terminal. If higher, a drain current ID1 flows from the second transistor terminal toward the first transistor terminal (in the direction of the arrow in FIG. 1). On the other hand, if the voltage between the first transistor terminal and the gate of the NMOS transistor MN1 is larger than the threshold voltage of the NMOS transistor MN1, and the voltage of the second transistor terminal is higher than the voltage of the first transistor terminal, A drain current ID1 flows from the second transistor terminal toward the first transistor terminal (the direction opposite to the arrow direction in FIG. 1).

  As described above, in the periods TM11 and TM12 close to the start time and end time of the period in which the AC signal V01 is equal to or higher than the threshold voltage of the NMOS transistor MN1, the voltage V02 at the second transistor terminal of the NMOS transistor MN1 is the NMOS transistor. The voltage is higher than the voltage of the first transistor terminal of MN1 (0V in the case of FIG. 4), and the drain current ID1 flows in the reverse direction (direction from the second transistor terminal toward the first transistor terminal). Therefore, in the semiconductor device 1 according to the first embodiment, the period during which the second capacitor C2 is charged by the drain current ID1 is the second period in which the AC signal V01 is equal to or higher than the threshold voltage of the NMOS transistor MN1. The period TM21 during which the transistor terminal voltage V02 is 0 V or less is entered. During the periods TM11 and TM12, the NMOS transistor MN1 is turned on, and a current flowing in the reverse direction from the second inter-element wiring L2 toward the first power supply wiring Lp1 is generated and stored in the second capacitor C2. Part of the generated charge is lost as a leakage current.

  However, in the semiconductor device 1 according to the first embodiment, the time of the periods TM11 and TM12 occupying one cycle of the AC signal is very short as compared with a comparative example described later. Therefore, the semiconductor device 1 according to the first embodiment can extremely reduce the amount of leakage current generated with respect to the sum of the charging currents in one cycle of the AC signal, as compared with a comparative example described later. Therefore, as a comparative example, an operation in the case where the bias voltage of the AC signal applied to the gate of the NMOS transistor MN1 and the AC signal applied to the gate of the PMOS transistor MP2 is both set to the common voltage Vcm will be described.

  A circuit diagram of the semiconductor device 100 according to the comparative example is shown in FIG. As shown in FIG. 5, in the semiconductor device 100, the gate of the NMOS transistor MN1 and the gate of the PMOS transistor MP1 are connected in common, and an AC signal is given to these transistors via the capacitor C1. Further, the gate of the NMOS transistor MN2 and the gate of the PMOS transistor MP2 are connected in common, and these transistor AC signals are given through the capacitor C2.

  Next, FIG. 6 shows a timing chart showing changes in current during operation of the semiconductor device 100 according to the comparative example shown in FIG. The timing chart shown in FIG. 6 is obtained by performing the same simulation as the simulation shown in FIG. 4 on the semiconductor device 100 according to the comparative example of FIG.

  As shown in FIG. 6, in the semiconductor device 100 according to the comparative example, both of the AC signals input to the gates of the transistors have an amplitude centered on the common voltage Vcm. Therefore, in the semiconductor device 100 according to the comparative example, the lengths of the periods TM11 and TM12 in which the AC signal V01 is equal to or higher than the threshold voltage of the NMOS transistor MN1 and the voltage V02 of the second transistor terminal is 0 V or higher are shown in FIG. It becomes longer than the periods TM11 and TM12 shown in FIG. As a result, the semiconductor device 100 according to the comparative example has a problem that the period during which the drain current ID1 flows in the reverse direction is longer than that of the semiconductor device 1 according to the first embodiment. That is, the semiconductor device 100 according to the comparative example has a problem in which a part of the charge stored in the second capacitor C2 flows more than the example illustrated in FIG. 4 in which the leakage current that flows toward the first power supply line Lp1 flows. There is.

  From the above description, in the semiconductor device 1 according to the first embodiment, the bias voltage Vb of the AC signal applied to the gate of the NMOS transistor is set lower than the bias voltage (for example, the common voltage Vcm) applied to the gate of the PMOS transistor. Thereby, the semiconductor device 1 according to the first embodiment can reduce the reverse current (leakage current) generated in the NMOS transistor and improve the conversion efficiency of the AC signal.

  In particular, when energy recovery is performed using an environmental radio wave having a small amplitude, the amplitude of the AC signal input to the transistor is very small, and the rising and falling of the AC signal are gradual voltage changes. In such a case, the period in which the voltage of the second transistor terminal of the NMOS transistor is higher than the voltage of the first transistor terminal tends to be longer in the vicinity of the polarity switching timing of the AC signal. However, in the semiconductor device 1 according to the first embodiment, the voltage at the second transistor terminal of the NMOS transistor is higher than the voltage at the first transistor terminal near the timing of switching the polarity of the AC signal due to the configuration and operation as described above. The period of increase can be made extremely short. In other words, the semiconductor device 1 according to the first embodiment has a great effect of improving efficiency particularly when energy is recovered from an AC signal having a small amplitude.

  Here, Patent Document 1 also discloses a technique for applying different bias voltages to an NMOS transistor and a PMOS transistor. However, in the rectifier circuit of Patent Document 1, a capacitor for cutting off a DC voltage component and a resistor for applying a bias voltage are provided for each gate of the transistor. In such a configuration, a capacitor and a resistor must be provided on the chip, which causes a problem that the chip area increases. For example, in the rectifier circuit described in Patent Document 1, when trying to obtain a leakage reduction effect equivalent to that of the semiconductor device 1 according to the first embodiment, it is necessary to use a resistance value having a resistance value of several MΩ on the simulation. As a result of the verification, it was found that the increase in the chip area was remarkable.

  On the other hand, the semiconductor device 1 according to the first embodiment has a higher leakage due to the connection method between the gate and the capacitor without using the resistor and the capacitor and the inter-element wiring by the first inter-element wiring L1 and the second inter-element wiring L2. Since a current reduction effect can be obtained, the chip area can be made smaller than that of the rectifier circuit described in Patent Document 1.

Embodiment 2
In the second embodiment, another form of the semiconductor device 1 will be described. In the description of the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 7 shows a block diagram of the semiconductor device 2 according to the second embodiment. As illustrated in FIG. 7, the semiconductor device 2 according to the second embodiment is obtained by replacing the bias circuit 12 according to the first embodiment with a bias circuit 20. The bias circuit 20 adds a bias voltage Vb to the AC signal output from the AC signal source 11 using a resonance circuit.

  An example of the bias circuit 20 is shown in FIG. As shown in FIG. 8, the bias circuit 20 includes inductors L1 to L6. In FIG. 8, the first terminal T <b> 1 to the fourth terminal T <b> 4 are shown as the terminals of the bias circuit 20.

  The inductors L1 and L3 are connected in series between the first terminal T1 and the third terminal T3. The inductors L2 and L4 are connected in series between the second terminal T2 and the fourth terminal T4. The inductors L5 and L6 are connected in series between a wiring connecting the inductor L1 and the inductor L3 and a wiring connecting the inductor L2 and the inductor L4. The ground voltage GND is supplied as the bias voltage Vb to the wiring connecting the inductor L5 and the inductor L6. Thereby, the bias circuit 20 superimposes an AC signal on the ground voltage GND as the bias voltage Vb.

  In the semiconductor device 2 according to the second embodiment, the bias voltage Vb is generated by the resonance circuit. Thereby, in the semiconductor device 2 according to the second embodiment, not only the leakage current when the transistor is off, but also the forward current when the transistor is on can be increased. Therefore, in the semiconductor device 2 according to the second embodiment, the conversion efficiency can be improved as compared with the semiconductor device 1 according to the first embodiment. Further, since the DC bias voltage Vb given to the gate terminals of the NMOS transistors MN1 and MN2 is given only by the passive element inside the resonance circuit, power is not consumed for generating the bias voltage, and therefore the semiconductor according to the second embodiment. The device 2 can also reduce power consumption.

Embodiment 3
In Embodiment 3, another form of the rectifier circuit will be described. FIG. 9 is a block diagram of the semiconductor device 3 according to the third embodiment. In the description of the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  As illustrated in FIG. 9, the semiconductor device 3 according to the third embodiment includes a rectifier circuit 30 instead of the rectifier circuit 10 of the semiconductor device 1 according to the first embodiment. In the semiconductor device 3, the bias circuit 12 is not used.

  The rectifier circuit 30 includes a first bias addition circuit 31, a second bias addition circuit 32, a first transistor (for example, an NMOS transistor MN1), a second transistor (for example, a PMOS transistor MP1), and capacitors C11 and C3. Have.

  The first bias adding circuit 31 generates a first input signal (for example, VC1 + vin) by superimposing a first AC signal (for example, an AC signal + vin) on the first bias voltage VC1. In the NMOS transistor MN1, the first transistor terminal is connected to the first power supply line Lp1, and the first input signal is input to the gate.

  The second bias adding circuit 32 generates a second input signal (for example, VC2 + vin) by superimposing the first AC signal on the second bias voltage VC2 having a voltage higher than the first bias voltage VC1. In the PMOS transistor MP1, the first transistor terminal is connected to the second power supply line Lp2, and the second input signal is input to the gate.

  The second transistor terminal of the NMOS transistor MN1 and the second transistor terminal of the PMOS transistor MP1 are connected by an inter-element wiring L3. The capacitor C11 has one end connected to the inter-element wiring L3 and the other end to which a second AC signal (for example, AC signal -vin) whose phase is inverted from that of the first AC signal is input.

  Here, the first bias voltage VC1 and the second bias voltage VC2 will be described. The first bias voltage VC1 is a voltage lower than the common voltage Vcm generated in the inter-element wiring. By setting the first bias voltage VC1 to such a voltage, the leakage current can be reduced as in the semiconductor device 1 according to the first embodiment.

  The second bias voltage VC2 is higher than the voltage obtained by subtracting the threshold voltage Vth of the PMOS transistor MP1 from the power supply voltage VDD (VC2> VDD−Vth). By setting the second bias voltage VC2 to such a voltage, the leakage current flowing through the PMOS transistor MP1 can be reduced.

  Here, the operation of the semiconductor device 3 according to the third embodiment will be described. In the semiconductor device 3 according to the third embodiment, when an AC signal that increases the gate voltage of the NMOS transistor MN1 is input, the NMOS transistor MN1 is turned on and the PMOS transistor MP1 is turned off. At this time, a low voltage is input to the terminal on the input terminal IN2 side of the capacitor C11. Therefore, when an AC signal for increasing the gate voltage of the NMOS transistor MN1 is input, the semiconductor device 3 is in a period for charging the capacitor C11 with the drain current ID1.

  On the other hand, in the semiconductor device 3 according to the third embodiment, when an AC signal for decreasing the gate voltage of the NMOS transistor MN1 is input, the NMOS transistor MN1 is turned off and the PMOS transistor MP1 is turned on. A high voltage is input to the terminal on the input terminal IN2 side of the capacitor C11. Therefore, when an AC signal that lowers the gate voltage of the NMOS transistor MN1 is input, the semiconductor device 3 is in a period for charging the capacitor C3 with the charge accumulated in the capacitor C11.

  In the above-described operation, the semiconductor device 3 according to the third embodiment has the first bias voltage VC1 superimposed on the AC signal input to the NMOS transistor MN1 higher than the common voltage Vcm generated in the third inter-element wiring L3. The bias voltage of the AC signal input to the PMOS transistor MP1 is set higher than the first bias voltage VC1. Thereby, the semiconductor device 3 according to the third embodiment can reduce the leakage current more than the semiconductor device 1 according to the first embodiment.

  As shown in FIG. 9, the semiconductor device 3 according to the third embodiment can be formed with fewer circuit elements than the semiconductor device 1 according to the third embodiment.

Embodiment 4
In the fourth embodiment, an example of a semiconductor device using a plurality of rectifier circuits 10 according to the first embodiment will be described. FIG. 10 shows a block diagram of the semiconductor device 4 according to the fourth embodiment.

  As shown in FIG. 10, in the semiconductor device 4 according to the fourth embodiment, a rectifier circuit 101 and a rectifier circuit core 102 are connected in series. The rectifier circuit core 101 and the rectifier circuit core 102 are the same as the rectifier circuit 10. More specifically, the rectifier circuit core 101 and the rectifier circuit core 102 include a first output terminal OUT1 provided on the first power supply wiring of the rectifier circuit core 101 arranged in the lower stage, and a rectifier arranged in the upper stage. A second output terminal OUT2 provided on the second power supply wiring of the circuit core 102 is connected in cascade. Note that, in the rectifier circuit core 101 and the rectifier circuit core 102, the second output terminal OUT1 and the first output terminal OUT1 are cascade-connected through an internal circuit. In the semiconductor device 3, the smoothing capacitor Cload is connected between the first power supply wiring of the rectifier circuit 101 arranged in the first stage and the second power supply wiring of the rectifier circuit 102 arranged in the last stage. .

  In the semiconductor device 4, a bias circuit (for example, bias circuits 121 and 122) and an AC signal source (for example, AC signal sources 111 and 112) are connected for each rectifier circuit.

  In this way, by connecting the plurality of rectifier circuits 10 in cascade, the voltages generated by the rectifier circuits 10 are added, and a power supply voltage VDD higher than the voltage generated by one rectifier circuit 10 is given to the load 13. be able to.

Embodiment 5
In the fifth embodiment, another example of a semiconductor device using a plurality of rectifier circuits 10 according to the first embodiment will be described. FIG. 11 shows a block diagram of the semiconductor device 5 according to the fifth embodiment.

  As shown in FIG. 11, in the semiconductor device 5 according to the fifth embodiment, n rectifier circuits 10 are connected in parallel. In FIG. 11, the rectifier circuit 101 and the rectifier circuit core 10 n among the n rectifier circuits 10 are illustrated. More specifically, in the semiconductor device 5, the first output terminals OUT1 of the rectifier circuit core 101 to the rectifier circuit core 10n are connected to the load 13 through the common wiring. A smoothing capacitor Cload is connected between the common wiring and the ground wiring.

  In the semiconductor device 5, a bias circuit (for example, bias circuits 121 to 12n) and an AC signal source (for example, AC signal sources 111 to 11n) are connected to each rectifier circuit.

  In this way, by connecting a plurality of rectifier circuits 10 in parallel, a higher current supply capability than that of a power source generated by one rectifier circuit 10 can be realized. Note that a plurality of rectifier circuits 10 connected in cascade as in the semiconductor device 4 according to the fourth embodiment are used as a set of power supplies, and a matrix connection that further connects the sets of power supplies in parallel is formed. Supply and high current supply capability can be realized simultaneously.

Embodiment 6
In the sixth embodiment, a semiconductor device that supplies power having high stability using the rectifier circuit 10 according to the first embodiment will be described. FIG. 12 is a block diagram of the semiconductor device 6 according to the sixth embodiment.

  As shown in FIG. 12, the semiconductor device 6 according to the sixth embodiment includes a power supply circuit 60 between the rectifier circuit 10 and a load 61. The power supply circuit 60 generates a second power supply voltage VDD2 by boosting or stepping down the first power supply voltage VDD1 transmitted through the second power supply wiring.

  In this way, by providing the power supply circuit 60 between the rectifier circuit 10 and the load 61, the voltage applied to the load 61 is constant even when an MCU (Micro Controller Unit) or the like with large fluctuations in power consumption is connected as the load 61. Can be maintained.

Embodiment 7
In the seventh embodiment, another form of the semiconductor device 1 according to the first embodiment will be described. In the description of the seventh embodiment, the components described in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.

  FIG. 13 is a block diagram of the semiconductor device 7 according to the seventh embodiment. As illustrated in FIG. 13, the semiconductor device 7 according to the seventh embodiment includes a rectifier circuit 70 instead of the rectifier circuit 10. In the semiconductor device 7, an AC signal output from the AC signal source 11 is applied to the rectifier circuit 70 without using the bias circuit 12.

  The rectifier circuit 70 includes a first transistor (for example, NMOS transistor MN1), a second transistor (for example, NMOS transistor MN2), a third transistor (for example, PMOS transistor MP1), and a fourth transistor (PMOS transistor MP2). , A fifth transistor (for example, PMOS transistor MP3), a sixth transistor (for example, PMOS transistor MP4), a seventh transistor (for example, NMOS transistor MN3), and capacitors C1, C2, and C3. In the semiconductor device 7 according to the seventh embodiment, since the NMOS transistor MN3 is inserted over the second power supply line Lp2, the PMOS transistor MP1 and MP2 side of the second power supply line Lp2 with respect to the NMOS transistor MN3. The second power supply wiring is Lp21, and the second power supply wiring closer to the first output terminal OUT1 than the NMOS transistor MN3 is Lp22.

  In the rectifier circuit 70, the first input wiring Li1 is connected to the first input terminal IN1 via the capacitor C1. In the rectifier circuit 70, the second input line Li2 is connected to the second input terminal IN2 via the capacitor C2. The first input wiring Li1 and the second input wiring Li2 are wirings through which alternating signals whose phases are inverted from each other are transmitted.

  In the NMOS transistor MN1, the first transistor terminal is connected to the first power supply line Lp1, and the first input line Li1 is connected to the gate. In the NMOS transistor MN2, the first transistor terminal is connected to the first power supply line Lp1, and the second input line Li2 is connected to the gate.

  The PMOS transistor MP1 has a first transistor terminal connected to the second power supply line Lp21, a second transistor terminal connected to the second transistor terminal of the NMOS transistor MN1, and a gate connected to the first input line Li1. Is done. In the PMOS transistor MP2, the first transistor terminal is connected to the second power supply wiring Lp21, the second transistor terminal of the NMOS transistor MN2 is connected to the second transistor terminal, and the second input wiring Li2 is connected to the gate. Is done.

  The PMOS transistor MP3 has a gate connected to the first input line Li1, and a second transistor terminal connected to the second transistor terminal of the PMOS transistor MP1. The PMOS transistor MP4 has a gate connected to the second input line Li2, and a second transistor terminal connected to the second transistor terminal of the PMOS transistor MP2. The NMOS transistor MN3 is inserted into the second power supply line Lp2 (between the second power supply line Lp21 and the second power supply line Lp22), and the gate thereof is the first transistor terminal of the PMOS transistor MP3 and the first transistor terminal of the PMOS transistor MP4. 1 transistor terminal.

  In the rectifier circuit 70, the capacitor C3 is connected between the first power supply line Lp1 and the second power supply line Lp2.

  Next, the operation of the semiconductor device 7 according to the seventh embodiment will be described. FIG. 14 is a timing chart showing the operation of the semiconductor device 7 according to the seventh embodiment. As shown in FIG. 14, in the semiconductor device 7 according to the seventh embodiment, the two AC signals have amplitudes centered on the common voltage Vcm. The gate voltage V03 of the NMOS transistor MN3 increases every time one of the two AC signals (voltages V01 and V02) increases. The voltage of the second power supply line Lp2 changes at a voltage lower than the gate voltage V03 of the NMOS transistor MN3 by the threshold voltage of the NMOS transistor MN3. As a result, the power supply voltage VDD generated at the first output terminal OUT1 is a voltage that is slightly lower than the voltage fluctuation of the second power supply wiring Lp21 and is substantially constant. This is because the capacitor C3 is charged from the capacitor C1 or the capacitor C2 in accordance with the change of the AC signals V01 and V02.

  Here, the semiconductor device 7 according to the seventh embodiment has an effect of reducing leakage current when the AC signal source 11 stops outputting signals (this state is referred to as a no-signal state). Hereinafter, the leakage current in the no-signal state is referred to as static leakage current.

  Therefore, the operation of the semiconductor device 7 in the no-signal state will be described. When the semiconductor device 7 according to the seventh embodiment is in the no-signal state, immediately after the no-signal state, the gate voltages of the NMOS transistors MN1 and MN2 and the PMOS transistors MP1 to MP4 are set to voltages near the common voltage Vcm. Become. Therefore, a leak current is generated from the second power supply line Lp22 toward the first power supply line Lp1.

  However, at this time, charge is also extracted from the wiring connected to the gate of the NMOS transistor MN3. Thereafter, charge is extracted from the wiring connected to the gate of the NMOS transistor MN3, and when the gate voltage V03 of the NMOS transistor MN3 decreases to a level lower than the threshold voltage of the NMOS transistor MN3, the NMOS transistor MN3 enters a cutoff state. Then, when the NMOS transistor MN3 is cut off, the leakage current flowing from the second power supply line Lp21 to the first power supply line Lp1 is cut off.

  The effect of reducing the static leakage current will be described below. First, a simulation circuit for verifying the effect of reducing static leakage current will be described. FIG. 15 is a diagram for explaining the conditions for the simulation of the leakage current amount in the semiconductor device according to the seventh embodiment. As shown in FIG. 15, in this simulation, a circuit in which a voltage source Vleak and an ammeter are connected in series is provided instead of the load 13. And the graph which shows the simulation result using the simulation circuit shown in FIG. 15 is shown in FIG.

  In FIG. 16, as a comparative example, the result of simulation using the circuit of the comparative example shown in FIG. 5 and the simulation conditions shown in FIG. 15 is shown together with the simulation result of the semiconductor device 7 according to the seventh embodiment.

  As shown in FIG. 16, in the semiconductor device 100 according to the comparative example, the leakage current Ileak increases as the voltage of the voltage source Vleak increases. On the other hand, in the semiconductor device 7 according to the seventh embodiment, when the voltage of the voltage source Vleak becomes a certain level or more, the increase in the leakage current Ileak is small so as to gradually approach a certain value. In the right end portion of the graph shown in FIG. 16, the leakage current of the semiconductor device 7 according to the seventh embodiment is approximately two orders of magnitude smaller than that of the semiconductor device 1 according to the comparative example.

  From the above description, in the semiconductor device 7 according to the seventh embodiment, it is possible to reduce the leakage current in the no-signal state where the AC signal output from the AC signal source 11 stops. This is particularly effective in a form in which a plurality of rectifier circuits 10 as shown in FIG. 10 are connected in series or in a form in which a plurality of rectifier circuits 10 as shown in FIG. 11 are connected in parallel. Is expensive. When a plurality of rectifier circuits 10 are connected, when an AC signal source corresponding to any one of the plurality of rectifier circuits 10 is in a no-signal state, the power generated by the other rectifier circuits 10 is in a no-signal state. This is because the rectifier circuit 10 is pulled out, and a power loss more than that in which one AC signal source becomes no signal is generated. Even in such a state, by using the semiconductor device 7 according to the seventh embodiment, the rectifier circuit 10 in the no-signal state does not lose the power generated by the rectifier circuit 10 during other operations. The semiconductor device 7 is effective for improving the conversion efficiency.

Embodiment 8
In the eighth embodiment, another form of the semiconductor device 1 according to the first embodiment will be described. Note that in the description of the eighth embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 17 is a block diagram of the semiconductor device 8 according to the eighth embodiment. As illustrated in FIG. 17, the semiconductor device 8 according to the eighth embodiment includes a rectifier circuit 80 instead of the rectifier circuit 10 according to the first embodiment. The rectifier circuit 80 is obtained by adding the PMOS transistors MP3 and MP4 and the NMOS transistor MN3 described in the rectifier circuit 70 to the rectifier circuit 10. That is, in the rectifier circuit 80, the PMOS transistor MP3 has a second transistor terminal connected to the second inter-element wiring L2 and a gate connected to the other end of the first capacitor C1. The PMOS transistor MP4 has a second transistor terminal connected to the first inter-element wiring L1, and a gate connected to the other end of the second capacitor C2. The NMOS transistor MN3 is inserted into the second power supply line Lp2 (between the second power supply line Lp21 and the second power supply line Lp22), and the gate thereof is the first transistor terminal of the PMOS transistor MP3 and the first transistor terminal of the PMOS transistor MP4. 1 transistor terminal.

  In this way, by adding the PMOS transistors MP3 and MP4 and the NMOS transistor MN3 described in the rectifier circuit 70 of the seventh embodiment to the rectifier circuit 10, in addition to the dynamic leakage current described in the first embodiment, the seventh embodiment. The static leakage current described in (1) can be reduced. Thereby, the semiconductor device 8 according to the eighth embodiment can realize a high leakage current reduction effect and can further increase the conversion efficiency.

Embodiment 9
In the ninth embodiment, another form of the semiconductor device 3 according to the third embodiment will be described. In the description of the ninth embodiment, the same components as those described in the third embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 18 is a block diagram of the semiconductor device 9 according to the ninth embodiment. As illustrated in FIG. 18, the semiconductor device 9 according to the ninth embodiment has the same deformation as the semiconductor device 7 according to the seventh embodiment from the first embodiment to the semiconductor device 3 according to the third embodiment. It has been applied. The semiconductor device 9 according to the ninth embodiment includes a rectifier circuit 90 instead of the rectifier circuit 30. The rectifier circuit 90 is obtained by adding the PMOS transistor MP3 and the NMOS transistor MN3 described in the rectifier circuit 70 to the rectifier circuit 30 and omitting the first bias addition circuit 31 and the second bias addition circuit 32. That is, in the rectifier circuit 90, the PMOS transistor MP3 has the second transistor terminal connected to the second transistor terminal of the PMOS transistor MP1, and the first AC signal is input to the gate. The NMOS transistor MN3 is inserted into the second power supply line Lp2 (between the second power supply line Lp21 and the second power supply line Lp22), and the gate is connected to the first transistor terminal of the PMOS transistor MP3.

  Thus, by adding the PMOS transistors MP3 and MP4 and the NMOS transistor MN3 described in the rectifier circuit 70 of the seventh embodiment to the rectifier circuit 30, the rectifier circuit 30 described in the third embodiment also has the seventh embodiment. The static leakage current described in (1) can be reduced. Thereby, the semiconductor device 9 according to the ninth embodiment can achieve a high leakage current reduction effect and further increase the conversion efficiency.

  In the semiconductor device 9 according to the ninth embodiment, the bias addition circuits 31 and 32 of the semiconductor device 3 according to the third embodiment shown in FIG. 9 can be applied. By applying the bias addition circuits 31 and 32, the dynamic leakage current can be reduced also in the semiconductor device 9 according to the ninth embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  From the above embodiment, the following viewpoints can be considered.

(Appendix 1)
A semiconductor device having a rectifier circuit, wherein the rectifier circuit is
First and second input wirings through which alternating signals whose phases are inverted from each other are transmitted;
A first transistor of a first conductivity type, wherein a first transistor terminal is connected to a first power supply wiring, and the first input wiring is connected to a gate;
A first conductivity type second transistor having a first transistor terminal connected to the first power supply wiring and a gate connected to the second input wiring;
A second transistor terminal is connected to a first transistor terminal, a second transistor terminal is connected to a second transistor terminal of the first transistor, and a gate is connected to the first input line. A third transistor of conductivity type;
A first transistor terminal is connected to the second power supply wiring, a second transistor terminal of the second transistor is connected to the second transistor terminal, and a second input wiring is connected to the gate. A second transistor of two conductivity types;
A second transistor of the second conductivity type having a gate connected to the first input wiring and a second transistor terminal connected to the second transistor terminal of the third transistor;
A second transistor of the second conductivity type having the gate connected to the second input wiring and the second transistor terminal connected to the second transistor terminal of the fourth transistor;
A seventh transistor of the first conductivity type inserted into the second power supply wiring and having a gate connected to a first transistor terminal of the fifth transistor and a first transistor terminal of the sixth transistor; ,
A semiconductor device.

(Appendix 2)
A semiconductor device having a rectifier circuit, wherein the rectifier circuit is
A first bias circuit for generating a first input signal by superimposing a first alternating signal on a first bias voltage;
A first transistor of a first conductivity type, wherein a first transistor terminal is connected to a first power supply wiring, and the first input signal is input to a gate;
A second bias circuit that generates a second input signal by superimposing the first AC signal on a second bias voltage that is higher than the first bias voltage;
A second transistor of a second conductivity type, wherein a first transistor terminal is connected to a second power supply wiring, and the second input signal is input to a gate;
An inter-element wiring connecting the second transistor terminal of the first transistor and the second transistor terminal of the second transistor;
A capacitor having one end connected to the inter-element wiring and the other end receiving a second AC signal whose phase is inverted from that of the first AC signal;
A semiconductor device.

(Appendix 3)
A semiconductor device having a rectifier circuit, wherein the rectifier circuit is
A first transistor of a first conductivity type, wherein a first transistor terminal is connected to a first power supply wiring, and the first AC signal is input to a gate;
A second transistor of a second conductivity type, wherein a first transistor terminal is connected to a second power supply wiring, and the first AC signal is input to a gate;
A second transistor of the second conductivity type having a gate connected to the first AC signal and a second transistor terminal connected to a second transistor terminal of the second transistor;
A fourth transistor of the first conductivity type inserted into the second power supply wiring and having a gate connected to a first transistor terminal of the third transistor;
An inter-element wiring connecting the second transistor terminal of the first transistor, the second transistor terminal of the second transistor, and the second transistor terminal of the third transistor;
A capacitor having one end connected to the inter-element wiring and the other end receiving a second AC signal whose phase is inverted from that of the first AC signal;
A semiconductor device.

1-9 Semiconductor device 10, 30, 70, 80, 90 Rectifier circuit 11, 111-11n AC signal source 12, 121-12n Bias circuit 13, 61 Load 20 Bias circuit 30 Rectifier circuit 31, 32 Bias addition circuit 501-50n Rectifier circuit 60 Power supply circuit 101, 102 Rectifier circuit core Li1 First input wiring Li2 Second input wiring L1 First inter-element wiring L2 Second inter-element wiring L3 Third inter-element wiring Lp1 First power supply wiring Lp2 Second power supply wiring MN1 to MN3 NMOS transistor MP1 to MP4 PMOS transistor L1 First element sensing wiring L2 Second element sensing wiring Li1 First input wiring Li2 Second input wiring

Claims (15)

A semiconductor device having a rectifier circuit, wherein the rectifier circuit is
First and second input wirings through which alternating signals whose phases are inverted from each other are transmitted;
A first transistor of a first conductivity type, wherein a first transistor terminal is connected to a first power supply wiring, and the first input wiring is connected to a gate;
A first conductivity type second transistor having a first transistor terminal connected to the first power supply wiring and a gate connected to the second input wiring;
A second transistor terminal is connected to a first transistor terminal, a second transistor terminal is connected to a second transistor terminal of the first transistor, and a gate is connected to the first input line. A third transistor of conductivity type;
A first transistor terminal is connected to the second power supply wiring, a second transistor terminal of the second transistor is connected to the second transistor terminal, and a second input wiring is connected to the gate. A second transistor of two conductivity types;
A second transistor of the second conductivity type having a gate connected to the first input wiring and a second transistor terminal connected to the second transistor terminal of the third transistor;
A second transistor of the second conductivity type having the gate connected to the second input wiring and the second transistor terminal connected to the second transistor terminal of the fourth transistor;
A seventh transistor of the first conductivity type inserted into the second power supply wiring and having a gate connected to a first transistor terminal of the fifth transistor and a first transistor terminal of the sixth transistor; ,
A semiconductor device.   The semiconductor device according to claim 1, further comprising a third capacitor connected between the first power supply wiring and the second power supply wiring. A plurality of rectifier circuits in which a first output terminal provided on the first power supply wiring and a second output terminal provided on the second power supply wiring are connected in cascade;
2. A smoothing capacitor connected between the first power supply wiring of the rectifier circuit arranged in the first stage and the second power supply wiring of the rectifier circuit arranged in the last stage. A semiconductor device according to 1. A plurality of rectifier circuits each having a first output terminal provided on the first power supply wiring additionally connected via a common wiring;
The semiconductor device according to claim 1, further comprising a smoothing capacitor connected between the common wiring and the ground wiring.   The second power supply is connected between the first power supply wiring and the second power supply wiring and boosts or steps down the first power supply voltage transmitted through the second power supply wiring. The semiconductor device according to claim 1, further comprising a power supply circuit that generates a voltage. A semiconductor device having a rectifier circuit, wherein the rectifier circuit is
A first bias circuit for generating a first input signal by superimposing a first alternating signal on a first bias voltage;
A first transistor of a first conductivity type, wherein a first transistor terminal is connected to a first power supply wiring, and the first input signal is input to a gate;
A second bias circuit that generates a second input signal by superimposing the first AC signal on a second bias voltage that is higher than the first bias voltage;
A second transistor of a second conductivity type, wherein a first transistor terminal is connected to a second power supply wiring, and the second input signal is input to a gate;
An inter-element wiring connecting the second transistor terminal of the first transistor and the second transistor terminal of the second transistor;
A capacitor having one end connected to the inter-element wiring and the other end receiving a second AC signal whose phase is inverted from that of the first AC signal;
A semiconductor device.   The semiconductor device according to claim 6, further comprising a third capacitor connected between the first power supply wiring and the second power supply wiring. A plurality of rectifier circuits in which a first output terminal provided on the first power supply wiring and a second output terminal provided on the second power supply wiring are connected in cascade;
7. A smoothing capacitor connected between the first power supply wiring of the rectifier circuit arranged in the first stage and the second power supply wiring of the rectifier circuit arranged in the final stage. A semiconductor device according to 1. A plurality of rectifier circuits each having a first output terminal provided on the first power supply wiring additionally connected via a common wiring;
The semiconductor device according to claim 6, further comprising a smoothing capacitor connected between the common wiring and the ground wiring.   The second power supply is connected between the first power supply wiring and the second power supply wiring and boosts or steps down the first power supply voltage transmitted through the second power supply wiring. The semiconductor device according to claim 6, further comprising a power supply circuit that generates a voltage. A semiconductor device having a rectifier circuit, wherein the rectifier circuit is
A first transistor of a first conductivity type having a first transistor terminal connected to the first power supply wiring and a first AC signal input to the gate;
A second transistor of a second conductivity type, wherein a first transistor terminal is connected to a second power supply wiring, and the first AC signal is input to a gate;
A second transistor of the second conductivity type having a gate connected to the first AC signal and a second transistor terminal connected to a second transistor terminal of the second transistor;
A fourth transistor of the first conductivity type inserted into the second power supply wiring and having a gate connected to a first transistor terminal of the third transistor;
An inter-element wiring connecting the second transistor terminal of the first transistor, the second transistor terminal of the second transistor, and the second transistor terminal of the third transistor;
A capacitor having one end connected to the inter-element wiring and the other end receiving a second AC signal whose phase is inverted from that of the first AC signal;
A semiconductor device.   The semiconductor device according to claim 11, further comprising a third capacitor connected between the first power supply wiring and the second power supply wiring. A plurality of rectifier circuits in which a first output terminal provided on the first power supply wiring and a second output terminal provided on the second power supply wiring are connected in cascade;
12. A smoothing capacitor connected between the first power supply wiring of the rectifier circuit arranged in the first stage and the second power supply wiring of the rectifier circuit arranged in the last stage. A semiconductor device according to 1. A plurality of rectifier circuits each having a first output terminal provided on the first power supply wiring additionally connected via a common wiring;
The semiconductor device according to claim 11, further comprising a smoothing capacitor connected between the common wiring and the ground wiring.   The second power supply is connected between the first power supply wiring and the second power supply wiring and boosts or steps down the first power supply voltage transmitted through the second power supply wiring. The semiconductor device according to claim 11, further comprising a power supply circuit that generates a voltage.

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