JP4932584B2 - Synchronous rectification type switching regulator - Google Patents

Description

  The present invention relates to a synchronous rectification type switching regulator, and more particularly to a synchronous rectification type switching regulator capable of achieving high efficiency at a light load in an IC circuit.

FIG. 5 is a diagram illustrating a circuit example of a conventional synchronous rectification switching regulator (see, for example, Patent Document 1).
The switching regulator of FIG. 5 is a step-down synchronous rectification switching regulator, and current flows backward from the output terminal 104 to the ground voltage GND through the NMOS transistor QN1 at a light load. In order to prevent the occurrence of such reverse current, the switching regulator of FIG. 5 uses the detection circuit 131 to cause the voltage at the connection portion K between the PMOS transistor QP1 and the NMOS transistor QN1 to undershoot below the ground voltage GND. After that, the rising timing again exceeding the ground voltage GND is detected at high speed, and the NMOS transistor QN1 is quickly turned off to prevent the occurrence of reverse current, thereby reducing power consumption.
JP 2004-56982 A

  However, in the switching regulator of FIG. 5, when the reverse current is detected by the detection circuit 131, the NMOS transistor QN1 is turned off via the output driver 132. For this reason, there is a problem that a delay time occurs from when the reverse current is detected until the NMOS transistor QN1 is turned off, and the time during which the reverse current flows from the output terminal 104 via the coil L1 becomes long, resulting in a decrease in efficiency. It was.

  The present invention has been made to solve the above-described problems, and can improve the efficiency by reducing the delay time from detection of the occurrence of reverse current until the reverse current is cut off. An object of the present invention is to obtain a synchronous rectification type switching regulator that can be made to operate.

A synchronous rectification switching regulator according to the present invention is a synchronous rectification switching regulator that converts an input voltage input to an input terminal to a predetermined constant voltage and outputs the voltage to a load connected to the output terminal.
A first switching element that performs switching according to an input control signal;
An inductor charged by the input voltage by switching of the first switching element;
A second switching element for synchronous rectification that performs switching according to an input control signal to discharge the inductor;
The switching control for the first switching element is performed so that the output voltage output from the output terminal becomes the predetermined constant voltage, and the second switching element is in conflict with the first switching element. A control circuit unit for performing a switching operation;
In order to prevent the occurrence of reverse current flowing from the output terminal to the second switching element, the wiring of the second switching element is cut off to cut off the connection of the second switching element. A reverse current prevention circuit section for cutting off a current flowing through the switching element;
Equipped with a,
When the reverse current prevention circuit unit detects that the voltages at both ends of the second switching element are equal, the reverse current prevention circuit unit determines that the sign of occurrence of the reverse current has been detected, and interrupts the wiring of the second switching element. Is.

  According to the synchronous rectification type switching regulator of the present invention, in order to prevent the generation of a reverse current flowing from the output terminal toward the second switching element, the second switching element is disconnected and the second switching element is disconnected. The current flowing through the switching element was cut off. Therefore, since the reverse current flowing through the second switching element can be interrupted using a circuit independent of the control circuit system of the second switching element, the reverse current is detected after the occurrence of the reverse current is detected. It is possible to shorten the delay time until the circuit is shut off, improve the efficiency, design is easy, and the design can be made more efficient.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram illustrating a circuit example of a synchronous rectification switching regulator according to a first embodiment of the present invention.
In FIG. 1, a switching regulator 1 is a synchronous rectification type switching regulator that converts an input voltage Vin input to an input terminal IN as an input voltage into a predetermined constant voltage, and outputs the voltage as an output voltage Vout from the output terminal OUT to the load 10. is there.
The switching regulator 1 includes a first switching element M1 made of a PMOS transistor that performs a switching operation for performing output control of the input voltage Vin, and a second switching element M2 for synchronous rectification made of an NMOS transistor. .

  Further, the switching regulator 1 includes a reference voltage generation circuit 2, output voltage detection resistors R1 and R2, an inductor L1, a smoothing capacitor C1, a phase compensation resistor R3 and capacitors C2 and C3, and an error. The amplifier circuit 3, the oscillation circuit 4, the PWM comparator 5, the buffers BF 1 and BF 2, the third switching element M 3 made of an NMOS transistor, and the reverse current detection circuit 6 are provided. The reverse current detection circuit 6 includes a comparator 11 and a buffer BF3. In the switching regulator 1, the reference voltage generating circuit 2, the resistors R1 to R3, the error amplifying circuit 3, the oscillation circuit 4, the PWM comparator 5, the buffers BF1 and BF2, and the capacitors C2 and C3 form a control circuit unit. The switching element M3 and the reverse current detection circuit 6 form a reverse current prevention circuit unit. In the switching regulator 1, each circuit excluding the inductor L1 and the capacitor C1 may be integrated in one IC. Depending on the case, the first to third switching elements M1 to M3, the inductor L1 and the capacitor may be integrated. Each circuit except C1 may be integrated in one IC.

The reference voltage generating circuit 2 generates and outputs a predetermined reference voltage Vref, and the output voltage detection resistors R1 and R2 divide the output voltage Vout to generate and output a divided voltage VFB. The error amplifying circuit 3 amplifies the voltage difference between the input divided voltage VFB and the reference voltage Vref to generate and output an output signal EAo.
The oscillation circuit 4 generates and outputs a predetermined triangular wave signal TW, and the PWM comparator 5 generates a pulse signal Spw for performing PWM control from the output signal EAo of the error amplification circuit 3 and the triangular wave signal TW. Output. The pulse signal Spw is input to the gate of the first switching element M1 through the buffer BF1, and is input to the gate of the second switching element M2 through the buffer BF2. The reverse current detection circuit 6 detects a sign that a reverse current is generated in the second switching element M2, and when the sign of the reverse current is detected, the third switching element M3 is turned off to turn off the second switching element M2. And the ground voltage is disconnected to prevent the occurrence of reverse current.

  The first to third switching elements M1 to M3 are connected in series between the input terminal IN and the ground voltage, and a connection portion between the first switching element M1 and the second switching element M2 is Lx1. . An inductor L1 is connected between the connection portion Lx1 and the output terminal OUT, and resistors R1 and R2 are connected in series and a capacitor C1 is connected between the output terminal OUT and the ground voltage. A divided voltage VFB is output from the connection with R2. In addition, a phase compensation capacitor C2 is connected in parallel to the resistor R1. In the error amplifier circuit 3, the divided voltage VFB is input to the inverting input terminal, the reference voltage Vref is input to the non-inverting input terminal, and the output terminal is connected to the inverting input terminal of the PWM comparator 5.

  Further, a series circuit of a resistor R3 and a capacitor C3 is connected between the output terminal of the error amplifier circuit 3 and the ground voltage, and the series circuit forms a phase compensation circuit. The triangular wave signal TW is input to the non-inverting input terminal of the PWM comparator 5, and the pulse signal Spw output from the PWM comparator 5 is supplied to the gate of the first switching element M1 through the buffer BF1 and through the buffer BF2. 2 are respectively input to the gates of the switching elements M2. The inverting input terminal of the comparator 11 is connected to the connection portion Lx1, and the non-inverting input terminal of the comparator 11 is connected to the ground voltage. The output terminal of the comparator 11 is connected to the gate of the third switching element M3 via the buffer BF3.

  In such a configuration, when the voltage at the connection portion Lx1 is less than the ground voltage and there is no sign that a reverse current flows from the connection portion Lx1 to the ground voltage, a high level signal is output from the comparator 11. The third switching element M3 is turned on and becomes conductive. In such a state, when the output voltage Vout of the switching regulator 1 increases, the voltage of the output signal EAo of the error amplifier circuit 3 decreases, and the duty cycle of the pulse signal Spw from the PWM comparator 5 decreases. As a result, the time for which the first switching element M1 is turned on is shortened, and the time for which the second switching element M2 is turned on is lengthened accordingly, so that the output voltage Vout of the switching regulator 1 is controlled to decrease. .

Further, when the output voltage Vout of the switching regulator 1 decreases, the voltage of the output signal EAo of the error amplifier circuit 3 increases, and the duty cycle of the pulse signal Spw from the PWM comparator 5 increases. As a result, the time for turning on the first switching element M1 is lengthened, and the time for turning on the second switching element M2 is shortened accordingly, and the output voltage Vout of the switching regulator 1 is controlled to rise. . By repeating such an operation, the output voltage Vout is controlled to be constant at a predetermined voltage.
Next, when the voltage of the connection part Lx1 becomes the ground voltage and the sign that the reverse current is generated is detected, or when the voltage of the connection part Lx1 exceeds the ground voltage and the generation of the reverse current is detected, the comparator 11 A low level signal is output, and the third switching element M3 is turned off to be in a cut-off state. At this time, the second switching element M2 remains on.

  As described above, the reverse current detection circuit 6 detects whether or not there is a sign that the reverse current flows to the second switching element M2 from the voltage of the connection portion Lx1, and when the sign is detected, the second switching element M2 is detected. The third switching element M3 connected in series is turned off to disconnect the connection between the second switching element M2 and the ground voltage. For this reason, generation | occurrence | production of the reverse current which flows into the 2nd switching element M2 can be prevented reliably. In addition, since the reverse current flowing through the second switching element M2 is cut off using a circuit independent of the control circuit system of the second switching element M2, the reverse current is detected after the occurrence of the reverse current is detected. The delay time until the current is cut off can be shortened, the efficiency can be improved, the design is easy, and the design efficiency can be improved.

Next, in FIG. 1, the voltage mode control type switching regulator has been described as an example. However, the present invention can also be applied to a current mode control type switching regulator. In this case, FIG. It becomes like this. 2 that are the same as or similar to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here, and only differences from FIG. 1 are described.
2 differs from FIG. 1 in that the oscillation circuit 4 in FIG. 1 is eliminated, a current detection circuit 15, an oscillation circuit 16 that generates and outputs a clock signal CLK having a predetermined rectangular wave, a slope compensation circuit 17, and an addition. The circuit 18 and the flip-flop circuit 19 are added.

  The switching regulator 1 of FIG. 2 includes a first switching element M1, a second switching element M2 for synchronous rectification, a reference voltage generation circuit 2, resistors R1 and R2 for output voltage detection, an inductor L1, Smoothing capacitor C1, phase compensation resistor R3 and capacitors C2 and C3, error amplifier circuit 3, PWM comparator 5, buffers BF1 and BF2, third switching element M3, and reverse current detection circuit 6 And. Furthermore, the switching regulator 1 includes a current detection circuit 15, an oscillation circuit 16 that generates and outputs a clock signal CLK, a slope compensation circuit 17 that generates and outputs a predetermined sawtooth wave signal Sstw from the clock signal CLK, An adder circuit 18 and a flip-flop circuit 19 are provided.

  The current detection circuit 15 is configured by a series circuit of a resistor R4 and a fourth switching element M4, and the fourth switching element M4 includes a MOS transistor having the same type as the first switching element M1, that is, a PMOS transistor. In FIG. 2, the reference voltage generation circuit 2, resistors R1 to R3, error amplification circuit 3, oscillation circuit 16, PWM comparator 5, buffers BF1 and BF2, capacitors C2 and C3, current detection circuit 15, slope compensation circuit 17, The adder circuit 18 and the flip-flop circuit 19 form a control circuit unit.

  The clock signal CLK output from the oscillation circuit 16 is input to the set input terminal S of the slope compensation circuit 17 and the flip-flop circuit 19, and the slope compensation circuit 17 generates a sawtooth signal Sstw from the input clock signal CLK. And output to the adder circuit 18. The series circuit of the resistor R4 and the fourth switching element M4 is connected in parallel with the first switching element M1. The gate of the fourth switching element M4 is connected to the gate of the first switching element M1, and the fourth switching element M4 is turned on / off in synchronization with the first switching element M1. A current proportional to the current output from the first switching element M1 flows through the resistor R4, the current is converted into a voltage by the resistor R4, and the voltage at the connection between the resistor R4 and the fourth switching element M4 is a signal. It is output to the adder circuit 18 as Scu.

The adder circuit 18 adds the input sawtooth wave signal Sstw and the signal Scu and outputs the result to the non-inverting input terminal of the PWM comparator 5.
The PWM comparator 5 generates a pulse signal Spw for performing PWM control from the output signal EAo of the error amplifier circuit 3 and the signal output from the adder circuit 18 and outputs the pulse signal Spw to the reset input terminal R of the flip-flop circuit 19. The inverting output terminal QB of the flip-flop circuit 19 is connected to the gates of the first and fourth switching elements M1 and M4 via the buffer BF1, and is connected to the gate of the second switching element M2 via the buffer BF2. It is connected to the.

  In such a configuration, the clock signal CLK is input to the set input terminal S of the flip-flop circuit 19, and the flip-flop circuit 19 is set at the rising or falling edge of the clock signal CLK, and the output terminal QB is set to the low level. To. The output terminal of the PWM comparator 5 is connected to the reset input terminal R of the flip-flop circuit 19. After the flip-flop circuit 19 is set, the flip-flop circuit 19 is reset by the pulse signal Spw from the PWM comparator 5, and the output terminal QB is connected. Return to high level. The signal output from the output terminal QB of the flip-flop circuit 19 is input to the gates of the first and fourth switching elements M1 and M4 via the buffer BF1, and the second signal via the buffer BF2. Input to the gate of the switching element M2. Since the operation of the reverse current detection circuit 6 is the same as that of FIG. As described above, even in the current mode control type switching regulator as shown in FIG. 2, the same effect as in the case of FIG. 1 can be obtained.

  1 and 2, the third switching element M3 is connected between the second switching element M2 and the ground voltage. However, the third switching element M3 is connected to the connection portion Lx1 and the second switching element M2. You may make it connect between.

Second embodiment.
In the first embodiment, the step-down type switching regulator has been described as an example. However, the present invention can also be applied to a step-up type switching regulator. Let it be an embodiment.
FIG. 3 is a diagram illustrating a circuit example of the synchronous rectification switching regulator according to the second embodiment of the present invention. In FIG. 3, the same or similar parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted here, and only differences from FIG. 1 will be described.
In FIG. 3, the switching regulator 1a includes a first switching element M11 made of an NMOS transistor that performs a switching operation for performing output control of the input voltage Vin, and a second switching element M12 for synchronous rectification made of a PMOS transistor. It has.

  Further, the switching regulator 1a includes a reference voltage generation circuit 2, output voltage detection resistors R1 and R2, an inductor L1, a smoothing capacitor C1, a phase compensation resistor R3 and capacitors C2 and C3, and an error. The amplifier circuit 3, the oscillation circuit 4, the PWM comparator 5, the buffer BF 1, the inverter INV 1, the third switching element M 13 formed of a PMOS transistor, and the reverse current detection circuit 6 a are provided. The reverse current detection circuit 6a includes a comparator 11 and a buffer BF3.

  In the switching regulator 1a, the reference voltage generating circuit 2, the resistors R1 to R3, the error amplifying circuit 3, the oscillation circuit 4, the PWM comparator 5, the buffer BF1, the inverter INV1, and the capacitors C2 and C3 form a control circuit unit. The switching element M13 and the reverse current detection circuit 6a form a reverse current prevention circuit unit. In the switching regulator 1a, each circuit excluding the inductor L1 and the capacitor C1 may be integrated in one IC. In some cases, the first to third switching elements M11 to M13, the inductor L1, and the capacitor Each circuit except C1 may be integrated in one IC.

The buffer BF1 outputs the pulse signal Spw input via the inverter INV1 to the gates of the first and second switching elements M11 and M12. The reverse current detection circuit 6a blocks the connection of the second switching element M12 and prevents the reverse current from being generated.
An inductor L1 and a first switching element M11 are connected in series between the input terminal IN and the ground voltage, and a connection portion between the inductor L1 and the first switching element M11 is Lx2. A second switching element M12 and a third switching element M13 are connected in series between the connection portion Lx2 and the output terminal OUT. The inverting input terminal of the comparator 11 is connected to the connection portion Lx2, and the non-inverting input terminal of the comparator 11 is connected to the output terminal OUT. The output terminal of the comparator 11 is connected to the gate of the third switching element M13 via the buffer BF3.

  In such a configuration, when the voltage at the connection portion Lx2 exceeds the output voltage Vout and there is no sign of a reverse current flowing from the output terminal OUT to the connection portion Lx2, a low level signal is output from the comparator 11. The third switching element M13 is turned on and becomes conductive. In such a state, when the output voltage Vout of the switching regulator 1a increases, the voltage of the output signal EAo of the error amplifier circuit 3 decreases, and the duty cycle of the pulse signal Spw from the PWM comparator 5 decreases. As a result, the time for turning on the first switching element M11 is lengthened, and the time for turning on the second switching element M12 is shortened accordingly, and the output voltage Vout of the switching regulator 1a is controlled to decrease. .

Further, when the output voltage Vout of the switching regulator 1a decreases, the voltage of the output signal EAo of the error amplifier circuit 3 increases, and the duty cycle of the pulse signal Spw from the PWM comparator 5 increases. As a result, the time for which the first switching element M11 is turned on is shortened, and accordingly, the time for which the second switching element M12 is turned on is lengthened, and the output voltage Vout of the switching regulator 1a is controlled to increase. . By repeating such an operation, the output voltage Vout is controlled to be constant at a predetermined voltage.
Next, when the voltage of the connection portion Lx2 becomes the output voltage Vout and a sign that a reverse current is generated is detected, or when the voltage of the connection portion Lx2 becomes less than the output voltage Vout and the occurrence of the reverse current is detected, A high level signal is output from the comparator 11, and the third switching element M13 is turned off to enter a cut-off state. At this time, the second switching element M12 remains on.

  As described above, the reverse current detection circuit 6a detects whether or not there is a sign that the reverse current flows to the second switching element M12 from the voltage of the connection portion Lx2, and when the sign is detected, the second switching element M12 is detected. The third switching element M13 connected in series is turned off to cut off the connection between the second switching element M12 and the output terminal OUT. For this reason, generation | occurrence | production of the reverse current which flows into the 2nd switching element M2 can be prevented reliably. Further, since the reverse current flowing through the second switching element M12 is interrupted using a circuit independent of the control circuit system of the second switching element M12, the reverse current is detected after the occurrence of the reverse current is detected. The delay time until the current is cut off can be shortened, the efficiency can be improved, the design is easy, and the design efficiency can be improved.

Next, in FIG. 3, the voltage mode control type switching regulator has been described as an example. However, the present invention can also be applied to a current mode control type switching regulator. In this case, FIG. It becomes like this. 4 that are the same as or similar to those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted here, and only differences from FIG. 3 are described.
4 differs from FIG. 3 in that the oscillation circuit 4 in FIG. 3 is eliminated, a current detection circuit 25, an oscillation circuit 26 that generates and outputs a clock signal CLK having a predetermined rectangular wave, a slope compensation circuit 27, and an addition. The circuit 28 and the flip-flop circuit 29 are added.

  The switching regulator 1a of FIG. 4 includes a first switching element M11, a second switching element M12 for synchronous rectification, a reference voltage generation circuit 2, resistors R1 and R2 for output voltage detection, an inductor L1, A smoothing capacitor C1, a phase compensation resistor R3 and capacitors C2 and C3, an error amplifier circuit 3, a PWM comparator 5, a buffer BF1, an inverter INV1, and a reverse current detection circuit 6a are provided. Further, the switching regulator 1a includes a current detection circuit 25, an oscillation circuit 26 that generates and outputs a clock signal CLK, a slope compensation circuit 27 that generates and outputs a predetermined sawtooth wave signal Sstw from the clock signal CLK, An adder circuit 28 and a flip-flop circuit 29 are provided.

  Further, the current detection circuit 25 is configured by a series circuit of a resistor R14 and a fourth switching element M14, and the fourth switching element M14 is formed of the same type of MOS transistor as the first switching element M11, that is, an NMOS transistor. In FIG. 4, the reference voltage generation circuit 2, resistors R1 to R3, error amplification circuit 3, oscillation circuit 26, PWM comparator 5, buffer BF1, inverter INV1, capacitors C2 and C3, current detection circuit 25, slope compensation circuit 27 The adder circuit 28 and the flip-flop circuit 29 form a control circuit unit.

  The clock signal CLK output from the oscillation circuit 26 is input to the set input terminal S of the slope compensation circuit 27 and the flip-flop circuit 29, and the slope compensation circuit 27 generates a sawtooth wave signal Sstw from the input clock signal CLK. And output to the adder circuit 28. The series circuit of the resistor R14 and the fourth switching element M14 is connected in parallel with the first switching element M11. The gate of the fourth switching element M14 is connected to the gate of the first switching element M11, and the fourth switching element M14 is turned on / off in synchronization with the first switching element M11. A current proportional to the current flowing through the first switching element M11 flows through the resistor R14. The current is converted into a voltage by the resistor R14, and the voltage at the connection between the resistor R14 and the fourth switching element M14 is the signal Scu. It is output to the adder circuit 28.

The adder circuit 28 adds the input sawtooth wave signal Sstw and the signal Scu and outputs the result to the non-inverting input terminal of the PWM comparator 5.
The PWM comparator 5 generates a pulse signal Spw for performing PWM control from the output signal EAo of the error amplifier circuit 3 and the signal input from the adder circuit 28, and the reset input terminal R of the flip-flop circuit 29 via the inverter INV1. Output to. The output terminal Q of the flip-flop circuit 29 is connected to the gates of the first, second, and fourth switching elements M11, M12, M14 via the buffer BF1, respectively.

  In such a configuration, the clock signal CLK is input to the set input terminal S of the flip-flop circuit 29. The flip-flop circuit 29 is set at the rising or falling edge of the clock signal CLK, and the output terminal Q is set to the high level. To. The pulse signal Spw from the PWM comparator 5 is input to the reset input terminal R of the flip-flop circuit 29 via the inverter INV1, and after the flip-flop circuit 29 is set, the pulse signal Spw from the PWM comparator 5 is set. It is reset and the output terminal Q is returned to the low level. The signal output from the output terminal Q of the flip-flop circuit 29 is input to the respective gates of the first, second and fourth switching elements M11, M12 and M14 via the buffer BF1. Since the operation of the reverse current detection circuit 6a is the same as that of FIG. 3, its description is omitted. Thus, the same effect as in the case of FIG. 3 can be obtained even in the current mode control type switching regulator as shown in FIG.

  3 and 4, the third switching element M13 is connected between the second switching element M12 and the output terminal OUT. However, the third switching element M13 is connected to the connection portion Lx1 and the second switching element. You may make it connect between M12.

  In FIG. 1, when the third switching element M3 is connected between the connection portion Lx1 and the second switching element M2, FIG. 1 becomes as shown in FIG. 6, and the same applies to FIG. . 3, when the third switching element M13 is connected between the connection portion Lx1 and the second switching element M12, FIG. 3 becomes as shown in FIG. 7, and the same applies to FIG. It is.

Third embodiment.
In the first embodiment, since the voltage comparison between the connection portion Lx1 and the ground voltage is performed in order to detect the sign of the occurrence of reverse current or the occurrence of reverse current, the comparator 11 of the reverse current detection circuit 6 is always used. When the third switching element M3 connected in series with the switching element M2 for synchronous rectification is turned off and turned off, the reverse switching is detected and the third switching element M3 is turned off. The voltage comparison operation of the comparator 11 may be stopped by latching the output signal of the comparator 11 input to the gate, and this is the third embodiment of the present invention. .

FIG. 8 is a diagram illustrating a circuit example of the synchronous rectification switching regulator according to the third embodiment of the present invention. In FIG. 8, the same or similar elements as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted here, and only differences from FIG. 1 will be described.
8 differs from FIG. 1 in that the comparator 11 of the reverse current detection circuit 6 of FIG. 1 is replaced with a voltage comparison circuit 41. Accordingly, the reverse current detection circuit 6 of FIG. The switching regulator 1 of FIG. 1 is used as the switching regulator 1b in the detection circuit 6b.

In FIG. 8, a switching regulator 1b is a synchronous rectification switching regulator that converts an input voltage Vin input to an input terminal IN as an input voltage into a predetermined constant voltage, and outputs the output voltage Vout from the output terminal OUT to the load 10. is there.
The switching regulator 1b includes a first switching element M1, a second switching element M2, a reference voltage generating circuit 2, output voltage detection resistors R1 and R2, an inductor L1, and a smoothing capacitor C1. A phase compensation resistor R3 and capacitors C2 and C3, an error amplifier circuit 3, an oscillation circuit 4, a PWM comparator 5, buffers BF1 and BF2, a third switching element M3, and a reverse current detection circuit 6b are provided. I have.

  The reverse current detection circuit 6b includes a voltage comparison circuit 41 and a buffer BF3. In the switching regulator 1b, the reference voltage generation circuit 2, resistors R1 to R3, error amplification circuit 3, oscillation circuit 4, PWM comparator 5, buffers BF1 and BF2, and capacitors C2 and C3 form a control circuit unit, and the third The switching element M3 and the reverse current detection circuit 6b form a reverse current prevention circuit unit. In the switching regulator 1b, each circuit excluding the inductor L1 and the capacitor C1 may be integrated in one IC. In some cases, the first to third switching elements M1 to M3, the inductor L1, and the capacitor Each circuit except C1 may be integrated in one IC.

  The reverse current detection circuit 6b detects a sign that a reverse current is generated in the second switching element M2, and when the sign of the reverse current is detected, the third switching element M3 is turned off to turn off the second switching element M2. And the ground voltage is disconnected to prevent the occurrence of reverse current. The voltage comparison circuit 41 receives the voltage of the connection portion Lx1 and the ground voltage, and further receives the output signal of the buffer BF2. The output terminal of the voltage comparison circuit 41 is connected to the gate of the third switching element M3 via the buffer BF3.

In such a configuration, when the voltage at the connection portion Lx1 is less than the ground voltage and there is no sign that a reverse current flows from the connection portion Lx1 to the ground voltage, a high level signal is output from the voltage comparison circuit 41. Then, the third switching element M3 is turned on and becomes conductive.
Next, when the sign of the reverse current is detected when the voltage at the connection Lx1 becomes the ground voltage, or when the occurrence of the reverse current is detected when the voltage at the connection Lx1 exceeds the ground voltage, the voltage comparison The circuit 41 latches and outputs a low level signal, stops the voltage comparison operation, and enters a low current consumption mode. For this reason, the third switching element M3 is turned off to be in a cut-off state, and at this time, the second switching element M2 remains on. When a low level signal is output from the buffer BF2 to turn off the second switching element M2, the voltage comparison circuit 41 starts a voltage comparison operation, and the voltage at the connection portion Lx1 is grounded. When the voltage is lower than the voltage, the low level signal is unlatched and a high level signal is output.

  In the above description, the case of having the circuit configuration of FIG. 1 has been described as an example, but the case of having the circuit configuration of FIG. 2 is also the same, and the reverse current detection circuit 6 of FIG. Since it may be replaced with the current detection circuit 6b, the description thereof is omitted.

  As described above, in the switching regulator according to the third embodiment, when the reverse current detection circuit 6b performs the same operation as the reverse current detection circuit 6 of FIG. 1 and detects a sign that the reverse current is generated, Or, when the voltage of the connection portion Lx1 exceeds the ground voltage and the occurrence of the reverse current is detected, a signal for turning off the third switching element M3 and latching it is output and then compared. The operation was stopped and the low current consumption mode was set. For this reason, the same effects as those of the first embodiment can be obtained, and the current consumption can be reduced.

Fourth embodiment.
In the second embodiment, since the voltage comparison between the connection portion Lx2 and the output voltage Vout is performed in order to detect the sign of the occurrence of reverse current or the occurrence of reverse current, the comparator 11 of the reverse current detection circuit 6a is When the third switching element M13 connected in series with the synchronous rectification switching element M12 is turned off and turned off, the third switching element M13 turned off is detected. The voltage comparison operation of the comparator 11 may be stopped by latching the output signal of the comparator 11 that is input to the gate of this, and this is the same as the fourth embodiment of the present invention. To do.

FIG. 9 is a diagram illustrating a circuit example of the synchronous rectification switching regulator according to the fourth embodiment of the present invention. In FIG. 9, the same or similar elements as those in FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted here, and only the differences from FIG. 3 will be described.
9 is different from FIG. 3 in that the comparator 11 of the reverse current detection circuit 6a of FIG. 3 is replaced with a voltage comparison circuit 45. Accordingly, the reverse current detection circuit 6a of FIG. The switching regulator 1a shown in FIG. 3 is used as the switching regulator 1c.

  In FIG. 9, the switching regulator 1c includes a first switching element M11, a second switching element M12, a reference voltage generation circuit 2, output voltage detection resistors R1 and R2, an inductor L1, and a smoothing regulator. Capacitor C1, phase compensation resistor R3 and capacitors C2 and C3, error amplifier circuit 3, oscillation circuit 4, PWM comparator 5, buffer BF1, inverter INV1, third switching element M13, and reverse And a current detection circuit 6c. The reverse current detection circuit 6c includes a voltage comparison circuit 45 and a buffer BF3.

  In the switching regulator 1c, the reference voltage generation circuit 2, the resistors R1 to R3, the error amplification circuit 3, the oscillation circuit 4, the PWM comparator 5, the buffer BF1, the inverter INV1, and the capacitors C2 and C3 form a control circuit unit. The switching element M13 and the reverse current detection circuit 6c form a reverse current prevention circuit unit. In the switching regulator 1c, each circuit excluding the inductor L1 and the capacitor C1 may be integrated in one IC. In some cases, the first to third switching elements M11 to M13, the inductor L1, and the capacitor Each circuit except C1 may be integrated in one IC.

  The reverse current detection circuit 6c detects a sign that a reverse current is generated in the second switching element M12. When the sign of the reverse current is detected, the reverse current detection circuit 6c turns off the third switching element M13 to turn off the second switching element M12. And the output terminal OUT are disconnected to prevent the occurrence of reverse current. The voltage comparison circuit 45 receives the voltage of the connection portion Lx2 and the output voltage Vout, and further receives the output signal of the buffer BF1. The output terminal of the voltage comparison circuit 45 is connected to the gate of the third switching element M13 via the buffer BF3.

In such a configuration, when the voltage of the connection portion Lx2 exceeds the output voltage Vout and there is no sign that a reverse current flows from the output terminal OUT to the connection portion Lx2, there is no low level from the voltage comparison circuit 45. A signal is output, and the third switching element M13 is turned on and becomes conductive.
Next, when the voltage of the connection Lx2 becomes the output voltage Vout and a sign that reverse current is generated is detected, or when the voltage of the connection Lx2 becomes less than the output voltage Vout and the occurrence of reverse current is detected The voltage comparison circuit 45 latches and outputs a high level signal, stops the voltage comparison operation, and enters a low current consumption mode. For this reason, the third switching element M13 is turned off to be in a cut-off state, and at this time, the second switching element M12 remains on. When a high level signal is output from the buffer BF1 in order to turn off the second switching element M12 and enter the cutoff state, the voltage comparison circuit 45 starts a voltage comparison operation, and the voltage at the connection portion Lx2 is output. When the voltage Vout is exceeded, the high level signal is unlatched and a low level signal is output.

  In the above description, the case of having the circuit configuration of FIG. 3 has been described as an example, but the case of having the circuit configuration of FIG. 4 is also the same, and the reverse current detection circuit 6a of FIG. Since it may be replaced with the current detection circuit 6c, the description thereof is omitted.

  As described above, in the switching regulator according to the fourth embodiment, the reverse current detection circuit 6c performs the same operation as the reverse current detection circuit 6a of FIG. 3, and the voltage at the connection portion Lx2 becomes the output voltage Vout. When the sign that the reverse current is generated is detected, or when the occurrence of the reverse current is detected when the voltage at the connection portion Lx2 becomes less than the output voltage Vout, the third switching element M13 is turned off to shut off the state. After latching and outputting the signal for the purpose, the voltage comparison operation is stopped to enter the low current consumption mode. For this reason, the same effect as that of the second embodiment can be obtained, and the current consumption can be reduced.

  In each of the first to fourth embodiments, each of the second and third switching elements has a large transistor size. Therefore, when the second and third switching elements connected in series are laid out, The chip area can be reduced by sharing the drain and source of the connecting portion of the two switching elements. For example, the second and third switching elements M2 and M3 in the case of FIG. 1 are shown in FIG. 10, and a layout pattern example of the second and third switching elements M2 and M3 in the case of FIG. 11. In FIG. 11, the source of the second switching element M2 and the drain of the third switching element are shared.

It is the figure which showed the circuit example of the synchronous rectification type | mold switching regulator in the 1st Embodiment of this invention. It is the figure which showed the other circuit example of the synchronous rectification type switching regulator in the 1st Embodiment of this invention. It is the figure which showed the circuit example of the synchronous rectification type | mold switching regulator in the 2nd Embodiment of this invention. It is the figure which showed the other circuit example of the synchronous rectification type | mold switching regulator in the 2nd Embodiment of this invention. It is the figure which showed the circuit example of the conventional synchronous rectification type switching regulator. It is the figure which showed the other circuit example of the synchronous rectification type switching regulator in the 1st Embodiment of this invention. It is the figure which showed the other circuit example of the synchronous rectification type | mold switching regulator in the 2nd Embodiment of this invention. It is the figure which showed the circuit example of the synchronous rectification type | mold switching regulator in the 3rd Embodiment of this invention. It is the figure which showed the circuit example of the synchronous rectification type | mold switching regulator in the 4th Embodiment of this invention. It is the figure which showed each 2nd and 3rd switching element of FIG. It is the figure which showed the example of a layout pattern in the case of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a Switching regulator 2 Reference voltage generation circuit 3 Error amplification circuit 4, 16, 26 Oscillation circuit 5 PWM comparator 6, 6a Reverse current detection circuit 10 Load 11 Comparator 15, 25 Current detection circuit 17, 27 Slope compensation circuit 18, 28 Adder circuit 19, 29 Flip-flop circuit R1, R2 Resistor L1 Inductor C1 Capacitor M1, M11 First switching element M2, M12 Second switching element M3, M13 Third switching element BF1 to BF3 Buffer INV1 Inverter 1b, 1c Switching Regulator 6b, 6c Reverse current detection circuit 41, 45 Voltage comparison circuit

Claims (1)

In the synchronous rectification type switching regulator that converts the input voltage input to the input terminal to a predetermined constant voltage and outputs it to the load connected to the output terminal.
A first switching element that performs switching according to an input control signal;
An inductor charged by the input voltage by switching of the first switching element;
A second switching element for synchronous rectification that performs switching according to an input control signal to discharge the inductor;
The switching control for the first switching element is performed so that the output voltage output from the output terminal becomes the predetermined constant voltage, and the second switching element is in conflict with the first switching element. A control circuit unit for performing a switching operation;
In order to prevent the occurrence of reverse current flowing from the output terminal to the second switching element, the wiring of the second switching element is cut off to cut off the connection of the second switching element. A reverse current prevention circuit section for cutting off a current flowing through the switching element;
Equipped with a,
When the reverse current prevention circuit unit detects that the voltages at both ends of the second switching element are equal, the reverse current prevention circuit unit determines that the sign of occurrence of the reverse current has been detected, and interrupts the wiring of the second switching element. The synchronous rectification type switching regulator characterized by the above-mentioned.

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